hwpmc_core.c revision 210012
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_core.c 210012 2010-07-13 19:37:45Z gnn $"); 33 34#include <sys/param.h> 35#include <sys/bus.h> 36#include <sys/pmc.h> 37#include <sys/pmckern.h> 38#include <sys/systm.h> 39 40#include <machine/intr_machdep.h> 41#include <machine/apicvar.h> 42#include <machine/cpu.h> 43#include <machine/cpufunc.h> 44#include <machine/specialreg.h> 45 46#define CORE_CPUID_REQUEST 0xA 47#define CORE_CPUID_REQUEST_SIZE 0x4 48#define CORE_CPUID_EAX 0x0 49#define CORE_CPUID_EBX 0x1 50#define CORE_CPUID_ECX 0x2 51#define CORE_CPUID_EDX 0x3 52 53#define IAF_PMC_CAPS \ 54 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT) 55#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 56 57#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 58 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 59 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 60 61/* 62 * "Architectural" events defined by Intel. The values of these 63 * symbols correspond to positions in the bitmask returned by 64 * the CPUID.0AH instruction. 65 */ 66enum core_arch_events { 67 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 68 CORE_AE_BRANCH_MISSES_RETIRED = 6, 69 CORE_AE_INSTRUCTION_RETIRED = 1, 70 CORE_AE_LLC_MISSES = 4, 71 CORE_AE_LLC_REFERENCE = 3, 72 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 73 CORE_AE_UNHALTED_CORE_CYCLES = 0 74}; 75 76static enum pmc_cputype core_cputype; 77 78struct core_cpu { 79 volatile uint32_t pc_resync; 80 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 81 volatile uint64_t pc_globalctrl; /* Global control register. */ 82 struct pmc_hw pc_corepmcs[]; 83}; 84 85static struct core_cpu **core_pcpu; 86 87static uint32_t core_architectural_events; 88static uint64_t core_pmcmask; 89 90static int core_iaf_ri; /* relative index of fixed counters */ 91static int core_iaf_width; 92static int core_iaf_npmc; 93 94static int core_iap_width; 95static int core_iap_npmc; 96 97static int 98core_pcpu_noop(struct pmc_mdep *md, int cpu) 99{ 100 (void) md; 101 (void) cpu; 102 return (0); 103} 104 105static int 106core_pcpu_init(struct pmc_mdep *md, int cpu) 107{ 108 struct pmc_cpu *pc; 109 struct core_cpu *cc; 110 struct pmc_hw *phw; 111 int core_ri, n, npmc; 112 113 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 114 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 115 116 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 117 118 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 119 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 120 121 if (core_cputype != PMC_CPU_INTEL_CORE) 122 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 123 124 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 125 M_PMC, M_WAITOK | M_ZERO); 126 127 core_pcpu[cpu] = cc; 128 pc = pmc_pcpu[cpu]; 129 130 KASSERT(pc != NULL && cc != NULL, 131 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 132 133 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 134 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 135 PMC_PHW_CPU_TO_STATE(cpu) | 136 PMC_PHW_INDEX_TO_STATE(n + core_ri); 137 phw->phw_pmc = NULL; 138 pc->pc_hwpmcs[n + core_ri] = phw; 139 } 140 141 return (0); 142} 143 144static int 145core_pcpu_fini(struct pmc_mdep *md, int cpu) 146{ 147 int core_ri, n, npmc; 148 struct pmc_cpu *pc; 149 struct core_cpu *cc; 150 uint64_t msr = 0; 151 152 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 153 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 154 155 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 156 157 if ((cc = core_pcpu[cpu]) == NULL) 158 return (0); 159 160 core_pcpu[cpu] = NULL; 161 162 pc = pmc_pcpu[cpu]; 163 164 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 165 cpu)); 166 167 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 168 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 169 170 for (n = 0; n < npmc; n++) { 171 msr = rdmsr(IAP_EVSEL0 + n); 172 wrmsr(IAP_EVSEL0 + n, msr & ~IAP_EVSEL_MASK); 173 } 174 175 if (core_cputype != PMC_CPU_INTEL_CORE) { 176 msr = rdmsr(IAF_CTRL); 177 wrmsr(IAF_CTRL, msr & ~IAF_CTRL_MASK); 178 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 179 } 180 181 for (n = 0; n < npmc; n++) 182 pc->pc_hwpmcs[n + core_ri] = NULL; 183 184 free(cc, M_PMC); 185 186 return (0); 187} 188 189/* 190 * Fixed function counters. 191 */ 192 193static pmc_value_t 194iaf_perfctr_value_to_reload_count(pmc_value_t v) 195{ 196 v &= (1ULL << core_iaf_width) - 1; 197 return (1ULL << core_iaf_width) - v; 198} 199 200static pmc_value_t 201iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 202{ 203 return (1ULL << core_iaf_width) - rlc; 204} 205 206static int 207iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 208 const struct pmc_op_pmcallocate *a) 209{ 210 enum pmc_event ev; 211 uint32_t caps, flags, validflags; 212 213 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 214 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 215 216 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 217 218 if (ri < 0 || ri > core_iaf_npmc) 219 return (EINVAL); 220 221 caps = a->pm_caps; 222 223 if (a->pm_class != PMC_CLASS_IAF || 224 (caps & IAF_PMC_CAPS) != caps) 225 return (EINVAL); 226 227 ev = pm->pm_event; 228 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 229 return (EINVAL); 230 231 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 232 return (EINVAL); 233 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 234 return (EINVAL); 235 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 236 return (EINVAL); 237 238 flags = a->pm_md.pm_iaf.pm_iaf_flags; 239 240 validflags = IAF_MASK; 241 242 if (core_cputype != PMC_CPU_INTEL_ATOM) 243 validflags &= ~IAF_ANY; 244 245 if ((flags & ~validflags) != 0) 246 return (EINVAL); 247 248 if (caps & PMC_CAP_INTERRUPT) 249 flags |= IAF_PMI; 250 if (caps & PMC_CAP_SYSTEM) 251 flags |= IAF_OS; 252 if (caps & PMC_CAP_USER) 253 flags |= IAF_USR; 254 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 255 flags |= (IAF_OS | IAF_USR); 256 257 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 258 259 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 260 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 261 262 return (0); 263} 264 265static int 266iaf_config_pmc(int cpu, int ri, struct pmc *pm) 267{ 268 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 269 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 270 271 KASSERT(ri >= 0 && ri < core_iaf_npmc, 272 ("[core,%d] illegal row-index %d", __LINE__, ri)); 273 274 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 275 276 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 277 cpu)); 278 279 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 280 281 return (0); 282} 283 284static int 285iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 286{ 287 int error; 288 struct pmc_hw *phw; 289 char iaf_name[PMC_NAME_MAX]; 290 291 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 292 293 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 294 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 295 NULL)) != 0) 296 return (error); 297 298 pi->pm_class = PMC_CLASS_IAF; 299 300 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 301 pi->pm_enabled = TRUE; 302 *ppmc = phw->phw_pmc; 303 } else { 304 pi->pm_enabled = FALSE; 305 *ppmc = NULL; 306 } 307 308 return (0); 309} 310 311static int 312iaf_get_config(int cpu, int ri, struct pmc **ppm) 313{ 314 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 315 316 return (0); 317} 318 319static int 320iaf_get_msr(int ri, uint32_t *msr) 321{ 322 KASSERT(ri >= 0 && ri < core_iaf_npmc, 323 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 324 325 *msr = IAF_RI_TO_MSR(ri); 326 327 return (0); 328} 329 330static int 331iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 332{ 333 struct pmc *pm; 334 pmc_value_t tmp; 335 336 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 337 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 338 KASSERT(ri >= 0 && ri < core_iaf_npmc, 339 ("[core,%d] illegal row-index %d", __LINE__, ri)); 340 341 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 342 343 KASSERT(pm, 344 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 345 ri, ri + core_iaf_ri)); 346 347 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 348 349 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 350 *v = iaf_perfctr_value_to_reload_count(tmp); 351 else 352 *v = tmp; 353 354 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 355 IAF_RI_TO_MSR(ri), *v); 356 357 return (0); 358} 359 360static int 361iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 362{ 363 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 364 365 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 366 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 367 KASSERT(ri >= 0 && ri < core_iaf_npmc, 368 ("[core,%d] illegal row-index %d", __LINE__, ri)); 369 370 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 371 ("[core,%d] PHW pmc non-NULL", __LINE__)); 372 373 return (0); 374} 375 376static int 377iaf_start_pmc(int cpu, int ri) 378{ 379 struct pmc *pm; 380 struct core_cpu *iafc; 381 uint64_t msr = 0; 382 383 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 384 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 385 KASSERT(ri >= 0 && ri < core_iaf_npmc, 386 ("[core,%d] illegal row-index %d", __LINE__, ri)); 387 388 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 389 390 iafc = core_pcpu[cpu]; 391 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 392 393 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 394 395 msr = rdmsr(IAF_CTRL); 396 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 397 398 do { 399 iafc->pc_resync = 0; 400 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 401 msr = rdmsr(IA_GLOBAL_CTRL); 402 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 403 IAF_GLOBAL_CTRL_MASK)); 404 } while (iafc->pc_resync != 0); 405 406 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 407 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 408 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 409 410 return (0); 411} 412 413static int 414iaf_stop_pmc(int cpu, int ri) 415{ 416 uint32_t fc; 417 struct core_cpu *iafc; 418 uint64_t msr = 0; 419 420 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 421 422 iafc = core_pcpu[cpu]; 423 424 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 425 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 426 KASSERT(ri >= 0 && ri < core_iaf_npmc, 427 ("[core,%d] illegal row-index %d", __LINE__, ri)); 428 429 fc = (IAF_MASK << (ri * 4)); 430 431 if (core_cputype != PMC_CPU_INTEL_ATOM) 432 fc &= ~IAF_ANY; 433 434 iafc->pc_iafctrl &= ~fc; 435 436 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 437 msr = rdmsr(IAF_CTRL); 438 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 439 440 do { 441 iafc->pc_resync = 0; 442 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 443 msr = rdmsr(IA_GLOBAL_CTRL); 444 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 445 IAF_GLOBAL_CTRL_MASK)); 446 } while (iafc->pc_resync != 0); 447 448 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 449 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 450 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 451 452 return (0); 453} 454 455static int 456iaf_write_pmc(int cpu, int ri, pmc_value_t v) 457{ 458 struct core_cpu *cc; 459 struct pmc *pm; 460 uint64_t msr; 461 462 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 463 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 464 KASSERT(ri >= 0 && ri < core_iaf_npmc, 465 ("[core,%d] illegal row-index %d", __LINE__, ri)); 466 467 cc = core_pcpu[cpu]; 468 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 469 470 KASSERT(pm, 471 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 472 473 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 474 v = iaf_reload_count_to_perfctr_value(v); 475 476 msr = rdmsr(IAF_CTRL); 477 wrmsr(IAF_CTRL, msr & ~IAF_CTRL_MASK); 478 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 479 msr = rdmsr(IAF_CTRL); 480 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 481 482 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 483 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 484 (uintmax_t) rdmsr(IAF_CTRL), 485 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 486 487 return (0); 488} 489 490 491static void 492iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 493{ 494 struct pmc_classdep *pcd; 495 496 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 497 498 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 499 500 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 501 502 pcd->pcd_caps = IAF_PMC_CAPS; 503 pcd->pcd_class = PMC_CLASS_IAF; 504 pcd->pcd_num = npmc; 505 pcd->pcd_ri = md->pmd_npmc; 506 pcd->pcd_width = pmcwidth; 507 508 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 509 pcd->pcd_config_pmc = iaf_config_pmc; 510 pcd->pcd_describe = iaf_describe; 511 pcd->pcd_get_config = iaf_get_config; 512 pcd->pcd_get_msr = iaf_get_msr; 513 pcd->pcd_pcpu_fini = core_pcpu_noop; 514 pcd->pcd_pcpu_init = core_pcpu_noop; 515 pcd->pcd_read_pmc = iaf_read_pmc; 516 pcd->pcd_release_pmc = iaf_release_pmc; 517 pcd->pcd_start_pmc = iaf_start_pmc; 518 pcd->pcd_stop_pmc = iaf_stop_pmc; 519 pcd->pcd_write_pmc = iaf_write_pmc; 520 521 md->pmd_npmc += npmc; 522} 523 524/* 525 * Intel programmable PMCs. 526 */ 527 528/* 529 * Event descriptor tables. 530 * 531 * For each event id, we track: 532 * 533 * 1. The CPUs that the event is valid for. 534 * 535 * 2. If the event uses a fixed UMASK, the value of the umask field. 536 * If the event doesn't use a fixed UMASK, a mask of legal bits 537 * to check against. 538 */ 539 540struct iap_event_descr { 541 enum pmc_event iap_ev; 542 unsigned char iap_evcode; 543 unsigned char iap_umask; 544 unsigned char iap_flags; 545}; 546 547#define IAP_F_CC (1 << 0) /* CPU: Core */ 548#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 549#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 550#define IAP_F_CA (1 << 3) /* CPU: Atom */ 551#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 552#define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 553#define IAP_F_WM (1 << 5) /* CPU: Westmere */ 554#define IAP_F_FM (1 << 6) /* Fixed mask */ 555 556#define IAP_F_ALLCPUSCORE2 \ 557 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 558 559/* Sub fields of UMASK that this event supports. */ 560#define IAP_M_CORE (1 << 0) /* Core specificity */ 561#define IAP_M_AGENT (1 << 1) /* Agent specificity */ 562#define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 563#define IAP_M_MESI (1 << 3) /* MESI */ 564#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 565#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 566#define IAP_M_TRANSITION (1 << 6) /* Transition */ 567 568#define IAP_F_CORE (0x3 << 14) /* Core specificity */ 569#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 570#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 571#define IAP_F_MESI (0xF << 8) /* MESI */ 572#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 573#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 574#define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 575 576#define IAP_PREFETCH_RESERVED (0x2 << 12) 577#define IAP_CORE_THIS (0x1 << 14) 578#define IAP_CORE_ALL (0x3 << 14) 579#define IAP_F_CMASK 0xFF000000 580 581static struct iap_event_descr iap_events[] = { 582#undef IAPDESCR 583#define IAPDESCR(N,EV,UM,FLAGS) { \ 584 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 585 .iap_evcode = (EV), \ 586 .iap_umask = (UM), \ 587 .iap_flags = (FLAGS) \ 588 } 589 590 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 591 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 592 593 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 594 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O), 595 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_WM), 596 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 597 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 598 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 599 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 600 601 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 602 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 603 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 604 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 605 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 606 607 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 608 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O), 609 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM), 610 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), 611 612 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 613 IAP_F_CC2E | IAP_F_CA), 614 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 615 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 616 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 617 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 618 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 619 620 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 621 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM), 622 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 623 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 624 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 625 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA), 626 627 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 628 IAP_F_I7 | IAP_F_WM), 629 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 630 IAP_F_I7 | IAP_F_WM), 631 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 632 IAP_F_WM), 633 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 634 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 635 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 636 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 637 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 638 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 639 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 640 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7), 641 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), 642 643 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 644 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 645 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 646 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 647 648 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 649 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 650 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 651 652 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 653 IAP_F_WM), 654 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 655 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 656 657 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 658 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 659 660 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 661 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 662 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 663 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 664 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 665 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 666 667 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 668 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 669 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 670 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 671 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 672 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 673 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 674 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 675 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 676 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 677 678 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 679 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA), 680 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 681 682 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 683 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 684 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 685 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 686 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 687 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 688 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 689 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 690 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 691 692 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 693 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 694 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 695 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 696 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 697 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 698 699 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 700 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 701 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 702 703 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 704 705 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 706 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 707 708 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 709 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 710 IAP_F_I7 | IAP_F_WM), 711 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 712 713 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 714 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 715 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 716 717 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 718 719 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 720 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 721 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 722 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 723 724 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 725 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 726 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 727 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 728 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 729 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 730 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 731 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 732 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 733 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 734 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 735 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 736 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 737 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 738 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 739 740 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 741 742 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 743 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 744 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 745 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 746 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 747 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 748 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 749 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 750 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 751 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 752 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 753 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 754 755 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 756 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 757 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 758 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O), 759 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 760 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 761 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 762 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 763 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 764 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 765 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 766 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 767 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 768 769 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 770 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 771 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 772 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 773 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 774 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 775 776 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 777 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 778 IAP_F_CA | IAP_F_CC2), 779 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 780 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 781 782 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 783 IAP_F_ALLCPUSCORE2), 784 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 785 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 786 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7), 787 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7), 788 789 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 790 IAP_F_ALLCPUSCORE2), 791 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 792 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 793 794 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 795 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 796 797 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 798 799 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 800 IAP_F_I7 | IAP_F_WM), 801 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 802 IAP_F_I7 | IAP_F_WM), 803 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 804 805 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 806 807 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 808 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 809 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 810 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 811 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 812 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 813 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 814 815 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 816 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 817 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 818 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 819 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 820 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 821 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 822 823 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 824 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 825 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 826 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 827 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 828 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 829 830 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 831 IAP_F_I7), 832 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 833 IAP_F_CC2 | IAP_F_I7), 834 835 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 836 837 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 838 839 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 840 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 841 842 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 843 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7), 844 845 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 846 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 847 IAP_F_I7 | IAP_F_WM), 848 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 849 IAP_F_I7 | IAP_F_WM), 850 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM), 851 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 852 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7O), 853 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O), 854 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 855 856 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 857 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 858 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 859 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 860 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 861 862 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 863 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 864 865 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 866 867 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 868 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 869 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 870 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 871 872 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 873 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 874 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 875 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 876 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 877 878 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 879 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 880 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 881 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 882 883 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 884 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 885 886 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 887 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 888 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 889 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 890 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 891 892 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 893 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 894 895 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 896 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 897 898 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 899 IAP_F_CA | IAP_F_CC2), 900 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 901 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 902 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 903 904 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 905 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 906 907 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 908 IAP_F_CA | IAP_F_CC2), 909 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 910 911 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 912 913 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 914 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 915 916 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 917 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 918 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 919 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 920 921 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 922 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 923 924 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 925 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 926 927 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 928 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 929 930 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 931 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 932 933 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 934 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 935 936 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 937 IAP_F_CA | IAP_F_CC2), 938 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 939 940 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 941 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 942 943 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 944 945 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 946 947 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 948 949 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 950 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 951 952 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 953 954 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 955 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 956 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 957 IAP_F_WM), 958 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 959 IAP_F_WM), 960 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 961 962 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 963 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 964 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 965 966 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 967 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 968 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 969 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 970 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 971 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 972 973 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 974 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 975 976 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 977 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 978 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 979 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 980 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O), 981 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O), 982 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O), 983 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 984 985 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 986 987 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 988 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 989 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 990 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 991 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 992 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 993 994 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 995 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 996 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 997 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 998 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 999 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1000 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1001 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1002 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1003 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1004 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1005 1006 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1007 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1008 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1009 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1010 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1011 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1012 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1013 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1014 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1015 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1016 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1017 1018 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1019 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1020 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1021 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1022 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1023 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1024 1025 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1026 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1027 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1028 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1029 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1030 1031 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1032 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1033 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1034 1035 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1036 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1037 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1038 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1039 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1040 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1041 1042 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1043 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1044 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1045 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1046 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1047 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1048 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1049 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1050 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1051 1052 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1053 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1054 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1055 1056 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1057 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1058 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1059 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1060 1061 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1062 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1063 1064 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1065 1066 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1067 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1068 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1069 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1070 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1071 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1072 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1073 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1074 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1075 1076 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1077 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1078 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1079 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1080 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1081 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1082 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1083 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1084 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1085 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1086 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1087 IAP_F_WM), 1088 1089 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1090 1091 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1092 IAP_F_WM | IAP_F_I7O), 1093 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1094 IAP_F_WM | IAP_F_I7O), 1095 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1096 IAP_F_WM | IAP_F_I7O), 1097 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1098 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1099 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1100 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1101 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1102 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1103 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1104 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1105 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1106 1107 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1108 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1109 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1110 1111 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1112 1113 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1114 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1115 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1116 1117 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1118 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1119 1120 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1121 1122 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1123 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1124 IAP_F_I7 | IAP_F_WM), 1125 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1126 IAP_F_I7 | IAP_F_WM), 1127 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1128 IAP_F_I7 | IAP_F_WM), 1129 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1130 1131 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1132 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1133 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1134 1135 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1136 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1137 IAP_F_I7 | IAP_F_WM), 1138 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1139 IAP_F_I7 | IAP_F_WM), 1140 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1141 IAP_F_I7 | IAP_F_WM), 1142 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1143 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1144 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1145 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 1146 1147 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1148 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1149 IAP_F_I7 | IAP_F_WM), 1150 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1151 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1152 IAP_F_I7 | IAP_F_WM), 1153 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1154 1155 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1156 IAP_F_I7 | IAP_F_WM), 1157 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1158 IAP_F_I7 | IAP_F_WM), 1159 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1160 IAP_F_I7 | IAP_F_WM), 1161 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1162 IAP_F_I7 | IAP_F_WM), 1163 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1164 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1165 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1166 1167 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1168 IAP_F_I7 | IAP_F_WM), 1169 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM), 1170 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1171 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM), 1172 1173 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1174 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1175 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1176 1177 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1178 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1179 IAP_F_I7 | IAP_F_WM), 1180 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1181 IAP_F_I7 | IAP_F_WM), 1182 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1183 IAP_F_I7 | IAP_F_WM), 1184 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1185 IAP_F_I7 | IAP_F_WM), 1186 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1187 IAP_F_I7 | IAP_F_WM), 1188 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1189 1190 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1191 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1192 1193 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1194 1195 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1196 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1197 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1198 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1199 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1200 1201 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1202 IAP_F_I7 | IAP_F_WM), 1203 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1204 IAP_F_I7 | IAP_F_WM), 1205 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1206 IAP_F_I7 | IAP_F_WM), 1207 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1208 IAP_F_I7 | IAP_F_WM), 1209 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1210 IAP_F_WM), 1211 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1212 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1213 1214 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1215 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1216 IAP_F_I7 | IAP_F_WM), 1217 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1218 IAP_F_I7 | IAP_F_WM), 1219 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1220 1221 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1222 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1223 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1224 1225 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1226 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1227 1228 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM), 1229 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1230 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1231 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1232 1233 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1234 IAP_F_I7 | IAP_F_WM), 1235 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1236 IAP_F_I7 | IAP_F_WM), 1237 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1238 IAP_F_I7 | IAP_F_WM), 1239 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1240 IAP_F_I7 | IAP_F_WM), 1241 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1242 IAP_F_I7 | IAP_F_WM), 1243 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1244 1245 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1246 IAP_F_I7 | IAP_F_WM), 1247 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1248 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1249 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1250 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1251 1252 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1253 IAP_F_I7 | IAP_F_WM), 1254 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1255 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1256 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1257 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1258 1259 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1260 1261 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1262 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1263 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1264 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1265 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1266 1267 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1268 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1269 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1270 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1271 1272 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1273 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1274 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1275 1276 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1277 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1278 1279 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1280 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1281 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1282 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1283 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1284 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1285 1286 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1287 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1288 IAP_F_WM), 1289 1290 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1291 1292 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1293 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1294 1295 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1296 1297 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1298 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1299 IAP_F_WM), 1300 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1301 1302 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1303 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1304 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7), 1305 1306 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1307 1308 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1309 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1310 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1311 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1312 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1313 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1314 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1315 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1316 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1317 1318 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1319 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1320 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1321 1322 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1323 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1324 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1325 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1326 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1327 1328 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1329 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1330 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1331 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1332 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1333 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1334 1335 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1336 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1337 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1338 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1339 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1340 1341 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1342 1343 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1344 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1345 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1346 1347 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1348 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1349 1350 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1351 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1352 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1353 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1354 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1355 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1356 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1357}; 1358 1359static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1360 1361static pmc_value_t 1362iap_perfctr_value_to_reload_count(pmc_value_t v) 1363{ 1364 v &= (1ULL << core_iap_width) - 1; 1365 return (1ULL << core_iap_width) - v; 1366} 1367 1368static pmc_value_t 1369iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1370{ 1371 return (1ULL << core_iap_width) - rlc; 1372} 1373 1374static int 1375iap_pmc_has_overflowed(int ri) 1376{ 1377 uint64_t v; 1378 1379 /* 1380 * We treat a Core (i.e., Intel architecture v1) PMC as has 1381 * having overflowed if its MSB is zero. 1382 */ 1383 v = rdpmc(ri); 1384 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1385} 1386 1387/* 1388 * Check an event against the set of supported architectural events. 1389 * 1390 * Returns 1 if the event is architectural and unsupported on this 1391 * CPU. Returns 0 otherwise. 1392 */ 1393 1394static int 1395iap_architectural_event_is_unsupported(enum pmc_event pe) 1396{ 1397 enum core_arch_events ae; 1398 1399 switch (pe) { 1400 case PMC_EV_IAP_EVENT_3CH_00H: 1401 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1402 break; 1403 case PMC_EV_IAP_EVENT_C0H_00H: 1404 ae = CORE_AE_INSTRUCTION_RETIRED; 1405 break; 1406 case PMC_EV_IAP_EVENT_3CH_01H: 1407 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1408 break; 1409 case PMC_EV_IAP_EVENT_2EH_4FH: 1410 ae = CORE_AE_LLC_REFERENCE; 1411 break; 1412 case PMC_EV_IAP_EVENT_2EH_41H: 1413 ae = CORE_AE_LLC_MISSES; 1414 break; 1415 case PMC_EV_IAP_EVENT_C4H_00H: 1416 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1417 break; 1418 case PMC_EV_IAP_EVENT_C5H_00H: 1419 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1420 break; 1421 1422 default: /* Non architectural event. */ 1423 return (0); 1424 } 1425 1426 return ((core_architectural_events & (1 << ae)) == 0); 1427} 1428 1429static int 1430iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1431{ 1432 uint32_t mask; 1433 1434 switch (pe) { 1435 /* 1436 * Events valid only on counter 0, 1. 1437 */ 1438 case PMC_EV_IAP_EVENT_40H_01H: 1439 case PMC_EV_IAP_EVENT_40H_02H: 1440 case PMC_EV_IAP_EVENT_40H_04H: 1441 case PMC_EV_IAP_EVENT_40H_08H: 1442 case PMC_EV_IAP_EVENT_40H_0FH: 1443 case PMC_EV_IAP_EVENT_41H_02H: 1444 case PMC_EV_IAP_EVENT_41H_04H: 1445 case PMC_EV_IAP_EVENT_41H_08H: 1446 case PMC_EV_IAP_EVENT_42H_01H: 1447 case PMC_EV_IAP_EVENT_42H_02H: 1448 case PMC_EV_IAP_EVENT_42H_04H: 1449 case PMC_EV_IAP_EVENT_42H_08H: 1450 case PMC_EV_IAP_EVENT_43H_01H: 1451 case PMC_EV_IAP_EVENT_43H_02H: 1452 case PMC_EV_IAP_EVENT_48H_02H: 1453 case PMC_EV_IAP_EVENT_51H_01H: 1454 case PMC_EV_IAP_EVENT_51H_02H: 1455 case PMC_EV_IAP_EVENT_51H_04H: 1456 case PMC_EV_IAP_EVENT_51H_08H: 1457 case PMC_EV_IAP_EVENT_63H_01H: 1458 case PMC_EV_IAP_EVENT_63H_02H: 1459 mask = 0x3; 1460 break; 1461 1462 default: 1463 mask = ~0; /* Any row index is ok. */ 1464 } 1465 1466 return (mask & (1 << ri)); 1467} 1468 1469static int 1470iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1471{ 1472 uint32_t mask; 1473 1474 switch (pe) { 1475 /* 1476 * Events valid only on counter 0. 1477 */ 1478 case PMC_EV_IAP_EVENT_B3H_01H: 1479 case PMC_EV_IAP_EVENT_B3H_02H: 1480 case PMC_EV_IAP_EVENT_B3H_04H: 1481 mask = 0x1; 1482 break; 1483 1484 /* 1485 * Events valid only on counter 0, 1. 1486 */ 1487 case PMC_EV_IAP_EVENT_51H_01H: 1488 case PMC_EV_IAP_EVENT_51H_02H: 1489 case PMC_EV_IAP_EVENT_51H_04H: 1490 case PMC_EV_IAP_EVENT_51H_08H: 1491 case PMC_EV_IAP_EVENT_63H_01H: 1492 case PMC_EV_IAP_EVENT_63H_02H: 1493 mask = 0x3; 1494 break; 1495 1496 default: 1497 mask = ~0; /* Any row index is ok. */ 1498 } 1499 1500 return (mask & (1 << ri)); 1501} 1502 1503static int 1504iap_event_ok_on_counter(enum pmc_event pe, int ri) 1505{ 1506 uint32_t mask; 1507 1508 switch (pe) { 1509 /* 1510 * Events valid only on counter 0. 1511 */ 1512 case PMC_EV_IAP_EVENT_10H_00H: 1513 case PMC_EV_IAP_EVENT_14H_00H: 1514 case PMC_EV_IAP_EVENT_18H_00H: 1515 case PMC_EV_IAP_EVENT_B3H_01H: 1516 case PMC_EV_IAP_EVENT_B3H_02H: 1517 case PMC_EV_IAP_EVENT_B3H_04H: 1518 case PMC_EV_IAP_EVENT_C1H_00H: 1519 case PMC_EV_IAP_EVENT_CBH_01H: 1520 case PMC_EV_IAP_EVENT_CBH_02H: 1521 mask = (1 << 0); 1522 break; 1523 1524 /* 1525 * Events valid only on counter 1. 1526 */ 1527 case PMC_EV_IAP_EVENT_11H_00H: 1528 case PMC_EV_IAP_EVENT_12H_00H: 1529 case PMC_EV_IAP_EVENT_13H_00H: 1530 mask = (1 << 1); 1531 break; 1532 1533 default: 1534 mask = ~0; /* Any row index is ok. */ 1535 } 1536 1537 return (mask & (1 << ri)); 1538} 1539 1540static int 1541iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1542 const struct pmc_op_pmcallocate *a) 1543{ 1544 int n; 1545 enum pmc_event ev; 1546 struct iap_event_descr *ie; 1547 uint32_t c, caps, config, cpuflag, evsel, mask; 1548 1549 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1550 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1551 KASSERT(ri >= 0 && ri < core_iap_npmc, 1552 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1553 1554 /* check requested capabilities */ 1555 caps = a->pm_caps; 1556 if ((IAP_PMC_CAPS & caps) != caps) 1557 return (EPERM); 1558 1559 ev = pm->pm_event; 1560 1561 if (iap_architectural_event_is_unsupported(ev)) 1562 return (EOPNOTSUPP); 1563 1564 switch (core_cputype) { 1565 case PMC_CPU_INTEL_COREI7: 1566 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 1567 return (EINVAL); 1568 break; 1569 case PMC_CPU_INTEL_WESTMERE: 1570 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 1571 return (EINVAL); 1572 break; 1573 default: 1574 if (iap_event_ok_on_counter(ev, ri) == 0) 1575 return (EINVAL); 1576 } 1577 1578 /* 1579 * Look for an event descriptor with matching CPU and event id 1580 * fields. 1581 */ 1582 1583 switch (core_cputype) { 1584 default: 1585 case PMC_CPU_INTEL_ATOM: 1586 cpuflag = IAP_F_CA; 1587 break; 1588 case PMC_CPU_INTEL_CORE: 1589 cpuflag = IAP_F_CC; 1590 break; 1591 case PMC_CPU_INTEL_CORE2: 1592 cpuflag = IAP_F_CC2; 1593 break; 1594 case PMC_CPU_INTEL_CORE2EXTREME: 1595 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1596 break; 1597 case PMC_CPU_INTEL_COREI7: 1598 cpuflag = IAP_F_I7; 1599 break; 1600 case PMC_CPU_INTEL_WESTMERE: 1601 cpuflag = IAP_F_WM; 1602 break; 1603 } 1604 1605 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 1606 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 1607 break; 1608 1609 if (n == niap_events) 1610 return (EINVAL); 1611 1612 /* 1613 * A matching event descriptor has been found, so start 1614 * assembling the contents of the event select register. 1615 */ 1616 evsel = ie->iap_evcode; 1617 1618 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 1619 1620 /* 1621 * If the event uses a fixed umask value, reject any umask 1622 * bits set by the user. 1623 */ 1624 if (ie->iap_flags & IAP_F_FM) { 1625 1626 if (IAP_UMASK(config) != 0) 1627 return (EINVAL); 1628 1629 evsel |= (ie->iap_umask << 8); 1630 1631 } else { 1632 1633 /* 1634 * Otherwise, the UMASK value needs to be taken from 1635 * the MD fields of the allocation request. Reject 1636 * requests that specify reserved bits. 1637 */ 1638 1639 mask = 0; 1640 1641 if (ie->iap_umask & IAP_M_CORE) { 1642 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 1643 c != IAP_CORE_THIS) 1644 return (EINVAL); 1645 mask |= IAP_F_CORE; 1646 } 1647 1648 if (ie->iap_umask & IAP_M_AGENT) 1649 mask |= IAP_F_AGENT; 1650 1651 if (ie->iap_umask & IAP_M_PREFETCH) { 1652 1653 if ((c = (config & IAP_F_PREFETCH)) == 1654 IAP_PREFETCH_RESERVED) 1655 return (EINVAL); 1656 1657 mask |= IAP_F_PREFETCH; 1658 } 1659 1660 if (ie->iap_umask & IAP_M_MESI) 1661 mask |= IAP_F_MESI; 1662 1663 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 1664 mask |= IAP_F_SNOOPRESPONSE; 1665 1666 if (ie->iap_umask & IAP_M_SNOOPTYPE) 1667 mask |= IAP_F_SNOOPTYPE; 1668 1669 if (ie->iap_umask & IAP_M_TRANSITION) 1670 mask |= IAP_F_TRANSITION; 1671 1672 /* 1673 * If bits outside of the allowed set of umask bits 1674 * are set, reject the request. 1675 */ 1676 if (config & ~mask) 1677 return (EINVAL); 1678 1679 evsel |= (config & mask); 1680 1681 } 1682 1683 /* 1684 * Only Atom CPUs support the 'ANY' qualifier. 1685 */ 1686 if (core_cputype == PMC_CPU_INTEL_ATOM) 1687 evsel |= (config & IAP_ANY); 1688 else if (config & IAP_ANY) 1689 return (EINVAL); 1690 1691 /* 1692 * Check offcore response configuration. 1693 */ 1694 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 1695 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 1696 ev != PMC_EV_IAP_EVENT_BBH_01H) 1697 return (EINVAL); 1698 if (core_cputype == PMC_CPU_INTEL_COREI7 && 1699 ev == PMC_EV_IAP_EVENT_BBH_01H) 1700 return (EINVAL); 1701 if ( a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK) 1702 return (EINVAL); 1703 pm->pm_md.pm_iap.pm_iap_rsp = 1704 a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK; 1705 } 1706 1707 if (caps & PMC_CAP_THRESHOLD) 1708 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 1709 if (caps & PMC_CAP_USER) 1710 evsel |= IAP_USR; 1711 if (caps & PMC_CAP_SYSTEM) 1712 evsel |= IAP_OS; 1713 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 1714 evsel |= (IAP_OS | IAP_USR); 1715 if (caps & PMC_CAP_EDGE) 1716 evsel |= IAP_EDGE; 1717 if (caps & PMC_CAP_INVERT) 1718 evsel |= IAP_INV; 1719 if (caps & PMC_CAP_INTERRUPT) 1720 evsel |= IAP_INT; 1721 1722 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 1723 1724 return (0); 1725} 1726 1727static int 1728iap_config_pmc(int cpu, int ri, struct pmc *pm) 1729{ 1730 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1731 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1732 1733 KASSERT(ri >= 0 && ri < core_iap_npmc, 1734 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1735 1736 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 1737 1738 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 1739 cpu)); 1740 1741 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 1742 1743 return (0); 1744} 1745 1746static int 1747iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 1748{ 1749 int error; 1750 struct pmc_hw *phw; 1751 char iap_name[PMC_NAME_MAX]; 1752 1753 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 1754 1755 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 1756 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 1757 NULL)) != 0) 1758 return (error); 1759 1760 pi->pm_class = PMC_CLASS_IAP; 1761 1762 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 1763 pi->pm_enabled = TRUE; 1764 *ppmc = phw->phw_pmc; 1765 } else { 1766 pi->pm_enabled = FALSE; 1767 *ppmc = NULL; 1768 } 1769 1770 return (0); 1771} 1772 1773static int 1774iap_get_config(int cpu, int ri, struct pmc **ppm) 1775{ 1776 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1777 1778 return (0); 1779} 1780 1781static int 1782iap_get_msr(int ri, uint32_t *msr) 1783{ 1784 KASSERT(ri >= 0 && ri < core_iap_npmc, 1785 ("[iap,%d] ri %d out of range", __LINE__, ri)); 1786 1787 *msr = ri; 1788 1789 return (0); 1790} 1791 1792static int 1793iap_read_pmc(int cpu, int ri, pmc_value_t *v) 1794{ 1795 struct pmc *pm; 1796 pmc_value_t tmp; 1797 1798 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1799 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1800 KASSERT(ri >= 0 && ri < core_iap_npmc, 1801 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1802 1803 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1804 1805 KASSERT(pm, 1806 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 1807 ri)); 1808 1809 tmp = rdpmc(ri); 1810 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1811 *v = iap_perfctr_value_to_reload_count(tmp); 1812 else 1813 *v = tmp; 1814 1815 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 1816 ri, *v); 1817 1818 return (0); 1819} 1820 1821static int 1822iap_release_pmc(int cpu, int ri, struct pmc *pm) 1823{ 1824 (void) pm; 1825 1826 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 1827 pm); 1828 1829 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1830 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1831 KASSERT(ri >= 0 && ri < core_iap_npmc, 1832 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1833 1834 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 1835 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 1836 1837 return (0); 1838} 1839 1840static int 1841iap_start_pmc(int cpu, int ri) 1842{ 1843 struct pmc *pm; 1844 uint32_t evsel; 1845 struct core_cpu *cc; 1846 1847 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1848 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1849 KASSERT(ri >= 0 && ri < core_iap_npmc, 1850 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1851 1852 cc = core_pcpu[cpu]; 1853 pm = cc->pc_corepmcs[ri].phw_pmc; 1854 1855 KASSERT(pm, 1856 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 1857 __LINE__, cpu, ri)); 1858 1859 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 1860 1861 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 1862 1863 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 1864 cpu, ri, IAP_EVSEL0 + ri, evsel); 1865 1866 /* Event specific configuration. */ 1867 switch (pm->pm_event) { 1868 case PMC_EV_IAP_EVENT_B7H_01H: 1869 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 1870 break; 1871 case PMC_EV_IAP_EVENT_BBH_01H: 1872 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 1873 break; 1874 default: 1875 break; 1876 } 1877 1878 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 1879 1880 if (core_cputype == PMC_CPU_INTEL_CORE) 1881 return (0); 1882 1883 do { 1884 cc->pc_resync = 0; 1885 cc->pc_globalctrl |= (1ULL << ri); 1886 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1887 } while (cc->pc_resync != 0); 1888 1889 return (0); 1890} 1891 1892static int 1893iap_stop_pmc(int cpu, int ri) 1894{ 1895 struct pmc *pm; 1896 struct core_cpu *cc; 1897 uint64_t msr; 1898 1899 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1900 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1901 KASSERT(ri >= 0 && ri < core_iap_npmc, 1902 ("[core,%d] illegal row index %d", __LINE__, ri)); 1903 1904 cc = core_pcpu[cpu]; 1905 pm = cc->pc_corepmcs[ri].phw_pmc; 1906 1907 KASSERT(pm, 1908 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1909 cpu, ri)); 1910 1911 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 1912 1913 msr = rdmsr(IAP_EVSEL0 + ri); 1914 wrmsr(IAP_EVSEL0 + ri, msr & IAP_EVSEL_MASK); /* stop hw */ 1915 1916 if (core_cputype == PMC_CPU_INTEL_CORE) 1917 return (0); 1918 1919 do { 1920 cc->pc_resync = 0; 1921 cc->pc_globalctrl &= ~(1ULL << ri); 1922 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1923 } while (cc->pc_resync != 0); 1924 1925 return (0); 1926} 1927 1928static int 1929iap_write_pmc(int cpu, int ri, pmc_value_t v) 1930{ 1931 struct pmc *pm; 1932 struct core_cpu *cc; 1933 1934 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1935 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1936 KASSERT(ri >= 0 && ri < core_iap_npmc, 1937 ("[core,%d] illegal row index %d", __LINE__, ri)); 1938 1939 cc = core_pcpu[cpu]; 1940 pm = cc->pc_corepmcs[ri].phw_pmc; 1941 1942 KASSERT(pm, 1943 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1944 cpu, ri)); 1945 1946 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1947 IAP_PMC0 + ri, v); 1948 1949 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1950 v = iap_reload_count_to_perfctr_value(v); 1951 1952 /* 1953 * Write the new value to the counter. The counter will be in 1954 * a stopped state when the pcd_write() entry point is called. 1955 */ 1956 1957 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 1958 1959 return (0); 1960} 1961 1962 1963static void 1964iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 1965 int flags) 1966{ 1967 struct pmc_classdep *pcd; 1968 1969 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 1970 1971 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 1972 1973 /* Remember the set of architectural events supported. */ 1974 core_architectural_events = ~flags; 1975 1976 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 1977 1978 pcd->pcd_caps = IAP_PMC_CAPS; 1979 pcd->pcd_class = PMC_CLASS_IAP; 1980 pcd->pcd_num = npmc; 1981 pcd->pcd_ri = md->pmd_npmc; 1982 pcd->pcd_width = pmcwidth; 1983 1984 pcd->pcd_allocate_pmc = iap_allocate_pmc; 1985 pcd->pcd_config_pmc = iap_config_pmc; 1986 pcd->pcd_describe = iap_describe; 1987 pcd->pcd_get_config = iap_get_config; 1988 pcd->pcd_get_msr = iap_get_msr; 1989 pcd->pcd_pcpu_fini = core_pcpu_fini; 1990 pcd->pcd_pcpu_init = core_pcpu_init; 1991 pcd->pcd_read_pmc = iap_read_pmc; 1992 pcd->pcd_release_pmc = iap_release_pmc; 1993 pcd->pcd_start_pmc = iap_start_pmc; 1994 pcd->pcd_stop_pmc = iap_stop_pmc; 1995 pcd->pcd_write_pmc = iap_write_pmc; 1996 1997 md->pmd_npmc += npmc; 1998} 1999 2000static int 2001core_intr(int cpu, struct trapframe *tf) 2002{ 2003 pmc_value_t v; 2004 struct pmc *pm; 2005 struct core_cpu *cc; 2006 int error, found_interrupt, ri; 2007 uint64_t msr = 0; 2008 2009 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2010 TRAPF_USERMODE(tf)); 2011 2012 found_interrupt = 0; 2013 cc = core_pcpu[cpu]; 2014 2015 for (ri = 0; ri < core_iap_npmc; ri++) { 2016 2017 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2018 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2019 continue; 2020 2021 if (!iap_pmc_has_overflowed(ri)) 2022 continue; 2023 2024 found_interrupt = 1; 2025 2026 if (pm->pm_state != PMC_STATE_RUNNING) 2027 continue; 2028 2029 error = pmc_process_interrupt(cpu, pm, tf, 2030 TRAPF_USERMODE(tf)); 2031 2032 v = pm->pm_sc.pm_reloadcount; 2033 v = iaf_reload_count_to_perfctr_value(v); 2034 2035 /* 2036 * Stop the counter, reload it but only restart it if 2037 * the PMC is not stalled. 2038 */ 2039 msr = rdmsr(IAP_EVSEL0 + ri); 2040 wrmsr(IAP_EVSEL0 + ri, msr & ~IAP_EVSEL_MASK); 2041 wrmsr(IAP_PMC0 + ri, v); 2042 2043 if (error) 2044 continue; 2045 2046 wrmsr(IAP_EVSEL0 + ri, 2047 pm->pm_md.pm_iap.pm_iap_evsel | IAP_EN); 2048 } 2049 2050 if (found_interrupt) 2051 lapic_reenable_pmc(); 2052 2053 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2054 &pmc_stats.pm_intr_ignored, 1); 2055 2056 return (found_interrupt); 2057} 2058 2059static int 2060core2_intr(int cpu, struct trapframe *tf) 2061{ 2062 int error, found_interrupt, n; 2063 uint64_t flag, intrstatus, intrenable; 2064 struct pmc *pm; 2065 struct core_cpu *cc; 2066 pmc_value_t v; 2067 2068 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2069 TRAPF_USERMODE(tf)); 2070 2071 /* 2072 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2073 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2074 * the current set of interrupting PMCs and process these 2075 * after stopping them. 2076 */ 2077 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2078 intrenable = intrstatus & core_pmcmask; 2079 2080 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2081 (uintmax_t) intrstatus); 2082 2083 found_interrupt = 0; 2084 cc = core_pcpu[cpu]; 2085 2086 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2087 2088 cc->pc_globalctrl &= ~intrenable; 2089 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2090 2091 /* 2092 * Stop PMCs and clear overflow status bits. 2093 */ 2094 wrmsr(IA_GLOBAL_CTRL, 0); 2095 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2096 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2097 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2098 2099 /* 2100 * Look for interrupts from fixed function PMCs. 2101 */ 2102 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2103 n++, flag <<= 1) { 2104 2105 if ((intrstatus & flag) == 0) 2106 continue; 2107 2108 found_interrupt = 1; 2109 2110 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2111 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2112 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2113 continue; 2114 2115 error = pmc_process_interrupt(cpu, pm, tf, 2116 TRAPF_USERMODE(tf)); 2117 if (error) 2118 intrenable &= ~flag; 2119 2120 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2121 2122 /* Reload sampling count. */ 2123 wrmsr(IAF_CTR0 + n, v); 2124 2125 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 2126 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2127 } 2128 2129 /* 2130 * Process interrupts from the programmable counters. 2131 */ 2132 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2133 if ((intrstatus & flag) == 0) 2134 continue; 2135 2136 found_interrupt = 1; 2137 2138 pm = cc->pc_corepmcs[n].phw_pmc; 2139 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2140 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2141 continue; 2142 2143 error = pmc_process_interrupt(cpu, pm, tf, 2144 TRAPF_USERMODE(tf)); 2145 if (error) 2146 intrenable &= ~flag; 2147 2148 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2149 2150 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2151 (uintmax_t) v); 2152 2153 /* Reload sampling count. */ 2154 wrmsr(IAP_PMC0 + n, v); 2155 } 2156 2157 /* 2158 * Reenable all non-stalled PMCs. 2159 */ 2160 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2161 (uintmax_t) intrenable); 2162 2163 cc->pc_globalctrl |= intrenable; 2164 2165 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2166 2167 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2168 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2169 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2170 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2171 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2172 2173 if (found_interrupt) 2174 lapic_reenable_pmc(); 2175 2176 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2177 &pmc_stats.pm_intr_ignored, 1); 2178 2179 return (found_interrupt); 2180} 2181 2182int 2183pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 2184{ 2185 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2186 int ipa_version, flags, nflags; 2187 2188 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2189 2190 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 2191 2192 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2193 md->pmd_cputype, maxcpu, ipa_version); 2194 2195 if (ipa_version < 1 || ipa_version > 3) /* Unknown PMC architecture. */ 2196 return (EPROGMISMATCH); 2197 2198 core_cputype = md->pmd_cputype; 2199 2200 core_pmcmask = 0; 2201 2202 /* 2203 * Initialize programmable counters. 2204 */ 2205 KASSERT(ipa_version >= 1, 2206 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 2207 2208 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2209 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2210 2211 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2212 2213 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2214 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2215 2216 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2217 2218 /* 2219 * Initialize fixed function counters, if present. 2220 */ 2221 if (core_cputype != PMC_CPU_INTEL_CORE) { 2222 KASSERT(ipa_version >= 2, 2223 ("[core,%d] ipa_version %d too small", __LINE__, 2224 ipa_version)); 2225 2226 core_iaf_ri = core_iap_npmc; 2227 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2228 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2229 2230 if (core_iaf_npmc > 0) { 2231 iaf_initialize(md, maxcpu, core_iaf_npmc, 2232 core_iaf_width); 2233 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << 2234 IAF_OFFSET; 2235 } else { 2236 /* 2237 * Adjust the number of classes exported to 2238 * user space. 2239 */ 2240 md->pmd_nclass--; 2241 KASSERT(md->pmd_nclass == 2, 2242 ("[core,%d] unexpected nclass %d", __LINE__, 2243 md->pmd_nclass)); 2244 } 2245 } 2246 2247 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2248 core_iaf_ri); 2249 2250 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 2251 M_ZERO | M_WAITOK); 2252 2253 /* 2254 * Choose the appropriate interrupt handler. 2255 */ 2256 if (ipa_version == 1) 2257 md->pmd_intr = core_intr; 2258 else 2259 md->pmd_intr = core2_intr; 2260 2261 md->pmd_pcpu_fini = NULL; 2262 md->pmd_pcpu_init = NULL; 2263 2264 return (0); 2265} 2266 2267void 2268pmc_core_finalize(struct pmc_mdep *md) 2269{ 2270 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2271 2272 free(core_pcpu, M_PMC); 2273 core_pcpu = NULL; 2274} 2275