hwpmc_core.c revision 187761
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_core.c 187761 2009-01-27 07:29:37Z jeff $"); 33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cpufunc.h> 41#include <machine/specialreg.h> 42 43#define CORE_CPUID_REQUEST 0xA 44#define CORE_CPUID_REQUEST_SIZE 0x4 45#define CORE_CPUID_EAX 0x0 46#define CORE_CPUID_EBX 0x1 47#define CORE_CPUID_ECX 0x2 48#define CORE_CPUID_EDX 0x3 49 50#define IAF_PMC_CAPS \ 51 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT) 52#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 53 54#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 55 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 56 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 57 58/* 59 * "Architectural" events defined by Intel. The values of these 60 * symbols correspond to positions in the bitmask returned by 61 * the CPUID.0AH instruction. 62 */ 63enum core_arch_events { 64 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 65 CORE_AE_BRANCH_MISSES_RETIRED = 6, 66 CORE_AE_INSTRUCTION_RETIRED = 1, 67 CORE_AE_LLC_MISSES = 4, 68 CORE_AE_LLC_REFERENCE = 3, 69 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 70 CORE_AE_UNHALTED_CORE_CYCLES = 0 71}; 72 73static enum pmc_cputype core_cputype; 74 75struct core_cpu { 76 volatile uint32_t pc_resync; 77 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 78 volatile uint64_t pc_globalctrl; /* Global control register. */ 79 struct pmc_hw pc_corepmcs[]; 80}; 81 82static struct core_cpu **core_pcpu; 83 84static uint32_t core_architectural_events; 85static uint64_t core_pmcmask; 86 87static int core_iaf_ri; /* relative index of fixed counters */ 88static int core_iaf_width; 89static int core_iaf_npmc; 90 91static int core_iap_width; 92static int core_iap_npmc; 93 94static int 95core_pcpu_noop(struct pmc_mdep *md, int cpu) 96{ 97 (void) md; 98 (void) cpu; 99 return (0); 100} 101 102static int 103core_pcpu_init(struct pmc_mdep *md, int cpu) 104{ 105 struct pmc_cpu *pc; 106 struct core_cpu *cc; 107 struct pmc_hw *phw; 108 int core_ri, n, npmc; 109 110 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 111 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 112 113 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 114 115 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 116 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 117 118 if (core_cputype != PMC_CPU_INTEL_CORE) 119 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 120 121 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 122 M_PMC, M_WAITOK | M_ZERO); 123 124 core_pcpu[cpu] = cc; 125 pc = pmc_pcpu[cpu]; 126 127 KASSERT(pc != NULL && cc != NULL, 128 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 129 130 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 131 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 132 PMC_PHW_CPU_TO_STATE(cpu) | 133 PMC_PHW_INDEX_TO_STATE(n + core_ri); 134 phw->phw_pmc = NULL; 135 pc->pc_hwpmcs[n + core_ri] = phw; 136 } 137 138 return (0); 139} 140 141static int 142core_pcpu_fini(struct pmc_mdep *md, int cpu) 143{ 144 int core_ri, n, npmc; 145 struct pmc_cpu *pc; 146 struct core_cpu *cc; 147 148 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 149 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 150 151 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 152 153 if ((cc = core_pcpu[cpu]) == NULL) 154 return (0); 155 156 core_pcpu[cpu] = NULL; 157 158 pc = pmc_pcpu[cpu]; 159 160 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 161 cpu)); 162 163 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 164 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 165 166 for (n = 0; n < npmc; n++) 167 wrmsr(IAP_EVSEL0 + n, 0); 168 169 if (core_cputype != PMC_CPU_INTEL_CORE) { 170 wrmsr(IAF_CTRL, 0); 171 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 172 } 173 174 for (n = 0; n < npmc; n++) 175 pc->pc_hwpmcs[n + core_ri] = NULL; 176 177 free(cc, M_PMC); 178 179 return (0); 180} 181 182/* 183 * Fixed function counters. 184 */ 185 186static pmc_value_t 187iaf_perfctr_value_to_reload_count(pmc_value_t v) 188{ 189 v &= (1ULL << core_iaf_width) - 1; 190 return (1ULL << core_iaf_width) - v; 191} 192 193static pmc_value_t 194iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 195{ 196 return (1ULL << core_iaf_width) - rlc; 197} 198 199static int 200iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 201 const struct pmc_op_pmcallocate *a) 202{ 203 enum pmc_event ev; 204 uint32_t caps, flags, validflags; 205 206 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 207 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 208 209 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 210 211 if (ri < 0 || ri > core_iaf_npmc) 212 return (EINVAL); 213 214 caps = a->pm_caps; 215 216 if (a->pm_class != PMC_CLASS_IAF || 217 (caps & IAF_PMC_CAPS) != caps) 218 return (EINVAL); 219 220 ev = pm->pm_event; 221 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 222 return (EINVAL); 223 224 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 225 return (EINVAL); 226 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 227 return (EINVAL); 228 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 229 return (EINVAL); 230 231 flags = a->pm_md.pm_iaf.pm_iaf_flags; 232 233 validflags = IAF_MASK; 234 235 if (core_cputype != PMC_CPU_INTEL_ATOM) 236 validflags &= ~IAF_ANY; 237 238 if ((flags & ~validflags) != 0) 239 return (EINVAL); 240 241 if (caps & PMC_CAP_INTERRUPT) 242 flags |= IAF_PMI; 243 if (caps & PMC_CAP_SYSTEM) 244 flags |= IAF_OS; 245 if (caps & PMC_CAP_USER) 246 flags |= IAF_USR; 247 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 248 flags |= (IAF_OS | IAF_USR); 249 250 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 251 252 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 253 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 254 255 return (0); 256} 257 258static int 259iaf_config_pmc(int cpu, int ri, struct pmc *pm) 260{ 261 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 262 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 263 264 KASSERT(ri >= 0 && ri < core_iaf_npmc, 265 ("[core,%d] illegal row-index %d", __LINE__, ri)); 266 267 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 268 269 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 270 cpu)); 271 272 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 273 274 return (0); 275} 276 277static int 278iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 279{ 280 int error; 281 struct pmc_hw *phw; 282 char iaf_name[PMC_NAME_MAX]; 283 284 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 285 286 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 287 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 288 NULL)) != 0) 289 return (error); 290 291 pi->pm_class = PMC_CLASS_IAF; 292 293 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 294 pi->pm_enabled = TRUE; 295 *ppmc = phw->phw_pmc; 296 } else { 297 pi->pm_enabled = FALSE; 298 *ppmc = NULL; 299 } 300 301 return (0); 302} 303 304static int 305iaf_get_config(int cpu, int ri, struct pmc **ppm) 306{ 307 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 308 309 return (0); 310} 311 312static int 313iaf_get_msr(int ri, uint32_t *msr) 314{ 315 KASSERT(ri >= 0 && ri < core_iaf_npmc, 316 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 317 318 *msr = IAF_RI_TO_MSR(ri); 319 320 return (0); 321} 322 323static int 324iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 325{ 326 struct pmc *pm; 327 pmc_value_t tmp; 328 329 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 330 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 331 KASSERT(ri >= 0 && ri < core_iaf_npmc, 332 ("[core,%d] illegal row-index %d", __LINE__, ri)); 333 334 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 335 336 KASSERT(pm, 337 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 338 ri, ri + core_iaf_ri)); 339 340 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 341 342 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 343 *v = iaf_perfctr_value_to_reload_count(tmp); 344 else 345 *v = tmp; 346 347 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 348 IAF_RI_TO_MSR(ri), *v); 349 350 return (0); 351} 352 353static int 354iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 355{ 356 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 357 358 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 359 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 360 KASSERT(ri >= 0 && ri < core_iaf_npmc, 361 ("[core,%d] illegal row-index %d", __LINE__, ri)); 362 363 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 364 ("[core,%d] PHW pmc non-NULL", __LINE__)); 365 366 return (0); 367} 368 369static int 370iaf_start_pmc(int cpu, int ri) 371{ 372 struct pmc *pm; 373 struct core_cpu *iafc; 374 375 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 376 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 377 KASSERT(ri >= 0 && ri < core_iaf_npmc, 378 ("[core,%d] illegal row-index %d", __LINE__, ri)); 379 380 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 381 382 iafc = core_pcpu[cpu]; 383 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 384 385 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 386 387 wrmsr(IAF_CTRL, iafc->pc_iafctrl); 388 389 do { 390 iafc->pc_resync = 0; 391 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 392 wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl); 393 } while (iafc->pc_resync != 0); 394 395 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 396 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 397 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 398 399 return (0); 400} 401 402static int 403iaf_stop_pmc(int cpu, int ri) 404{ 405 uint32_t fc; 406 struct core_cpu *iafc; 407 408 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 409 410 iafc = core_pcpu[cpu]; 411 412 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 413 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 414 KASSERT(ri >= 0 && ri < core_iaf_npmc, 415 ("[core,%d] illegal row-index %d", __LINE__, ri)); 416 417 fc = (IAF_MASK << (ri * 4)); 418 419 if (core_cputype != PMC_CPU_INTEL_ATOM) 420 fc &= ~IAF_ANY; 421 422 iafc->pc_iafctrl &= ~fc; 423 424 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 425 wrmsr(IAF_CTRL, iafc->pc_iafctrl); 426 427 do { 428 iafc->pc_resync = 0; 429 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 430 wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl); 431 } while (iafc->pc_resync != 0); 432 433 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 434 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 435 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 436 437 return (0); 438} 439 440static int 441iaf_write_pmc(int cpu, int ri, pmc_value_t v) 442{ 443 struct core_cpu *cc; 444 struct pmc *pm; 445 446 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 447 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 448 KASSERT(ri >= 0 && ri < core_iaf_npmc, 449 ("[core,%d] illegal row-index %d", __LINE__, ri)); 450 451 cc = core_pcpu[cpu]; 452 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 453 454 KASSERT(pm, 455 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 456 457 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 458 v = iaf_reload_count_to_perfctr_value(v); 459 460 wrmsr(IAF_CTRL, 0); /* Turn off fixed counters */ 461 wrmsr(IAF_CTR0 + ri, v); 462 wrmsr(IAF_CTRL, cc->pc_iafctrl); 463 464 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 465 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 466 (uintmax_t) rdmsr(IAF_CTRL), 467 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 468 469 return (0); 470} 471 472 473static void 474iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 475{ 476 struct pmc_classdep *pcd; 477 478 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 479 480 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 481 482 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 483 484 pcd->pcd_caps = IAF_PMC_CAPS; 485 pcd->pcd_class = PMC_CLASS_IAF; 486 pcd->pcd_num = npmc; 487 pcd->pcd_ri = md->pmd_npmc; 488 pcd->pcd_width = pmcwidth; 489 490 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 491 pcd->pcd_config_pmc = iaf_config_pmc; 492 pcd->pcd_describe = iaf_describe; 493 pcd->pcd_get_config = iaf_get_config; 494 pcd->pcd_get_msr = iaf_get_msr; 495 pcd->pcd_pcpu_fini = core_pcpu_noop; 496 pcd->pcd_pcpu_init = core_pcpu_noop; 497 pcd->pcd_read_pmc = iaf_read_pmc; 498 pcd->pcd_release_pmc = iaf_release_pmc; 499 pcd->pcd_start_pmc = iaf_start_pmc; 500 pcd->pcd_stop_pmc = iaf_stop_pmc; 501 pcd->pcd_write_pmc = iaf_write_pmc; 502 503 md->pmd_npmc += npmc; 504} 505 506/* 507 * Intel programmable PMCs. 508 */ 509 510/* 511 * Event descriptor tables. 512 * 513 * For each event id, we track: 514 * 515 * 1. The CPUs that the event is valid for. 516 * 517 * 2. If the event uses a fixed UMASK, the value of the umask field. 518 * If the event doesn't use a fixed UMASK, a mask of legal bits 519 * to check against. 520 */ 521 522struct iap_event_descr { 523 enum pmc_event iap_ev; 524 unsigned char iap_evcode; 525 unsigned char iap_umask; 526 unsigned char iap_flags; 527}; 528 529#define IAP_F_CC (1 << 0) /* CPU: Core */ 530#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 531#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 532#define IAP_F_CA (1 << 3) /* CPU: Atom */ 533#define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 534#define IAP_F_FM (1 << 5) /* Fixed mask */ 535 536#define IAP_F_ALLCPUS \ 537 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA | IAP_F_I7) 538 539/* Sub fields of UMASK that this event supports. */ 540#define IAP_M_CORE (1 << 0) /* Core specificity */ 541#define IAP_M_AGENT (1 << 1) /* Agent specificity */ 542#define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 543#define IAP_M_MESI (1 << 3) /* MESI */ 544#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 545#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 546#define IAP_M_TRANSITION (1 << 6) /* Transition */ 547 548#define IAP_F_CORE (0x3 << 14) /* Core specificity */ 549#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 550#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 551#define IAP_F_MESI (0xF << 8) /* MESI */ 552#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 553#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 554#define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 555 556#define IAP_PREFETCH_RESERVED (0x2 << 12) 557#define IAP_CORE_THIS (0x1 << 14) 558#define IAP_CORE_ALL (0x3 << 14) 559#define IAP_F_CMASK 0xFF000000 560 561static struct iap_event_descr iap_events[] = { 562#undef IAPDESCR 563#define IAPDESCR(N,EV,UM,FLAGS) { \ 564 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 565 .iap_evcode = (EV), \ 566 .iap_umask = (UM), \ 567 .iap_flags = (FLAGS) \ 568 } 569 570 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 571 572 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 573 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 574 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 575 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 576 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 577 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 578 579 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 580 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 581 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 582 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 583 584 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 585 586 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 587 588 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 589 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 590 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUS), 591 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUS), 592 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 593 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA), 594 595 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 596 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 597 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 598 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 599 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 600 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 601 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 602 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 603 604 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 605 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 606 607 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7), 608 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 609 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 610 611 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 612 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7), 613 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 614 615 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 616 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA), 617 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 618 619 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 620 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7), 621 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 622 623 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 624 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7), 625 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 626 627 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 628 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7), 629 630 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 631 632 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 633 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 634 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 635 636 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUS), 637 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 638 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUS), 639 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUS), 640 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUS), 641 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUS), 642 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUS), 643 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUS), 644 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 645 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 646 IAP_F_CA | IAP_F_CC2), 647 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUS), 648 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 649 650 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 651 IAP_F_ALLCPUS), 652 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUS), 653 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUS), 654 655 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 656 IAP_F_ALLCPUS), 657 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 658 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 659 660 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 661 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 662 663 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUS), 664 665 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 666 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 667 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUS), 668 669 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC), 670 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 671 672 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 673 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 674 675 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUS), 676 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 677 678 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 679 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 680 681 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 682 683 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUS), 684 685 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 686 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 687 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 688 689 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 690 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 691 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 692 693 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 694 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 695 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUS), 696 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 697 698 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 699 700 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 701 702 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 703 704 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 705 706 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 707 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 708 709 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUS), 710 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 711 712 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 713 IAP_F_CA | IAP_F_CC2), 714 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 715 716 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 717 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 718 719 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 720 IAP_F_CA | IAP_F_CC2), 721 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 722 723 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 724 725 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 726 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 727 728 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 729 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 730 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 731 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 732 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 733 734 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 735 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 736 737 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 738 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 739 740 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 741 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 742 743 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 744 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 745 746 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 747 IAP_F_CA | IAP_F_CC2), 748 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 749 750 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 751 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 752 753 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 754 755 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 756 757 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUS), 758 759 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 760 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 761 762 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 763 764 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 765 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7), 766 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7), 767 768 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 769 770 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 771 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 772 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 773 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 774 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 775 776 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 777 778 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 779 780 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 781 782 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 783 784 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 785 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 786 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 787 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 788 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 789 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 790 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 791 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 792 793 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 794 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 795 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 796 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 797 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 798 799 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 800 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 801 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 802 803 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 804 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 805 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 806 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 807 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 808 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 809 810 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 811 812 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 813 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 814 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 815 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 816 817 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 818 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 819 820 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 821 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7), 822 823 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 824 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7), 825 826 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 827 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUS), 828 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUS), 829 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUS), 830 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUS), 831 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUS), 832 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 833 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 834 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 835 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 836 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 837 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 838 839 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 840 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 841 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 842 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 843 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 844 845 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 846 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 847 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 848 849 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 850 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 851 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 852 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 853 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 854 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 855 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 856 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 857 858 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 859 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 860 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 861 862 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 863 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 864 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 865 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 866 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 867 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 868 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 869 870 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 871 872 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 873 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 874 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 875 876 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 877 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 878 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 879 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 880 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 881 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 882 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 883 884 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 885 886 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 887 888 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 889 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 890 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 891 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 892 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 893 894 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 895 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 896 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 897 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 898 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7), 899 900 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 901 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 902 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 903 904 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 905 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 906 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 907 908 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 909 910 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 911 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 912 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 913 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 914 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 915 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 916 917 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 918 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 919 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 920 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 921 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 922 923 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), 924 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 925 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 926 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 927 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 928 929 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 930 931 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 932 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 933 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 934 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 935 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 936 937 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 938 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 939 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 940 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 941 942 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 943 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 944 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 945 946 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 947 948 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 949 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 950 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 951 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 952 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 953 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 954 955 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 956 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7), 957 958 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 959 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 960 961 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 962 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA), 963 964 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 965 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 966 967 /* Added with nehalem. */ 968 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7), 969 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7), 970 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7), 971 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7), 972 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7), 973 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7), 974 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7), 975 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7), 976 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7), 977 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7), 978 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7), 979 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7), 980 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7), 981 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), 982 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7), 983 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7), 984 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7), 985 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7), 986 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7), 987 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7), 988 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7), 989 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7), 990 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7), 991 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7), 992 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7), 993 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7), 994 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7), 995 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7), 996 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7), 997 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7), 998 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7), 999 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7), 1000 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7), 1001 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7), 1002 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7), 1003 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7), 1004 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7), 1005 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7), 1006 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7), 1007 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7), 1008 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7), 1009 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7), 1010 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7), 1011 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7), 1012 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7), 1013 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7), 1014 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7), 1015 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7), 1016 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7), 1017 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7), 1018 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7), 1019 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7), 1020 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7), 1021 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7), 1022 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7), 1023 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7), 1024 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7), 1025 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7), 1026 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7), 1027 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7), 1028 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7), 1029 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7), 1030 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7), 1031 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7), 1032 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7), 1033 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7), 1034 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7), 1035 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7), 1036 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7), 1037 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7), 1038 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7), 1039 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7), 1040 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7), 1041 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7), 1042 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7), 1043 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7), 1044 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7), 1045 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7), 1046 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7), 1047 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7), 1048 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7), 1049 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7), 1050 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7), 1051 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7), 1052 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7), 1053 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7), 1054 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7), 1055 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7), 1056 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7), 1057 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7), 1058 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 1059 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 1060 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 1061 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 1062 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 1063 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7), 1064 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 1065 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 1066 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 1067 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7), 1068 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 1069 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 1070 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 1071 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 1072 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7), 1073 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7), 1074 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7), 1075 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7), 1076 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_I7), 1077 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7), 1078 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7), 1079 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7), 1080 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7), 1081 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7), 1082 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7), 1083 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7), 1084 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7), 1085 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7), 1086 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7), 1087 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7), 1088 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7), 1089 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7), 1090 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7), 1091 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7), 1092 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_I7), 1093 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_I7), 1094 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_I7), 1095 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_I7), 1096 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7), 1097 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7), 1098 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7), 1099 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7), 1100 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7), 1101 IAPDESCR(80H_10H, 0x80, 0x10, IAP_F_FM | IAP_F_I7), 1102 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7), 1103 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7), 1104 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7), 1105 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7), 1106 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7), 1107 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7), 1108 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_I7), 1109 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7), 1110 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7), 1111 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7), 1112 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_I7), 1113 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7), 1114 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7), 1115 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7), 1116 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7), 1117 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7), 1118 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7), 1119 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7), 1120 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7), 1121 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7), 1122 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7), 1123 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7), 1124 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7), 1125 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7), 1126 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7), 1127 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7), 1128 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7), 1129 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7), 1130 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7), 1131 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7), 1132 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7), 1133 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7), 1134 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7), 1135 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7), 1136 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7), 1137 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7), 1138 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7), 1139 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7), 1140 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7), 1141 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7), 1142 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7), 1143 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7), 1144 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7), 1145 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7), 1146 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7), 1147 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7), 1148 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_I7), 1149 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_I7), 1150 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_I7), 1151 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_I7), 1152 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7), 1153 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7), 1154 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7), 1155 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7), 1156 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7), 1157 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7), 1158 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7), 1159 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7), 1160 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7), 1161 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7), 1162 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7), 1163 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7), 1164 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7), 1165 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7), 1166 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7), 1167 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7), 1168 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7), 1169 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7), 1170 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7), 1171 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7), 1172 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7), 1173 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7), 1174 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7), 1175 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7), 1176 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7), 1177 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7), 1178 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7), 1179 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7), 1180 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7), 1181 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7), 1182 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7), 1183 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7), 1184 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7), 1185 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7), 1186 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7), 1187 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7), 1188 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_I7), 1189 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7), 1190 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7), 1191 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7), 1192 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_I7), 1193 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_I7), 1194 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_I7), 1195 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7), 1196 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_I7), 1197 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_I7), 1198 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_I7), 1199 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_I7), 1200 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_I7), 1201 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_I7), 1202 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_I7), 1203}; 1204 1205static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1206 1207static pmc_value_t 1208iap_perfctr_value_to_reload_count(pmc_value_t v) 1209{ 1210 v &= (1ULL << core_iap_width) - 1; 1211 return (1ULL << core_iap_width) - v; 1212} 1213 1214static pmc_value_t 1215iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1216{ 1217 return (1ULL << core_iap_width) - rlc; 1218} 1219 1220static int 1221iap_pmc_has_overflowed(int ri) 1222{ 1223 uint64_t v; 1224 1225 /* 1226 * We treat a Core (i.e., Intel architecture v1) PMC as has 1227 * having overflowed if its MSB is zero. 1228 */ 1229 v = rdpmc(ri); 1230 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1231} 1232 1233/* 1234 * Check an event against the set of supported architectural events. 1235 * 1236 * Returns 1 if the event is architectural and unsupported on this 1237 * CPU. Returns 0 otherwise. 1238 */ 1239 1240static int 1241iap_architectural_event_is_unsupported(enum pmc_event pe) 1242{ 1243 enum core_arch_events ae; 1244 1245 switch (pe) { 1246 case PMC_EV_IAP_EVENT_3CH_00H: 1247 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1248 break; 1249 case PMC_EV_IAP_EVENT_C0H_00H: 1250 ae = CORE_AE_INSTRUCTION_RETIRED; 1251 break; 1252 case PMC_EV_IAP_EVENT_3CH_01H: 1253 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1254 break; 1255 case PMC_EV_IAP_EVENT_2EH_4FH: 1256 ae = CORE_AE_LLC_REFERENCE; 1257 break; 1258 case PMC_EV_IAP_EVENT_2EH_41H: 1259 ae = CORE_AE_LLC_MISSES; 1260 break; 1261 case PMC_EV_IAP_EVENT_C4H_00H: 1262 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1263 break; 1264 case PMC_EV_IAP_EVENT_C5H_00H: 1265 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1266 break; 1267 1268 default: /* Non architectural event. */ 1269 return (0); 1270 } 1271 1272 return ((core_architectural_events & (1 << ae)) == 0); 1273} 1274 1275static int 1276iap_event_ok_on_counter(enum pmc_event pe, int ri) 1277{ 1278 uint32_t mask; 1279 1280 switch (pe) { 1281 /* 1282 * Events valid only on counter 0. 1283 */ 1284 case PMC_EV_IAP_EVENT_10H_00H: 1285 case PMC_EV_IAP_EVENT_14H_00H: 1286 case PMC_EV_IAP_EVENT_18H_00H: 1287 case PMC_EV_IAP_EVENT_C1H_00H: 1288 case PMC_EV_IAP_EVENT_CBH_01H: 1289 case PMC_EV_IAP_EVENT_CBH_02H: 1290 mask = (1 << 0); 1291 break; 1292 1293 /* 1294 * Events valid only on counter 1. 1295 */ 1296 case PMC_EV_IAP_EVENT_11H_00H: 1297 case PMC_EV_IAP_EVENT_12H_00H: 1298 case PMC_EV_IAP_EVENT_13H_00H: 1299 mask = (1 << 1); 1300 break; 1301 1302 default: 1303 mask = ~0; /* Any row index is ok. */ 1304 } 1305 1306 return (mask & (1 << ri)); 1307} 1308 1309static int 1310iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1311 const struct pmc_op_pmcallocate *a) 1312{ 1313 int n; 1314 enum pmc_event ev; 1315 struct iap_event_descr *ie; 1316 uint32_t c, caps, config, cpuflag, evsel, mask; 1317 1318 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1319 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1320 KASSERT(ri >= 0 && ri < core_iap_npmc, 1321 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1322 1323 /* check requested capabilities */ 1324 caps = a->pm_caps; 1325 if ((IAP_PMC_CAPS & caps) != caps) 1326 return (EPERM); 1327 1328 ev = pm->pm_event; 1329 1330 if (iap_architectural_event_is_unsupported(ev)) 1331 return (EOPNOTSUPP); 1332 1333 if (iap_event_ok_on_counter(ev, ri) == 0) 1334 return (EINVAL); 1335 1336 /* 1337 * Look for an event descriptor with matching CPU and event id 1338 * fields. 1339 */ 1340 1341 switch (core_cputype) { 1342 default: 1343 case PMC_CPU_INTEL_ATOM: 1344 cpuflag = IAP_F_CA; 1345 break; 1346 case PMC_CPU_INTEL_CORE: 1347 cpuflag = IAP_F_CC; 1348 break; 1349 case PMC_CPU_INTEL_CORE2: 1350 cpuflag = IAP_F_CC2; 1351 break; 1352 case PMC_CPU_INTEL_CORE2EXTREME: 1353 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1354 break; 1355 case PMC_CPU_INTEL_COREI7: 1356 cpuflag = IAP_F_I7; 1357 break; 1358 } 1359 1360 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 1361 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 1362 break; 1363 1364 if (n == niap_events) 1365 return (EINVAL); 1366 1367 /* 1368 * A matching event descriptor has been found, so start 1369 * assembling the contents of the event select register. 1370 */ 1371 evsel = ie->iap_evcode; 1372 1373 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 1374 1375 /* 1376 * If the event uses a fixed umask value, reject any umask 1377 * bits set by the user. 1378 */ 1379 if (ie->iap_flags & IAP_F_FM) { 1380 1381 if (IAP_UMASK(config) != 0) 1382 return (EINVAL); 1383 1384 evsel |= (ie->iap_umask << 8); 1385 1386 } else { 1387 1388 /* 1389 * Otherwise, the UMASK value needs to be taken from 1390 * the MD fields of the allocation request. Reject 1391 * requests that specify reserved bits. 1392 */ 1393 1394 mask = 0; 1395 1396 if (ie->iap_flags & IAP_M_CORE) { 1397 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 1398 c != IAP_CORE_THIS) 1399 return (EINVAL); 1400 mask |= IAP_F_CORE; 1401 } 1402 1403 if (ie->iap_flags & IAP_M_AGENT) 1404 mask |= IAP_F_AGENT; 1405 1406 if (ie->iap_flags & IAP_M_PREFETCH) { 1407 1408 if ((c = (config & IAP_F_PREFETCH)) == 1409 IAP_PREFETCH_RESERVED) 1410 return (EINVAL); 1411 1412 mask |= IAP_F_PREFETCH; 1413 } 1414 1415 if (ie->iap_flags & IAP_M_MESI) 1416 mask |= IAP_F_MESI; 1417 1418 if (ie->iap_flags & IAP_M_SNOOPRESPONSE) 1419 mask |= IAP_F_SNOOPRESPONSE; 1420 1421 if (ie->iap_flags & IAP_M_SNOOPTYPE) 1422 mask |= IAP_F_SNOOPTYPE; 1423 1424 if (ie->iap_flags & IAP_M_TRANSITION) 1425 mask |= IAP_F_TRANSITION; 1426 1427 /* 1428 * If bits outside of the allowed set of umask bits 1429 * are set, reject the request. 1430 */ 1431 if (config & ~mask) 1432 return (EINVAL); 1433 1434 evsel |= (config & mask); 1435 1436 } 1437 1438 /* 1439 * Only Atom CPUs support the 'ANY' qualifier. 1440 */ 1441 if (core_cputype == PMC_CPU_INTEL_ATOM) 1442 evsel |= (config & IAP_ANY); 1443 else if (config & IAP_ANY) 1444 return (EINVAL); 1445 1446 if (caps & PMC_CAP_THRESHOLD) 1447 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 1448 if (caps & PMC_CAP_USER) 1449 evsel |= IAP_USR; 1450 if (caps & PMC_CAP_SYSTEM) 1451 evsel |= IAP_OS; 1452 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 1453 evsel |= (IAP_OS | IAP_USR); 1454 if (caps & PMC_CAP_EDGE) 1455 evsel |= IAP_EDGE; 1456 if (caps & PMC_CAP_INVERT) 1457 evsel |= IAP_INV; 1458 if (caps & PMC_CAP_INTERRUPT) 1459 evsel |= IAP_INT; 1460 1461 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 1462 1463 return (0); 1464} 1465 1466static int 1467iap_config_pmc(int cpu, int ri, struct pmc *pm) 1468{ 1469 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1470 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1471 1472 KASSERT(ri >= 0 && ri < core_iap_npmc, 1473 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1474 1475 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 1476 1477 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 1478 cpu)); 1479 1480 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 1481 1482 return (0); 1483} 1484 1485static int 1486iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 1487{ 1488 int error; 1489 struct pmc_hw *phw; 1490 char iap_name[PMC_NAME_MAX]; 1491 1492 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 1493 1494 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 1495 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 1496 NULL)) != 0) 1497 return (error); 1498 1499 pi->pm_class = PMC_CLASS_IAP; 1500 1501 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 1502 pi->pm_enabled = TRUE; 1503 *ppmc = phw->phw_pmc; 1504 } else { 1505 pi->pm_enabled = FALSE; 1506 *ppmc = NULL; 1507 } 1508 1509 return (0); 1510} 1511 1512static int 1513iap_get_config(int cpu, int ri, struct pmc **ppm) 1514{ 1515 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1516 1517 return (0); 1518} 1519 1520static int 1521iap_get_msr(int ri, uint32_t *msr) 1522{ 1523 KASSERT(ri >= 0 && ri < core_iap_npmc, 1524 ("[iap,%d] ri %d out of range", __LINE__, ri)); 1525 1526 *msr = ri; 1527 1528 return (0); 1529} 1530 1531static int 1532iap_read_pmc(int cpu, int ri, pmc_value_t *v) 1533{ 1534 struct pmc *pm; 1535 pmc_value_t tmp; 1536 1537 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1538 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1539 KASSERT(ri >= 0 && ri < core_iap_npmc, 1540 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1541 1542 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1543 1544 KASSERT(pm, 1545 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 1546 ri)); 1547 1548 tmp = rdpmc(ri); 1549 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1550 *v = iap_perfctr_value_to_reload_count(tmp); 1551 else 1552 *v = tmp; 1553 1554 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 1555 ri, *v); 1556 1557 return (0); 1558} 1559 1560static int 1561iap_release_pmc(int cpu, int ri, struct pmc *pm) 1562{ 1563 (void) pm; 1564 1565 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 1566 pm); 1567 1568 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1569 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1570 KASSERT(ri >= 0 && ri < core_iap_npmc, 1571 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1572 1573 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 1574 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 1575 1576 return (0); 1577} 1578 1579static int 1580iap_start_pmc(int cpu, int ri) 1581{ 1582 struct pmc *pm; 1583 uint32_t evsel; 1584 struct core_cpu *cc; 1585 1586 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1587 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1588 KASSERT(ri >= 0 && ri < core_iap_npmc, 1589 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1590 1591 cc = core_pcpu[cpu]; 1592 pm = cc->pc_corepmcs[ri].phw_pmc; 1593 1594 KASSERT(pm, 1595 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 1596 __LINE__, cpu, ri)); 1597 1598 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 1599 1600 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 1601 1602 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 1603 cpu, ri, IAP_EVSEL0 + ri, evsel); 1604 1605 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 1606 1607 if (core_cputype == PMC_CPU_INTEL_CORE) 1608 return (0); 1609 1610 do { 1611 cc->pc_resync = 0; 1612 cc->pc_globalctrl |= (1ULL << ri); 1613 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1614 } while (cc->pc_resync != 0); 1615 1616 return (0); 1617} 1618 1619static int 1620iap_stop_pmc(int cpu, int ri) 1621{ 1622 struct pmc *pm; 1623 struct core_cpu *cc; 1624 1625 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1626 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1627 KASSERT(ri >= 0 && ri < core_iap_npmc, 1628 ("[core,%d] illegal row index %d", __LINE__, ri)); 1629 1630 cc = core_pcpu[cpu]; 1631 pm = cc->pc_corepmcs[ri].phw_pmc; 1632 1633 KASSERT(pm, 1634 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1635 cpu, ri)); 1636 1637 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 1638 1639 wrmsr(IAP_EVSEL0 + ri, 0); /* stop hw */ 1640 1641 if (core_cputype == PMC_CPU_INTEL_CORE) 1642 return (0); 1643 1644 do { 1645 cc->pc_resync = 0; 1646 cc->pc_globalctrl &= ~(1ULL << ri); 1647 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1648 } while (cc->pc_resync != 0); 1649 1650 return (0); 1651} 1652 1653static int 1654iap_write_pmc(int cpu, int ri, pmc_value_t v) 1655{ 1656 struct pmc *pm; 1657 struct core_cpu *cc; 1658 1659 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1660 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1661 KASSERT(ri >= 0 && ri < core_iap_npmc, 1662 ("[core,%d] illegal row index %d", __LINE__, ri)); 1663 1664 cc = core_pcpu[cpu]; 1665 pm = cc->pc_corepmcs[ri].phw_pmc; 1666 1667 KASSERT(pm, 1668 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1669 cpu, ri)); 1670 1671 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1672 IAP_PMC0 + ri, v); 1673 1674 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1675 v = iap_reload_count_to_perfctr_value(v); 1676 1677 /* 1678 * Write the new value to the counter. The counter will be in 1679 * a stopped state when the pcd_write() entry point is called. 1680 */ 1681 1682 wrmsr(IAP_PMC0 + ri, v); 1683 1684 return (0); 1685} 1686 1687 1688static void 1689iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 1690 int flags) 1691{ 1692 struct pmc_classdep *pcd; 1693 1694 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 1695 1696 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 1697 1698 /* Remember the set of architectural events supported. */ 1699 core_architectural_events = ~flags; 1700 1701 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 1702 1703 pcd->pcd_caps = IAP_PMC_CAPS; 1704 pcd->pcd_class = PMC_CLASS_IAP; 1705 pcd->pcd_num = npmc; 1706 pcd->pcd_ri = md->pmd_npmc; 1707 pcd->pcd_width = pmcwidth; 1708 1709 pcd->pcd_allocate_pmc = iap_allocate_pmc; 1710 pcd->pcd_config_pmc = iap_config_pmc; 1711 pcd->pcd_describe = iap_describe; 1712 pcd->pcd_get_config = iap_get_config; 1713 pcd->pcd_get_msr = iap_get_msr; 1714 pcd->pcd_pcpu_fini = core_pcpu_fini; 1715 pcd->pcd_pcpu_init = core_pcpu_init; 1716 pcd->pcd_read_pmc = iap_read_pmc; 1717 pcd->pcd_release_pmc = iap_release_pmc; 1718 pcd->pcd_start_pmc = iap_start_pmc; 1719 pcd->pcd_stop_pmc = iap_stop_pmc; 1720 pcd->pcd_write_pmc = iap_write_pmc; 1721 1722 md->pmd_npmc += npmc; 1723} 1724 1725static int 1726core_intr(int cpu, struct trapframe *tf) 1727{ 1728 pmc_value_t v; 1729 struct pmc *pm; 1730 struct core_cpu *cc; 1731 int error, found_interrupt, ri; 1732 1733 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 1734 TRAPF_USERMODE(tf)); 1735 1736 found_interrupt = 0; 1737 cc = core_pcpu[cpu]; 1738 1739 for (ri = 0; ri < core_iap_npmc; ri++) { 1740 1741 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 1742 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1743 continue; 1744 1745 if (!iap_pmc_has_overflowed(ri)) 1746 continue; 1747 1748 found_interrupt = 1; 1749 1750 if (pm->pm_state != PMC_STATE_RUNNING) 1751 continue; 1752 1753 error = pmc_process_interrupt(cpu, pm, tf, 1754 TRAPF_USERMODE(tf)); 1755 1756 v = pm->pm_sc.pm_reloadcount; 1757 v = iaf_reload_count_to_perfctr_value(v); 1758 1759 /* 1760 * Stop the counter, reload it but only restart it if 1761 * the PMC is not stalled. 1762 */ 1763 wrmsr(IAP_EVSEL0 + ri, 0); 1764 wrmsr(IAP_PMC0 + ri, v); 1765 1766 if (error) 1767 continue; 1768 1769 wrmsr(IAP_EVSEL0 + ri, 1770 pm->pm_md.pm_iap.pm_iap_evsel | IAP_EN); 1771 } 1772 1773 if (found_interrupt) 1774 pmc_x86_lapic_enable_pmc_interrupt(); 1775 1776 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 1777 &pmc_stats.pm_intr_ignored, 1); 1778 1779 return (found_interrupt); 1780} 1781 1782static int 1783core2_intr(int cpu, struct trapframe *tf) 1784{ 1785 int error, found_interrupt, n; 1786 uint64_t flag, intrstatus, intrenable; 1787 struct pmc *pm; 1788 struct core_cpu *cc; 1789 pmc_value_t v; 1790 1791 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 1792 TRAPF_USERMODE(tf)); 1793 1794 /* 1795 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 1796 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 1797 * the current set of interrupting PMCs and process these 1798 * after stopping them. 1799 */ 1800 intrstatus = rdmsr(IA_GLOBAL_STATUS); 1801 intrenable = intrstatus & core_pmcmask; 1802 1803 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 1804 (uintmax_t) intrstatus); 1805 1806 found_interrupt = 0; 1807 cc = core_pcpu[cpu]; 1808 1809 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 1810 1811 cc->pc_globalctrl &= ~intrenable; 1812 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 1813 1814 /* 1815 * Stop PMCs and clear overflow status bits. 1816 */ 1817 wrmsr(IA_GLOBAL_CTRL, 0); 1818 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 1819 IA_GLOBAL_STATUS_FLAG_OVFBUF | 1820 IA_GLOBAL_STATUS_FLAG_CONDCHG); 1821 1822 /* 1823 * Look for interrupts from fixed function PMCs. 1824 */ 1825 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 1826 n++, flag <<= 1) { 1827 1828 if ((intrstatus & flag) == 0) 1829 continue; 1830 1831 found_interrupt = 1; 1832 1833 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 1834 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 1835 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1836 continue; 1837 1838 error = pmc_process_interrupt(cpu, pm, tf, 1839 TRAPF_USERMODE(tf)); 1840 1841 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 1842 1843 /* Reload sampling count. */ 1844 wrmsr(IAF_CTR0 + n, v); 1845 1846 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 1847 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 1848 1849 if (error) 1850 intrenable &= ~flag; 1851 } 1852 1853 /* 1854 * Process interrupts from the programmable counters. 1855 */ 1856 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 1857 if ((intrstatus & flag) == 0) 1858 continue; 1859 1860 found_interrupt = 1; 1861 1862 pm = cc->pc_corepmcs[n].phw_pmc; 1863 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 1864 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1865 continue; 1866 1867 error = pmc_process_interrupt(cpu, pm, tf, 1868 TRAPF_USERMODE(tf)); 1869 if (error) 1870 intrenable &= ~flag; 1871 1872 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 1873 1874 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 1875 (uintmax_t) v); 1876 1877 /* Reload sampling count. */ 1878 wrmsr(IAP_PMC0 + n, v); 1879 } 1880 1881 /* 1882 * Reenable all non-stalled PMCs. 1883 */ 1884 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 1885 (uintmax_t) intrenable); 1886 1887 cc->pc_globalctrl |= intrenable; 1888 1889 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1890 1891 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 1892 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 1893 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 1894 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 1895 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 1896 1897 if (found_interrupt) 1898 pmc_x86_lapic_enable_pmc_interrupt(); 1899 1900 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 1901 &pmc_stats.pm_intr_ignored, 1); 1902 1903 return (found_interrupt); 1904} 1905 1906int 1907pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 1908{ 1909 int cpuid[CORE_CPUID_REQUEST_SIZE]; 1910 int ipa_version, flags, nflags; 1911 1912 do_cpuid(CORE_CPUID_REQUEST, cpuid); 1913 1914 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 1915 1916 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 1917 md->pmd_cputype, maxcpu, ipa_version); 1918 1919 if (ipa_version < 1 || ipa_version > 3) /* Unknown PMC architecture. */ 1920 return (EPROGMISMATCH); 1921 1922 core_cputype = md->pmd_cputype; 1923 1924 core_pmcmask = 0; 1925 1926 /* 1927 * Initialize programmable counters. 1928 */ 1929 KASSERT(ipa_version >= 1, 1930 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 1931 1932 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 1933 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 1934 1935 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 1936 1937 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 1938 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 1939 1940 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 1941 1942 /* 1943 * Initialize fixed function counters, if present. 1944 */ 1945 if (core_cputype != PMC_CPU_INTEL_CORE) { 1946 KASSERT(ipa_version >= 2, 1947 ("[core,%d] ipa_version %d too small", __LINE__, 1948 ipa_version)); 1949 1950 core_iaf_ri = core_iap_npmc; 1951 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 1952 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 1953 1954 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 1955 1956 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << 1957 IAF_OFFSET; 1958 1959 } 1960 1961 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 1962 core_iaf_ri); 1963 1964 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 1965 M_ZERO | M_WAITOK); 1966 1967 /* 1968 * Choose the appropriate interrupt handler. 1969 */ 1970 if (ipa_version == 1) 1971 md->pmd_intr = core_intr; 1972 else 1973 md->pmd_intr = core2_intr; 1974 1975 md->pmd_pcpu_fini = NULL; 1976 md->pmd_pcpu_init = NULL; 1977 1978 return (0); 1979} 1980 1981void 1982pmc_core_finalize(struct pmc_mdep *md) 1983{ 1984 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 1985 1986 free(core_pcpu, M_PMC); 1987 core_pcpu = NULL; 1988} 1989