hwpmc_core.c revision 186177
1/*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_core.c 186177 2008-12-16 11:04:02Z jkoshy $"); 33 34#include <sys/param.h> 35#include <sys/pmc.h> 36#include <sys/pmckern.h> 37#include <sys/systm.h> 38 39#include <machine/cpu.h> 40#include <machine/cpufunc.h> 41#include <machine/specialreg.h> 42 43#define CORE_CPUID_REQUEST 0xA 44#define CORE_CPUID_REQUEST_SIZE 0x4 45#define CORE_CPUID_EAX 0x0 46#define CORE_CPUID_EBX 0x1 47#define CORE_CPUID_ECX 0x2 48#define CORE_CPUID_EDX 0x3 49 50#define IAF_PMC_CAPS \ 51 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT) 52#define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 53 54#define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 55 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 56 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 57 58/* 59 * "Architectural" events defined by Intel. The values of these 60 * symbols correspond to positions in the bitmask returned by 61 * the CPUID.0AH instruction. 62 */ 63enum core_arch_events { 64 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 65 CORE_AE_BRANCH_MISSES_RETIRED = 6, 66 CORE_AE_INSTRUCTION_RETIRED = 1, 67 CORE_AE_LLC_MISSES = 4, 68 CORE_AE_LLC_REFERENCE = 3, 69 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 70 CORE_AE_UNHALTED_CORE_CYCLES = 0 71}; 72 73static enum pmc_cputype core_cputype; 74 75struct core_cpu { 76 volatile uint32_t pc_resync; 77 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 78 volatile uint64_t pc_globalctrl; /* Global control register. */ 79 struct pmc_hw pc_corepmcs[]; 80}; 81 82static struct core_cpu **core_pcpu; 83 84static uint32_t core_architectural_events; 85static uint64_t core_pmcmask; 86 87static int core_iaf_ri; /* relative index of fixed counters */ 88static int core_iaf_width; 89static int core_iaf_npmc; 90 91static int core_iap_width; 92static int core_iap_npmc; 93 94static int 95core_pcpu_noop(struct pmc_mdep *md, int cpu) 96{ 97 (void) md; 98 (void) cpu; 99 return (0); 100} 101 102static int 103core_pcpu_init(struct pmc_mdep *md, int cpu) 104{ 105 struct pmc_cpu *pc; 106 struct core_cpu *cc; 107 struct pmc_hw *phw; 108 int core_ri, n, npmc; 109 110 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 111 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 112 113 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 114 115 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 116 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 117 118 if (core_cputype != PMC_CPU_INTEL_CORE) 119 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 120 121 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 122 M_PMC, M_WAITOK | M_ZERO); 123 124 core_pcpu[cpu] = cc; 125 pc = pmc_pcpu[cpu]; 126 127 KASSERT(pc != NULL && cc != NULL, 128 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 129 130 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 131 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 132 PMC_PHW_CPU_TO_STATE(cpu) | 133 PMC_PHW_INDEX_TO_STATE(n + core_ri); 134 phw->phw_pmc = NULL; 135 pc->pc_hwpmcs[n + core_ri] = phw; 136 } 137 138 return (0); 139} 140 141static int 142core_pcpu_fini(struct pmc_mdep *md, int cpu) 143{ 144 int core_ri, n, npmc; 145 struct pmc_cpu *pc; 146 struct core_cpu *cc; 147 148 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 149 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 150 151 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 152 153 if ((cc = core_pcpu[cpu]) == NULL) 154 return (0); 155 156 core_pcpu[cpu] = NULL; 157 158 pc = pmc_pcpu[cpu]; 159 160 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 161 cpu)); 162 163 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 164 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 165 166 for (n = 0; n < npmc; n++) 167 wrmsr(IAP_EVSEL0 + n, 0); 168 169 if (core_cputype != PMC_CPU_INTEL_CORE) { 170 wrmsr(IAF_CTRL, 0); 171 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 172 } 173 174 for (n = 0; n < npmc; n++) 175 pc->pc_hwpmcs[n + core_ri] = NULL; 176 177 free(cc, M_PMC); 178 179 return (0); 180} 181 182/* 183 * Fixed function counters. 184 */ 185 186static pmc_value_t 187iaf_perfctr_value_to_reload_count(pmc_value_t v) 188{ 189 v &= (1ULL << core_iaf_width) - 1; 190 return (1ULL << core_iaf_width) - v; 191} 192 193static pmc_value_t 194iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 195{ 196 return (1ULL << core_iaf_width) - rlc; 197} 198 199static int 200iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 201 const struct pmc_op_pmcallocate *a) 202{ 203 enum pmc_event ev; 204 uint32_t caps, flags, validflags; 205 206 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 207 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 208 209 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 210 211 if (ri < 0 || ri > core_iaf_npmc) 212 return (EINVAL); 213 214 caps = a->pm_caps; 215 216 if (a->pm_class != PMC_CLASS_IAF || 217 (caps & IAF_PMC_CAPS) != caps) 218 return (EINVAL); 219 220 ev = pm->pm_event; 221 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 222 return (EINVAL); 223 224 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 225 return (EINVAL); 226 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 227 return (EINVAL); 228 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 229 return (EINVAL); 230 231 flags = a->pm_md.pm_iaf.pm_iaf_flags; 232 233 validflags = IAF_MASK; 234 235 if (core_cputype != PMC_CPU_INTEL_ATOM) 236 validflags &= ~IAF_ANY; 237 238 if ((flags & ~validflags) != 0) 239 return (EINVAL); 240 241 if (caps & PMC_CAP_INTERRUPT) 242 flags |= IAF_PMI; 243 if (caps & PMC_CAP_SYSTEM) 244 flags |= IAF_OS; 245 if (caps & PMC_CAP_USER) 246 flags |= IAF_USR; 247 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 248 flags |= (IAF_OS | IAF_USR); 249 250 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 251 252 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 253 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 254 255 return (0); 256} 257 258static int 259iaf_config_pmc(int cpu, int ri, struct pmc *pm) 260{ 261 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 262 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 263 264 KASSERT(ri >= 0 && ri < core_iaf_npmc, 265 ("[core,%d] illegal row-index %d", __LINE__, ri)); 266 267 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 268 269 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 270 cpu)); 271 272 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 273 274 return (0); 275} 276 277static int 278iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 279{ 280 int error; 281 struct pmc_hw *phw; 282 char iaf_name[PMC_NAME_MAX]; 283 284 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 285 286 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 287 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 288 NULL)) != 0) 289 return (error); 290 291 pi->pm_class = PMC_CLASS_IAF; 292 293 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 294 pi->pm_enabled = TRUE; 295 *ppmc = phw->phw_pmc; 296 } else { 297 pi->pm_enabled = FALSE; 298 *ppmc = NULL; 299 } 300 301 return (0); 302} 303 304static int 305iaf_get_config(int cpu, int ri, struct pmc **ppm) 306{ 307 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 308 309 return (0); 310} 311 312static int 313iaf_get_msr(int ri, uint32_t *msr) 314{ 315 KASSERT(ri >= 0 && ri < core_iaf_npmc, 316 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 317 318 *msr = IAF_RI_TO_MSR(ri); 319 320 return (0); 321} 322 323static int 324iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 325{ 326 struct pmc *pm; 327 pmc_value_t tmp; 328 329 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 330 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 331 KASSERT(ri >= 0 && ri < core_iaf_npmc, 332 ("[core,%d] illegal row-index %d", __LINE__, ri)); 333 334 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 335 336 KASSERT(pm, 337 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 338 ri, ri + core_iaf_ri)); 339 340 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 341 342 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 343 *v = iaf_perfctr_value_to_reload_count(tmp); 344 else 345 *v = tmp; 346 347 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 348 IAF_RI_TO_MSR(ri), *v); 349 350 return (0); 351} 352 353static int 354iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 355{ 356 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 357 358 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 359 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 360 KASSERT(ri >= 0 && ri < core_iaf_npmc, 361 ("[core,%d] illegal row-index %d", __LINE__, ri)); 362 363 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 364 ("[core,%d] PHW pmc non-NULL", __LINE__)); 365 366 return (0); 367} 368 369static int 370iaf_start_pmc(int cpu, int ri) 371{ 372 struct pmc *pm; 373 struct core_cpu *iafc; 374 375 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 376 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 377 KASSERT(ri >= 0 && ri < core_iaf_npmc, 378 ("[core,%d] illegal row-index %d", __LINE__, ri)); 379 380 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 381 382 iafc = core_pcpu[cpu]; 383 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 384 385 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 386 387 wrmsr(IAF_CTRL, iafc->pc_iafctrl); 388 389 do { 390 iafc->pc_resync = 0; 391 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 392 wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl); 393 } while (iafc->pc_resync != 0); 394 395 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 396 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 397 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 398 399 return (0); 400} 401 402static int 403iaf_stop_pmc(int cpu, int ri) 404{ 405 uint32_t fc; 406 struct core_cpu *iafc; 407 408 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 409 410 iafc = core_pcpu[cpu]; 411 412 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 413 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 414 KASSERT(ri >= 0 && ri < core_iaf_npmc, 415 ("[core,%d] illegal row-index %d", __LINE__, ri)); 416 417 fc = (IAF_MASK << (ri * 4)); 418 419 if (core_cputype != PMC_CPU_INTEL_ATOM) 420 fc &= ~IAF_ANY; 421 422 iafc->pc_iafctrl &= ~fc; 423 424 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 425 wrmsr(IAF_CTRL, iafc->pc_iafctrl); 426 427 do { 428 iafc->pc_resync = 0; 429 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 430 wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl); 431 } while (iafc->pc_resync != 0); 432 433 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 434 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 435 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 436 437 return (0); 438} 439 440static int 441iaf_write_pmc(int cpu, int ri, pmc_value_t v) 442{ 443 struct core_cpu *cc; 444 struct pmc *pm; 445 446 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 447 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 448 KASSERT(ri >= 0 && ri < core_iaf_npmc, 449 ("[core,%d] illegal row-index %d", __LINE__, ri)); 450 451 cc = core_pcpu[cpu]; 452 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 453 454 KASSERT(pm, 455 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 456 457 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 458 v = iaf_reload_count_to_perfctr_value(v); 459 460 wrmsr(IAF_CTRL, 0); /* Turn off fixed counters */ 461 wrmsr(IAF_CTR0 + ri, v); 462 wrmsr(IAF_CTRL, cc->pc_iafctrl); 463 464 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 465 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 466 (uintmax_t) rdmsr(IAF_CTRL), 467 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 468 469 return (0); 470} 471 472 473static void 474iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 475{ 476 struct pmc_classdep *pcd; 477 478 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 479 480 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 481 482 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 483 484 pcd->pcd_caps = IAF_PMC_CAPS; 485 pcd->pcd_class = PMC_CLASS_IAF; 486 pcd->pcd_num = npmc; 487 pcd->pcd_ri = md->pmd_npmc; 488 pcd->pcd_width = pmcwidth; 489 490 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 491 pcd->pcd_config_pmc = iaf_config_pmc; 492 pcd->pcd_describe = iaf_describe; 493 pcd->pcd_get_config = iaf_get_config; 494 pcd->pcd_get_msr = iaf_get_msr; 495 pcd->pcd_pcpu_fini = core_pcpu_noop; 496 pcd->pcd_pcpu_init = core_pcpu_noop; 497 pcd->pcd_read_pmc = iaf_read_pmc; 498 pcd->pcd_release_pmc = iaf_release_pmc; 499 pcd->pcd_start_pmc = iaf_start_pmc; 500 pcd->pcd_stop_pmc = iaf_stop_pmc; 501 pcd->pcd_write_pmc = iaf_write_pmc; 502 503 md->pmd_npmc += npmc; 504} 505 506/* 507 * Intel programmable PMCs. 508 */ 509 510/* 511 * Event descriptor tables. 512 * 513 * For each event id, we track: 514 * 515 * 1. The CPUs that the event is valid for. 516 * 517 * 2. If the event uses a fixed UMASK, the value of the umask field. 518 * If the event doesn't use a fixed UMASK, a mask of legal bits 519 * to check against. 520 */ 521 522struct iap_event_descr { 523 enum pmc_event iap_ev; 524 unsigned char iap_evcode; 525 unsigned char iap_umask; 526 unsigned char iap_flags; 527}; 528 529#define IAP_F_CC (1 << 0) /* CPU: Core */ 530#define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 531#define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 532#define IAP_F_CA (1 << 3) /* CPU: Atom */ 533#define IAP_F_FM (1 << 4) /* Fixed mask */ 534 535#define IAP_F_ALLCPUS (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 536 537/* Sub fields of UMASK that this event supports. */ 538#define IAP_M_CORE (1 << 0) /* Core specificity */ 539#define IAP_M_AGENT (1 << 1) /* Agent specificity */ 540#define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 541#define IAP_M_MESI (1 << 3) /* MESI */ 542#define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 543#define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 544#define IAP_M_TRANSITION (1 << 6) /* Transition */ 545 546#define IAP_F_CORE (0x3 << 14) /* Core specificity */ 547#define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 548#define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 549#define IAP_F_MESI (0xF << 8) /* MESI */ 550#define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 551#define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 552#define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 553 554#define IAP_PREFETCH_RESERVED (0x2 << 12) 555#define IAP_CORE_THIS (0x1 << 14) 556#define IAP_CORE_ALL (0x3 << 14) 557#define IAP_F_CMASK 0xFF000000 558 559static struct iap_event_descr iap_events[] = { 560#undef IAPDESCR 561#define IAPDESCR(N,EV,UM,FLAGS) { \ 562 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 563 .iap_evcode = (EV), \ 564 .iap_umask = (UM), \ 565 .iap_flags = (FLAGS) \ 566 } 567 568 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 569 570 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 571 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 572 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 573 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 574 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 575 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 576 577 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 578 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 579 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 580 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 581 582 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 583 584 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 585 586 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 587 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 588 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUS), 589 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUS), 590 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 591 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA), 592 593 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 594 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 595 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 596 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 597 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 598 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 599 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 600 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 601 602 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 603 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 604 605 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2), 606 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 607 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 608 609 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 610 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA), 611 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 612 613 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 614 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA), 615 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 616 617 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 618 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA), 619 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 620 621 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 622 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA), 623 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 624 625 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 626 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA), 627 628 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 629 630 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 631 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 632 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 633 634 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUS), 635 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 636 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUS), 637 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUS), 638 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUS), 639 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUS), 640 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUS), 641 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUS), 642 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 643 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 644 IAP_F_CA | IAP_F_CC2), 645 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUS), 646 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 647 648 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 649 IAP_F_ALLCPUS), 650 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUS), 651 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUS), 652 653 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 654 IAP_F_ALLCPUS), 655 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 656 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 657 658 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 659 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 660 661 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUS), 662 663 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 664 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 665 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUS), 666 667 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC), 668 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 669 670 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 671 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 672 673 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUS), 674 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 675 676 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 677 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 678 679 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 680 681 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUS), 682 683 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 684 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 685 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 686 687 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 688 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 689 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 690 691 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 692 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 693 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUS), 694 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 695 696 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 697 698 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 699 700 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 701 702 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 703 704 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 705 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 706 707 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUS), 708 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 709 710 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 711 IAP_F_CA | IAP_F_CC2), 712 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 713 714 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 715 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 716 717 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 718 IAP_F_CA | IAP_F_CC2), 719 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 720 721 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 722 723 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 724 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 725 726 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 727 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 728 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 729 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 730 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUS), 731 732 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 733 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 734 735 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 736 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 737 738 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 739 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 740 741 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 742 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 743 744 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 745 IAP_F_CA | IAP_F_CC2), 746 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 747 748 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 749 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 750 751 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 752 753 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 754 755 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUS), 756 757 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 758 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 759 760 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 761 762 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 763 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA), 764 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA), 765 766 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 767 768 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 769 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 770 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 771 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 772 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 773 774 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 775 776 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 777 778 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 779 780 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 781 782 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 783 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 784 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 785 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 786 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 787 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 788 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 789 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 790 791 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 792 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 793 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 794 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 795 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 796 797 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 798 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 799 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 800 801 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 802 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 803 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 804 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 805 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 806 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 807 808 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 809 810 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 811 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 812 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 813 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 814 815 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 816 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 817 818 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 819 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA), 820 821 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 822 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA), 823 824 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 825 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUS), 826 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUS), 827 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUS), 828 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUS), 829 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUS), 830 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 831 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 832 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 833 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 834 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 835 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 836 837 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 838 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 839 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 840 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 841 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 842 843 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 844 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 845 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 846 847 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 848 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 849 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 850 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 851 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 852 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 853 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 854 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 855 856 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 857 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 858 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 859 860 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 861 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 862 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 863 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 864 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 865 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 866 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 867 868 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 869 870 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 871 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 872 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 873 874 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 875 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 876 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 877 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 878 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 879 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 880 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 881 882 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 883 884 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 885 886 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 887 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 888 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 889 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 890 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 891 892 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 893 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 894 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 895 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 896 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2), 897 898 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 899 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUS), 900 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 901 902 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 903 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 904 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 905 906 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 907 908 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 909 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 910 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 911 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 912 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 913 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 914 915 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 916 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 917 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 918 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 919 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 920 921 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 922 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 923 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 924 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 925 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 926 927 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 928 929 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 930 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 931 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 932 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 933 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 934 935 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 936 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 937 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 938 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 939 940 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 941 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 942 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 943 944 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 945 946 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 947 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 948 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 949 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 950 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 951 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 952 953 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 954 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA), 955 956 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 957 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 958 959 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 960 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA), 961 962 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUS), 963 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUS) 964}; 965 966static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 967 968static pmc_value_t 969iap_perfctr_value_to_reload_count(pmc_value_t v) 970{ 971 v &= (1ULL << core_iap_width) - 1; 972 return (1ULL << core_iap_width) - v; 973} 974 975static pmc_value_t 976iap_reload_count_to_perfctr_value(pmc_value_t rlc) 977{ 978 return (1ULL << core_iap_width) - rlc; 979} 980 981static int 982iap_pmc_has_overflowed(int ri) 983{ 984 uint64_t v; 985 986 /* 987 * We treat a Core (i.e., Intel architecture v1) PMC as has 988 * having overflowed if its MSB is zero. 989 */ 990 v = rdpmc(ri); 991 return ((v & (1ULL << (core_iap_width - 1))) == 0); 992} 993 994/* 995 * Check an event against the set of supported architectural events. 996 * 997 * Returns 1 if the event is architectural and unsupported on this 998 * CPU. Returns 0 otherwise. 999 */ 1000 1001static int 1002iap_architectural_event_is_unsupported(enum pmc_event pe) 1003{ 1004 enum core_arch_events ae; 1005 1006 switch (pe) { 1007 case PMC_EV_IAP_EVENT_3CH_00H: 1008 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1009 break; 1010 case PMC_EV_IAP_EVENT_C0H_00H: 1011 ae = CORE_AE_INSTRUCTION_RETIRED; 1012 break; 1013 case PMC_EV_IAP_EVENT_3CH_01H: 1014 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1015 break; 1016 case PMC_EV_IAP_EVENT_2EH_4FH: 1017 ae = CORE_AE_LLC_REFERENCE; 1018 break; 1019 case PMC_EV_IAP_EVENT_2EH_41H: 1020 ae = CORE_AE_LLC_MISSES; 1021 break; 1022 case PMC_EV_IAP_EVENT_C4H_00H: 1023 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1024 break; 1025 case PMC_EV_IAP_EVENT_C5H_00H: 1026 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1027 break; 1028 1029 default: /* Non architectural event. */ 1030 return (0); 1031 } 1032 1033 return ((core_architectural_events & (1 << ae)) == 0); 1034} 1035 1036static int 1037iap_event_ok_on_counter(enum pmc_event pe, int ri) 1038{ 1039 uint32_t mask; 1040 1041 switch (pe) { 1042 /* 1043 * Events valid only on counter 0. 1044 */ 1045 case PMC_EV_IAP_EVENT_10H_00H: 1046 case PMC_EV_IAP_EVENT_14H_00H: 1047 case PMC_EV_IAP_EVENT_18H_00H: 1048 case PMC_EV_IAP_EVENT_C1H_00H: 1049 case PMC_EV_IAP_EVENT_CBH_01H: 1050 case PMC_EV_IAP_EVENT_CBH_02H: 1051 mask = (1 << 0); 1052 break; 1053 1054 /* 1055 * Events valid only on counter 1. 1056 */ 1057 case PMC_EV_IAP_EVENT_11H_00H: 1058 case PMC_EV_IAP_EVENT_12H_00H: 1059 case PMC_EV_IAP_EVENT_13H_00H: 1060 mask = (1 << 1); 1061 break; 1062 1063 default: 1064 mask = ~0; /* Any row index is ok. */ 1065 } 1066 1067 return (mask & (1 << ri)); 1068} 1069 1070static int 1071iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1072 const struct pmc_op_pmcallocate *a) 1073{ 1074 int n; 1075 enum pmc_event ev; 1076 struct iap_event_descr *ie; 1077 uint32_t c, caps, config, cpuflag, evsel, mask; 1078 1079 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1080 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1081 KASSERT(ri >= 0 && ri < core_iap_npmc, 1082 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1083 1084 /* check requested capabilities */ 1085 caps = a->pm_caps; 1086 if ((IAP_PMC_CAPS & caps) != caps) 1087 return (EPERM); 1088 1089 ev = pm->pm_event; 1090 1091 if (iap_architectural_event_is_unsupported(ev)) 1092 return (EOPNOTSUPP); 1093 1094 if (iap_event_ok_on_counter(ev, ri) == 0) 1095 return (EINVAL); 1096 1097 /* 1098 * Look for an event descriptor with matching CPU and event id 1099 * fields. 1100 */ 1101 1102 switch (core_cputype) { 1103 default: 1104 case PMC_CPU_INTEL_ATOM: 1105 cpuflag = IAP_F_CA; 1106 break; 1107 case PMC_CPU_INTEL_CORE: 1108 cpuflag = IAP_F_CC; 1109 break; 1110 case PMC_CPU_INTEL_CORE2: 1111 cpuflag = IAP_F_CC2; 1112 break; 1113 case PMC_CPU_INTEL_CORE2EXTREME: 1114 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1115 break; 1116 } 1117 1118 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 1119 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 1120 break; 1121 1122 if (n == niap_events) 1123 return (EINVAL); 1124 1125 /* 1126 * A matching event descriptor has been found, so start 1127 * assembling the contents of the event select register. 1128 */ 1129 evsel = ie->iap_evcode; 1130 1131 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 1132 1133 /* 1134 * If the event uses a fixed umask value, reject any umask 1135 * bits set by the user. 1136 */ 1137 if (ie->iap_flags & IAP_F_FM) { 1138 1139 if (IAP_UMASK(config) != 0) 1140 return (EINVAL); 1141 1142 evsel |= (ie->iap_umask << 8); 1143 1144 } else { 1145 1146 /* 1147 * Otherwise, the UMASK value needs to be taken from 1148 * the MD fields of the allocation request. Reject 1149 * requests that specify reserved bits. 1150 */ 1151 1152 mask = 0; 1153 1154 if (ie->iap_flags & IAP_M_CORE) { 1155 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 1156 c != IAP_CORE_THIS) 1157 return (EINVAL); 1158 mask |= IAP_F_CORE; 1159 } 1160 1161 if (ie->iap_flags & IAP_M_AGENT) 1162 mask |= IAP_F_AGENT; 1163 1164 if (ie->iap_flags & IAP_M_PREFETCH) { 1165 1166 if ((c = (config & IAP_F_PREFETCH)) == 1167 IAP_PREFETCH_RESERVED) 1168 return (EINVAL); 1169 1170 mask |= IAP_F_PREFETCH; 1171 } 1172 1173 if (ie->iap_flags & IAP_M_MESI) 1174 mask |= IAP_F_MESI; 1175 1176 if (ie->iap_flags & IAP_M_SNOOPRESPONSE) 1177 mask |= IAP_F_SNOOPRESPONSE; 1178 1179 if (ie->iap_flags & IAP_M_SNOOPTYPE) 1180 mask |= IAP_F_SNOOPTYPE; 1181 1182 if (ie->iap_flags & IAP_M_TRANSITION) 1183 mask |= IAP_F_TRANSITION; 1184 1185 /* 1186 * If bits outside of the allowed set of umask bits 1187 * are set, reject the request. 1188 */ 1189 if (config & ~mask) 1190 return (EINVAL); 1191 1192 evsel |= (config & mask); 1193 1194 } 1195 1196 /* 1197 * Only Atom CPUs support the 'ANY' qualifier. 1198 */ 1199 if (core_cputype == PMC_CPU_INTEL_ATOM) 1200 evsel |= (config & IAP_ANY); 1201 else if (config & IAP_ANY) 1202 return (EINVAL); 1203 1204 if (caps & PMC_CAP_THRESHOLD) 1205 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 1206 if (caps & PMC_CAP_USER) 1207 evsel |= IAP_USR; 1208 if (caps & PMC_CAP_SYSTEM) 1209 evsel |= IAP_OS; 1210 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 1211 evsel |= (IAP_OS | IAP_USR); 1212 if (caps & PMC_CAP_EDGE) 1213 evsel |= IAP_EDGE; 1214 if (caps & PMC_CAP_INVERT) 1215 evsel |= IAP_INV; 1216 if (caps & PMC_CAP_INTERRUPT) 1217 evsel |= IAP_INT; 1218 1219 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 1220 1221 return (0); 1222} 1223 1224static int 1225iap_config_pmc(int cpu, int ri, struct pmc *pm) 1226{ 1227 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1228 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1229 1230 KASSERT(ri >= 0 && ri < core_iap_npmc, 1231 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1232 1233 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 1234 1235 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 1236 cpu)); 1237 1238 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 1239 1240 return (0); 1241} 1242 1243static int 1244iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 1245{ 1246 int error; 1247 struct pmc_hw *phw; 1248 char iap_name[PMC_NAME_MAX]; 1249 1250 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 1251 1252 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 1253 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 1254 NULL)) != 0) 1255 return (error); 1256 1257 pi->pm_class = PMC_CLASS_IAP; 1258 1259 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 1260 pi->pm_enabled = TRUE; 1261 *ppmc = phw->phw_pmc; 1262 } else { 1263 pi->pm_enabled = FALSE; 1264 *ppmc = NULL; 1265 } 1266 1267 return (0); 1268} 1269 1270static int 1271iap_get_config(int cpu, int ri, struct pmc **ppm) 1272{ 1273 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1274 1275 return (0); 1276} 1277 1278static int 1279iap_get_msr(int ri, uint32_t *msr) 1280{ 1281 KASSERT(ri >= 0 && ri < core_iap_npmc, 1282 ("[iap,%d] ri %d out of range", __LINE__, ri)); 1283 1284 *msr = ri; 1285 1286 return (0); 1287} 1288 1289static int 1290iap_read_pmc(int cpu, int ri, pmc_value_t *v) 1291{ 1292 struct pmc *pm; 1293 pmc_value_t tmp; 1294 1295 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1296 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1297 KASSERT(ri >= 0 && ri < core_iap_npmc, 1298 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1299 1300 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1301 1302 KASSERT(pm, 1303 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 1304 ri)); 1305 1306 tmp = rdpmc(ri); 1307 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1308 *v = iap_perfctr_value_to_reload_count(tmp); 1309 else 1310 *v = tmp; 1311 1312 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 1313 ri, *v); 1314 1315 return (0); 1316} 1317 1318static int 1319iap_release_pmc(int cpu, int ri, struct pmc *pm) 1320{ 1321 (void) pm; 1322 1323 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 1324 pm); 1325 1326 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1327 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1328 KASSERT(ri >= 0 && ri < core_iap_npmc, 1329 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1330 1331 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 1332 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 1333 1334 return (0); 1335} 1336 1337static int 1338iap_start_pmc(int cpu, int ri) 1339{ 1340 struct pmc *pm; 1341 uint32_t evsel; 1342 struct core_cpu *cc; 1343 1344 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1345 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1346 KASSERT(ri >= 0 && ri < core_iap_npmc, 1347 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1348 1349 cc = core_pcpu[cpu]; 1350 pm = cc->pc_corepmcs[ri].phw_pmc; 1351 1352 KASSERT(pm, 1353 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 1354 __LINE__, cpu, ri)); 1355 1356 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 1357 1358 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 1359 1360 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 1361 cpu, ri, IAP_EVSEL0 + ri, evsel); 1362 1363 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 1364 1365 if (core_cputype == PMC_CPU_INTEL_CORE) 1366 return (0); 1367 1368 do { 1369 cc->pc_resync = 0; 1370 cc->pc_globalctrl |= (1ULL << ri); 1371 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1372 } while (cc->pc_resync != 0); 1373 1374 return (0); 1375} 1376 1377static int 1378iap_stop_pmc(int cpu, int ri) 1379{ 1380 struct pmc *pm; 1381 struct core_cpu *cc; 1382 1383 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1384 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1385 KASSERT(ri >= 0 && ri < core_iap_npmc, 1386 ("[core,%d] illegal row index %d", __LINE__, ri)); 1387 1388 cc = core_pcpu[cpu]; 1389 pm = cc->pc_corepmcs[ri].phw_pmc; 1390 1391 KASSERT(pm, 1392 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1393 cpu, ri)); 1394 1395 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 1396 1397 wrmsr(IAP_EVSEL0 + ri, 0); /* stop hw */ 1398 1399 if (core_cputype == PMC_CPU_INTEL_CORE) 1400 return (0); 1401 1402 do { 1403 cc->pc_resync = 0; 1404 cc->pc_globalctrl &= ~(1ULL << ri); 1405 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1406 } while (cc->pc_resync != 0); 1407 1408 return (0); 1409} 1410 1411static int 1412iap_write_pmc(int cpu, int ri, pmc_value_t v) 1413{ 1414 struct pmc *pm; 1415 struct core_cpu *cc; 1416 1417 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1418 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1419 KASSERT(ri >= 0 && ri < core_iap_npmc, 1420 ("[core,%d] illegal row index %d", __LINE__, ri)); 1421 1422 cc = core_pcpu[cpu]; 1423 pm = cc->pc_corepmcs[ri].phw_pmc; 1424 1425 KASSERT(pm, 1426 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1427 cpu, ri)); 1428 1429 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1430 IAP_PMC0 + ri, v); 1431 1432 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1433 v = iap_reload_count_to_perfctr_value(v); 1434 1435 /* 1436 * Write the new value to the counter. The counter will be in 1437 * a stopped state when the pcd_write() entry point is called. 1438 */ 1439 1440 wrmsr(IAP_PMC0 + ri, v); 1441 1442 return (0); 1443} 1444 1445 1446static void 1447iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 1448 int flags) 1449{ 1450 struct pmc_classdep *pcd; 1451 1452 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 1453 1454 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 1455 1456 /* Remember the set of architectural events supported. */ 1457 core_architectural_events = ~flags; 1458 1459 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 1460 1461 pcd->pcd_caps = IAP_PMC_CAPS; 1462 pcd->pcd_class = PMC_CLASS_IAP; 1463 pcd->pcd_num = npmc; 1464 pcd->pcd_ri = md->pmd_npmc; 1465 pcd->pcd_width = pmcwidth; 1466 1467 pcd->pcd_allocate_pmc = iap_allocate_pmc; 1468 pcd->pcd_config_pmc = iap_config_pmc; 1469 pcd->pcd_describe = iap_describe; 1470 pcd->pcd_get_config = iap_get_config; 1471 pcd->pcd_get_msr = iap_get_msr; 1472 pcd->pcd_pcpu_fini = core_pcpu_fini; 1473 pcd->pcd_pcpu_init = core_pcpu_init; 1474 pcd->pcd_read_pmc = iap_read_pmc; 1475 pcd->pcd_release_pmc = iap_release_pmc; 1476 pcd->pcd_start_pmc = iap_start_pmc; 1477 pcd->pcd_stop_pmc = iap_stop_pmc; 1478 pcd->pcd_write_pmc = iap_write_pmc; 1479 1480 md->pmd_npmc += npmc; 1481} 1482 1483static int 1484core_intr(int cpu, struct trapframe *tf) 1485{ 1486 pmc_value_t v; 1487 struct pmc *pm; 1488 struct core_cpu *cc; 1489 int error, found_interrupt, ri; 1490 1491 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 1492 TRAPF_USERMODE(tf)); 1493 1494 found_interrupt = 0; 1495 cc = core_pcpu[cpu]; 1496 1497 for (ri = 0; ri < core_iap_npmc; ri++) { 1498 1499 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 1500 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1501 continue; 1502 1503 if (!iap_pmc_has_overflowed(ri)) 1504 continue; 1505 1506 found_interrupt = 1; 1507 1508 if (pm->pm_state != PMC_STATE_RUNNING) 1509 continue; 1510 1511 error = pmc_process_interrupt(cpu, pm, tf, 1512 TRAPF_USERMODE(tf)); 1513 1514 v = pm->pm_sc.pm_reloadcount; 1515 v = iaf_reload_count_to_perfctr_value(v); 1516 1517 /* 1518 * Stop the counter, reload it but only restart it if 1519 * the PMC is not stalled. 1520 */ 1521 wrmsr(IAP_EVSEL0 + ri, 0); 1522 wrmsr(IAP_PMC0 + ri, v); 1523 1524 if (error) 1525 continue; 1526 1527 wrmsr(IAP_EVSEL0 + ri, 1528 pm->pm_md.pm_iap.pm_iap_evsel | IAP_EN); 1529 } 1530 1531 if (found_interrupt) 1532 pmc_x86_lapic_enable_pmc_interrupt(); 1533 1534 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 1535 &pmc_stats.pm_intr_ignored, 1); 1536 1537 return (found_interrupt); 1538} 1539 1540static int 1541core2_intr(int cpu, struct trapframe *tf) 1542{ 1543 int error, found_interrupt, n; 1544 uint64_t flag, intrstatus, intrenable; 1545 struct pmc *pm; 1546 struct core_cpu *cc; 1547 pmc_value_t v; 1548 1549 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 1550 TRAPF_USERMODE(tf)); 1551 1552 /* 1553 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 1554 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 1555 * the current set of interrupting PMCs and process these 1556 * after stopping them. 1557 */ 1558 intrstatus = rdmsr(IA_GLOBAL_STATUS); 1559 intrenable = intrstatus & core_pmcmask; 1560 1561 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 1562 (uintmax_t) intrstatus); 1563 1564 found_interrupt = 0; 1565 cc = core_pcpu[cpu]; 1566 1567 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 1568 1569 cc->pc_globalctrl &= ~intrenable; 1570 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 1571 1572 /* 1573 * Stop PMCs and clear overflow status bits. 1574 */ 1575 wrmsr(IA_GLOBAL_CTRL, 0); 1576 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 1577 IA_GLOBAL_STATUS_FLAG_OVFBUF | 1578 IA_GLOBAL_STATUS_FLAG_CONDCHG); 1579 1580 /* 1581 * Look for interrupts from fixed function PMCs. 1582 */ 1583 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 1584 n++, flag <<= 1) { 1585 1586 if ((intrstatus & flag) == 0) 1587 continue; 1588 1589 found_interrupt = 1; 1590 1591 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 1592 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 1593 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1594 continue; 1595 1596 error = pmc_process_interrupt(cpu, pm, tf, 1597 TRAPF_USERMODE(tf)); 1598 1599 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 1600 1601 /* Reload sampling count. */ 1602 wrmsr(IAF_CTR0 + n, v); 1603 1604 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 1605 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 1606 1607 if (error) 1608 intrenable &= ~flag; 1609 } 1610 1611 /* 1612 * Process interrupts from the programmable counters. 1613 */ 1614 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 1615 if ((intrstatus & flag) == 0) 1616 continue; 1617 1618 found_interrupt = 1; 1619 1620 pm = cc->pc_corepmcs[n].phw_pmc; 1621 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 1622 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1623 continue; 1624 1625 error = pmc_process_interrupt(cpu, pm, tf, 1626 TRAPF_USERMODE(tf)); 1627 if (error) 1628 intrenable &= ~flag; 1629 1630 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 1631 1632 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 1633 (uintmax_t) v); 1634 1635 /* Reload sampling count. */ 1636 wrmsr(IAP_PMC0 + n, v); 1637 } 1638 1639 /* 1640 * Reenable all non-stalled PMCs. 1641 */ 1642 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 1643 (uintmax_t) intrenable); 1644 1645 cc->pc_globalctrl |= intrenable; 1646 1647 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1648 1649 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 1650 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 1651 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 1652 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 1653 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 1654 1655 if (found_interrupt) 1656 pmc_x86_lapic_enable_pmc_interrupt(); 1657 1658 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 1659 &pmc_stats.pm_intr_ignored, 1); 1660 1661 return (found_interrupt); 1662} 1663 1664int 1665pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 1666{ 1667 int cpuid[CORE_CPUID_REQUEST_SIZE]; 1668 int ipa_version, flags, nflags; 1669 1670 do_cpuid(CORE_CPUID_REQUEST, cpuid); 1671 1672 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 1673 1674 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 1675 md->pmd_cputype, maxcpu, ipa_version); 1676 1677 if (ipa_version < 1 || ipa_version > 3) /* Unknown PMC architecture. */ 1678 return (EPROGMISMATCH); 1679 1680 core_cputype = md->pmd_cputype; 1681 1682 core_pmcmask = 0; 1683 1684 /* 1685 * Initialize programmable counters. 1686 */ 1687 KASSERT(ipa_version >= 1, 1688 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 1689 1690 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 1691 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 1692 1693 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 1694 1695 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 1696 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 1697 1698 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 1699 1700 /* 1701 * Initialize fixed function counters, if present. 1702 */ 1703 if (core_cputype != PMC_CPU_INTEL_CORE) { 1704 KASSERT(ipa_version >= 2, 1705 ("[core,%d] ipa_version %d too small", __LINE__, 1706 ipa_version)); 1707 1708 core_iaf_ri = core_iap_npmc; 1709 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 1710 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 1711 1712 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 1713 1714 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << 1715 IAF_OFFSET; 1716 1717 } 1718 1719 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 1720 core_iaf_ri); 1721 1722 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 1723 M_ZERO | M_WAITOK); 1724 1725 /* 1726 * Choose the appropriate interrupt handler. 1727 */ 1728 if (ipa_version == 1) 1729 md->pmd_intr = core_intr; 1730 else 1731 md->pmd_intr = core2_intr; 1732 1733 md->pmd_pcpu_fini = NULL; 1734 md->pmd_pcpu_init = NULL; 1735 1736 return (0); 1737} 1738 1739void 1740pmc_core_finalize(struct pmc_mdep *md) 1741{ 1742 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 1743 1744 free(core_pcpu, M_PMC); 1745 core_pcpu = NULL; 1746} 1747