hwpmc_amd.c revision 149360
165253Sache/*- 265253Sache * Copyright (c) 2003-2005 Joseph Koshy 365253Sache * All rights reserved. 465253Sache * 565253Sache * Redistribution and use in source and binary forms, with or without 665253Sache * modification, are permitted provided that the following conditions 765253Sache * are met: 865253Sache * 1. Redistributions of source code must retain the above copyright 965253Sache * notice, this list of conditions and the following disclaimer. 1065253Sache * 2. Redistributions in binary form must reproduce the above copyright 1165253Sache * notice, this list of conditions and the following disclaimer in the 1265253Sache * documentation and/or other materials provided with the distribution. 1365253Sache * 1465253Sache * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1565253Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1665253Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1765253Sache * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1865253Sache * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1965253Sache * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2065253Sache * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2165253Sache * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2265253Sache * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2365253Sache * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2465253Sache * SUCH DAMAGE. 2565253Sache * 2665253Sache */ 2765253Sache 2865253Sache#include <sys/cdefs.h> 2965253Sache__FBSDID("$FreeBSD: head/sys/dev/hwpmc/hwpmc_amd.c 149360 2005-08-22 02:59:51Z jkoshy $"); 3065253Sache 3165253Sache/* Support for the AMD K7 and later processors */ 3265253Sache 3365253Sache#include <sys/param.h> 3465253Sache#include <sys/lock.h> 3565253Sache#include <sys/malloc.h> 3665253Sache#include <sys/mutex.h> 3765253Sache#include <sys/pmc.h> 3865253Sache#include <sys/smp.h> 3965253Sache#include <sys/systm.h> 4065253Sache 4165253Sache#include <machine/cpufunc.h> 4265253Sache#include <machine/md_var.h> 4365253Sache#include <machine/pmc_mdep.h> 4465253Sache#include <machine/specialreg.h> 4565253Sache 4665253Sache#if DEBUG 4765253Sacheenum pmc_class amd_pmc_class; 4865253Sache#endif 4965253Sache 5065253Sache/* AMD K7 & K8 PMCs */ 5165253Sachestruct amd_descr { 5265253Sache struct pmc_descr pm_descr; /* "base class" */ 5365253Sache uint32_t pm_evsel; /* address of EVSEL register */ 5465253Sache uint32_t pm_perfctr; /* address of PERFCTR register */ 5565253Sache}; 5665253Sache 5765253Sachestatic struct amd_descr amd_pmcdesc[AMD_NPMCS] = 5865253Sache{ 5965253Sache { 6065253Sache .pm_descr = 6165253Sache { 6265253Sache .pd_name = "TSC", 6365253Sache .pd_class = PMC_CLASS_TSC, 6465253Sache .pd_caps = PMC_CAP_READ, 6565253Sache .pd_width = 64 6665253Sache }, 6765253Sache .pm_evsel = MSR_TSC, 6865253Sache .pm_perfctr = 0 /* unused */ 6965253Sache }, 7065253Sache 7165253Sache { 7265253Sache .pm_descr = 7365253Sache { 7465253Sache .pd_name = "", 7565253Sache .pd_class = -1, 7665253Sache .pd_caps = AMD_PMC_CAPS, 7765253Sache .pd_width = 48 7865253Sache }, 7965253Sache .pm_evsel = AMD_PMC_EVSEL_0, 8065253Sache .pm_perfctr = AMD_PMC_PERFCTR_0 8165253Sache }, 8265253Sache { 8365253Sache .pm_descr = 8465253Sache { 8565253Sache .pd_name = "", 8665253Sache .pd_class = -1, 8765253Sache .pd_caps = AMD_PMC_CAPS, 8865253Sache .pd_width = 48 8965253Sache }, 9065253Sache .pm_evsel = AMD_PMC_EVSEL_1, 9165253Sache .pm_perfctr = AMD_PMC_PERFCTR_1 9265253Sache }, 9365253Sache { 9465253Sache .pm_descr = 9565253Sache { 9665253Sache .pd_name = "", 9765253Sache .pd_class = -1, 9865253Sache .pd_caps = AMD_PMC_CAPS, 9965253Sache .pd_width = 48 10065253Sache }, 10165253Sache .pm_evsel = AMD_PMC_EVSEL_2, 10265253Sache .pm_perfctr = AMD_PMC_PERFCTR_2 10365253Sache }, 10465253Sache { 10565253Sache .pm_descr = 10665253Sache { 10765253Sache .pd_name = "", 10865253Sache .pd_class = -1, 10965253Sache .pd_caps = AMD_PMC_CAPS, 11065253Sache .pd_width = 48 11165253Sache }, 11265253Sache .pm_evsel = AMD_PMC_EVSEL_3, 11365253Sache .pm_perfctr = AMD_PMC_PERFCTR_3 11465253Sache } 11565253Sache}; 11665253Sache 11765253Sachestruct amd_event_code_map { 11865253Sache enum pmc_event pe_ev; /* enum value */ 11965253Sache uint8_t pe_code; /* encoded event mask */ 12065253Sache uint8_t pe_mask; /* bits allowed in unit mask */ 12165253Sache}; 12265253Sache 12365253Sacheconst struct amd_event_code_map amd_event_codes[] = { 12465253Sache#if defined(__i386__) /* 32 bit Athlon (K7) only */ 12565253Sache { PMC_EV_K7_DC_ACCESSES, 0x40, 0 }, 12665253Sache { PMC_EV_K7_DC_MISSES, 0x41, 0 }, 12765253Sache { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI }, 12865253Sache { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI }, 12965253Sache { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI }, 130 { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 }, 131 { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 }, 132 { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 }, 133 134 { PMC_EV_K7_IC_FETCHES, 0x80, 0 }, 135 { PMC_EV_K7_IC_MISSES, 0x81, 0 }, 136 137 { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 }, 138 { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 }, 139 140 { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 }, 141 { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 }, 142 { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 }, 143 { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 }, 144 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 }, 145 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 }, 146 { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 }, 147 { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 }, 148 { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 }, 149 { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 }, 150 { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 }, 151#endif 152 153 { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F }, 154 { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 }, 155 { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 }, 156 157 { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F }, 158 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE, 159 0x21, 0x00 }, 160 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 }, 161 { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 }, 162 { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 }, 163 { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 }, 164 { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 }, 165 { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 }, 166 167 { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 }, 168 { PMC_EV_K8_DC_MISS, 0x41, 0x00 }, 169 { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F }, 170 { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F }, 171 { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F }, 172 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 }, 173 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 }, 174 { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 }, 175 { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 }, 176 { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 }, 177 { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 }, 178 { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 }, 179 { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 }, 180 181 { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 }, 182 { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F }, 183 { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 }, 184 { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 }, 185 186 { PMC_EV_K8_IC_FETCH, 0x80, 0x00 }, 187 { PMC_EV_K8_IC_MISS, 0x81, 0x00 }, 188 { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 }, 189 { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 }, 190 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 }, 191 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 }, 192 { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 }, 193 { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 }, 194 { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 }, 195 { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 }, 196 197 { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 }, 198 { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 }, 199 { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 }, 200 { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 }, 201 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 }, 202 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 }, 203 { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 }, 204 { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 }, 205 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 }, 206 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 }, 207 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE, 208 0xCA, 0x00 }, 209 { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F }, 210 { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS, 211 0xCC, 0x07 }, 212 { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 }, 213 { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 }, 214 { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 }, 215 216 { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 }, 217 { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 }, 218 { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE, 219 0xD2, 0x00 }, 220 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 }, 221 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 }, 222 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL, 223 0xD5, 0x00 }, 224 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL, 225 0xD6, 0x00 }, 226 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 }, 227 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 }, 228 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET, 229 0xD9, 0x00 }, 230 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING, 231 0xDA, 0x00 }, 232 { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F }, 233 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 }, 234 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 }, 235 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 }, 236 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 }, 237 238 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 }, 239 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 }, 240 { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED, 241 0xE2, 0x00 }, 242 { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 }, 243 { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F }, 244 { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F }, 245 { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F }, 246 { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F }, 247 { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F }, 248 { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F } 249 250}; 251 252const int amd_event_codes_size = 253 sizeof(amd_event_codes) / sizeof(amd_event_codes[0]); 254 255/* 256 * read a pmc register 257 */ 258 259static int 260amd_read_pmc(int cpu, int ri, pmc_value_t *v) 261{ 262 enum pmc_mode mode; 263 const struct amd_descr *pd; 264 struct pmc *pm; 265 const struct pmc_hw *phw; 266 pmc_value_t tmp; 267 268 KASSERT(cpu >= 0 && cpu < mp_ncpus, 269 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 270 KASSERT(ri >= 0 && ri < AMD_NPMCS, 271 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 272 273 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri]; 274 pd = &amd_pmcdesc[ri]; 275 pm = phw->phw_pmc; 276 277 KASSERT(pm != NULL, 278 ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__, 279 cpu, ri)); 280 281 mode = PMC_TO_MODE(pm); 282 283 PMCDBG(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class); 284 285 /* Reading the TSC is a special case */ 286 if (pd->pm_descr.pd_class == PMC_CLASS_TSC) { 287 KASSERT(PMC_IS_COUNTING_MODE(mode), 288 ("[amd,%d] TSC counter in non-counting mode", __LINE__)); 289 *v = rdtsc(); 290 PMCDBG(MDP,REA,2,"amd-read id=%d -> %jd", ri, *v); 291 return 0; 292 } 293 294#if DEBUG 295 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 296 ("[amd,%d] unknown PMC class (%d)", __LINE__, 297 pd->pm_descr.pd_class)); 298#endif 299 300 tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */ 301 if (PMC_IS_SAMPLING_MODE(mode)) 302 *v = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 303 else 304 *v = tmp; 305 306 PMCDBG(MDP,REA,2,"amd-read id=%d -> %jd", ri, *v); 307 308 return 0; 309} 310 311/* 312 * Write a PMC MSR. 313 */ 314 315static int 316amd_write_pmc(int cpu, int ri, pmc_value_t v) 317{ 318 const struct amd_descr *pd; 319 struct pmc *pm; 320 const struct pmc_hw *phw; 321 enum pmc_mode mode; 322 323 KASSERT(cpu >= 0 && cpu < mp_ncpus, 324 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 325 KASSERT(ri >= 0 && ri < AMD_NPMCS, 326 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 327 328 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri]; 329 pd = &amd_pmcdesc[ri]; 330 pm = phw->phw_pmc; 331 332 KASSERT(pm != NULL, 333 ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__, 334 cpu, ri)); 335 336 mode = PMC_TO_MODE(pm); 337 338 if (pd->pm_descr.pd_class == PMC_CLASS_TSC) 339 return 0; 340 341#if DEBUG 342 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 343 ("[amd,%d] unknown PMC class (%d)", __LINE__, 344 pd->pm_descr.pd_class)); 345#endif 346 347 /* use 2's complement of the count for sampling mode PMCs */ 348 if (PMC_IS_SAMPLING_MODE(mode)) 349 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 350 351 PMCDBG(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v); 352 353 /* write the PMC value */ 354 wrmsr(pd->pm_perfctr, v); 355 return 0; 356} 357 358/* 359 * configure hardware pmc according to the configuration recorded in 360 * pmc 'pm'. 361 */ 362 363static int 364amd_config_pmc(int cpu, int ri, struct pmc *pm) 365{ 366 struct pmc_hw *phw; 367 368 PMCDBG(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 369 370 KASSERT(cpu >= 0 && cpu < mp_ncpus, 371 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 372 KASSERT(ri >= 0 && ri < AMD_NPMCS, 373 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 374 375 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri]; 376 377 KASSERT(pm == NULL || phw->phw_pmc == NULL, 378 ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 379 __LINE__, pm, phw->phw_pmc)); 380 381 phw->phw_pmc = pm; 382 return 0; 383} 384 385/* 386 * Retrieve a configured PMC pointer from hardware state. 387 */ 388 389static int 390amd_get_config(int cpu, int ri, struct pmc **ppm) 391{ 392 *ppm = pmc_pcpu[cpu]->pc_hwpmcs[ri]->phw_pmc; 393 394 return 0; 395} 396 397/* 398 * Machine dependent actions taken during the context switch in of a 399 * thread. 400 */ 401 402static int 403amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 404{ 405 (void) pc; 406 407 PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 408 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0); 409 410 /* enable the RDPMC instruction if needed */ 411 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 412 load_cr4(rcr4() | CR4_PCE); 413 414 return 0; 415} 416 417/* 418 * Machine dependent actions taken during the context switch out of a 419 * thread. 420 */ 421 422static int 423amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 424{ 425 (void) pc; 426 (void) pp; /* can be NULL */ 427 428 PMCDBG(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ? 429 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0); 430 431 /* always turn off the RDPMC instruction */ 432 load_cr4(rcr4() & ~CR4_PCE); 433 434 return 0; 435} 436 437/* 438 * Check if a given allocation is feasible. 439 */ 440 441static int 442amd_allocate_pmc(int cpu, int ri, struct pmc *pm, 443 const struct pmc_op_pmcallocate *a) 444{ 445 int i; 446 uint32_t allowed_unitmask, caps, config, unitmask; 447 enum pmc_event pe; 448 const struct pmc_descr *pd; 449 450 (void) cpu; 451 452 KASSERT(cpu >= 0 && cpu < mp_ncpus, 453 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 454 KASSERT(ri >= 0 && ri < AMD_NPMCS, 455 ("[amd,%d] illegal row index %d", __LINE__, ri)); 456 457 pd = &amd_pmcdesc[ri].pm_descr; 458 459 /* check class match */ 460 if (pd->pd_class != a->pm_class) 461 return EINVAL; 462 463 caps = pm->pm_caps; 464 465 PMCDBG(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps); 466 467 if ((pd->pd_caps & caps) != caps) 468 return EPERM; 469 if (pd->pd_class == PMC_CLASS_TSC) { 470 /* TSC's are always allocated in system-wide counting mode */ 471 if (a->pm_ev != PMC_EV_TSC_TSC || 472 a->pm_mode != PMC_MODE_SC) 473 return EINVAL; 474 return 0; 475 } 476 477#if __amd64__ 478 if (pd->pd_caps & PMC_CAP_INTERRUPT) 479 return EOPNOTSUPP; /* XXX avoid a processor double fault */ 480#endif 481 482#if DEBUG 483 KASSERT(pd->pd_class == amd_pmc_class, 484 ("[amd,%d] Unknown PMC class (%d)", __LINE__, pd->pd_class)); 485#endif 486 487 pe = a->pm_ev; 488 489 /* map ev to the correct event mask code */ 490 config = allowed_unitmask = 0; 491 for (i = 0; i < amd_event_codes_size; i++) 492 if (amd_event_codes[i].pe_ev == pe) { 493 config = 494 AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code); 495 allowed_unitmask = 496 AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask); 497 break; 498 } 499 if (i == amd_event_codes_size) 500 return EINVAL; 501 502 unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK; 503 if (unitmask & ~allowed_unitmask) /* disallow reserved bits */ 504 return EINVAL; 505 506 if (unitmask && (caps & PMC_CAP_QUALIFIER)) 507 config |= unitmask; 508 509 if (caps & PMC_CAP_THRESHOLD) 510 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK; 511 512 /* set at least one of the 'usr' or 'os' caps */ 513 if (caps & PMC_CAP_USER) 514 config |= AMD_PMC_USR; 515 if (caps & PMC_CAP_SYSTEM) 516 config |= AMD_PMC_OS; 517 if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0) 518 config |= (AMD_PMC_USR|AMD_PMC_OS); 519 520 if (caps & PMC_CAP_EDGE) 521 config |= AMD_PMC_EDGE; 522 if (caps & PMC_CAP_INVERT) 523 config |= AMD_PMC_INVERT; 524 if (caps & PMC_CAP_INTERRUPT) 525 config |= AMD_PMC_INT; 526 527 pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */ 528 529 PMCDBG(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config); 530 531 return 0; 532} 533 534/* 535 * Release machine dependent state associated with a PMC. This is a 536 * no-op on this architecture. 537 * 538 */ 539 540/* ARGSUSED0 */ 541static int 542amd_release_pmc(int cpu, int ri, struct pmc *pmc) 543{ 544#if DEBUG 545 const struct amd_descr *pd; 546#endif 547 struct pmc_hw *phw; 548 549 (void) pmc; 550 551 KASSERT(cpu >= 0 && cpu < mp_ncpus, 552 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 553 KASSERT(ri >= 0 && ri < AMD_NPMCS, 554 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 555 556 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri]; 557 558 KASSERT(phw->phw_pmc == NULL, 559 ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 560 561#if DEBUG 562 pd = &amd_pmcdesc[ri]; 563 if (pd->pm_descr.pd_class == amd_pmc_class) 564 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 565 ("[amd,%d] PMC %d released while active", __LINE__, ri)); 566#endif 567 568 return 0; 569} 570 571/* 572 * start a PMC. 573 */ 574 575static int 576amd_start_pmc(int cpu, int ri) 577{ 578 uint32_t config; 579 struct pmc *pm; 580 struct pmc_hw *phw; 581 const struct amd_descr *pd; 582 583 KASSERT(cpu >= 0 && cpu < mp_ncpus, 584 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 585 KASSERT(ri >= 0 && ri < AMD_NPMCS, 586 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 587 588 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri]; 589 pm = phw->phw_pmc; 590 pd = &amd_pmcdesc[ri]; 591 592 KASSERT(pm != NULL, 593 ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__, 594 cpu, ri)); 595 596 PMCDBG(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri); 597 598 if (pd->pm_descr.pd_class == PMC_CLASS_TSC) 599 return 0; /* TSCs are always running */ 600 601#if DEBUG 602 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 603 ("[amd,%d] unknown PMC class (%d)", __LINE__, 604 pd->pm_descr.pd_class)); 605#endif 606 607 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 608 ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__, 609 ri, cpu, pd->pm_descr.pd_name)); 610 611 /* turn on the PMC ENABLE bit */ 612 config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE; 613 614 PMCDBG(MDP,STA,2,"amd-start config=0x%x", config); 615 616 wrmsr(pd->pm_evsel, config); 617 return 0; 618} 619 620/* 621 * Stop a PMC. 622 */ 623 624static int 625amd_stop_pmc(int cpu, int ri) 626{ 627 struct pmc *pm; 628 struct pmc_hw *phw; 629 const struct amd_descr *pd; 630 uint64_t config; 631 632 KASSERT(cpu >= 0 && cpu < mp_ncpus, 633 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 634 KASSERT(ri >= 0 && ri < AMD_NPMCS, 635 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 636 637 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri]; 638 pm = phw->phw_pmc; 639 pd = &amd_pmcdesc[ri]; 640 641 KASSERT(pm != NULL, 642 ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__, 643 cpu, ri)); 644 645 /* can't stop a TSC */ 646 if (pd->pm_descr.pd_class == PMC_CLASS_TSC) 647 return 0; 648 649#if DEBUG 650 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 651 ("[amd,%d] unknown PMC class (%d)", __LINE__, 652 pd->pm_descr.pd_class)); 653#endif 654 655 KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel), 656 ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped", 657 __LINE__, ri, cpu, pd->pm_descr.pd_name)); 658 659 PMCDBG(MDP,STO,1,"amd-stop ri=%d", ri); 660 661 /* turn off the PMC ENABLE bit */ 662 config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE; 663 wrmsr(pd->pm_evsel, config); 664 return 0; 665} 666 667/* 668 * Interrupt handler. This function needs to return '1' if the 669 * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed 670 * to sleep or do anything a 'fast' interrupt handler is not allowed 671 * to do. 672 */ 673 674static int 675amd_intr(int cpu, uintptr_t eip, int usermode) 676{ 677 int i, error, retval, ri; 678 uint32_t config, evsel, perfctr; 679 struct pmc *pm; 680 struct pmc_cpu *pc; 681 struct pmc_hw *phw; 682 pmc_value_t v; 683 684 KASSERT(cpu >= 0 && cpu < mp_ncpus, 685 ("[amd,%d] out of range CPU %d", __LINE__, cpu)); 686 687 PMCDBG(MDP,INT,1, "cpu=%d eip=%p um=%d", cpu, (void *) eip, 688 usermode); 689 690 retval = 0; 691 692 pc = pmc_pcpu[cpu]; 693 694 /* 695 * look for all PMCs that have interrupted: 696 * - skip over the TSC [PMC#0] 697 * - look for a running, sampling PMC which has overflowed 698 * and which has a valid 'struct pmc' association 699 * 700 * If found, we call a helper to process the interrupt. 701 */ 702 703 for (i = 0; i < AMD_NPMCS-1; i++) { 704 705 ri = i + 1; /* row index; TSC is at ri == 0 */ 706 707 if (!AMD_PMC_HAS_OVERFLOWED(i)) 708 continue; 709 710 phw = pc->pc_hwpmcs[ri]; 711 712 KASSERT(phw != NULL, ("[amd,%d] null PHW pointer", __LINE__)); 713 714 if ((pm = phw->phw_pmc) == NULL || 715 pm->pm_state != PMC_STATE_RUNNING || 716 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 717 continue; 718 } 719 720 /* stop the PMC, reload count */ 721 evsel = AMD_PMC_EVSEL_0 + i; 722 perfctr = AMD_PMC_PERFCTR_0 + i; 723 v = pm->pm_sc.pm_reloadcount; 724 config = rdmsr(evsel); 725 726 KASSERT((config & ~AMD_PMC_ENABLE) == 727 (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE), 728 ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__, 729 config, pm->pm_md.pm_amd.pm_amd_evsel)); 730 731 wrmsr(evsel, config & ~AMD_PMC_ENABLE); 732 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); 733 734 /* restart if there was no error during logging */ 735 error = pmc_process_interrupt(cpu, pm, eip, usermode); 736 if (error == 0) 737 wrmsr(evsel, config | AMD_PMC_ENABLE); 738 739 retval = 1; /* found an interrupting PMC */ 740 } 741 742 atomic_add_int(retval ? &pmc_stats.pm_intr_processed : 743 &pmc_stats.pm_intr_ignored, 1); 744 745 return retval; 746} 747 748/* 749 * describe a PMC 750 */ 751static int 752amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 753{ 754 int error; 755 size_t copied; 756 const struct amd_descr *pd; 757 struct pmc_hw *phw; 758 759 KASSERT(cpu >= 0 && cpu < mp_ncpus, 760 ("[amd,%d] illegal CPU %d", __LINE__, cpu)); 761 KASSERT(ri >= 0 && ri < AMD_NPMCS, 762 ("[amd,%d] row-index %d out of range", __LINE__, ri)); 763 764 phw = pmc_pcpu[cpu]->pc_hwpmcs[ri]; 765 pd = &amd_pmcdesc[ri]; 766 767 if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name, 768 PMC_NAME_MAX, &copied)) != 0) 769 return error; 770 771 pi->pm_class = pd->pm_descr.pd_class; 772 773 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 774 pi->pm_enabled = TRUE; 775 *ppmc = phw->phw_pmc; 776 } else { 777 pi->pm_enabled = FALSE; 778 *ppmc = NULL; 779 } 780 781 return 0; 782} 783 784/* 785 * i386 specific entry points 786 */ 787 788/* 789 * return the MSR address of the given PMC. 790 */ 791 792static int 793amd_get_msr(int ri, uint32_t *msr) 794{ 795 KASSERT(ri >= 0 && ri < AMD_NPMCS, 796 ("[amd,%d] ri %d out of range", __LINE__, ri)); 797 798 *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; 799 return 0; 800} 801 802/* 803 * processor dependent initialization. 804 */ 805 806/* 807 * Per-processor data structure 808 * 809 * [common stuff] 810 * [5 struct pmc_hw pointers] 811 * [5 struct pmc_hw structures] 812 */ 813 814struct amd_cpu { 815 struct pmc_cpu pc_common; 816 struct pmc_hw *pc_hwpmcs[AMD_NPMCS]; 817 struct pmc_hw pc_amdpmcs[AMD_NPMCS]; 818}; 819 820 821static int 822amd_init(int cpu) 823{ 824 int n; 825 struct amd_cpu *pcs; 826 struct pmc_hw *phw; 827 828 KASSERT(cpu >= 0 && cpu < mp_ncpus, 829 ("[amd,%d] insane cpu number %d", __LINE__, cpu)); 830 831 PMCDBG(MDP,INI,1,"amd-init cpu=%d", cpu); 832 833 MALLOC(pcs, struct amd_cpu *, sizeof(struct amd_cpu), M_PMC, 834 M_WAITOK|M_ZERO); 835 836 phw = &pcs->pc_amdpmcs[0]; 837 838 /* 839 * Initialize the per-cpu mutex and set the content of the 840 * hardware descriptors to a known state. 841 */ 842 843 for (n = 0; n < AMD_NPMCS; n++, phw++) { 844 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 845 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); 846 phw->phw_pmc = NULL; 847 pcs->pc_hwpmcs[n] = phw; 848 } 849 850 /* Mark the TSC as shareable */ 851 pcs->pc_hwpmcs[0]->phw_state |= PMC_PHW_FLAG_IS_SHAREABLE; 852 853 pmc_pcpu[cpu] = (struct pmc_cpu *) pcs; 854 855 return 0; 856} 857 858 859/* 860 * processor dependent cleanup prior to the KLD 861 * being unloaded 862 */ 863 864static int 865amd_cleanup(int cpu) 866{ 867 int i; 868 uint32_t evsel; 869 struct pmc_cpu *pcs; 870 871 KASSERT(cpu >= 0 && cpu < mp_ncpus, 872 ("[amd,%d] insane cpu number (%d)", __LINE__, cpu)); 873 874 PMCDBG(MDP,INI,1,"amd-cleanup cpu=%d", cpu); 875 876 /* 877 * First, turn off all PMCs on this CPU. 878 */ 879 880 for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */ 881 evsel = rdmsr(AMD_PMC_EVSEL_0 + i); 882 evsel &= ~AMD_PMC_ENABLE; 883 wrmsr(AMD_PMC_EVSEL_0 + i, evsel); 884 } 885 886 /* 887 * Next, free up allocated space. 888 */ 889 890 if ((pcs = pmc_pcpu[cpu]) == NULL) 891 return 0; 892 893#if DEBUG 894 /* check the TSC */ 895 KASSERT(pcs->pc_hwpmcs[0]->phw_pmc == NULL, 896 ("[amd,%d] CPU%d,PMC0 still in use", __LINE__, cpu)); 897 for (i = 1; i < AMD_NPMCS; i++) { 898 KASSERT(pcs->pc_hwpmcs[i]->phw_pmc == NULL, 899 ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i)); 900 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + (i-1)), 901 ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i)); 902 } 903#endif 904 905 pmc_pcpu[cpu] = NULL; 906 FREE(pcs, M_PMC); 907 return 0; 908} 909 910/* 911 * Initialize ourselves. 912 */ 913 914struct pmc_mdep * 915pmc_amd_initialize(void) 916{ 917 enum pmc_cputype cputype; 918 enum pmc_class class; 919 struct pmc_mdep *pmc_mdep; 920 char *name; 921 int i; 922 923 /* 924 * The presence of hardware performance counters on the AMD 925 * Athlon, Duron or later processors, is _not_ indicated by 926 * any of the processor feature flags set by the 'CPUID' 927 * instruction, so we only check the 'instruction family' 928 * field returned by CPUID for instruction family >= 6. 929 */ 930 931 class = cputype = -1; 932 name = NULL; 933 switch (cpu_id & 0xF00) { 934 case 0x600: /* Athlon(tm) processor */ 935 cputype = PMC_CPU_AMD_K7; 936 class = PMC_CLASS_K7; 937 name = "K7"; 938 break; 939 case 0xF00: /* Athlon64/Opteron processor */ 940 cputype = PMC_CPU_AMD_K8; 941 class = PMC_CLASS_K8; 942 name = "K8"; 943 break; 944 } 945 946 if ((int) cputype == -1) { 947 (void) printf("pmc: Unknown AMD CPU.\n"); 948 return NULL; 949 } 950 951#if DEBUG 952 amd_pmc_class = class; 953#endif 954 955 MALLOC(pmc_mdep, struct pmc_mdep *, sizeof(struct pmc_mdep), 956 M_PMC, M_WAITOK|M_ZERO); 957 958 pmc_mdep->pmd_cputype = cputype; 959 pmc_mdep->pmd_npmc = AMD_NPMCS; 960 961 /* this processor has two classes of usable PMCs */ 962 pmc_mdep->pmd_nclass = 2; 963 964 /* TSC */ 965 pmc_mdep->pmd_classes[0].pm_class = PMC_CLASS_TSC; 966 pmc_mdep->pmd_classes[0].pm_caps = PMC_CAP_READ; 967 pmc_mdep->pmd_classes[0].pm_width = 64; 968 969 /* AMD K7/K8 PMCs */ 970 pmc_mdep->pmd_classes[1].pm_class = class; 971 pmc_mdep->pmd_classes[1].pm_caps = AMD_PMC_CAPS; 972 pmc_mdep->pmd_classes[1].pm_width = 48; 973 974 pmc_mdep->pmd_nclasspmcs[0] = 1; 975 pmc_mdep->pmd_nclasspmcs[1] = (AMD_NPMCS-1); 976 977 /* fill in the correct pmc name and class */ 978 for (i = 1; i < AMD_NPMCS; i++) { 979 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name, 980 sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d", 981 name, i-1); 982 amd_pmcdesc[i].pm_descr.pd_class = class; 983 } 984 985 pmc_mdep->pmd_init = amd_init; 986 pmc_mdep->pmd_cleanup = amd_cleanup; 987 pmc_mdep->pmd_switch_in = amd_switch_in; 988 pmc_mdep->pmd_switch_out = amd_switch_out; 989 pmc_mdep->pmd_read_pmc = amd_read_pmc; 990 pmc_mdep->pmd_write_pmc = amd_write_pmc; 991 pmc_mdep->pmd_config_pmc = amd_config_pmc; 992 pmc_mdep->pmd_get_config = amd_get_config; 993 pmc_mdep->pmd_allocate_pmc = amd_allocate_pmc; 994 pmc_mdep->pmd_release_pmc = amd_release_pmc; 995 pmc_mdep->pmd_start_pmc = amd_start_pmc; 996 pmc_mdep->pmd_stop_pmc = amd_stop_pmc; 997 pmc_mdep->pmd_intr = amd_intr; 998 pmc_mdep->pmd_describe = amd_describe; 999 pmc_mdep->pmd_get_msr = amd_get_msr; /* i386 */ 1000 1001 PMCDBG(MDP,INI,0,"%s","amd-initialize"); 1002 1003 return pmc_mdep; 1004} 1005