him.h revision 281957 
1/* $Id: him.h,v 1.57 2011/02/21 06:03:21 zsf Exp $ */
2/*-
3 * Copyright (C) 2004-2005 HighPoint Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/10/sys/dev/hptnr/him.h 281957 2015-04-25 00:32:47Z delphij $
28 */
29#include <dev/hptnr/hptnr_config.h>
30#ifndef _HPT_HIM_H_
31#define _HPT_HIM_H_
32
33#define VERMAGIC_HIM 55
34
35#if defined(__cplusplus)
36extern "C" {
37#endif
38
39#include <dev/hptnr/list.h>
40
41#define SECTOR_TO_BYTE_SHIFT 9
42#define SECTOR_TO_BYTE(x)       ((HPT_U32)(x) << SECTOR_TO_BYTE_SHIFT)
43#define BYTE_TO_SECTOR(x)       ((x)>>SECTOR_TO_BYTE_SHIFT)
44
45typedef struct _PCI_ID
46{
47	HPT_U16 vid;
48	HPT_U16 did;
49	HPT_U32 subsys;
50	HPT_U8  rev;
51	HPT_U8  nbase;
52	HPT_U16 reserve;
53}
54PCI_ID;
55
56typedef struct _PCI_ADDRESS
57{
58	HPT_U8 tree;
59	HPT_U8 bus;
60	HPT_U8 device;
61	HPT_U8 function;
62}
63PCI_ADDRESS;
64
65typedef struct _HIM_ADAPTER_CONFIG
66{
67	PCI_ADDRESS pci_addr;
68	PCI_ID  pci_id;
69
70	HPT_U8  max_devices;
71
72	HPT_U8  bProbeInInitializing:1;
73
74	HPT_U8  bSpinupOneDevEachTime:1;
75
76	HPT_U8  bGlobalNcq:1;
77	HPT_U8  bSGPIOPartSupport:1;
78
79	HPT_U8  bNeedSASIdleTimer:1;
80	HPT_U8  reserved:3;
81
82	HPT_U8  bDevsPerBus;
83	HPT_U8  first_on_slot;
84
85	HPT_U8  bChipType;
86	HPT_U8  bChipIntrNum;
87	HPT_U8  bChipFlags;
88	HPT_U8  bNumBuses;
89
90	HPT_U8  szVendorID[36];
91	HPT_U8  szProductID[36];
92	HPT_U32 nvramSize;
93	HPT_U64 nvramAddress;
94	HPT_U8  slot_index;
95	HPT_U8  maxWidth;
96	HPT_U8  currentWidth;
97	HPT_U8  maxSpeed;
98	HPT_U8  currentSpeed;
99	HPT_U8  reserved2[7];
100}
101HIM_ADAPTER_CONFIG, *PHIM_ADAPTER_CONFIG;
102
103typedef struct _HIM_CHANNEL_CONFIG
104{
105	HPT_U32 io_port;
106	HPT_U32 ctl_port;
107} HIM_CHANNEL_CONFIG, *PHIM_CHANNEL_CONFIG;
108
109typedef struct _HIM_DEVICE_FLAGS
110{
111	HPT_UINT df_atapi               :1;
112	HPT_UINT df_removable_drive     :1;
113	HPT_UINT df_on_line             :1;
114	HPT_UINT df_reduce_mode         :1;
115	HPT_UINT df_sata                :1;
116	HPT_UINT df_on_pm_port          :1;
117	HPT_UINT df_support_read_ahead  :1;
118	HPT_UINT df_read_ahead_enabled  :1;
119	HPT_UINT df_support_write_cache :1;
120	HPT_UINT df_write_cache_enabled :1;
121	HPT_UINT df_cdrom_device        :1;
122	HPT_UINT df_tape_device         :1;
123	HPT_UINT df_support_tcq         :1;
124	HPT_UINT df_tcq_enabled         :1;
125	HPT_UINT df_support_ncq         :1;
126	HPT_UINT df_ncq_enabled         :1;
127	HPT_UINT df_sas                 :1;
128	HPT_UINT df_in_enclosure        :1;
129	HPT_UINT df_ssd                 :1;
130} DEVICE_FLAGS, *PDEVICE_FLAGS;
131
132#pragma pack(1)
133typedef struct _IDENTIFY_DATA {
134	HPT_U16 GeneralConfiguration;
135	HPT_U16 NumberOfCylinders;
136	HPT_U16 Reserved1;
137	HPT_U16 NumberOfHeads;
138	HPT_U16 UnformattedBytesPerTrack;
139	HPT_U16 UnformattedBytesPerSector;
140	HPT_U8  SasAddress[8];
141	HPT_U16 SerialNumber[10];
142	HPT_U16 BufferType;
143	HPT_U16 BufferSectorSize;
144	HPT_U16 NumberOfEccBytes;
145	HPT_U16 FirmwareRevision[4];
146	HPT_U16 ModelNumber[20];
147	HPT_U8  MaximumBlockTransfer;
148	HPT_U8  VendorUnique2;
149	HPT_U16 DoubleWordIo;
150	HPT_U16 Capabilities;
151	HPT_U16 Reserved2;
152	HPT_U8  VendorUnique3;
153	HPT_U8  PioCycleTimingMode;
154	HPT_U8  VendorUnique4;
155	HPT_U8  DmaCycleTimingMode;
156	HPT_U16 TranslationFieldsValid;
157	HPT_U16 NumberOfCurrentCylinders;
158	HPT_U16 NumberOfCurrentHeads;
159	HPT_U16 CurrentSectorsPerTrack;
160	HPT_U32 CurrentSectorCapacity;
161	HPT_U16 CurrentMultiSectorSetting;
162	HPT_U32 UserAddressableSectors;
163	HPT_U8  SingleWordDMASupport;
164	HPT_U8  SingleWordDMAActive;
165	HPT_U8  MultiWordDMASupport;
166	HPT_U8  MultiWordDMAActive;
167	HPT_U8  AdvancedPIOModes;
168	HPT_U8  Reserved4;
169	HPT_U16 MinimumMWXferCycleTime;
170	HPT_U16 RecommendedMWXferCycleTime;
171	HPT_U16 MinimumPIOCycleTime;
172	HPT_U16 MinimumPIOCycleTimeIORDY;
173	HPT_U16 Reserved5[2];
174	HPT_U16 ReleaseTimeOverlapped;
175	HPT_U16 ReleaseTimeServiceCommand;
176	HPT_U16 MajorRevision;
177	HPT_U16 MinorRevision;
178	HPT_U16 MaxQueueDepth;
179	HPT_U16 SataCapability;
180	HPT_U16 Reserved6[9];
181	HPT_U16 CommandSupport;
182	HPT_U16 CommandEnable;
183	HPT_U16 UtralDmaMode;
184	HPT_U16 Reserved7[11];
185	HPT_U32 Lba48BitLow;
186	HPT_U32 Lba48BitHigh;
187	HPT_U16 Reserved8[23];
188	HPT_U16 SpecialFunctionsEnabled;
189	HPT_U16 Reserved9[128];
190}
191#ifdef __GNUC__
192__attribute__((packed))
193#endif
194IDENTIFY_DATA, *PIDENTIFY_DATA;
195#pragma pack()
196
197typedef struct _HIM_DEVICE_CONFIG
198{
199	HPT_U64 capacity;
200	HPT_U32 logical_sector_size;
201
202	DEVICE_FLAGS flags;
203
204	HPT_U8  path_id;
205	HPT_U8  target_id;
206	HPT_U8  max_queue_depth;
207	HPT_U8  spin_up_mode;
208
209	HPT_U8  reserved;
210	HPT_U8  transfer_mode;
211	HPT_U8  bMaxShowMode;
212	HPT_U8  bDeUsable_Mode;
213
214	HPT_U16 max_sectors_per_cmd;
215
216	PIDENTIFY_DATA pIdentifyData;
217
218
219	HPT_U8  fixed_path_id; /*equals to phy id */
220}
221HIM_DEVICE_CONFIG, *PHIM_DEVICE_CONFIG;
222
223
224#define _DIT_MODE               0
225#define _DIT_601                1
226#define _DIT_READ_AHEAD         2
227#define _DIT_WRITE_CACHE        3
228#define _DIT_TCQ                4
229#define _DIT_NCQ                5
230#define _DIT_BEEP_OFF           6
231#define _DIT_SPIN_UP_MODE       7
232#define _DIT_IDLE_STANDBY       8
233#define _DIT_IDENTIFY           9
234
235#define SPIN_UP_MODE_NOSUPPORT 0
236#define SPIN_UP_MODE_FULL      1
237#define SPIN_UP_MODE_STANDBY   2
238
239struct tcq_control {
240	HPT_U8 enable;
241	HPT_U8 depth;
242};
243
244struct ncq_control {
245	HPT_U8 enable;
246	HPT_U8 depth;
247};
248
249typedef struct _HIM_ALTERABLE_DEV_INFO{
250	HPT_U8 type;
251	union {
252		HPT_U8 mode;
253		HPT_U8 enable_read_ahead;
254		HPT_U8 enable_read_cache;
255		HPT_U8 enable_write_cache;
256		struct tcq_control tcq;
257		struct ncq_control ncq;
258		void * adapter;
259		HPT_U8 spin_up_mode;
260		HPT_U8 idle_standby_timeout;
261		HPT_U8 identify_indicator;
262	}u;
263} HIM_ALTERABLE_DEV_INFO, *PHIM_ALTERABLE_DEV_INFO;
264
265struct _COMMAND;
266struct _IOCTL_ARG;
267
268typedef void (*PROBE_CALLBACK)(void *arg, void *dev, int index);
269
270typedef struct _HIM {
271	char *name;
272	struct _HIM *next;
273	HPT_UINT max_sg_descriptors;
274	#define _HIM_INTERFACE(_type, _fn, _args) _type (* _fn) _args;
275	#include <dev/hptnr/himfuncs.h>
276}
277HIM, *PHIM;
278
279
280#pragma pack(1)
281#ifdef SG_FLAG_EOT
282#error "don't use SG_FLAG_EOT with _SG.eot. clean the code!"
283#endif
284
285typedef struct _SG {
286	HPT_U32 size;
287	HPT_UINT eot;
288	union {
289		HPT_U8 FAR * _logical;
290		BUS_ADDRESS bus;
291	}
292	addr;
293}
294SG, *PSG;
295#pragma pack()
296
297typedef struct _AtaCommand
298{
299    HPT_U64     Lba;
300    HPT_U16     nSectors;
301    HPT_U16     pad;
302} AtaComm, *PAtaComm;
303
304#define ATA_CMD_NOP          0x0
305
306#define ATA_CMD_SET_FEATURES    0xef
307#define ATA_CMD_FLUSH           0xE7
308#define ATA_CMD_VERIFY          0x40
309#define ATA_CMD_STANDBY         0xe2
310#define ATA_CMD_READ_MULTI      0xC4
311#define ATA_CMD_READ_MULTI_EXT  0x29
312#define ATA_CMD_WRITE_MULTI     0xC5
313#define ATA_CMD_WRITE_MULTI_EXT 0x39
314#define ATA_CMD_WRITE_MULTI_FUA_EXT     0xCE
315
316#define ATA_CMD_READ_DMA        0xc8  /* IDE DMA read command           */
317#define ATA_CMD_WRITE_DMA       0xca  /* IDE DMA write command          */
318#define ATA_CMD_READ_DMA_EXT        0x25
319#define ATA_CMD_READ_QUEUE_EXT      0x26
320#define ATA_CMD_READ_MAX_ADDR       0x27
321#define ATA_CMD_READ_EXT            0x24
322#define ATA_CMD_VERIFY_EXT          0x42
323#define ATA_CMD_WRITE_DMA_EXT       0x35
324#define ATA_CMD_WRITE_QUEUE_EXT     0x36
325#define ATA_CMD_WRITE_EXT           0x34
326
327#define ATA_SET_FEATURES_XFER 0x3
328#define ATA_SECTOR_SIZE 512
329
330typedef struct _PassthroughCmd {
331	HPT_U16    bFeaturesReg;
332	HPT_U16    bSectorCountReg;
333	HPT_U16    bLbaLowReg;
334	HPT_U16    bLbaMidReg;
335	HPT_U16    bLbaHighReg;
336	HPT_U8     bDriveHeadReg;
337	HPT_U8     bCommandReg;
338	HPT_U16    nSectors;
339	HPT_U8    *pDataBuffer;
340}
341PassthroughCmd;
342
343typedef struct _ScsiComm {
344	HPT_U8  cdbLength;
345	HPT_U8  senseLength;
346	HPT_U8  scsiStatus;
347	HPT_U8  reserve1;
348	HPT_U32 dataLength;
349	HPT_U8 cdb[16];
350	HPT_U8 *senseBuffer;
351}
352ScsiComm;
353
354
355#define CTRL_CMD_REBUILD 1
356#define CTRL_CMD_VERIFY  2
357#define CTRL_CMD_INIT    3
358
359
360typedef struct _R5ControlCmd {
361	HPT_U64  StripeLine;
362	HPT_U16 Offset;
363	HPT_U8  Command;
364	HPT_U8  CmdTarget;
365}
366R5ControlCmd, *PR5ControlCmd;
367
368typedef struct _HPT_ADDRESS
369{
370	HPT_U8 * logical;
371	BUS_ADDRESS bus;
372}
373HPT_ADDRESS;
374
375
376typedef struct ctl_pages {
377	HPT_ADDRESS *pages;
378	HPT_UINT        page_size;
379	HPT_UINT        npages;
380	HPT_UINT min_sg_descriptors;
381} CONTROL_PAGES, *PCONTROL_PAGES;
382
383typedef struct _R1ControlCmd {
384	HPT_U64  Lba;
385	HPT_U16 nSectors;
386	HPT_U8  Command;
387	HPT_U8  CmdTarget;
388	PCONTROL_PAGES ctl_pages;
389}
390R1ControlCmd, *PR1ControlCmd;
391
392typedef void (*TQ_PROC)(void *arg);
393
394struct tq_item {
395	TQ_PROC proc;
396	void *arg;
397	struct tq_item *next;
398};
399
400#define INIT_TQ_ITEM(t, p, a) \
401	do { (t)->proc = p; (t)->arg = a; (t)->next = 0; } while (0)
402
403typedef struct _COMMAND
404{
405
406	struct _VBUS * vbus;
407
408	struct freelist *grplist;
409	HPT_UINT grpcnt;
410
411
412	struct list_head q_link;
413	struct tq_item done_dpc;
414
415	HPT_UINT extsize;
416	void *ext;
417
418
419
420	void *target;
421	void *priv;
422	HPT_UPTR priv2;
423
424	int priority;
425	struct lock_request *owned_lock;
426	struct lock_request *lock_req;
427	void (*dtor)(struct _COMMAND *, void *);
428	void *dtor_arg;
429
430	union{
431		AtaComm Ide;
432		PassthroughCmd Passthrough;
433		ScsiComm Scsi;
434		R5ControlCmd R5Control;
435		R1ControlCmd R1Control;
436	} uCmd;
437
438	HPT_U8 type; /* CMD_TYPE_* */
439
440	struct {
441		HPT_U8  physical_sg: 1;
442		HPT_U8  data_in: 1;
443		HPT_U8  data_out: 1;
444		HPT_U8  transform : 1;
445		HPT_U8  hard_flush: 2;
446		HPT_U8  from_cc: 1;
447		HPT_U8  force_cc: 1;
448	} flags;
449
450	/* return status */
451	HPT_U8  Result;
452	/* retry count */
453	HPT_U8  RetryCount;
454
455
456	PSG psg;
457
458
459	int  (*buildsgl)(struct _COMMAND *cmd, PSG psg, int logical);
460	void (*done)(struct _COMMAND *cmd);
461}
462COMMAND, *PCOMMAND;
463
464/* command types */
465#define   CMD_TYPE_IO           0
466#define   CMD_TYPE_CONTROL      1
467#define   CMD_TYPE_ATAPI        2
468#define   CMD_TYPE_SCSI         CMD_TYPE_ATAPI
469#define   CMD_TYPE_PASSTHROUGH  3
470#define   CMD_TYPE_FLUSH        4
471#define   CMD_TYPE_IO_INDIRECT  0x80
472
473/* flush command flags */
474#define   CF_HARD_FLUSH_CACHE   1
475#define   CF_HARD_FLUSH_STANDBY 2
476
477/* command return values */
478#define   RETURN_PENDING             0
479#define   RETURN_SUCCESS             1
480#define   RETURN_BAD_DEVICE          2
481#define   RETURN_BAD_PARAMETER       3
482#define   RETURN_WRITE_NO_DRQ        4
483#define   RETURN_DEVICE_BUSY         5
484#define   RETURN_INVALID_REQUEST     6
485#define   RETURN_SELECTION_TIMEOUT   7
486#define   RETURN_IDE_ERROR           8
487#define   RETURN_NEED_LOGICAL_SG     9
488#define   RETURN_NEED_PHYSICAL_SG    10
489#define   RETURN_RETRY               11
490#define   RETURN_DATA_ERROR          12
491#define   RETURN_BUS_RESET           13
492#define   RETURN_BAD_TRANSFER_LENGTH 14
493#define   RETURN_INSUFFICIENT_MEMORY 15
494#define   RETURN_SECTOR_ERROR        16
495#define   RETURN_NEED_SPINUP         17
496
497#if defined(__cplusplus)
498}
499#endif
500#endif
501