hpt27xx_os_bsd.c revision 285830
1207753Smm/*- 2207753Smm * HighPoint RAID Driver for FreeBSD 3207753Smm * 4207753Smm * Copyright (C) 2005-2011 HighPoint Technologies, Inc. All Rights Reserved. 5207753Smm * All rights reserved. 6207753Smm * 7207753Smm * Redistribution and use in source and binary forms, with or without 8207753Smm * modification, are permitted provided that the following conditions 9207753Smm * are met: 10207753Smm * 1. Redistributions of source code must retain the above copyright 11207753Smm * notice, this list of conditions and the following disclaimer. 12207753Smm * 2. Redistributions in binary form must reproduce the above copyright 13207753Smm * notice, this list of conditions and the following disclaimer in the 14207753Smm * documentation and/or other materials provided with the distribution. 15207753Smm * 16207753Smm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17207753Smm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18207753Smm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19207753Smm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20207753Smm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21207753Smm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22207753Smm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23207753Smm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24207753Smm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25207753Smm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26207753Smm * SUCH DAMAGE. 27207753Smm * 28207753Smm * $FreeBSD: releng/10.2/sys/dev/hpt27xx/hpt27xx_os_bsd.c 284879 2015-06-26 19:55:01Z delphij $ 29207753Smm */ 30207753Smm 31207753Smm#include <dev/hpt27xx/hpt27xx_config.h> 32207753Smm 33207753Smm#include <dev/hpt27xx/os_bsd.h> 34207753Smm 35207753SmmBUS_ADDRESS get_dmapool_phy_addr(void *osext, void * dmapool_virt_addr); 36207753Smm 37207753Smm/* hardware access */ 38207753SmmHPT_U8 os_inb (void *port) { return inb((unsigned)(HPT_UPTR)port); } 39207753SmmHPT_U16 os_inw (void *port) { return inw((unsigned)(HPT_UPTR)port); } 40207753SmmHPT_U32 os_inl (void *port) { return inl((unsigned)(HPT_UPTR)port); } 41207753Smm 42207753Smmvoid os_outb (void *port, HPT_U8 value) { outb((unsigned)(HPT_UPTR)port, (value)); } 43207753Smmvoid os_outw (void *port, HPT_U16 value) { outw((unsigned)(HPT_UPTR)port, (value)); } 44207753Smmvoid os_outl (void *port, HPT_U32 value) { outl((unsigned)(HPT_UPTR)port, (value)); } 45207753Smm 46207753Smmvoid os_insw (void *port, HPT_U16 *buffer, HPT_U32 count) 47207753Smm{ insw((unsigned)(HPT_UPTR)port, (void *)buffer, count); } 48207753Smm 49207753Smmvoid os_outsw(void *port, HPT_U16 *buffer, HPT_U32 count) 50207753Smm{ outsw((unsigned)(HPT_UPTR)port, (void *)buffer, count); } 51207753Smm 52207753SmmHPT_U32 __dummy_reg = 0; 53207753Smm 54207753Smm/* PCI configuration space */ 55207753SmmHPT_U8 os_pci_readb (void *osext, HPT_U8 offset) 56207753Smm{ 57207753Smm return pci_read_config(((PHBA)osext)->pcidev, offset, 1); 58207753Smm} 59207753Smm 60278433SrpauloHPT_U16 os_pci_readw (void *osext, HPT_U8 offset) 61278433Srpaulo{ 62278433Srpaulo return pci_read_config(((PHBA)osext)->pcidev, offset, 2); 63278433Srpaulo} 64207753Smm 65207753SmmHPT_U32 os_pci_readl (void *osext, HPT_U8 offset) 66207753Smm{ 67207753Smm return pci_read_config(((PHBA)osext)->pcidev, offset, 4); 68207753Smm} 69207753Smm 70207753Smmvoid os_pci_writeb (void *osext, HPT_U8 offset, HPT_U8 value) 71207753Smm{ 72207753Smm pci_write_config(((PHBA)osext)->pcidev, offset, value, 1); 73207753Smm} 74207753Smm 75207753Smmvoid os_pci_writew (void *osext, HPT_U8 offset, HPT_U16 value) 76207753Smm{ 77207753Smm pci_write_config(((PHBA)osext)->pcidev, offset, value, 2); 78207753Smm} 79207753Smm 80207753Smmvoid os_pci_writel (void *osext, HPT_U8 offset, HPT_U32 value) 81207753Smm{ 82207753Smm pci_write_config(((PHBA)osext)->pcidev, offset, value, 4); 83207753Smm} 84207753Smm 85207753SmmBUS_ADDRESS get_dmapool_phy_addr(void *osext, void * dmapool_virt_addr) 86207753Smm{ 87278433Srpaulo return (BUS_ADDRESS)vtophys(dmapool_virt_addr); 88207753Smm} 89207753Smm 90207753Smm/* PCI space access */ 91207753SmmHPT_U8 pcicfg_read_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg) 92207753Smm{ 93207753Smm return (HPT_U8)pci_cfgregread(bus, dev, func, reg, 1); 94207753Smm} 95207753SmmHPT_U32 pcicfg_read_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg) 96207753Smm{ 97207753Smm return (HPT_U32)pci_cfgregread(bus, dev, func, reg, 4); 98207753Smm} 99207753Smmvoid pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v) 100207753Smm{ 101207753Smm pci_cfgregwrite(bus, dev, func, reg, v, 1); 102207753Smm} 103278433Srpaulovoid pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v) 104207753Smm{ 105207753Smm pci_cfgregwrite(bus, dev, func, reg, v, 4); 106207753Smm}/* PCI space access */ 107207753Smm 108207753Smmvoid *os_map_pci_bar( 109207753Smm void *osext, 110207753Smm int index, 111207753Smm HPT_U32 offset, 112207753Smm HPT_U32 length 113207753Smm) 114207753Smm{ 115207753Smm PHBA hba = (PHBA)osext; 116207753Smm HPT_U32 base; 117207753Smm 118207753Smm hba->pcibar[index].rid = 0x10 + index * 4; 119207753Smm base = pci_read_config(hba->pcidev, hba->pcibar[index].rid, 4); 120207753Smm 121207753Smm if (base & 1) { 122207753Smm hba->pcibar[index].type = SYS_RES_IOPORT; 123207753Smm hba->pcibar[index].res = bus_alloc_resource(hba->pcidev, 124207753Smm hba->pcibar[index].type, &hba->pcibar[index].rid, 0, ~0, length, RF_ACTIVE); 125207753Smm hba->pcibar[index].base = (void *)(unsigned long)(base & ~0x1); 126207753Smm } else { 127207753Smm hba->pcibar[index].type = SYS_RES_MEMORY; 128207753Smm hba->pcibar[index].res = bus_alloc_resource(hba->pcidev, 129207753Smm hba->pcibar[index].type, &hba->pcibar[index].rid, 0, ~0, length, RF_ACTIVE); 130207753Smm hba->pcibar[index].base = (char *)rman_get_virtual(hba->pcibar[index].res) + offset; 131207753Smm } 132207753Smm 133207753Smm return hba->pcibar[index].base; 134207753Smm} 135207753Smm 136207753Smmvoid os_unmap_pci_bar(void *osext, void *base) 137207753Smm{ 138207753Smm PHBA hba = (PHBA)osext; 139207753Smm int index; 140207753Smm 141207753Smm for (index=0; index<6; index++) { 142207753Smm if (hba->pcibar[index].base==base) { 143207753Smm bus_release_resource(hba->pcidev, hba->pcibar[index].type, 144207753Smm hba->pcibar[index].rid, hba->pcibar[index].res); 145207753Smm hba->pcibar[index].base = 0; 146207753Smm return; 147207753Smm } 148207753Smm } 149207753Smm} 150207753Smm 151207753Smmvoid freelist_reserve(struct freelist *list, void *osext, HPT_UINT size, HPT_UINT count) 152207753Smm{ 153207753Smm PVBUS_EXT vbus_ext = osext; 154207753Smm 155207753Smm if (vbus_ext->ext_type!=EXT_TYPE_VBUS) 156207753Smm vbus_ext = ((PHBA)osext)->vbus_ext; 157207753Smm 158207753Smm list->next = vbus_ext->freelist_head; 159207753Smm vbus_ext->freelist_head = list; 160207753Smm list->dma = 0; 161207753Smm list->size = size; 162207753Smm list->head = 0; 163207753Smm#if DBG 164207753Smm list->reserved_count = 165207753Smm#endif 166207753Smm list->count = count; 167207753Smm} 168207753Smm 169207753Smmvoid *freelist_get(struct freelist *list) 170207753Smm{ 171207753Smm void * result; 172207753Smm if (list->count) { 173207753Smm HPT_ASSERT(list->head); 174207753Smm result = list->head; 175207753Smm list->head = *(void **)result; 176207753Smm list->count--; 177207753Smm return result; 178207753Smm } 179207753Smm return 0; 180207753Smm} 181207753Smm 182207753Smmvoid freelist_put(struct freelist * list, void *p) 183207753Smm{ 184207753Smm HPT_ASSERT(list->dma==0); 185207753Smm list->count++; 186207753Smm *(void **)p = list->head; 187207753Smm list->head = p; 188207753Smm} 189278433Srpaulo 190278433Srpaulovoid freelist_reserve_dma(struct freelist *list, void *osext, HPT_UINT size, HPT_UINT alignment, HPT_UINT count) 191207753Smm{ 192207753Smm PVBUS_EXT vbus_ext = osext; 193207753Smm 194207753Smm if (vbus_ext->ext_type!=EXT_TYPE_VBUS) 195207753Smm vbus_ext = ((PHBA)osext)->vbus_ext; 196207753Smm 197207753Smm list->next = vbus_ext->freelist_dma_head; 198207753Smm vbus_ext->freelist_dma_head = list; 199207753Smm list->dma = 1; 200207753Smm list->alignment = alignment; 201207753Smm list->size = size; 202278433Srpaulo list->head = 0; 203278433Srpaulo#if DBG 204278433Srpaulo list->reserved_count = 205278433Srpaulo#endif 206278433Srpaulo list->count = count; 207207753Smm} 208207753Smm 209207753Smmvoid *freelist_get_dma(struct freelist *list, BUS_ADDRESS *busaddr) 210207753Smm{ 211207753Smm void *result; 212207753Smm HPT_ASSERT(list->dma); 213207753Smm result = freelist_get(list); 214207753Smm if (result) 215207753Smm *busaddr = *(BUS_ADDRESS *)((void **)result+1); 216207753Smm return result; 217207753Smm} 218207753Smm 219207753Smmvoid freelist_put_dma(struct freelist *list, void *p, BUS_ADDRESS busaddr) 220207753Smm{ 221207753Smm HPT_ASSERT(list->dma); 222207753Smm list->count++; 223207753Smm *(void **)p = list->head; 224207753Smm *(BUS_ADDRESS *)((void **)p+1) = busaddr; 225207753Smm list->head = p; 226207753Smm} 227207753Smm 228207753SmmHPT_U32 os_get_stamp(void) 229207753Smm{ 230207753Smm HPT_U32 stamp; 231207753Smm do { stamp = random(); } while (stamp==0); 232207753Smm return stamp; 233207753Smm} 234207753Smm 235207753Smmvoid os_stallexec(HPT_U32 microseconds) 236207753Smm{ 237207753Smm DELAY(microseconds); 238207753Smm} 239207753Smm 240207753Smmstatic void os_timer_for_ldm(void *arg) 241207753Smm{ 242207753Smm PVBUS_EXT vbus_ext = (PVBUS_EXT)arg; 243207753Smm ldm_on_timer((PVBUS)vbus_ext->vbus); 244207753Smm} 245207753Smm 246207753Smmvoid os_request_timer(void * osext, HPT_U32 interval) 247207753Smm{ 248207753Smm PVBUS_EXT vbus_ext = osext; 249207753Smm 250207753Smm HPT_ASSERT(vbus_ext->ext_type==EXT_TYPE_VBUS); 251207753Smm 252207753Smm#if (__FreeBSD_version >= 1000510) 253207753Smm callout_reset_sbt(&vbus_ext->timer, SBT_1US * interval, 0, 254207753Smm os_timer_for_ldm, vbus_ext, 0); 255207753Smm#else 256207753Smm untimeout(os_timer_for_ldm, vbus_ext, vbus_ext->timer); 257207753Smm vbus_ext->timer = timeout(os_timer_for_ldm, vbus_ext, interval * hz / 1000000); 258207753Smm#endif 259207753Smm} 260207753Smm 261207753SmmHPT_TIME os_query_time(void) 262207753Smm{ 263207753Smm return ticks * (1000000 / hz); 264207753Smm} 265207753Smm 266207753Smmvoid os_schedule_task(void *osext, OSM_TASK *task) 267207753Smm{ 268207753Smm PVBUS_EXT vbus_ext = osext; 269207753Smm 270207753Smm HPT_ASSERT(task->next==0); 271207753Smm 272207753Smm if (vbus_ext->tasks==0) 273207753Smm vbus_ext->tasks = task; 274207753Smm else { 275207753Smm OSM_TASK *t = vbus_ext->tasks; 276207753Smm while (t->next) t = t->next; 277207753Smm t->next = task; 278207753Smm } 279207753Smm 280207753Smm if (vbus_ext->worker.ta_context) 281207753Smm TASK_ENQUEUE(&vbus_ext->worker); 282207753Smm} 283207753Smm 284207753Smmint os_revalidate_device(void *osext, int id) 285207753Smm{ 286207753Smm 287207753Smm return 0; 288207753Smm} 289207753Smm 290207753Smmint os_query_remove_device(void *osext, int id) 291207753Smm{ 292207753Smm return 0; 293207753Smm} 294207753Smm 295207753SmmHPT_U8 os_get_vbus_seq(void *osext) 296207753Smm{ 297207753Smm return ((PVBUS_EXT)osext)->sim->path_id; 298207753Smm} 299207753Smm 300207753Smmint os_printk(char *fmt, ...) 301207753Smm{ 302207753Smm va_list args; 303207753Smm static char buf[512]; 304207753Smm 305207753Smm va_start(args, fmt); 306207753Smm vsnprintf(buf, sizeof(buf), fmt, args); 307207753Smm va_end(args); 308207753Smm return printf("%s: %s\n", driver_name, buf); 309207753Smm} 310207753Smm 311207753Smm#if DBG 312207753Smmvoid os_check_stack(const char *location, int size){} 313207753Smm 314207753Smmvoid __os_dbgbreak(const char *file, int line) 315207753Smm{ 316207753Smm printf("*** break at %s:%d ***", file, line); 317207753Smm while (1); 318207753Smm} 319207753Smm 320207753Smmint hpt_dbg_level = 1; 321207753Smm#endif 322207753Smm