mb86960.h revision 139790
1139790Simp/*- 28027Swollman * All Rights Reserved, Copyright (C) Fujitsu Limited 1995 38027Swollman * 48027Swollman * This software may be used, modified, copied, distributed, and sold, in 58027Swollman * both source and binary form provided that the above copyright, these 68027Swollman * terms and the following disclaimer are retained. The name of the author 78027Swollman * and/or the contributor may not be used to endorse or promote products 88027Swollman * derived from this software without specific prior written permission. 98027Swollman * 108027Swollman * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND 118027Swollman * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 128027Swollman * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 138027Swollman * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE 148027Swollman * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 158027Swollman * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 168027Swollman * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 178027Swollman * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 188027Swollman * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 198027Swollman * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 208027Swollman * SUCH DAMAGE. 2159874Speter * 2259874Speter * $FreeBSD: head/sys/dev/fe/mb86960.h 139790 2005-01-06 22:18:23Z imp $ 238027Swollman */ 248027Swollman 258027Swollman/* 2621694Swollman * Registers of Fujitsu MB86960A/MB86965A series Ethernet controllers. 278027Swollman * Written and contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp> 288027Swollman */ 298027Swollman 308027Swollman/* 318027Swollman * Notes on register naming: 328027Swollman * 338027Swollman * Fujitsu documents for MB86960A/MB86965A uses no mnemorable names 348027Swollman * for their registers. They defined only three names for 32 358027Swollman * registers and appended numbers to distinguish registers of 368027Swollman * same name. Surprisingly, the numbers represent I/O address 378027Swollman * offsets of the registers from the base addresses, and their 388027Swollman * names correspond to the "bank" the registers are allocated. 398027Swollman * All this means that, for example, to say "read DLCR8" has no more 408027Swollman * than to say "read a register at offset 8 on bank DLCR." 418027Swollman * 428027Swollman * The following definitions may look silly, but that's what Fujitsu 438027Swollman * did, and it is necessary to know these names to read Fujitsu 448027Swollman * documents.. 458027Swollman */ 468027Swollman 478027Swollman/* Data Link Control Registrs, on invaliant port addresses. */ 488027Swollman#define FE_DLCR0 0 498027Swollman#define FE_DLCR1 1 508027Swollman#define FE_DLCR2 2 518027Swollman#define FE_DLCR3 3 528027Swollman#define FE_DLCR4 4 538027Swollman#define FE_DLCR5 5 548027Swollman#define FE_DLCR6 6 558027Swollman#define FE_DLCR7 7 568027Swollman 578027Swollman/* More DLCRs, on register bank #0. */ 588027Swollman#define FE_DLCR8 8 598027Swollman#define FE_DLCR9 9 608027Swollman#define FE_DLCR10 10 618027Swollman#define FE_DLCR11 11 628027Swollman#define FE_DLCR12 12 638027Swollman#define FE_DLCR13 13 648027Swollman#define FE_DLCR14 14 658027Swollman#define FE_DLCR15 15 668027Swollman 678027Swollman/* Malticast Address Registers. On register bank #1. */ 688027Swollman#define FE_MAR8 8 698027Swollman#define FE_MAR9 9 708027Swollman#define FE_MAR10 10 718027Swollman#define FE_MAR11 11 728027Swollman#define FE_MAR12 12 738027Swollman#define FE_MAR13 13 748027Swollman#define FE_MAR14 14 758027Swollman#define FE_MAR15 15 768027Swollman 778027Swollman/* Buffer Memory Port Registers. On register back #2. */ 788027Swollman#define FE_BMPR8 8 798027Swollman#define FE_BMPR9 9 808027Swollman#define FE_BMPR10 10 818027Swollman#define FE_BMPR11 11 828027Swollman#define FE_BMPR12 12 838027Swollman#define FE_BMPR13 13 848027Swollman#define FE_BMPR14 14 858027Swollman#define FE_BMPR15 15 868027Swollman 8721694Swollman/* More BMPRs, only on 86965, accessible only when JLI mode. */ 888027Swollman#define FE_BMPR16 16 898027Swollman#define FE_BMPR17 17 908027Swollman#define FE_BMPR18 18 918027Swollman#define FE_BMPR19 19 928027Swollman 938027Swollman/* 948027Swollman * Definitions of registers. 958027Swollman * I don't have Fujitsu documents of MB86960A/MB86965A, so I don't 968027Swollman * know the official names for each flags and fields. The following 978027Swollman * names are assigned by me (the author of this file,) since I cannot 988027Swollman * mnemorize hexadecimal constants for all of these functions. 9921694Swollman * Comments? 10021694Swollman * 10121694Swollman * I've got documents from Fujitsu web site, recently. However, it's 10221694Swollman * too late. Names for some fields (bits) are kept different from 10321694Swollman * those used in the Fujitsu documents... 1048027Swollman */ 1058027Swollman 1068027Swollman/* DLCR0 -- transmitter status */ 10721694Swollman#define FE_D0_BUSERR 0x01 /* Bus write error? */ 1088027Swollman#define FE_D0_COLL16 0x02 /* Collision limit (16) encountered */ 1098027Swollman#define FE_D0_COLLID 0x04 /* Collision on last transmission */ 1108027Swollman#define FE_D0_JABBER 0x08 /* Jabber */ 1118027Swollman#define FE_D0_CRLOST 0x10 /* Carrier lost on last transmission */ 11221694Swollman#define FE_D0_PKTRCD 0x20 /* Last packet looped back correctly */ 1138027Swollman#define FE_D0_NETBSY 0x40 /* Network Busy (Carrier Detected) */ 1148027Swollman#define FE_D0_TXDONE 0x80 /* Transmission complete */ 1158027Swollman 1168027Swollman/* DLCR1 -- receiver status */ 1178027Swollman#define FE_D1_OVRFLO 0x01 /* Receiver buffer overflow */ 1188027Swollman#define FE_D1_CRCERR 0x02 /* CRC error on last packet */ 1198027Swollman#define FE_D1_ALGERR 0x04 /* Alignment error on last packet */ 1208027Swollman#define FE_D1_SRTPKT 0x08 /* Short (RUNT) packet is received */ 1218027Swollman#define FE_D1_RMTRST 0x10 /* Remote reset packet (type = 0x0900) */ 1228027Swollman#define FE_D1_DMAEOP 0x20 /* Host asserted End of DMA OPeration */ 1238027Swollman#define FE_D1_BUSERR 0x40 /* Bus read error */ 1248027Swollman#define FE_D1_PKTRDY 0x80 /* Packet(s) ready on receive buffer */ 1258027Swollman 1268027Swollman/* DLCR2 -- transmitter interrupt control; same layout as DLCR0 */ 1278027Swollman#define FE_D2_BUSERR FE_D0_BUSERR 1288027Swollman#define FE_D2_COLL16 FE_D0_COLL16 1298027Swollman#define FE_D2_COLLID FE_D0_COLLID 1308027Swollman#define FE_D2_JABBER FE_D0_JABBER 1318027Swollman#define FE_D2_TXDONE FE_D0_TXDONE 1328027Swollman 1338027Swollman#define FE_D2_RESERVED 0x70 1348027Swollman 1358027Swollman/* DLCR3 -- receiver interrupt control; same layout as DLCR1 */ 1368027Swollman#define FE_D3_OVRFLO FE_D1_OVRFLO 1378027Swollman#define FE_D3_CRCERR FE_D1_CRCERR 1388027Swollman#define FE_D3_ALGERR FE_D1_ALGERR 1398027Swollman#define FE_D3_SRTPKT FE_D1_SRTPKT 1408027Swollman#define FE_D3_RMTRST FE_D1_RMTRST 1418027Swollman#define FE_D3_DMAEOP FE_D1_DMAEOP 1428027Swollman#define FE_D3_BUSERR FE_D1_BUSERR 1438027Swollman#define FE_D3_PKTRDY FE_D1_PKTRDY 1448027Swollman 1458027Swollman/* DLCR4 -- transmitter operation mode */ 1468027Swollman#define FE_D4_DSC 0x01 /* Disable carrier sense on trans. */ 1478027Swollman#define FE_D4_LBC 0x02 /* Loop back test control */ 14821694Swollman#define FE_D4_CNTRL 0x04 /* - tied to CNTRL pin of the chip */ 1498027Swollman#define FE_D4_TEST1 0x08 /* Test output #1 */ 1508027Swollman#define FE_D4_COL 0xF0 /* Collision counter */ 1518027Swollman 1528027Swollman#define FE_D4_LBC_ENABLE 0x00 /* Perform loop back test */ 1538027Swollman#define FE_D4_LBC_DISABLE 0x02 /* Normal operation */ 1548027Swollman 1558027Swollman#define FE_D4_COL_SHIFT 4 1568027Swollman 1578027Swollman/* DLCR5 -- receiver operation mode */ 1588027Swollman#define FE_D5_AFM0 0x01 /* Receive packets for other stations */ 1598027Swollman#define FE_D5_AFM1 0x02 /* Receive packets for this station */ 1608027Swollman#define FE_D5_RMTRST 0x04 /* Enable remote reset operation */ 1618027Swollman#define FE_D5_SRTPKT 0x08 /* Accept short (RUNT) packets */ 1628027Swollman#define FE_D5_SRTADR 0x10 /* Short (16 bits?) MAC address */ 1638027Swollman#define FE_D5_BADPKT 0x20 /* Accept packets with error */ 1648027Swollman#define FE_D5_BUFEMP 0x40 /* Receive buffer is empty */ 1658027Swollman#define FE_D5_TEST2 0x80 /* Test output #2 */ 1668027Swollman 1678027Swollman/* DLCR6 -- hardware configuration #0 */ 1688027Swollman#define FE_D6_BUFSIZ 0x03 /* Size of NIC buffer SRAM */ 1698027Swollman#define FE_D6_TXBSIZ 0x0C /* Size (and config)of trans. buffer */ 1708027Swollman#define FE_D6_BBW 0x10 /* Buffer SRAM bus width */ 1718027Swollman#define FE_D6_SBW 0x20 /* System bus width */ 1728027Swollman#define FE_D6_SRAM 0x40 /* Buffer SRAM access time */ 1738027Swollman#define FE_D6_DLC 0x80 /* Disable DLC (recever/transmitter) */ 1748027Swollman 1758027Swollman#define FE_D6_BUFSIZ_8KB 0x00 /* The board has 8KB SRAM */ 1768027Swollman#define FE_D6_BUFSIZ_16KB 0x01 /* The board has 16KB SRAM */ 1778027Swollman#define FE_D6_BUFSIZ_32KB 0x02 /* The board has 32KB SRAM */ 1788027Swollman#define FE_D6_BUFSIZ_64KB 0x03 /* The board has 64KB SRAM */ 1798027Swollman 1808027Swollman#define FE_D6_TXBSIZ_1x2KB 0x00 /* Single 2KB buffer for trans. */ 1818027Swollman#define FE_D6_TXBSIZ_2x2KB 0x04 /* Double 2KB buffers */ 1828027Swollman#define FE_D6_TXBSIZ_2x4KB 0x08 /* Double 4KB buffers */ 1838027Swollman#define FE_D6_TXBSIZ_2x8KB 0x0C /* Double 8KB buffers */ 1848027Swollman 1858027Swollman#define FE_D6_BBW_WORD 0x00 /* SRAM has 16 bit data line */ 1868027Swollman#define FE_D6_BBW_BYTE 0x10 /* SRAM has 8 bit data line */ 1878027Swollman 1888027Swollman#define FE_D6_SBW_WORD 0x00 /* Access with 16 bit (AT) bus */ 1898027Swollman#define FE_D6_SBW_BYTE 0x20 /* Access with 8 bit (XT) bus */ 1908027Swollman 1918027Swollman#define FE_D6_SRAM_150ns 0x00 /* The board has slow SRAM */ 1928027Swollman#define FE_D6_SRAM_100ns 0x40 /* The board has fast SRAM */ 1938027Swollman 1948027Swollman#define FE_D6_DLC_ENABLE 0x00 /* Normal operation */ 1958027Swollman#define FE_D6_DLC_DISABLE 0x80 /* Stop sending/receiving */ 1968027Swollman 1978027Swollman/* DLC7 -- hardware configuration #1 */ 1988027Swollman#define FE_D7_BYTSWP 0x01 /* Host byte order control */ 1998027Swollman#define FE_D7_EOPPOL 0x02 /* Polarity of DMA EOP signal */ 2008027Swollman#define FE_D7_RBS 0x0C /* Register bank select */ 2018027Swollman#define FE_D7_RDYPNS 0x10 /* Senses RDYPNSEL input signal */ 2028027Swollman#define FE_D7_POWER 0x20 /* Stand-by (power down) mode control */ 2038027Swollman#define FE_D7_IDENT 0xC0 /* Chip identification */ 2048027Swollman 2058027Swollman#define FE_D7_BYTSWP_LH 0x00 /* DEC/Intel byte order */ 2068027Swollman#define FE_D7_BYTSWP_HL 0x01 /* IBM/Motorolla byte order */ 2078027Swollman 2088027Swollman#define FE_D7_RBS_DLCR 0x00 /* Select DLCR8-15 */ 2098027Swollman#define FE_D7_RBS_MAR 0x04 /* Select MAR8-15 */ 2108027Swollman#define FE_D7_RBS_BMPR 0x08 /* Select BMPR8-15 */ 2118027Swollman 2128027Swollman#define FE_D7_POWER_DOWN 0x00 /* Power down (stand-by) mode */ 2138027Swollman#define FE_D7_POWER_UP 0x20 /* Normal operation */ 2148027Swollman 21521694Swollman#define FE_D7_IDENT_TDK 0x00 /* TDK chips? */ 21621694Swollman#define FE_D7_IDENT_NICE 0x80 /* Fujitsu NICE (86960) */ 21721694Swollman#define FE_D7_IDENT_EC 0xC0 /* Fujitsu EtherCoupler (86965) */ 2188027Swollman 2198027Swollman/* DLCR8 thru DLCR13 are for Ethernet station address. */ 2208027Swollman 22121694Swollman/* DLCR14 and DLCR15 are for TDR. (TDR is used for cable diagnostic.) */ 2228027Swollman 2238027Swollman/* MAR8 thru MAR15 are for Multicast address filter. */ 2248027Swollman 2258027Swollman/* BMPR8 and BMPR9 are for packet data. */ 2268027Swollman 2278027Swollman/* BMPR10 -- transmitter start trigger */ 2288027Swollman#define FE_B10_START 0x80 /* Start transmitter */ 2298027Swollman#define FE_B10_COUNT 0x7F /* Packet count */ 2308027Swollman 2318027Swollman/* BMPR11 -- 16 collisions control */ 2328027Swollman#define FE_B11_CTRL 0x01 /* Skip or resend errored packets */ 2338027Swollman#define FE_B11_MODE1 0x02 /* Restart transmitter after COLL16 */ 2348027Swollman#define FE_B11_MODE2 0x04 /* Automatic restart enable */ 2358027Swollman 2368027Swollman#define FE_B11_CTRL_RESEND 0x00 /* Re-send the collided packet */ 2378027Swollman#define FE_B11_CTRL_SKIP 0x01 /* Skip the collided packet */ 2388027Swollman 2398027Swollman/* BMPR12 -- DMA enable */ 2408027Swollman#define FE_B12_TXDMA 0x01 /* Enable transmitter DMA */ 2418027Swollman#define FE_B12_RXDMA 0x02 /* Enable receiver DMA */ 2428027Swollman 2438027Swollman/* BMPR13 -- DMA control */ 2448027Swollman#define FE_B13_BSTCTL 0x03 /* DMA burst mode control */ 2458027Swollman#define FE_B13_TPTYPE 0x04 /* Twisted pair cable impedance */ 2468027Swollman#define FE_B13_PORT 0x18 /* Port (TP/AUI) selection */ 2478027Swollman#define FE_B13_LNKTST 0x20 /* Link test enable */ 2488027Swollman#define FE_B13_SQTHLD 0x40 /* Lower squelch threshold */ 24921694Swollman#define FE_B13_IOUNLK 0x80 /* Change I/O base address, on JLI mode */ 2508027Swollman 2518027Swollman#define FE_B13_BSTCTL_1 0x00 2528027Swollman#define FE_B13_BSTCTL_4 0x01 2538027Swollman#define FE_B13_BSTCTL_8 0x02 2548027Swollman#define FE_B13_BSTCLT_12 0x03 2558027Swollman 2568027Swollman#define FE_B13_TPTYPE_UTP 0x00 /* Unshielded (standard) cable */ 2578027Swollman#define FE_B13_TPTYPE_STP 0x04 /* Shielded (IBM) cable */ 2588027Swollman 2598027Swollman#define FE_B13_PORT_AUTO 0x00 /* Auto detected */ 2608027Swollman#define FE_B13_PORT_TP 0x08 /* Force TP */ 2618027Swollman#define FE_B13_PORT_AUI 0x18 /* Force AUI */ 2628027Swollman 2638027Swollman/* BMPR14 -- More receiver control and more transmission interrupts */ 2648027Swollman#define FE_B14_FILTER 0x01 /* Filter out self-originated packets */ 2658027Swollman#define FE_B14_SQE 0x02 /* SQE interrupt enable */ 2668027Swollman#define FE_B14_SKIP 0x04 /* Skip a received packet */ 2678027Swollman#define FE_B14_RJAB 0x20 /* RJAB interrupt enable */ 2688027Swollman#define FE_B14_LLD 0x40 /* Local-link-down interrupt enable */ 2698027Swollman#define FE_B14_RLD 0x80 /* Remote-link-down interrupt enable */ 2708027Swollman 2718027Swollman/* BMPR15 -- More transmitter status; basically same layout as BMPR14 */ 2728027Swollman#define FE_B15_SQE FE_B14_SQE 2738027Swollman#define FE_B15_RCVPOL 0x08 /* Reversed receive line polarity */ 2748027Swollman#define FE_B15_RMTPRT 0x10 /* ??? */ 2758027Swollman#define FE_B15_RAJB FE_B14_RJAB 2768027Swollman#define FE_B15_LLD FE_B14_LLD 2778027Swollman#define FE_B15_RLD FE_B14_RLD 2788027Swollman 2798027Swollman/* BMPR16 -- EEPROM control */ 2808027Swollman#define FE_B16_DOUT 0x04 /* EEPROM Data in (CPU to EEPROM) */ 2818027Swollman#define FE_B16_SELECT 0x20 /* EEPROM chip select */ 2828027Swollman#define FE_B16_CLOCK 0x40 /* EEPROM shift clock */ 2838027Swollman#define FE_B16_DIN 0x80 /* EEPROM data out (EEPROM to CPU) */ 2848027Swollman 2858027Swollman/* BMPR17 -- EEPROM data */ 2868027Swollman#define FE_B17_DATA 0x80 /* EEPROM data bit */ 2878027Swollman 28821694Swollman/* BMPR18 -- cycle I/O address setting in JLI mode */ 2898027Swollman 29021694Swollman/* BMPR19 -- ISA interface configuration in JLI mode */ 2918027Swollman#define FE_B19_IRQ 0xC0 2928027Swollman#define FE_B19_IRQ_SHIFT 6 2938027Swollman 2948027Swollman#define FE_B19_ROM 0x38 2958027Swollman#define FE_B19_ROM_SHIFT 3 2968027Swollman 2978027Swollman#define FE_B19_ADDR 0x07 2988027Swollman#define FE_B19_ADDR_SHIFT 0 2998027Swollman 3008027Swollman/* 30121694Swollman * An extra I/O port address to reset 86965. This location is called 30221694Swollman * "ID ROM area" by Fujitsu document. 30321694Swollman */ 30421694Swollman 30521694Swollman/* 30621694Swollman * Flags in Receive Packet Header... Basically same layout as DLCR1. 30721694Swollman */ 30821694Swollman#define FE_RPH_OVRFLO FE_D1_OVRFLO 30921694Swollman#define FE_RPH_CRCERR FE_D1_CRCERR 31021694Swollman#define FE_RPH_ALGERR FE_D1_ALGERR 31121694Swollman#define FE_RPH_SRTPKT FE_D1_SRTPKT 31221694Swollman#define FE_RPH_RMTRST FE_D1_RMTRST 31321694Swollman#define FE_RPH_GOOD 0x20 /* Good packet follows */ 31421694Swollman 31521694Swollman/* 3168027Swollman * EEPROM specification (of JLI mode). 3178027Swollman */ 3188027Swollman 3198027Swollman/* Number of bytes in an EEPROM accessible through 86965. */ 3208027Swollman#define FE_EEPROM_SIZE 32 3218027Swollman 3228027Swollman/* Offset for JLI config; automatically copied into BMPR19 at startup. */ 3238027Swollman#define FE_EEPROM_CONF 0 3248027Swollman 3258027Swollman/* 32621694Swollman * Some 8696x specific constants. 3278027Swollman */ 3288027Swollman 3298027Swollman/* Length (in bytes) of a Multicast Address Filter. */ 3308027Swollman#define FE_FILTER_LEN 8 3318027Swollman 3328027Swollman/* How many packets we can put in the transmission buffer on NIC memory. */ 3338027Swollman#define FE_QUEUEING_MAX 127 3348027Swollman 3358027Swollman/* Length (in bytes) of a "packet length" word in transmission buffer. */ 3368027Swollman#define FE_DATA_LEN_LEN 2 3378027Swollman 3388027Swollman/* Special Multicast Address Filter value. */ 3398027Swollman#define FE_FILTER_NOTHING { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } 3408027Swollman#define FE_FILTER_ALL { 0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF } 341