if_exreg.h revision 57987
1/* 2 * Copyright (c) 1996, Javier Mart�n Rueda (jmrueda@diatel.upm.es) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/dev/ex/if_exreg.h 57987 2000-03-13 12:23:32Z mdodd $ 28 */ 29 30/* 31 * Intel EtherExpress Pro/10 Ethernet driver 32 */ 33 34/* 35 * Several constants. 36 */ 37 38/* Length of an ethernet address. */ 39#define ETHER_ADDR_LEN 6 40/* Default RAM size in board. */ 41#define CARD_RAM_SIZE 0x8000 42/* Number of I/O ports used. */ 43#define EX_IOSIZE 16 44 45/* 46 * Intel EtherExpress Pro (i82595 based) registers 47 */ 48 49/* Common registers to all banks. */ 50 51#define CMD_REG 0 52#define REG1 1 53#define REG2 2 54#define REG3 3 55#define REG4 4 56#define REG5 5 57#define REG6 6 58#define REG7 7 59#define REG8 8 60#define REG9 9 61#define REG10 10 62#define REG11 11 63#define REG12 12 64#define REG13 13 65#define REG14 14 66#define REG15 15 67 68/* Definitions for command register (CMD_REG). */ 69 70#define Switch_Bank_CMD 0 71#define MC_Setup_CMD 3 72#define Transmit_CMD 4 73#define Diagnose_CMD 7 74#define Rcv_Enable_CMD 8 75#define Rcv_Stop 11 76#define Reset_CMD 14 77#define Resume_XMT_List_CMD 28 78#define Sel_Reset_CMD 30 79#define Abort 0x20 80#define Bank0_Sel 0x00 81#define Bank1_Sel 0x40 82#define Bank2_Sel 0x80 83 84/* Bank 0 specific registers. */ 85 86#define STATUS_REG 1 87#define ID_REG 2 88#define Id_Mask 0x2c 89#define Id_Sig 0x24 90#define Counter_bits 0xc0 91#define MASK_REG 3 92#define Exec_Int 0x08 93#define Tx_Int 0x04 94#define Rx_Int 0x02 95#define Rx_Stp_Int 0x01 96#define All_Int 0x0f 97#define RCV_BAR 4 98#define RCV_BAR_Lo 4 99#define RCV_BAR_Hi 5 100#define RCV_STOP_REG 6 101#define XMT_BAR 10 102#define HOST_ADDR_REG 12 /* 16-bit register */ 103#define IO_PORT_REG 14 /* 16-bit register */ 104 105/* Bank 1 specific registers. */ 106 107#define TriST_INT 0x80 108#define INT_NO_REG 2 109#define RCV_LOWER_LIMIT_REG 8 110#define RCV_UPPER_LIMIT_REG 9 111#define XMT_LOWER_LIMIT_REG 10 112#define XMT_UPPER_LIMIT_REG 11 113 114/* Bank 2 specific registers. */ 115 116#define Disc_Bad_Fr 0x80 117#define Tx_Chn_ErStp 0x40 118#define Tx_Chn_Int_Md 0x20 119#define No_SA_Ins 0x10 120#define RX_CRC_InMem 0x04 121#define BNC_bit 0x20 122#define TPE_bit 0x04 123#define I_ADDR_REG0 4 124#define EEPROM_REG 10 125#define Trnoff_Enable 0x10 126 127/* EEPROM memory positions (16-bit wide). */ 128 129#define EE_W0 0x00 130# define EE_W0_PNP 0x0001 131# define EE_W0_BUS16 0x0004 132# define EE_W0_FLASH_ADDR_MASK 0x0038 133# define EE_W0_FLASH_ADDR_SHIFT 3 134# define EE_W0_AUTO_IO 0x0040 135# define EE_W0_FLASH 0x0100 136# define EE_W0_AUTO_NEG 0x0200 137# define EE_W0_IO_MASK 0xFC00 138# define EE_W0_IO_SHIFT 10 139 140#define EE_IRQ_No 1 141#define IRQ_No_Mask 0x07 142 143#define EE_W1 0x01 144# define EE_W1_INT_SEL 0x0007 145# define EE_W1_NO_LINK_INT 0x0008 /* Link Integrity Off */ 146# define EE_W1_NO_POLARITY 0x0010 /* Polarity Correction Off */ 147# define EE_W1_TPE_AUI 0x0020 /* 1 = TPE, 0 = AUI */ 148# define EE_W1_NO_JABBER_PREV 0x0040 /* Jabber prevention Off */ 149# define EE_W1_NO_AUTO_SELECT 0x0080 /* Auto Port Selection Off */ 150# define EE_W1_SMOUT 0x0100 /* SMout Pin Control 0= Input */ 151# define EE_W1_PROM 0x0200 /* Flash = 0, PROM = 1 */ 152# define EE_W1_ALT_READY 0x2000 /* Alternate Ready, 0=normal */ 153# define EE_W1_FULL_DUPLEX 0x8000 154 155#define EE_W2 0x02 156#define EE_W3 0x03 157#define EE_W4 0x04 158 159#define EE_Eth_Addr_Lo 2 160#define EE_Eth_Addr_Mid 3 161#define EE_Eth_Addr_Hi 4 162 163#define EE_W5 0x05 164# define EE_W5_BNC_TPE 0x0001 /* 0 = TPE, 1 = BNC */ 165# define EE_W5_BOOT_IPX 0x0002 166# define EE_W5_BOOT_ODI 0x0004 167# define EE_W5_BOOT_NDIS (EE_W5_BOOT_IPX|EE_W5_BOOT_ODI) 168# define EE_W5_NUM_CONN 0x0008 /* 0 = 2, 1 = 3 */ 169# define EE_W5_NOFLASH 0x0010 /* No flash socket present */ 170# define EE_W5_PORT_TPE 0x0020 /* TPE present */ 171# define EE_W5_PORT_BNC 0x0040 /* BNC present */ 172# define EE_W5_PORT_AUI 0x0080 /* AUI present */ 173# define EE_W5_PWR_MGT 0x0100 /* Power Management */ 174# define EE_W5_CP 0x0200 /* COncurrent Processing */ 175 176#define EE_W6 0x05 177# define EE_W6_STEP_MASK 0x000F 178# define EE_W6_BOARD_MASK 0xFFF0 179# define EE_W6_BOARD_SHIFT 4 180 181/* EEPROM serial interface. */ 182 183#define EESK 0x01 184#define EECS 0x02 185#define EEDI 0x04 186#define EEDO 0x08 187#define EE_READ_CMD (6 << 6) 188 189/* Frame chain constants. */ 190 191/* Transmit header length (in board's ring buffer). */ 192#define XMT_HEADER_LEN 8 193#define XMT_Chain_Point 4 194#define XMT_Byte_Count 6 195#define Done_bit 0x0080 196#define Ch_bit 0x8000 197/* Transmit result bits. */ 198#define No_Collisions_bits 0x000f 199#define TX_OK_bit 0x2000 200/* Receive result bits. */ 201#define RCV_Done 8 202#define RCV_OK_bit 0x2000 203