1226381Smarius/* $NetBSD: ncr53c9xreg.h,v 1.16 2009/09/07 13:31:44 tsutsui Exp $ */ 2130293Sscottl 3139749Simp/*- 4130293Sscottl * Copyright (c) 1994 Peter Galbavy. All rights reserved. 5130293Sscottl * 6130293Sscottl * Redistribution and use in source and binary forms, with or without 7130293Sscottl * modification, are permitted provided that the following conditions 8130293Sscottl * are met: 9130293Sscottl * 1. Redistributions of source code must retain the above copyright 10130293Sscottl * notice, this list of conditions and the following disclaimer. 11130293Sscottl * 2. Redistributions in binary form must reproduce the above copyright 12130293Sscottl * notice, this list of conditions and the following disclaimer in the 13130293Sscottl * documentation and/or other materials provided with the distribution. 14130293Sscottl * 3. All advertising materials mentioning features or use of this software 15130293Sscottl * must display the following acknowledgement: 16130293Sscottl * This product includes software developed by Peter Galbavy. 17130293Sscottl * 4. The name of the author may not be used to endorse or promote products 18130293Sscottl * derived from this software without specific prior written permission. 19130293Sscottl * 20130293Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21130293Sscottl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22130293Sscottl * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23130293Sscottl * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24130293Sscottl * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25130293Sscottl * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26130293Sscottl * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27130293Sscottl * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28130293Sscottl * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29130293Sscottl * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30130293Sscottl */ 31130293Sscottl 32130293Sscottl/* $FreeBSD: releng/10.2/sys/dev/esp/ncr53c9xreg.h 226950 2011-10-30 21:45:36Z marius $ */ 33130293Sscottl 34226950Smarius#ifndef _NCR53C9XREG_H_ 35226950Smarius#define _NCR53C9XREG_H_ 36226950Smarius 37130293Sscottl/* 38130293Sscottl * Register addresses, relative to some base address 39130293Sscottl */ 40130293Sscottl 41130293Sscottl#define NCR_TCL 0x00 /* RW - Transfer Count Low */ 42130293Sscottl#define NCR_TCM 0x01 /* RW - Transfer Count Mid */ 43130293Sscottl#define NCR_TCH 0x0e /* RW - Transfer Count High */ 44130293Sscottl /* NOT on 53C90 */ 45130293Sscottl 46130293Sscottl#define NCR_FIFO 0x02 /* RW - FIFO data */ 47130293Sscottl 48145202Smarius#define NCR_CMD 0x03 /* RW - Command (2 deep) */ 49226381Smarius#define NCRCMD_DMA 0x80 /* DMA Bit */ 50226381Smarius#define NCRCMD_NOP 0x00 /* No Operation */ 51226381Smarius#define NCRCMD_FLUSH 0x01 /* Flush FIFO */ 52226381Smarius#define NCRCMD_RSTCHIP 0x02 /* Reset Chip */ 53226381Smarius#define NCRCMD_RSTSCSI 0x03 /* Reset SCSI Bus */ 54226381Smarius#define NCRCMD_RESEL 0x40 /* Reselect Sequence */ 55226381Smarius#define NCRCMD_SELNATN 0x41 /* Select without ATN */ 56226381Smarius#define NCRCMD_SELATN 0x42 /* Select with ATN */ 57226381Smarius#define NCRCMD_SELATNS 0x43 /* Select with ATN & Stop */ 58226381Smarius#define NCRCMD_ENSEL 0x44 /* Enable (Re)Selection */ 59226381Smarius#define NCRCMD_DISSEL 0x45 /* Disable (Re)Selection */ 60226381Smarius#define NCRCMD_SELATN3 0x46 /* Select with ATN3 */ 61226381Smarius#define NCRCMD_RESEL3 0x47 /* Reselect3 Sequence */ 62226381Smarius#define NCRCMD_SNDMSG 0x20 /* Send Message */ 63226381Smarius#define NCRCMD_SNDSTAT 0x21 /* Send Status */ 64226381Smarius#define NCRCMD_SNDDATA 0x22 /* Send Data */ 65226381Smarius#define NCRCMD_DISCSEQ 0x23 /* Disconnect Sequence */ 66226381Smarius#define NCRCMD_TERMSEQ 0x24 /* Terminate Sequence */ 67226381Smarius#define NCRCMD_TCCS 0x25 /* Target Command Comp Seq */ 68226381Smarius#define NCRCMD_DISC 0x27 /* Disconnect */ 69226381Smarius#define NCRCMD_RECMSG 0x28 /* Receive Message */ 70226381Smarius#define NCRCMD_RECCMD 0x29 /* Receive Command */ 71226381Smarius#define NCRCMD_RECDATA 0x2a /* Receive Data */ 72226381Smarius#define NCRCMD_RECCSEQ 0x2b /* Receive Command Sequence*/ 73226381Smarius#define NCRCMD_ABORT 0x04 /* Target Abort DMA */ 74226381Smarius#define NCRCMD_TRANS 0x10 /* Transfer Information */ 75226381Smarius#define NCRCMD_ICCS 0x11 /* Initiator Cmd Comp Seq */ 76226381Smarius#define NCRCMD_MSGOK 0x12 /* Message Accepted */ 77226381Smarius#define NCRCMD_TRPAD 0x18 /* Transfer Pad */ 78226381Smarius#define NCRCMD_SETATN 0x1a /* Set ATN */ 79226381Smarius#define NCRCMD_RSTATN 0x1b /* Reset ATN */ 80130293Sscottl 81145202Smarius#define NCR_STAT 0x04 /* RO - Status */ 82226381Smarius#define NCRSTAT_INT 0x80 /* Interrupt */ 83226381Smarius#define NCRSTAT_GE 0x40 /* Gross Error */ 84226381Smarius#define NCRSTAT_PE 0x20 /* Parity Error */ 85226381Smarius#define NCRSTAT_TC 0x10 /* Terminal Count */ 86226381Smarius#define NCRSTAT_VGC 0x08 /* Valid Group Code */ 87226381Smarius#define NCRSTAT_PHASE 0x07 /* Phase bits */ 88130293Sscottl 89145202Smarius#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */ 90226381Smarius#define NCR_BUSID_HMEXC32 0x40 /* HME xfer counter is 32bit */ 91226381Smarius#define NCR_BUSID_HMEENCID 0x10 /* HME encode reselection ID */ 92130293Sscottl 93145202Smarius#define NCR_INTR 0x05 /* RO - Interrupt */ 94226381Smarius#define NCRINTR_SBR 0x80 /* SCSI Bus Reset */ 95226381Smarius#define NCRINTR_ILL 0x40 /* Illegal Command */ 96226381Smarius#define NCRINTR_DIS 0x20 /* Disconnect */ 97226381Smarius#define NCRINTR_BS 0x10 /* Bus Service */ 98226381Smarius#define NCRINTR_FC 0x08 /* Function Complete */ 99226381Smarius#define NCRINTR_RESEL 0x04 /* Reselected */ 100226381Smarius#define NCRINTR_SELATN 0x02 /* Select with ATN */ 101226381Smarius#define NCRINTR_SEL 0x01 /* Selected */ 102130293Sscottl 103145202Smarius#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */ 104130293Sscottl 105145202Smarius#define NCR_STEP 0x06 /* RO - Sequence Step */ 106226381Smarius#define NCRSTEP_MASK 0x07 /* the last 3 bits */ 107226381Smarius#define NCRSTEP_DONE 0x04 /* command went out */ 108130293Sscottl 109145202Smarius#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */ 110130293Sscottl /* Default 5 (53C9X) */ 111130293Sscottl 112145202Smarius#define NCR_FFLAG 0x07 /* RO - FIFO Flags */ 113226381Smarius#define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */ 114226381Smarius#define NCRFIFO_FF 0x1f /* Bytes in FIFO */ 115130293Sscottl 116130293Sscottl#define NCR_SYNCOFF 0x07 /* WO - Synch Offset */ 117130293Sscottl /* 0 = ASYNC */ 118130293Sscottl /* 1 - 15 = SYNC bytes */ 119130293Sscottl 120145202Smarius#define NCR_CFG1 0x08 /* RW - Configuration #1 */ 121226381Smarius#define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */ 122226381Smarius#define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */ 123226381Smarius#define NCRCFG1_PTEST 0x20 /* Parity Test Mod */ 124226381Smarius#define NCRCFG1_PARENB 0x10 /* Enable Parity Check */ 125226381Smarius#define NCRCFG1_CTEST 0x08 /* Enable Chip Test */ 126226381Smarius#define NCRCFG1_BUSID 0x07 /* Bus ID */ 127130293Sscottl 128145202Smarius#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */ 129130293Sscottl /* 0 = 35.01 - 40MHz */ 130130293Sscottl /* NEVER SET TO 1 */ 131130293Sscottl /* 2 = 10MHz */ 132130293Sscottl /* 3 = 10.01 - 15MHz */ 133130293Sscottl /* 4 = 15.01 - 20MHz */ 134130293Sscottl /* 5 = 20.01 - 25MHz */ 135130293Sscottl /* 6 = 25.01 - 30MHz */ 136130293Sscottl /* 7 = 30.01 - 35MHz */ 137130293Sscottl 138145202Smarius#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */ 139130293Sscottl 140145202Smarius#define NCR_CFG2 0x0b /* RW - Configuration #2 */ 141130293Sscottl#define NCRCFG2_RSVD 0xa0 /* reserved */ 142226381Smarius#define NCRCFG2_FE 0x40 /* Features Enable */ 143226381Smarius#define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */ 144226381Smarius#define NCRCFG2_SCSI2 0x08 /* SCSI-2 Enable */ 145226381Smarius#define NCRCFG2_BPA 0x04 /* Target Bad Parity Abort */ 146226381Smarius#define NCRCFG2_RPE 0x02 /* Register Parity Error */ 147226381Smarius#define NCRCFG2_DPE 0x01 /* DMA Parity Error */ 148130293Sscottl 149226381Smarius#define NCRCFG2_HMEFE 0x10 /* HME feature enable */ 150130293Sscottl#define NCRCFG2_HME32 0x80 /* HME 32 extended */ 151130293Sscottl 152130293Sscottl/* Config #3 only on 53C9X */ 153145202Smarius#define NCR_CFG3 0x0c /* RW - Configuration #3 */ 154130293Sscottl#define NCRCFG3_RSVD 0xe0 /* reserved */ 155226381Smarius#define NCRCFG3_IDM 0x10 /* ID Message Res Check */ 156226381Smarius#define NCRCFG3_QTE 0x08 /* Queue Tag Enable */ 157226381Smarius#define NCRCFG3_CDB 0x04 /* CDB 10-bytes OK */ 158226381Smarius#define NCRCFG3_FSCSI 0x02 /* Fast SCSI */ 159226381Smarius#define NCRCFG3_FCLK 0x01 /* Fast Clock (>25MHz) */ 160130293Sscottl 161130293Sscottl/* 162130293Sscottl * For some unknown reason, the ESP406/FAS408 looks like every 163130293Sscottl * other ncr53c9x, except for configuration #3 register. At any 164130293Sscottl * rate, if you're dealing with these chips, you need to use these 165130293Sscottl * defines instead. 166130293Sscottl */ 167130293Sscottl 168130293Sscottl/* Config #3 different on ESP406/FAS408 */ 169145202Smarius#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */ 170226381Smarius#define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */ 171226381Smarius#define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */ 172226381Smarius#define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */ 173226381Smarius#define NCRESPCFG3_FSCSI 0x10 /* Fast SCSI */ 174130293Sscottl#define NCRESPCFG3_SRESB 0x08 /* Save Residual Byte */ 175226381Smarius#define NCRESPCFG3_FCLK 0x04 /* Fast Clock (>25MHz) */ 176130293Sscottl#define NCRESPCFG3_ADMA 0x02 /* Alternate DMA Mode */ 177130293Sscottl#define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */ 178130293Sscottl 179146392Smarius/* Config #3 also different on NCR53CF9x/FAS100A/FAS216/FAS236 */ 180145202Smarius#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */ 181226381Smarius#define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */ 182226381Smarius#define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */ 183226381Smarius#define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */ 184226381Smarius#define NCRF9XCFG3_FSCSI 0x10 /* Fast SCSI */ 185226381Smarius#define NCRF9XCFG3_FCLK 0x08 /* Fast Clock (>25MHz) */ 186226381Smarius#define NCRF9XCFG3_SRESB 0x04 /* Save Residual Byte */ 187226381Smarius#define NCRF9XCFG3_ADMA 0x02 /* Alternate DMA Mode */ 188226381Smarius#define NCRF9XCFG3_T8M 0x01 /* Threshold 8 Mode */ 189130293Sscottl 190130293Sscottl/* Config #3 on FAS366 */ 191226381Smarius#define NCRFASCFG3_OBAUTO 0x80 /* auto push odd-byte to DMA */ 192226381Smarius#define NCRFASCFG3_EWIDE 0x40 /* Enable Wide-SCSI */ 193226381Smarius#define NCRFASCFG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID */ 194226381Smarius#define NCRFASCFG3_IDRESCHK 0x10 /* ID message checking */ 195226381Smarius#define NCRFASCFG3_QUENB 0x08 /* 3-byte msg support */ 196226381Smarius#define NCRFASCFG3_CDB10 0x04 /* group 2 scsi-2 support */ 197226381Smarius#define NCRFASCFG3_FASTSCSI 0x02 /* 10 MB/S fast scsi mode */ 198226381Smarius#define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */ 199130293Sscottl 200130293Sscottl/* Config #4 only on ESP406/FAS408 */ 201145202Smarius#define NCR_CFG4 0x0d /* RW - Configuration #4 */ 202130293Sscottl#define NCRCFG4_CRS1 0x80 /* Select register set #1 */ 203130293Sscottl#define NCRCFG4_RSVD 0x7b /* reserved */ 204130293Sscottl#define NCRCFG4_ACTNEG 0x04 /* Active negation */ 205130293Sscottl 206130293Sscottl/* 207130293Sscottl The following registers are only on the ESP406/FAS408. The 208130293Sscottl documentation refers to them as "Control Register Set #1". 209145202Smarius These are the registers that are visible when bit 7 of 210130293Sscottl register 0x0d is set. This bit is common to both register sets. 211130293Sscottl*/ 212130293Sscottl 213145202Smarius#define NCR_JMP 0x00 /* RO - Jumper Sense Register */ 214226381Smarius#define NCRJMP_RSVD 0xc0 /* reserved */ 215226381Smarius#define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */ 216130293Sscottl#define NCRJMP_J4 0x10 /* Jumper #4 */ 217130293Sscottl#define NCRJMP_J3 0x08 /* Jumper #3 */ 218130293Sscottl#define NCRJMP_J2 0x04 /* Jumper #2 */ 219130293Sscottl#define NCRJMP_J1 0x02 /* Jumper #1 */ 220130293Sscottl#define NCRJMP_J0 0x01 /* Jumper #0 */ 221130293Sscottl 222145202Smarius#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */ 223130293Sscottl 224226381Smarius#define NCR_PSTAT 0x08 /* RW - PIO Status Register */ 225226381Smarius#define NCRPSTAT_PERR 0x80 /* PIO Error */ 226226381Smarius#define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */ 227226381Smarius#define NCRPSTAT_ATAI 0x20 /* ATA IRQ */ 228226381Smarius#define NCRPSTAT_FEMPT 0x10 /* PIO FIFO Empty */ 229226381Smarius#define NCRPSTAT_F13 0x08 /* PIO FIFO 1/3 */ 230226381Smarius#define NCRPSTAT_F23 0x04 /* PIO FIFO 2/3 */ 231226381Smarius#define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */ 232226381Smarius#define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */ 233130293Sscottl 234226381Smarius#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */ 235130293Sscottl#define NCRPIOI_RSVD 0xe0 /* reserved */ 236130293Sscottl#define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */ 237130293Sscottl#define NCRPIOI_13 0x08 /* IRQ When 1/3 */ 238130293Sscottl#define NCRPIOI_23 0x04 /* IRQ When 2/3 */ 239130293Sscottl#define NCRPIOI_FULL 0x02 /* IRQ When Full */ 240130293Sscottl#define NCRPIOI_FINV 0x01 /* Flag Invert */ 241130293Sscottl 242145202Smarius#define NCR_CFG5 0x0d /* RW - Configuration #5 */ 243130293Sscottl#define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */ 244130293Sscottl#define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */ 245226381Smarius#define NCRCFG5_AADDR 0x20 /* Auto Address */ 246226381Smarius#define NCRCFG5_PTRINC 0x10 /* Pointer Increment */ 247226381Smarius#define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */ 248226381Smarius#define NCRCFG5_SINT 0x04 /* SCSI Interrupt Enable */ 249226381Smarius#define NCRCFG5_INTP 0x02 /* INT Polarity */ 250226381Smarius#define NCRCFG5_AINT 0x01 /* ATA Interrupt Enable */ 251130293Sscottl 252145202Smarius#define NCR_SIGNTR 0x0e /* RO - Signature */ 253130293Sscottl 254130293Sscottl/* Am53c974 Config #3 */ 255145202Smarius#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */ 256130293Sscottl#define NCRAMDCFG3_IDM 0x80 /* ID Message Res Check */ 257130293Sscottl#define NCRAMDCFG3_QTE 0x40 /* Queue Tag Enable */ 258130293Sscottl#define NCRAMDCFG3_CDB 0x20 /* CDB 10-bytes OK */ 259130293Sscottl#define NCRAMDCFG3_FSCSI 0x10 /* Fast SCSI */ 260130293Sscottl#define NCRAMDCFG3_FCLK 0x08 /* Fast Clock (40MHz) */ 261130293Sscottl#define NCRAMDCFG3_RSVD 0x07 /* Reserved */ 262130293Sscottl 263130293Sscottl/* Am53c974 Config #4 */ 264145202Smarius#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */ 265130293Sscottl#define NCRAMDCFG4_GE 0xc0 /* Glitch Eater */ 266130293Sscottl#define NCRAMDCFG4_GE12NS 0x00 /* Signal window 12ns */ 267130293Sscottl#define NCRAMDCFG4_GE25NS 0x80 /* Signal window 25ns */ 268130293Sscottl#define NCRAMDCFG4_GE35NS 0x40 /* Signal window 35ns */ 269130293Sscottl#define NCRAMDCFG4_GE0NS 0xc0 /* Signal window 0ns */ 270130293Sscottl#define NCRAMDCFG4_PWD 0x20 /* Reduced power feature */ 271130293Sscottl#define NCRAMDCFG4_RSVD 0x13 /* Reserved */ 272130293Sscottl#define NCRAMDCFG4_RAE 0x08 /* Active neg. REQ/ACK */ 273130293Sscottl#define NCRAMDCFG4_RADE 0x04 /* Active neg. REQ/ACK/DAT */ 274130293Sscottl 275130293Sscottl/* 276130293Sscottl * FAS366 277145202Smarius */ 278226381Smarius#define NCR_RCL NCR_TCH /* Recommand counter low */ 279226381Smarius#define NCR_RCH 0xf /* Recommand counter high */ 280226381Smarius#define NCR_UID NCR_RCL /* fas366 part-uniq id */ 281130293Sscottl 282130293Sscottl 283130293Sscottl/* status register #2 definitions (read only) */ 284226381Smarius#define NCR_STAT2 NCR_CCF 285145202Smarius#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */ 286145202Smarius#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */ 287145202Smarius#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */ 288145202Smarius#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */ 289145202Smarius#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */ 290145202Smarius#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */ 291145202Smarius#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */ 292145202Smarius#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */ 293130293Sscottl 294226950Smarius#endif /* _NCR53C9XREG_H_ */ 295