e1000_phy.c revision 185353
1/****************************************************************************** 2 3 Copyright (c) 2001-2008, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_phy.c 185353 2008-11-26 23:57:23Z jfv $*/ 34 35#include "e1000_api.h" 36 37static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); 38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read); 40/* Cable length tables */ 41static const u16 e1000_m88_cable_length_table[] = 42 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 43#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 44 (sizeof(e1000_m88_cable_length_table) / \ 45 sizeof(e1000_m88_cable_length_table[0])) 46 47static const u16 e1000_igp_2_cable_length_table[] = 48 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 55 104, 109, 114, 118, 121, 124}; 56#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 57 (sizeof(e1000_igp_2_cable_length_table) / \ 58 sizeof(e1000_igp_2_cable_length_table[0])) 59 60/** 61 * e1000_init_phy_ops_generic - Initialize PHY function pointers 62 * @hw: pointer to the HW structure 63 * 64 * Setups up the function pointers to no-op functions 65 **/ 66void e1000_init_phy_ops_generic(struct e1000_hw *hw) 67{ 68 struct e1000_phy_info *phy = &hw->phy; 69 DEBUGFUNC("e1000_init_phy_ops_generic"); 70 71 /* Initialize function pointers */ 72 phy->ops.init_params = e1000_null_ops_generic; 73 phy->ops.acquire = e1000_null_ops_generic; 74 phy->ops.check_polarity = e1000_null_ops_generic; 75 phy->ops.check_reset_block = e1000_null_ops_generic; 76 phy->ops.commit = e1000_null_ops_generic; 77 phy->ops.force_speed_duplex = e1000_null_ops_generic; 78 phy->ops.get_cfg_done = e1000_null_ops_generic; 79 phy->ops.get_cable_length = e1000_null_ops_generic; 80 phy->ops.get_info = e1000_null_ops_generic; 81 phy->ops.read_reg = e1000_null_read_reg; 82 phy->ops.release = e1000_null_phy_generic; 83 phy->ops.reset = e1000_null_ops_generic; 84 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 85 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 86 phy->ops.write_reg = e1000_null_write_reg; 87 phy->ops.power_up = e1000_null_phy_generic; 88 phy->ops.power_down = e1000_null_phy_generic; 89 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 90} 91 92/** 93 * e1000_null_read_reg - No-op function, return 0 94 * @hw: pointer to the HW structure 95 **/ 96s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data) 97{ 98 DEBUGFUNC("e1000_null_read_reg"); 99 return E1000_SUCCESS; 100} 101 102/** 103 * e1000_null_phy_generic - No-op function, return void 104 * @hw: pointer to the HW structure 105 **/ 106void e1000_null_phy_generic(struct e1000_hw *hw) 107{ 108 DEBUGFUNC("e1000_null_phy_generic"); 109 return; 110} 111 112/** 113 * e1000_null_lplu_state - No-op function, return 0 114 * @hw: pointer to the HW structure 115 **/ 116s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active) 117{ 118 DEBUGFUNC("e1000_null_lplu_state"); 119 return E1000_SUCCESS; 120} 121 122/** 123 * e1000_null_write_reg - No-op function, return 0 124 * @hw: pointer to the HW structure 125 **/ 126s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data) 127{ 128 DEBUGFUNC("e1000_null_write_reg"); 129 return E1000_SUCCESS; 130} 131 132/** 133 * e1000_check_reset_block_generic - Check if PHY reset is blocked 134 * @hw: pointer to the HW structure 135 * 136 * Read the PHY management control register and check whether a PHY reset 137 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 138 * return E1000_BLK_PHY_RESET (12). 139 **/ 140s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 141{ 142 u32 manc; 143 144 DEBUGFUNC("e1000_check_reset_block"); 145 146 manc = E1000_READ_REG(hw, E1000_MANC); 147 148 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 149 E1000_BLK_PHY_RESET : E1000_SUCCESS; 150} 151 152/** 153 * e1000_get_phy_id - Retrieve the PHY ID and revision 154 * @hw: pointer to the HW structure 155 * 156 * Reads the PHY registers and stores the PHY ID and possibly the PHY 157 * revision in the hardware structure. 158 **/ 159s32 e1000_get_phy_id(struct e1000_hw *hw) 160{ 161 struct e1000_phy_info *phy = &hw->phy; 162 s32 ret_val = E1000_SUCCESS; 163 u16 phy_id; 164 165 DEBUGFUNC("e1000_get_phy_id"); 166 167 if (!(phy->ops.read_reg)) 168 goto out; 169 170 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 171 if (ret_val) 172 goto out; 173 174 phy->id = (u32)(phy_id << 16); 175 usec_delay(20); 176 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 177 if (ret_val) 178 goto out; 179 180 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 181 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 182 183out: 184 return ret_val; 185} 186 187/** 188 * e1000_phy_reset_dsp_generic - Reset PHY DSP 189 * @hw: pointer to the HW structure 190 * 191 * Reset the digital signal processor. 192 **/ 193s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 194{ 195 s32 ret_val = E1000_SUCCESS; 196 197 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 198 199 if (!(hw->phy.ops.write_reg)) 200 goto out; 201 202 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 203 if (ret_val) 204 goto out; 205 206 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 207 208out: 209 return ret_val; 210} 211 212/** 213 * e1000_read_phy_reg_mdic - Read MDI control register 214 * @hw: pointer to the HW structure 215 * @offset: register offset to be read 216 * @data: pointer to the read data 217 * 218 * Reads the MDI control register in the PHY at offset and stores the 219 * information read to data. 220 **/ 221s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 222{ 223 struct e1000_phy_info *phy = &hw->phy; 224 u32 i, mdic = 0; 225 s32 ret_val = E1000_SUCCESS; 226 227 DEBUGFUNC("e1000_read_phy_reg_mdic"); 228 229 /* 230 * Set up Op-code, Phy Address, and register offset in the MDI 231 * Control register. The MAC will take care of interfacing with the 232 * PHY to retrieve the desired data. 233 */ 234 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 235 (phy->addr << E1000_MDIC_PHY_SHIFT) | 236 (E1000_MDIC_OP_READ)); 237 238 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 239 240 /* 241 * Poll the ready bit to see if the MDI read completed 242 * Increasing the time out as testing showed failures with 243 * the lower time out 244 */ 245 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 246 usec_delay(50); 247 mdic = E1000_READ_REG(hw, E1000_MDIC); 248 if (mdic & E1000_MDIC_READY) 249 break; 250 } 251 if (!(mdic & E1000_MDIC_READY)) { 252 DEBUGOUT("MDI Read did not complete\n"); 253 ret_val = -E1000_ERR_PHY; 254 goto out; 255 } 256 if (mdic & E1000_MDIC_ERROR) { 257 DEBUGOUT("MDI Error\n"); 258 ret_val = -E1000_ERR_PHY; 259 goto out; 260 } 261 *data = (u16) mdic; 262 263out: 264 return ret_val; 265} 266 267/** 268 * e1000_write_phy_reg_mdic - Write MDI control register 269 * @hw: pointer to the HW structure 270 * @offset: register offset to write to 271 * @data: data to write to register at offset 272 * 273 * Writes data to MDI control register in the PHY at offset. 274 **/ 275s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 276{ 277 struct e1000_phy_info *phy = &hw->phy; 278 u32 i, mdic = 0; 279 s32 ret_val = E1000_SUCCESS; 280 281 DEBUGFUNC("e1000_write_phy_reg_mdic"); 282 283 /* 284 * Set up Op-code, Phy Address, and register offset in the MDI 285 * Control register. The MAC will take care of interfacing with the 286 * PHY to retrieve the desired data. 287 */ 288 mdic = (((u32)data) | 289 (offset << E1000_MDIC_REG_SHIFT) | 290 (phy->addr << E1000_MDIC_PHY_SHIFT) | 291 (E1000_MDIC_OP_WRITE)); 292 293 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 294 295 /* 296 * Poll the ready bit to see if the MDI read completed 297 * Increasing the time out as testing showed failures with 298 * the lower time out 299 */ 300 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 301 usec_delay(50); 302 mdic = E1000_READ_REG(hw, E1000_MDIC); 303 if (mdic & E1000_MDIC_READY) 304 break; 305 } 306 if (!(mdic & E1000_MDIC_READY)) { 307 DEBUGOUT("MDI Write did not complete\n"); 308 ret_val = -E1000_ERR_PHY; 309 goto out; 310 } 311 if (mdic & E1000_MDIC_ERROR) { 312 DEBUGOUT("MDI Error\n"); 313 ret_val = -E1000_ERR_PHY; 314 goto out; 315 } 316 317out: 318 return ret_val; 319} 320 321/** 322 * e1000_read_phy_reg_m88 - Read m88 PHY register 323 * @hw: pointer to the HW structure 324 * @offset: register offset to be read 325 * @data: pointer to the read data 326 * 327 * Acquires semaphore, if necessary, then reads the PHY register at offset 328 * and storing the retrieved information in data. Release any acquired 329 * semaphores before exiting. 330 **/ 331s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 332{ 333 s32 ret_val = E1000_SUCCESS; 334 335 DEBUGFUNC("e1000_read_phy_reg_m88"); 336 337 if (!(hw->phy.ops.acquire)) 338 goto out; 339 340 ret_val = hw->phy.ops.acquire(hw); 341 if (ret_val) 342 goto out; 343 344 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 345 data); 346 347 hw->phy.ops.release(hw); 348 349out: 350 return ret_val; 351} 352 353/** 354 * e1000_write_phy_reg_m88 - Write m88 PHY register 355 * @hw: pointer to the HW structure 356 * @offset: register offset to write to 357 * @data: data to write at register offset 358 * 359 * Acquires semaphore, if necessary, then writes the data to PHY register 360 * at the offset. Release any acquired semaphores before exiting. 361 **/ 362s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 363{ 364 s32 ret_val = E1000_SUCCESS; 365 366 DEBUGFUNC("e1000_write_phy_reg_m88"); 367 368 if (!(hw->phy.ops.acquire)) 369 goto out; 370 371 ret_val = hw->phy.ops.acquire(hw); 372 if (ret_val) 373 goto out; 374 375 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 376 data); 377 378 hw->phy.ops.release(hw); 379 380out: 381 return ret_val; 382} 383 384/** 385 * e1000_read_phy_reg_igp - Read igp PHY register 386 * @hw: pointer to the HW structure 387 * @offset: register offset to be read 388 * @data: pointer to the read data 389 * 390 * Acquires semaphore, if necessary, then reads the PHY register at offset 391 * and storing the retrieved information in data. Release any acquired 392 * semaphores before exiting. 393 **/ 394s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 395{ 396 s32 ret_val = E1000_SUCCESS; 397 398 DEBUGFUNC("e1000_read_phy_reg_igp"); 399 400 if (!(hw->phy.ops.acquire)) 401 goto out; 402 403 ret_val = hw->phy.ops.acquire(hw); 404 if (ret_val) 405 goto out; 406 407 if (offset > MAX_PHY_MULTI_PAGE_REG) { 408 ret_val = e1000_write_phy_reg_mdic(hw, 409 IGP01E1000_PHY_PAGE_SELECT, 410 (u16)offset); 411 if (ret_val) { 412 hw->phy.ops.release(hw); 413 goto out; 414 } 415 } 416 417 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 418 data); 419 420 hw->phy.ops.release(hw); 421 422out: 423 return ret_val; 424} 425 426/** 427 * e1000_write_phy_reg_igp - Write igp PHY register 428 * @hw: pointer to the HW structure 429 * @offset: register offset to write to 430 * @data: data to write at register offset 431 * 432 * Acquires semaphore, if necessary, then writes the data to PHY register 433 * at the offset. Release any acquired semaphores before exiting. 434 **/ 435s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 436{ 437 s32 ret_val = E1000_SUCCESS; 438 439 DEBUGFUNC("e1000_write_phy_reg_igp"); 440 441 if (!(hw->phy.ops.acquire)) 442 goto out; 443 444 ret_val = hw->phy.ops.acquire(hw); 445 if (ret_val) 446 goto out; 447 448 if (offset > MAX_PHY_MULTI_PAGE_REG) { 449 ret_val = e1000_write_phy_reg_mdic(hw, 450 IGP01E1000_PHY_PAGE_SELECT, 451 (u16)offset); 452 if (ret_val) { 453 hw->phy.ops.release(hw); 454 goto out; 455 } 456 } 457 458 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 459 data); 460 461 hw->phy.ops.release(hw); 462 463out: 464 return ret_val; 465} 466 467/** 468 * e1000_read_kmrn_reg_generic - Read kumeran register 469 * @hw: pointer to the HW structure 470 * @offset: register offset to be read 471 * @data: pointer to the read data 472 * 473 * Acquires semaphore, if necessary. Then reads the PHY register at offset 474 * using the kumeran interface. The information retrieved is stored in data. 475 * Release any acquired semaphores before exiting. 476 **/ 477s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 478{ 479 u32 kmrnctrlsta; 480 s32 ret_val = E1000_SUCCESS; 481 482 DEBUGFUNC("e1000_read_kmrn_reg_generic"); 483 484 if (!(hw->phy.ops.acquire)) 485 goto out; 486 487 ret_val = hw->phy.ops.acquire(hw); 488 if (ret_val) 489 goto out; 490 491 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 492 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 493 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 494 495 usec_delay(2); 496 497 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 498 *data = (u16)kmrnctrlsta; 499 500 hw->phy.ops.release(hw); 501 502out: 503 return ret_val; 504} 505 506/** 507 * e1000_write_kmrn_reg_generic - Write kumeran register 508 * @hw: pointer to the HW structure 509 * @offset: register offset to write to 510 * @data: data to write at register offset 511 * 512 * Acquires semaphore, if necessary. Then write the data to PHY register 513 * at the offset using the kumeran interface. Release any acquired semaphores 514 * before exiting. 515 **/ 516s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 517{ 518 u32 kmrnctrlsta; 519 s32 ret_val = E1000_SUCCESS; 520 521 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 522 523 if (!(hw->phy.ops.acquire)) 524 goto out; 525 526 ret_val = hw->phy.ops.acquire(hw); 527 if (ret_val) 528 goto out; 529 530 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 531 E1000_KMRNCTRLSTA_OFFSET) | data; 532 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 533 534 usec_delay(2); 535 hw->phy.ops.release(hw); 536 537out: 538 return ret_val; 539} 540 541/** 542 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 543 * @hw: pointer to the HW structure 544 * 545 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 546 * and downshift values are set also. 547 **/ 548s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 549{ 550 struct e1000_phy_info *phy = &hw->phy; 551 s32 ret_val; 552 u16 phy_data; 553 554 DEBUGFUNC("e1000_copper_link_setup_m88"); 555 556 if (phy->reset_disable) { 557 ret_val = E1000_SUCCESS; 558 goto out; 559 } 560 561 /* Enable CRS on TX. This must be set for half-duplex operation. */ 562 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 563 if (ret_val) 564 goto out; 565 566 /* For newer PHYs this bit is downshift enable */ 567 if (phy->type == e1000_phy_m88) 568 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 569 570 /* 571 * Options: 572 * MDI/MDI-X = 0 (default) 573 * 0 - Auto for all speeds 574 * 1 - MDI mode 575 * 2 - MDI-X mode 576 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 577 */ 578 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 579 580 switch (phy->mdix) { 581 case 1: 582 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 583 break; 584 case 2: 585 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 586 break; 587 case 3: 588 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 589 break; 590 case 0: 591 default: 592 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 593 break; 594 } 595 596 /* 597 * Options: 598 * disable_polarity_correction = 0 (default) 599 * Automatic Correction for Reversed Cable Polarity 600 * 0 - Disabled 601 * 1 - Enabled 602 */ 603 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 604 if (phy->disable_polarity_correction == 1) 605 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 606 607 /* Enable downshift on BM (disabled by default) */ 608 if (phy->type == e1000_phy_bm) 609 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 610 611 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 612 if (ret_val) 613 goto out; 614 615 if ((phy->type == e1000_phy_m88) && 616 (phy->revision < E1000_REVISION_4) && 617 (phy->id != BME1000_E_PHY_ID_R2)) { 618 /* 619 * Force TX_CLK in the Extended PHY Specific Control Register 620 * to 25MHz clock. 621 */ 622 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 623 &phy_data); 624 if (ret_val) 625 goto out; 626 627 phy_data |= M88E1000_EPSCR_TX_CLK_25; 628 629 if ((phy->revision == E1000_REVISION_2) && 630 (phy->id == M88E1111_I_PHY_ID)) { 631 /* 82573L PHY - set the downshift counter to 5x. */ 632 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 633 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 634 } else { 635 /* Configure Master and Slave downshift values */ 636 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 637 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 638 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 639 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 640 } 641 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 642 phy_data); 643 if (ret_val) 644 goto out; 645 } 646 647 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 648 /* Set PHY page 0, register 29 to 0x0003 */ 649 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 650 if (ret_val) 651 goto out; 652 653 /* Set PHY page 0, register 30 to 0x0000 */ 654 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 655 if (ret_val) 656 goto out; 657 } 658 659 /* Commit the changes. */ 660 ret_val = phy->ops.commit(hw); 661 if (ret_val) { 662 DEBUGOUT("Error committing the PHY changes\n"); 663 goto out; 664 } 665 666out: 667 return ret_val; 668} 669 670/** 671 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 672 * @hw: pointer to the HW structure 673 * 674 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 675 * igp PHY's. 676 **/ 677s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 678{ 679 struct e1000_phy_info *phy = &hw->phy; 680 s32 ret_val; 681 u16 data; 682 683 DEBUGFUNC("e1000_copper_link_setup_igp"); 684 685 if (phy->reset_disable) { 686 ret_val = E1000_SUCCESS; 687 goto out; 688 } 689 690 ret_val = hw->phy.ops.reset(hw); 691 if (ret_val) { 692 DEBUGOUT("Error resetting the PHY.\n"); 693 goto out; 694 } 695 696 /* 697 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 698 * timeout issues when LFS is enabled. 699 */ 700 msec_delay(100); 701 702 /* 703 * The NVM settings will configure LPLU in D3 for 704 * non-IGP1 PHYs. 705 */ 706 if (phy->type == e1000_phy_igp) { 707 /* disable lplu d3 during driver init */ 708 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 709 if (ret_val) { 710 DEBUGOUT("Error Disabling LPLU D3\n"); 711 goto out; 712 } 713 } 714 715 /* disable lplu d0 during driver init */ 716 if (hw->phy.ops.set_d0_lplu_state) { 717 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 718 if (ret_val) { 719 DEBUGOUT("Error Disabling LPLU D0\n"); 720 goto out; 721 } 722 } 723 /* Configure mdi-mdix settings */ 724 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 725 if (ret_val) 726 goto out; 727 728 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 729 730 switch (phy->mdix) { 731 case 1: 732 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 733 break; 734 case 2: 735 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 736 break; 737 case 0: 738 default: 739 data |= IGP01E1000_PSCR_AUTO_MDIX; 740 break; 741 } 742 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 743 if (ret_val) 744 goto out; 745 746 /* set auto-master slave resolution settings */ 747 if (hw->mac.autoneg) { 748 /* 749 * when autonegotiation advertisement is only 1000Mbps then we 750 * should disable SmartSpeed and enable Auto MasterSlave 751 * resolution as hardware default. 752 */ 753 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 754 /* Disable SmartSpeed */ 755 ret_val = phy->ops.read_reg(hw, 756 IGP01E1000_PHY_PORT_CONFIG, 757 &data); 758 if (ret_val) 759 goto out; 760 761 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 762 ret_val = phy->ops.write_reg(hw, 763 IGP01E1000_PHY_PORT_CONFIG, 764 data); 765 if (ret_val) 766 goto out; 767 768 /* Set auto Master/Slave resolution process */ 769 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 770 if (ret_val) 771 goto out; 772 773 data &= ~CR_1000T_MS_ENABLE; 774 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 775 if (ret_val) 776 goto out; 777 } 778 779 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 780 if (ret_val) 781 goto out; 782 783 /* load defaults for future use */ 784 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 785 ((data & CR_1000T_MS_VALUE) ? 786 e1000_ms_force_master : 787 e1000_ms_force_slave) : 788 e1000_ms_auto; 789 790 switch (phy->ms_type) { 791 case e1000_ms_force_master: 792 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 793 break; 794 case e1000_ms_force_slave: 795 data |= CR_1000T_MS_ENABLE; 796 data &= ~(CR_1000T_MS_VALUE); 797 break; 798 case e1000_ms_auto: 799 data &= ~CR_1000T_MS_ENABLE; 800 default: 801 break; 802 } 803 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 804 if (ret_val) 805 goto out; 806 } 807 808out: 809 return ret_val; 810} 811 812/** 813 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 814 * @hw: pointer to the HW structure 815 * 816 * Performs initial bounds checking on autoneg advertisement parameter, then 817 * configure to advertise the full capability. Setup the PHY to autoneg 818 * and restart the negotiation process between the link partner. If 819 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 820 **/ 821s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 822{ 823 struct e1000_phy_info *phy = &hw->phy; 824 s32 ret_val; 825 u16 phy_ctrl; 826 827 DEBUGFUNC("e1000_copper_link_autoneg"); 828 829 /* 830 * Perform some bounds checking on the autoneg advertisement 831 * parameter. 832 */ 833 phy->autoneg_advertised &= phy->autoneg_mask; 834 835 /* 836 * If autoneg_advertised is zero, we assume it was not defaulted 837 * by the calling code so we set to advertise full capability. 838 */ 839 if (phy->autoneg_advertised == 0) 840 phy->autoneg_advertised = phy->autoneg_mask; 841 842 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 843 ret_val = e1000_phy_setup_autoneg(hw); 844 if (ret_val) { 845 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 846 goto out; 847 } 848 DEBUGOUT("Restarting Auto-Neg\n"); 849 850 /* 851 * Restart auto-negotiation by setting the Auto Neg Enable bit and 852 * the Auto Neg Restart bit in the PHY control register. 853 */ 854 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 855 if (ret_val) 856 goto out; 857 858 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 859 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 860 if (ret_val) 861 goto out; 862 863 /* 864 * Does the user want to wait for Auto-Neg to complete here, or 865 * check at a later time (for example, callback routine). 866 */ 867 if (phy->autoneg_wait_to_complete) { 868 ret_val = hw->mac.ops.wait_autoneg(hw); 869 if (ret_val) { 870 DEBUGOUT("Error while waiting for " 871 "autoneg to complete\n"); 872 goto out; 873 } 874 } 875 876 hw->mac.get_link_status = TRUE; 877 878out: 879 return ret_val; 880} 881 882/** 883 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 884 * @hw: pointer to the HW structure 885 * 886 * Reads the MII auto-neg advertisement register and/or the 1000T control 887 * register and if the PHY is already setup for auto-negotiation, then 888 * return successful. Otherwise, setup advertisement and flow control to 889 * the appropriate values for the wanted auto-negotiation. 890 **/ 891s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 892{ 893 struct e1000_phy_info *phy = &hw->phy; 894 s32 ret_val; 895 u16 mii_autoneg_adv_reg; 896 u16 mii_1000t_ctrl_reg = 0; 897 898 DEBUGFUNC("e1000_phy_setup_autoneg"); 899 900 phy->autoneg_advertised &= phy->autoneg_mask; 901 902 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 903 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 904 if (ret_val) 905 goto out; 906 907 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 908 /* Read the MII 1000Base-T Control Register (Address 9). */ 909 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 910 &mii_1000t_ctrl_reg); 911 if (ret_val) 912 goto out; 913 } 914 915 /* 916 * Need to parse both autoneg_advertised and fc and set up 917 * the appropriate PHY registers. First we will parse for 918 * autoneg_advertised software override. Since we can advertise 919 * a plethora of combinations, we need to check each bit 920 * individually. 921 */ 922 923 /* 924 * First we clear all the 10/100 mb speed bits in the Auto-Neg 925 * Advertisement Register (Address 4) and the 1000 mb speed bits in 926 * the 1000Base-T Control Register (Address 9). 927 */ 928 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 929 NWAY_AR_100TX_HD_CAPS | 930 NWAY_AR_10T_FD_CAPS | 931 NWAY_AR_10T_HD_CAPS); 932 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 933 934 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 935 936 /* Do we want to advertise 10 Mb Half Duplex? */ 937 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 938 DEBUGOUT("Advertise 10mb Half duplex\n"); 939 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 940 } 941 942 /* Do we want to advertise 10 Mb Full Duplex? */ 943 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 944 DEBUGOUT("Advertise 10mb Full duplex\n"); 945 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 946 } 947 948 /* Do we want to advertise 100 Mb Half Duplex? */ 949 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 950 DEBUGOUT("Advertise 100mb Half duplex\n"); 951 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 952 } 953 954 /* Do we want to advertise 100 Mb Full Duplex? */ 955 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 956 DEBUGOUT("Advertise 100mb Full duplex\n"); 957 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 958 } 959 960 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 961 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 962 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 963 964 /* Do we want to advertise 1000 Mb Full Duplex? */ 965 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 966 DEBUGOUT("Advertise 1000mb Full duplex\n"); 967 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 968 } 969 970 /* 971 * Check for a software override of the flow control settings, and 972 * setup the PHY advertisement registers accordingly. If 973 * auto-negotiation is enabled, then software will have to set the 974 * "PAUSE" bits to the correct value in the Auto-Negotiation 975 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 976 * negotiation. 977 * 978 * The possible values of the "fc" parameter are: 979 * 0: Flow control is completely disabled 980 * 1: Rx flow control is enabled (we can receive pause frames 981 * but not send pause frames). 982 * 2: Tx flow control is enabled (we can send pause frames 983 * but we do not support receiving pause frames). 984 * 3: Both Rx and Tx flow control (symmetric) are enabled. 985 * other: No software override. The flow control configuration 986 * in the EEPROM is used. 987 */ 988 switch (hw->fc.current_mode) { 989 case e1000_fc_none: 990 /* 991 * Flow control (Rx & Tx) is completely disabled by a 992 * software over-ride. 993 */ 994 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 995 break; 996 case e1000_fc_rx_pause: 997 /* 998 * Rx Flow control is enabled, and Tx Flow control is 999 * disabled, by a software over-ride. 1000 * 1001 * Since there really isn't a way to advertise that we are 1002 * capable of Rx Pause ONLY, we will advertise that we 1003 * support both symmetric and asymmetric Rx PAUSE. Later 1004 * (in e1000_config_fc_after_link_up) we will disable the 1005 * hw's ability to send PAUSE frames. 1006 */ 1007 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1008 break; 1009 case e1000_fc_tx_pause: 1010 /* 1011 * Tx Flow control is enabled, and Rx Flow control is 1012 * disabled, by a software over-ride. 1013 */ 1014 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1015 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1016 break; 1017 case e1000_fc_full: 1018 /* 1019 * Flow control (both Rx and Tx) is enabled by a software 1020 * over-ride. 1021 */ 1022 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1023 break; 1024 default: 1025 DEBUGOUT("Flow control param set incorrectly\n"); 1026 ret_val = -E1000_ERR_CONFIG; 1027 goto out; 1028 } 1029 1030 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1031 if (ret_val) 1032 goto out; 1033 1034 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1035 1036 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1037 ret_val = phy->ops.write_reg(hw, 1038 PHY_1000T_CTRL, 1039 mii_1000t_ctrl_reg); 1040 if (ret_val) 1041 goto out; 1042 } 1043 1044out: 1045 return ret_val; 1046} 1047 1048/** 1049 * e1000_setup_copper_link_generic - Configure copper link settings 1050 * @hw: pointer to the HW structure 1051 * 1052 * Calls the appropriate function to configure the link for auto-neg or forced 1053 * speed and duplex. Then we check for link, once link is established calls 1054 * to configure collision distance and flow control are called. If link is 1055 * not established, we return -E1000_ERR_PHY (-2). 1056 **/ 1057s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1058{ 1059 s32 ret_val; 1060 bool link; 1061 1062 DEBUGFUNC("e1000_setup_copper_link_generic"); 1063 1064 if (hw->mac.autoneg) { 1065 /* 1066 * Setup autoneg and flow control advertisement and perform 1067 * autonegotiation. 1068 */ 1069 ret_val = e1000_copper_link_autoneg(hw); 1070 if (ret_val) 1071 goto out; 1072 } else { 1073 /* 1074 * PHY will be set to 10H, 10F, 100H or 100F 1075 * depending on user settings. 1076 */ 1077 DEBUGOUT("Forcing Speed and Duplex\n"); 1078 ret_val = hw->phy.ops.force_speed_duplex(hw); 1079 if (ret_val) { 1080 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1081 goto out; 1082 } 1083 } 1084 1085 /* 1086 * Check link status. Wait up to 100 microseconds for link to become 1087 * valid. 1088 */ 1089 ret_val = e1000_phy_has_link_generic(hw, 1090 COPPER_LINK_UP_LIMIT, 1091 10, 1092 &link); 1093 if (ret_val) 1094 goto out; 1095 1096 if (link) { 1097 DEBUGOUT("Valid link established!!!\n"); 1098 e1000_config_collision_dist_generic(hw); 1099 ret_val = e1000_config_fc_after_link_up_generic(hw); 1100 } else { 1101 DEBUGOUT("Unable to establish link!!!\n"); 1102 } 1103 1104out: 1105 return ret_val; 1106} 1107 1108/** 1109 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1110 * @hw: pointer to the HW structure 1111 * 1112 * Calls the PHY setup function to force speed and duplex. Clears the 1113 * auto-crossover to force MDI manually. Waits for link and returns 1114 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1115 **/ 1116s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1117{ 1118 struct e1000_phy_info *phy = &hw->phy; 1119 s32 ret_val; 1120 u16 phy_data; 1121 bool link; 1122 1123 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1124 1125 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1126 if (ret_val) 1127 goto out; 1128 1129 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1130 1131 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1132 if (ret_val) 1133 goto out; 1134 1135 /* 1136 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1137 * forced whenever speed and duplex are forced. 1138 */ 1139 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1140 if (ret_val) 1141 goto out; 1142 1143 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1144 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1145 1146 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1147 if (ret_val) 1148 goto out; 1149 1150 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1151 1152 usec_delay(1); 1153 1154 if (phy->autoneg_wait_to_complete) { 1155 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1156 1157 ret_val = e1000_phy_has_link_generic(hw, 1158 PHY_FORCE_LIMIT, 1159 100000, 1160 &link); 1161 if (ret_val) 1162 goto out; 1163 1164 if (!link) 1165 DEBUGOUT("Link taking longer than expected.\n"); 1166 1167 /* Try once more */ 1168 ret_val = e1000_phy_has_link_generic(hw, 1169 PHY_FORCE_LIMIT, 1170 100000, 1171 &link); 1172 if (ret_val) 1173 goto out; 1174 } 1175 1176out: 1177 return ret_val; 1178} 1179 1180/** 1181 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1182 * @hw: pointer to the HW structure 1183 * 1184 * Calls the PHY setup function to force speed and duplex. Clears the 1185 * auto-crossover to force MDI manually. Resets the PHY to commit the 1186 * changes. If time expires while waiting for link up, we reset the DSP. 1187 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1188 * successful completion, else return corresponding error code. 1189 **/ 1190s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1191{ 1192 struct e1000_phy_info *phy = &hw->phy; 1193 s32 ret_val; 1194 u16 phy_data; 1195 bool link; 1196 1197 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1198 1199 /* 1200 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1201 * forced whenever speed and duplex are forced. 1202 */ 1203 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1204 if (ret_val) 1205 goto out; 1206 1207 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1208 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1209 if (ret_val) 1210 goto out; 1211 1212 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1213 1214 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1215 if (ret_val) 1216 goto out; 1217 1218 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1219 1220 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1221 if (ret_val) 1222 goto out; 1223 1224 /* Reset the phy to commit changes. */ 1225 ret_val = hw->phy.ops.commit(hw); 1226 if (ret_val) 1227 goto out; 1228 1229 if (phy->autoneg_wait_to_complete) { 1230 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1231 1232 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1233 100000, &link); 1234 if (ret_val) 1235 goto out; 1236 1237 if (!link) { 1238 /* 1239 * We didn't get link. 1240 * Reset the DSP and cross our fingers. 1241 */ 1242 ret_val = phy->ops.write_reg(hw, 1243 M88E1000_PHY_PAGE_SELECT, 1244 0x001d); 1245 if (ret_val) 1246 goto out; 1247 ret_val = e1000_phy_reset_dsp_generic(hw); 1248 if (ret_val) 1249 goto out; 1250 } 1251 1252 /* Try once more */ 1253 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1254 100000, &link); 1255 if (ret_val) 1256 goto out; 1257 } 1258 1259 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1260 if (ret_val) 1261 goto out; 1262 1263 /* 1264 * Resetting the phy means we need to re-force TX_CLK in the 1265 * Extended PHY Specific Control Register to 25MHz clock from 1266 * the reset value of 2.5MHz. 1267 */ 1268 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1269 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1270 if (ret_val) 1271 goto out; 1272 1273 /* 1274 * In addition, we must re-enable CRS on Tx for both half and full 1275 * duplex. 1276 */ 1277 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1278 if (ret_val) 1279 goto out; 1280 1281 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1282 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1283 1284out: 1285 return ret_val; 1286} 1287 1288/** 1289 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1290 * @hw: pointer to the HW structure 1291 * @phy_ctrl: pointer to current value of PHY_CONTROL 1292 * 1293 * Forces speed and duplex on the PHY by doing the following: disable flow 1294 * control, force speed/duplex on the MAC, disable auto speed detection, 1295 * disable auto-negotiation, configure duplex, configure speed, configure 1296 * the collision distance, write configuration to CTRL register. The 1297 * caller must write to the PHY_CONTROL register for these settings to 1298 * take affect. 1299 **/ 1300void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 1301{ 1302 struct e1000_mac_info *mac = &hw->mac; 1303 u32 ctrl; 1304 1305 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 1306 1307 /* Turn off flow control when forcing speed/duplex */ 1308 hw->fc.current_mode = e1000_fc_none; 1309 1310 /* Force speed/duplex on the mac */ 1311 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1312 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1313 ctrl &= ~E1000_CTRL_SPD_SEL; 1314 1315 /* Disable Auto Speed Detection */ 1316 ctrl &= ~E1000_CTRL_ASDE; 1317 1318 /* Disable autoneg on the phy */ 1319 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1320 1321 /* Forcing Full or Half Duplex? */ 1322 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1323 ctrl &= ~E1000_CTRL_FD; 1324 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1325 DEBUGOUT("Half Duplex\n"); 1326 } else { 1327 ctrl |= E1000_CTRL_FD; 1328 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1329 DEBUGOUT("Full Duplex\n"); 1330 } 1331 1332 /* Forcing 10mb or 100mb? */ 1333 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1334 ctrl |= E1000_CTRL_SPD_100; 1335 *phy_ctrl |= MII_CR_SPEED_100; 1336 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1337 DEBUGOUT("Forcing 100mb\n"); 1338 } else { 1339 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1340 *phy_ctrl |= MII_CR_SPEED_10; 1341 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1342 DEBUGOUT("Forcing 10mb\n"); 1343 } 1344 1345 e1000_config_collision_dist_generic(hw); 1346 1347 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1348} 1349 1350/** 1351 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 1352 * @hw: pointer to the HW structure 1353 * @active: boolean used to enable/disable lplu 1354 * 1355 * Success returns 0, Failure returns 1 1356 * 1357 * The low power link up (lplu) state is set to the power management level D3 1358 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 1359 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1360 * is used during Dx states where the power conservation is most important. 1361 * During driver activity, SmartSpeed should be enabled so performance is 1362 * maintained. 1363 **/ 1364s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 1365{ 1366 struct e1000_phy_info *phy = &hw->phy; 1367 s32 ret_val = E1000_SUCCESS; 1368 u16 data; 1369 1370 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 1371 1372 if (!(hw->phy.ops.read_reg)) 1373 goto out; 1374 1375 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1376 if (ret_val) 1377 goto out; 1378 1379 if (!active) { 1380 data &= ~IGP02E1000_PM_D3_LPLU; 1381 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1382 data); 1383 if (ret_val) 1384 goto out; 1385 /* 1386 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1387 * during Dx states where the power conservation is most 1388 * important. During driver activity we should enable 1389 * SmartSpeed, so performance is maintained. 1390 */ 1391 if (phy->smart_speed == e1000_smart_speed_on) { 1392 ret_val = phy->ops.read_reg(hw, 1393 IGP01E1000_PHY_PORT_CONFIG, 1394 &data); 1395 if (ret_val) 1396 goto out; 1397 1398 data |= IGP01E1000_PSCFR_SMART_SPEED; 1399 ret_val = phy->ops.write_reg(hw, 1400 IGP01E1000_PHY_PORT_CONFIG, 1401 data); 1402 if (ret_val) 1403 goto out; 1404 } else if (phy->smart_speed == e1000_smart_speed_off) { 1405 ret_val = phy->ops.read_reg(hw, 1406 IGP01E1000_PHY_PORT_CONFIG, 1407 &data); 1408 if (ret_val) 1409 goto out; 1410 1411 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1412 ret_val = phy->ops.write_reg(hw, 1413 IGP01E1000_PHY_PORT_CONFIG, 1414 data); 1415 if (ret_val) 1416 goto out; 1417 } 1418 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1419 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1420 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1421 data |= IGP02E1000_PM_D3_LPLU; 1422 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1423 data); 1424 if (ret_val) 1425 goto out; 1426 1427 /* When LPLU is enabled, we should disable SmartSpeed */ 1428 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1429 &data); 1430 if (ret_val) 1431 goto out; 1432 1433 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1434 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1435 data); 1436 } 1437 1438out: 1439 return ret_val; 1440} 1441 1442/** 1443 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 1444 * @hw: pointer to the HW structure 1445 * 1446 * Success returns 0, Failure returns 1 1447 * 1448 * A downshift is detected by querying the PHY link health. 1449 **/ 1450s32 e1000_check_downshift_generic(struct e1000_hw *hw) 1451{ 1452 struct e1000_phy_info *phy = &hw->phy; 1453 s32 ret_val; 1454 u16 phy_data, offset, mask; 1455 1456 DEBUGFUNC("e1000_check_downshift_generic"); 1457 1458 switch (phy->type) { 1459 case e1000_phy_m88: 1460 case e1000_phy_gg82563: 1461 case e1000_phy_bm: 1462 offset = M88E1000_PHY_SPEC_STATUS; 1463 mask = M88E1000_PSSR_DOWNSHIFT; 1464 break; 1465 case e1000_phy_igp_2: 1466 case e1000_phy_igp: 1467 case e1000_phy_igp_3: 1468 offset = IGP01E1000_PHY_LINK_HEALTH; 1469 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1470 break; 1471 default: 1472 /* speed downshift not supported */ 1473 phy->speed_downgraded = FALSE; 1474 ret_val = E1000_SUCCESS; 1475 goto out; 1476 } 1477 1478 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1479 1480 if (!ret_val) 1481 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE; 1482 1483out: 1484 return ret_val; 1485} 1486 1487/** 1488 * e1000_check_polarity_m88 - Checks the polarity. 1489 * @hw: pointer to the HW structure 1490 * 1491 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1492 * 1493 * Polarity is determined based on the PHY specific status register. 1494 **/ 1495s32 e1000_check_polarity_m88(struct e1000_hw *hw) 1496{ 1497 struct e1000_phy_info *phy = &hw->phy; 1498 s32 ret_val; 1499 u16 data; 1500 1501 DEBUGFUNC("e1000_check_polarity_m88"); 1502 1503 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1504 1505 if (!ret_val) 1506 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1507 ? e1000_rev_polarity_reversed 1508 : e1000_rev_polarity_normal; 1509 1510 return ret_val; 1511} 1512 1513/** 1514 * e1000_check_polarity_igp - Checks the polarity. 1515 * @hw: pointer to the HW structure 1516 * 1517 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1518 * 1519 * Polarity is determined based on the PHY port status register, and the 1520 * current speed (since there is no polarity at 100Mbps). 1521 **/ 1522s32 e1000_check_polarity_igp(struct e1000_hw *hw) 1523{ 1524 struct e1000_phy_info *phy = &hw->phy; 1525 s32 ret_val; 1526 u16 data, offset, mask; 1527 1528 DEBUGFUNC("e1000_check_polarity_igp"); 1529 1530 /* 1531 * Polarity is determined based on the speed of 1532 * our connection. 1533 */ 1534 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1535 if (ret_val) 1536 goto out; 1537 1538 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1539 IGP01E1000_PSSR_SPEED_1000MBPS) { 1540 offset = IGP01E1000_PHY_PCS_INIT_REG; 1541 mask = IGP01E1000_PHY_POLARITY_MASK; 1542 } else { 1543 /* 1544 * This really only applies to 10Mbps since 1545 * there is no polarity for 100Mbps (always 0). 1546 */ 1547 offset = IGP01E1000_PHY_PORT_STATUS; 1548 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1549 } 1550 1551 ret_val = phy->ops.read_reg(hw, offset, &data); 1552 1553 if (!ret_val) 1554 phy->cable_polarity = (data & mask) 1555 ? e1000_rev_polarity_reversed 1556 : e1000_rev_polarity_normal; 1557 1558out: 1559 return ret_val; 1560} 1561 1562/** 1563 * e1000_wait_autoneg_generic - Wait for auto-neg completion 1564 * @hw: pointer to the HW structure 1565 * 1566 * Waits for auto-negotiation to complete or for the auto-negotiation time 1567 * limit to expire, which ever happens first. 1568 **/ 1569s32 e1000_wait_autoneg_generic(struct e1000_hw *hw) 1570{ 1571 s32 ret_val = E1000_SUCCESS; 1572 u16 i, phy_status; 1573 1574 DEBUGFUNC("e1000_wait_autoneg_generic"); 1575 1576 if (!(hw->phy.ops.read_reg)) 1577 return E1000_SUCCESS; 1578 1579 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1580 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1581 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1582 if (ret_val) 1583 break; 1584 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1585 if (ret_val) 1586 break; 1587 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1588 break; 1589 msec_delay(100); 1590 } 1591 1592 /* 1593 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1594 * has completed. 1595 */ 1596 return ret_val; 1597} 1598 1599/** 1600 * e1000_phy_has_link_generic - Polls PHY for link 1601 * @hw: pointer to the HW structure 1602 * @iterations: number of times to poll for link 1603 * @usec_interval: delay between polling attempts 1604 * @success: pointer to whether polling was successful or not 1605 * 1606 * Polls the PHY status register for link, 'iterations' number of times. 1607 **/ 1608s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 1609 u32 usec_interval, bool *success) 1610{ 1611 s32 ret_val = E1000_SUCCESS; 1612 u16 i, phy_status; 1613 1614 DEBUGFUNC("e1000_phy_has_link_generic"); 1615 1616 if (!(hw->phy.ops.read_reg)) 1617 return E1000_SUCCESS; 1618 1619 for (i = 0; i < iterations; i++) { 1620 /* 1621 * Some PHYs require the PHY_STATUS register to be read 1622 * twice due to the link bit being sticky. No harm doing 1623 * it across the board. 1624 */ 1625 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1626 if (ret_val) 1627 break; 1628 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1629 if (ret_val) 1630 break; 1631 if (phy_status & MII_SR_LINK_STATUS) 1632 break; 1633 if (usec_interval >= 1000) 1634 msec_delay_irq(usec_interval/1000); 1635 else 1636 usec_delay(usec_interval); 1637 } 1638 1639 *success = (i < iterations) ? TRUE : FALSE; 1640 1641 return ret_val; 1642} 1643 1644/** 1645 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 1646 * @hw: pointer to the HW structure 1647 * 1648 * Reads the PHY specific status register to retrieve the cable length 1649 * information. The cable length is determined by averaging the minimum and 1650 * maximum values to get the "average" cable length. The m88 PHY has four 1651 * possible cable length values, which are: 1652 * Register Value Cable Length 1653 * 0 < 50 meters 1654 * 1 50 - 80 meters 1655 * 2 80 - 110 meters 1656 * 3 110 - 140 meters 1657 * 4 > 140 meters 1658 **/ 1659s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 1660{ 1661 struct e1000_phy_info *phy = &hw->phy; 1662 s32 ret_val; 1663 u16 phy_data, index; 1664 1665 DEBUGFUNC("e1000_get_cable_length_m88"); 1666 1667 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1668 if (ret_val) 1669 goto out; 1670 1671 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1672 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1673 if (index < M88E1000_CABLE_LENGTH_TABLE_SIZE + 1) { 1674 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1675 phy->max_cable_length = e1000_m88_cable_length_table[index+1]; 1676 1677 phy->cable_length = (phy->min_cable_length + 1678 phy->max_cable_length) / 2; 1679 } else { 1680 ret_val = E1000_ERR_PHY; 1681 } 1682 1683out: 1684 return ret_val; 1685} 1686 1687/** 1688 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1689 * @hw: pointer to the HW structure 1690 * 1691 * The automatic gain control (agc) normalizes the amplitude of the 1692 * received signal, adjusting for the attenuation produced by the 1693 * cable. By reading the AGC registers, which represent the 1694 * combination of coarse and fine gain value, the value can be put 1695 * into a lookup table to obtain the approximate cable length 1696 * for each channel. 1697 **/ 1698s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 1699{ 1700 struct e1000_phy_info *phy = &hw->phy; 1701 s32 ret_val = E1000_SUCCESS; 1702 u16 phy_data, i, agc_value = 0; 1703 u16 cur_agc_index, max_agc_index = 0; 1704 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1705 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = 1706 {IGP02E1000_PHY_AGC_A, 1707 IGP02E1000_PHY_AGC_B, 1708 IGP02E1000_PHY_AGC_C, 1709 IGP02E1000_PHY_AGC_D}; 1710 1711 DEBUGFUNC("e1000_get_cable_length_igp_2"); 1712 1713 /* Read the AGC registers for all channels */ 1714 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1715 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1716 if (ret_val) 1717 goto out; 1718 1719 /* 1720 * Getting bits 15:9, which represent the combination of 1721 * coarse and fine gain values. The result is a number 1722 * that can be put into the lookup table to obtain the 1723 * approximate cable length. 1724 */ 1725 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1726 IGP02E1000_AGC_LENGTH_MASK; 1727 1728 /* Array index bound check. */ 1729 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1730 (cur_agc_index == 0)) { 1731 ret_val = -E1000_ERR_PHY; 1732 goto out; 1733 } 1734 1735 /* Remove min & max AGC values from calculation. */ 1736 if (e1000_igp_2_cable_length_table[min_agc_index] > 1737 e1000_igp_2_cable_length_table[cur_agc_index]) 1738 min_agc_index = cur_agc_index; 1739 if (e1000_igp_2_cable_length_table[max_agc_index] < 1740 e1000_igp_2_cable_length_table[cur_agc_index]) 1741 max_agc_index = cur_agc_index; 1742 1743 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1744 } 1745 1746 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1747 e1000_igp_2_cable_length_table[max_agc_index]); 1748 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1749 1750 /* Calculate cable length with the error range of +/- 10 meters. */ 1751 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1752 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1753 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1754 1755 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1756 1757out: 1758 return ret_val; 1759} 1760 1761/** 1762 * e1000_get_phy_info_m88 - Retrieve PHY information 1763 * @hw: pointer to the HW structure 1764 * 1765 * Valid for only copper links. Read the PHY status register (sticky read) 1766 * to verify that link is up. Read the PHY special control register to 1767 * determine the polarity and 10base-T extended distance. Read the PHY 1768 * special status register to determine MDI/MDIx and current speed. If 1769 * speed is 1000, then determine cable length, local and remote receiver. 1770 **/ 1771s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 1772{ 1773 struct e1000_phy_info *phy = &hw->phy; 1774 s32 ret_val; 1775 u16 phy_data; 1776 bool link; 1777 1778 DEBUGFUNC("e1000_get_phy_info_m88"); 1779 1780 if (hw->phy.media_type != e1000_media_type_copper) { 1781 DEBUGOUT("Phy info is only valid for copper media\n"); 1782 ret_val = -E1000_ERR_CONFIG; 1783 goto out; 1784 } 1785 1786 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1787 if (ret_val) 1788 goto out; 1789 1790 if (!link) { 1791 DEBUGOUT("Phy info is only valid if link is up\n"); 1792 ret_val = -E1000_ERR_CONFIG; 1793 goto out; 1794 } 1795 1796 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1797 if (ret_val) 1798 goto out; 1799 1800 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1801 ? TRUE : FALSE; 1802 1803 ret_val = e1000_check_polarity_m88(hw); 1804 if (ret_val) 1805 goto out; 1806 1807 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1808 if (ret_val) 1809 goto out; 1810 1811 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE; 1812 1813 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1814 ret_val = hw->phy.ops.get_cable_length(hw); 1815 if (ret_val) 1816 goto out; 1817 1818 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 1819 if (ret_val) 1820 goto out; 1821 1822 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1823 ? e1000_1000t_rx_status_ok 1824 : e1000_1000t_rx_status_not_ok; 1825 1826 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1827 ? e1000_1000t_rx_status_ok 1828 : e1000_1000t_rx_status_not_ok; 1829 } else { 1830 /* Set values to "undefined" */ 1831 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1832 phy->local_rx = e1000_1000t_rx_status_undefined; 1833 phy->remote_rx = e1000_1000t_rx_status_undefined; 1834 } 1835 1836out: 1837 return ret_val; 1838} 1839 1840/** 1841 * e1000_get_phy_info_igp - Retrieve igp PHY information 1842 * @hw: pointer to the HW structure 1843 * 1844 * Read PHY status to determine if link is up. If link is up, then 1845 * set/determine 10base-T extended distance and polarity correction. Read 1846 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1847 * determine on the cable length, local and remote receiver. 1848 **/ 1849s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 1850{ 1851 struct e1000_phy_info *phy = &hw->phy; 1852 s32 ret_val; 1853 u16 data; 1854 bool link; 1855 1856 DEBUGFUNC("e1000_get_phy_info_igp"); 1857 1858 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 1859 if (ret_val) 1860 goto out; 1861 1862 if (!link) { 1863 DEBUGOUT("Phy info is only valid if link is up\n"); 1864 ret_val = -E1000_ERR_CONFIG; 1865 goto out; 1866 } 1867 1868 phy->polarity_correction = TRUE; 1869 1870 ret_val = e1000_check_polarity_igp(hw); 1871 if (ret_val) 1872 goto out; 1873 1874 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1875 if (ret_val) 1876 goto out; 1877 1878 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE; 1879 1880 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1881 IGP01E1000_PSSR_SPEED_1000MBPS) { 1882 ret_val = hw->phy.ops.get_cable_length(hw); 1883 if (ret_val) 1884 goto out; 1885 1886 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 1887 if (ret_val) 1888 goto out; 1889 1890 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 1891 ? e1000_1000t_rx_status_ok 1892 : e1000_1000t_rx_status_not_ok; 1893 1894 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 1895 ? e1000_1000t_rx_status_ok 1896 : e1000_1000t_rx_status_not_ok; 1897 } else { 1898 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1899 phy->local_rx = e1000_1000t_rx_status_undefined; 1900 phy->remote_rx = e1000_1000t_rx_status_undefined; 1901 } 1902 1903out: 1904 return ret_val; 1905} 1906 1907/** 1908 * e1000_phy_sw_reset_generic - PHY software reset 1909 * @hw: pointer to the HW structure 1910 * 1911 * Does a software reset of the PHY by reading the PHY control register and 1912 * setting/write the control register reset bit to the PHY. 1913 **/ 1914s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 1915{ 1916 s32 ret_val = E1000_SUCCESS; 1917 u16 phy_ctrl; 1918 1919 DEBUGFUNC("e1000_phy_sw_reset_generic"); 1920 1921 if (!(hw->phy.ops.read_reg)) 1922 goto out; 1923 1924 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1925 if (ret_val) 1926 goto out; 1927 1928 phy_ctrl |= MII_CR_RESET; 1929 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1930 if (ret_val) 1931 goto out; 1932 1933 usec_delay(1); 1934 1935out: 1936 return ret_val; 1937} 1938 1939/** 1940 * e1000_phy_hw_reset_generic - PHY hardware reset 1941 * @hw: pointer to the HW structure 1942 * 1943 * Verify the reset block is not blocking us from resetting. Acquire 1944 * semaphore (if necessary) and read/set/write the device control reset 1945 * bit in the PHY. Wait the appropriate delay time for the device to 1946 * reset and release the semaphore (if necessary). 1947 **/ 1948s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 1949{ 1950 struct e1000_phy_info *phy = &hw->phy; 1951 s32 ret_val = E1000_SUCCESS; 1952 u32 ctrl; 1953 1954 DEBUGFUNC("e1000_phy_hw_reset_generic"); 1955 1956 ret_val = phy->ops.check_reset_block(hw); 1957 if (ret_val) { 1958 ret_val = E1000_SUCCESS; 1959 goto out; 1960 } 1961 1962 ret_val = phy->ops.acquire(hw); 1963 if (ret_val) 1964 goto out; 1965 1966 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1967 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 1968 E1000_WRITE_FLUSH(hw); 1969 1970 usec_delay(phy->reset_delay_us); 1971 1972 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1973 E1000_WRITE_FLUSH(hw); 1974 1975 usec_delay(150); 1976 1977 phy->ops.release(hw); 1978 1979 ret_val = phy->ops.get_cfg_done(hw); 1980 1981out: 1982 return ret_val; 1983} 1984 1985/** 1986 * e1000_get_cfg_done_generic - Generic configuration done 1987 * @hw: pointer to the HW structure 1988 * 1989 * Generic function to wait 10 milli-seconds for configuration to complete 1990 * and return success. 1991 **/ 1992s32 e1000_get_cfg_done_generic(struct e1000_hw *hw) 1993{ 1994 DEBUGFUNC("e1000_get_cfg_done_generic"); 1995 1996 msec_delay_irq(10); 1997 1998 return E1000_SUCCESS; 1999} 2000 2001/** 2002 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2003 * @hw: pointer to the HW structure 2004 * 2005 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2006 **/ 2007s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2008{ 2009 DEBUGOUT("Running IGP 3 PHY init script\n"); 2010 2011 /* PHY init IGP 3 */ 2012 /* Enable rise/fall, 10-mode work in class-A */ 2013 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2014 /* Remove all caps from Replica path filter */ 2015 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2016 /* Bias trimming for ADC, AFE and Driver (Default) */ 2017 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2018 /* Increase Hybrid poly bias */ 2019 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2020 /* Add 4% to Tx amplitude in Gig mode */ 2021 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2022 /* Disable trimming (TTT) */ 2023 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2024 /* Poly DC correction to 94.6% + 2% for all channels */ 2025 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2026 /* ABS DC correction to 95.9% */ 2027 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2028 /* BG temp curve trim */ 2029 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2030 /* Increasing ADC OPAMP stage 1 currents to max */ 2031 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2032 /* Force 1000 ( required for enabling PHY regs configuration) */ 2033 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2034 /* Set upd_freq to 6 */ 2035 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2036 /* Disable NPDFE */ 2037 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2038 /* Disable adaptive fixed FFE (Default) */ 2039 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2040 /* Enable FFE hysteresis */ 2041 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2042 /* Fixed FFE for short cable lengths */ 2043 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2044 /* Fixed FFE for medium cable lengths */ 2045 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2046 /* Fixed FFE for long cable lengths */ 2047 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2048 /* Enable Adaptive Clip Threshold */ 2049 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2050 /* AHT reset limit to 1 */ 2051 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2052 /* Set AHT master delay to 127 msec */ 2053 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2054 /* Set scan bits for AHT */ 2055 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2056 /* Set AHT Preset bits */ 2057 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2058 /* Change integ_factor of channel A to 3 */ 2059 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2060 /* Change prop_factor of channels BCD to 8 */ 2061 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2062 /* Change cg_icount + enable integbp for channels BCD */ 2063 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2064 /* 2065 * Change cg_icount + enable integbp + change prop_factor_master 2066 * to 8 for channel A 2067 */ 2068 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2069 /* Disable AHT in Slave mode on channel A */ 2070 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2071 /* 2072 * Enable LPLU and disable AN to 1000 in non-D0a states, 2073 * Enable SPD+B2B 2074 */ 2075 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2076 /* Enable restart AN on an1000_dis change */ 2077 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2078 /* Enable wh_fifo read clock in 10/100 modes */ 2079 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2080 /* Restart AN, Speed selection is 1000 */ 2081 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2082 2083 return E1000_SUCCESS; 2084} 2085 2086/** 2087 * e1000_get_phy_type_from_id - Get PHY type from id 2088 * @phy_id: phy_id read from the phy 2089 * 2090 * Returns the phy type from the id. 2091 **/ 2092enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2093{ 2094 enum e1000_phy_type phy_type = e1000_phy_unknown; 2095 2096 switch (phy_id) { 2097 case M88E1000_I_PHY_ID: 2098 case M88E1000_E_PHY_ID: 2099 case M88E1111_I_PHY_ID: 2100 case M88E1011_I_PHY_ID: 2101 phy_type = e1000_phy_m88; 2102 break; 2103 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 2104 phy_type = e1000_phy_igp_2; 2105 break; 2106 case GG82563_E_PHY_ID: 2107 phy_type = e1000_phy_gg82563; 2108 break; 2109 case IGP03E1000_E_PHY_ID: 2110 phy_type = e1000_phy_igp_3; 2111 break; 2112 case IFE_E_PHY_ID: 2113 case IFE_PLUS_E_PHY_ID: 2114 case IFE_C_E_PHY_ID: 2115 phy_type = e1000_phy_ife; 2116 break; 2117 case BME1000_E_PHY_ID: 2118 case BME1000_E_PHY_ID_R2: 2119 phy_type = e1000_phy_bm; 2120 break; 2121 default: 2122 phy_type = e1000_phy_unknown; 2123 break; 2124 } 2125 return phy_type; 2126} 2127 2128/** 2129 * e1000_determine_phy_address - Determines PHY address. 2130 * @hw: pointer to the HW structure 2131 * 2132 * This uses a trial and error method to loop through possible PHY 2133 * addresses. It tests each by reading the PHY ID registers and 2134 * checking for a match. 2135 **/ 2136s32 e1000_determine_phy_address(struct e1000_hw *hw) 2137{ 2138 s32 ret_val = -E1000_ERR_PHY_TYPE; 2139 u32 phy_addr = 0; 2140 u32 i; 2141 enum e1000_phy_type phy_type = e1000_phy_unknown; 2142 2143 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 2144 hw->phy.addr = phy_addr; 2145 i = 0; 2146 2147 do { 2148 e1000_get_phy_id(hw); 2149 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 2150 2151 /* 2152 * If phy_type is valid, break - we found our 2153 * PHY address 2154 */ 2155 if (phy_type != e1000_phy_unknown) { 2156 ret_val = E1000_SUCCESS; 2157 goto out; 2158 } 2159 msec_delay(1); 2160 i++; 2161 } while (i < 10); 2162 } 2163 2164out: 2165 return ret_val; 2166} 2167 2168/** 2169 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 2170 * @page: page to access 2171 * 2172 * Returns the phy address for the page requested. 2173 **/ 2174static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 2175{ 2176 u32 phy_addr = 2; 2177 2178 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 2179 phy_addr = 1; 2180 2181 return phy_addr; 2182} 2183 2184/** 2185 * e1000_write_phy_reg_bm - Write BM PHY register 2186 * @hw: pointer to the HW structure 2187 * @offset: register offset to write to 2188 * @data: data to write at register offset 2189 * 2190 * Acquires semaphore, if necessary, then writes the data to PHY register 2191 * at the offset. Release any acquired semaphores before exiting. 2192 **/ 2193s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 2194{ 2195 s32 ret_val; 2196 u32 page_select = 0; 2197 u32 page = offset >> IGP_PAGE_SHIFT; 2198 u32 page_shift = 0; 2199 2200 DEBUGFUNC("e1000_write_phy_reg_bm"); 2201 2202 /* Page 800 works differently than the rest so it has its own func */ 2203 if (page == BM_WUC_PAGE) { 2204 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2205 FALSE); 2206 goto out; 2207 } 2208 2209 ret_val = hw->phy.ops.acquire(hw); 2210 if (ret_val) 2211 goto out; 2212 2213 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2214 2215 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2216 /* 2217 * Page select is register 31 for phy address 1 and 22 for 2218 * phy address 2 and 3. Page select is shifted only for 2219 * phy address 1. 2220 */ 2221 if (hw->phy.addr == 1) { 2222 page_shift = IGP_PAGE_SHIFT; 2223 page_select = IGP01E1000_PHY_PAGE_SELECT; 2224 } else { 2225 page_shift = 0; 2226 page_select = BM_PHY_PAGE_SELECT; 2227 } 2228 2229 /* Page is shifted left, PHY expects (page x 32) */ 2230 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2231 (page << page_shift)); 2232 if (ret_val) { 2233 hw->phy.ops.release(hw); 2234 goto out; 2235 } 2236 } 2237 2238 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2239 data); 2240 2241 hw->phy.ops.release(hw); 2242 2243out: 2244 return ret_val; 2245} 2246 2247/** 2248 * e1000_read_phy_reg_bm - Read BM PHY register 2249 * @hw: pointer to the HW structure 2250 * @offset: register offset to be read 2251 * @data: pointer to the read data 2252 * 2253 * Acquires semaphore, if necessary, then reads the PHY register at offset 2254 * and storing the retrieved information in data. Release any acquired 2255 * semaphores before exiting. 2256 **/ 2257s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 2258{ 2259 s32 ret_val; 2260 u32 page_select = 0; 2261 u32 page = offset >> IGP_PAGE_SHIFT; 2262 u32 page_shift = 0; 2263 2264 DEBUGFUNC("e1000_read_phy_reg_bm"); 2265 2266 /* Page 800 works differently than the rest so it has its own func */ 2267 if (page == BM_WUC_PAGE) { 2268 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2269 TRUE); 2270 goto out; 2271 } 2272 2273 ret_val = hw->phy.ops.acquire(hw); 2274 if (ret_val) 2275 goto out; 2276 2277 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 2278 2279 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2280 /* 2281 * Page select is register 31 for phy address 1 and 22 for 2282 * phy address 2 and 3. Page select is shifted only for 2283 * phy address 1. 2284 */ 2285 if (hw->phy.addr == 1) { 2286 page_shift = IGP_PAGE_SHIFT; 2287 page_select = IGP01E1000_PHY_PAGE_SELECT; 2288 } else { 2289 page_shift = 0; 2290 page_select = BM_PHY_PAGE_SELECT; 2291 } 2292 2293 /* Page is shifted left, PHY expects (page x 32) */ 2294 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 2295 (page << page_shift)); 2296 if (ret_val) { 2297 hw->phy.ops.release(hw); 2298 goto out; 2299 } 2300 } 2301 2302 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2303 data); 2304 hw->phy.ops.release(hw); 2305 2306out: 2307 return ret_val; 2308} 2309 2310/** 2311 * e1000_read_phy_reg_bm2 - Read BM PHY register 2312 * @hw: pointer to the HW structure 2313 * @offset: register offset to be read 2314 * @data: pointer to the read data 2315 * 2316 * Acquires semaphore, if necessary, then reads the PHY register at offset 2317 * and storing the retrieved information in data. Release any acquired 2318 * semaphores before exiting. 2319 **/ 2320s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 2321{ 2322 s32 ret_val; 2323 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2324 2325 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2326 2327 /* Page 800 works differently than the rest so it has its own func */ 2328 if (page == BM_WUC_PAGE) { 2329 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 2330 TRUE); 2331 goto out; 2332 } 2333 2334 ret_val = hw->phy.ops.acquire(hw); 2335 if (ret_val) 2336 goto out; 2337 2338 hw->phy.addr = 1; 2339 2340 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2341 2342 /* Page is shifted left, PHY expects (page x 32) */ 2343 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2344 page); 2345 2346 if (ret_val) { 2347 hw->phy.ops.release(hw); 2348 goto out; 2349 } 2350 } 2351 2352 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2353 data); 2354 hw->phy.ops.release(hw); 2355 2356out: 2357 return ret_val; 2358} 2359 2360/** 2361 * e1000_write_phy_reg_bm2 - Write BM PHY register 2362 * @hw: pointer to the HW structure 2363 * @offset: register offset to write to 2364 * @data: data to write at register offset 2365 * 2366 * Acquires semaphore, if necessary, then writes the data to PHY register 2367 * at the offset. Release any acquired semaphores before exiting. 2368 **/ 2369s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 2370{ 2371 s32 ret_val; 2372 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 2373 2374 DEBUGFUNC("e1000_write_phy_reg_bm2"); 2375 2376 /* Page 800 works differently than the rest so it has its own func */ 2377 if (page == BM_WUC_PAGE) { 2378 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 2379 FALSE); 2380 goto out; 2381 } 2382 2383 ret_val = hw->phy.ops.acquire(hw); 2384 if (ret_val) 2385 goto out; 2386 2387 hw->phy.addr = 1; 2388 2389 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2390 /* Page is shifted left, PHY expects (page x 32) */ 2391 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 2392 page); 2393 2394 if (ret_val) { 2395 hw->phy.ops.release(hw); 2396 goto out; 2397 } 2398 } 2399 2400 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 2401 data); 2402 2403 hw->phy.ops.release(hw); 2404 2405out: 2406 return ret_val; 2407} 2408 2409/** 2410 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register 2411 * @hw: pointer to the HW structure 2412 * @offset: register offset to be read or written 2413 * @data: pointer to the data to read or write 2414 * @read: determines if operation is read or write 2415 * 2416 * Acquires semaphore, if necessary, then reads the PHY register at offset 2417 * and storing the retrieved information in data. Release any acquired 2418 * semaphores before exiting. Note that procedure to read the wakeup 2419 * registers are different. It works as such: 2420 * 1) Set page 769, register 17, bit 2 = 1 2421 * 2) Set page to 800 for host (801 if we were manageability) 2422 * 3) Write the address using the address opcode (0x11) 2423 * 4) Read or write the data using the data opcode (0x12) 2424 * 5) Restore 769_17.2 to its original value 2425 **/ 2426static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 2427 u16 *data, bool read) 2428{ 2429 s32 ret_val; 2430 u16 reg = ((u16)offset); 2431 u16 phy_reg = 0; 2432 u8 phy_acquired = 1; 2433 2434 DEBUGFUNC("e1000_read_phy_wakeup_reg_bm"); 2435 2436 ret_val = hw->phy.ops.acquire(hw); 2437 if (ret_val) { 2438 DEBUGOUT("Could not acquire PHY\n"); 2439 phy_acquired = 0; 2440 goto out; 2441 } 2442 2443 /* All operations in this function are phy address 1 */ 2444 hw->phy.addr = 1; 2445 2446 /* Set page 769 */ 2447 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2448 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2449 2450 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); 2451 if (ret_val) { 2452 DEBUGOUT("Could not read PHY page 769\n"); 2453 goto out; 2454 } 2455 2456 /* First clear bit 4 to avoid a power state change */ 2457 phy_reg &= ~(BM_WUC_HOST_WU_BIT); 2458 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2459 if (ret_val) { 2460 DEBUGOUT("Could not clear PHY page 769 bit 4\n"); 2461 goto out; 2462 } 2463 2464 /* Write bit 2 = 1, and clear bit 4 to 769_17 */ 2465 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, 2466 phy_reg | BM_WUC_ENABLE_BIT); 2467 if (ret_val) { 2468 DEBUGOUT("Could not write PHY page 769 bit 2\n"); 2469 goto out; 2470 } 2471 2472 /* Select page 800 */ 2473 ret_val = e1000_write_phy_reg_mdic(hw, 2474 IGP01E1000_PHY_PAGE_SELECT, 2475 (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2476 2477 /* Write the page 800 offset value using opcode 0x11 */ 2478 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 2479 if (ret_val) { 2480 DEBUGOUT("Could not write address opcode to page 800\n"); 2481 goto out; 2482 } 2483 2484 if (read) { 2485 /* Read the page 800 value using opcode 0x12 */ 2486 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2487 data); 2488 } else { 2489 /* Read the page 800 value using opcode 0x12 */ 2490 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 2491 *data); 2492 } 2493 2494 if (ret_val) { 2495 DEBUGOUT("Could not read data value from page 800\n"); 2496 goto out; 2497 } 2498 2499 /* 2500 * Restore 769_17.2 to its original value 2501 * Set page 769 2502 */ 2503 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 2504 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); 2505 2506 /* Clear 769_17.2 */ 2507 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 2508 if (ret_val) { 2509 DEBUGOUT("Could not clear PHY page 769 bit 2\n"); 2510 goto out; 2511 } 2512 2513out: 2514 if (phy_acquired == 1) 2515 hw->phy.ops.release(hw); 2516 return ret_val; 2517} 2518 2519/** 2520 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 2521 * @hw: pointer to the HW structure 2522 * 2523 * In the case of a PHY power down to save power, or to turn off link during a 2524 * driver unload, or wake on lan is not enabled, restore the link to previous 2525 * settings. 2526 **/ 2527void e1000_power_up_phy_copper(struct e1000_hw *hw) 2528{ 2529 u16 mii_reg = 0; 2530 2531 /* The PHY will retain its settings across a power down/up cycle */ 2532 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2533 mii_reg &= ~MII_CR_POWER_DOWN; 2534 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2535} 2536 2537/** 2538 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 2539 * @hw: pointer to the HW structure 2540 * 2541 * In the case of a PHY power down to save power, or to turn off link during a 2542 * driver unload, or wake on lan is not enabled, restore the link to previous 2543 * settings. 2544 **/ 2545void e1000_power_down_phy_copper(struct e1000_hw *hw) 2546{ 2547 u16 mii_reg = 0; 2548 2549 /* The PHY will retain its settings across a power down/up cycle */ 2550 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2551 mii_reg |= MII_CR_POWER_DOWN; 2552 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2553 msec_delay(1); 2554} 2555