1209616Sjfv/******************************************************************************
2209616Sjfv
3269196Sjfv  Copyright (c) 2001-2014, Intel Corporation
4209616Sjfv  All rights reserved.
5209616Sjfv
6209616Sjfv  Redistribution and use in source and binary forms, with or without
7209616Sjfv  modification, are permitted provided that the following conditions are met:
8209616Sjfv
9209616Sjfv   1. Redistributions of source code must retain the above copyright notice,
10209616Sjfv      this list of conditions and the following disclaimer.
11209616Sjfv
12209616Sjfv   2. Redistributions in binary form must reproduce the above copyright
13209616Sjfv      notice, this list of conditions and the following disclaimer in the
14209616Sjfv      documentation and/or other materials provided with the distribution.
15209616Sjfv
16209616Sjfv   3. Neither the name of the Intel Corporation nor the names of its
17209616Sjfv      contributors may be used to endorse or promote products derived from
18209616Sjfv      this software without specific prior written permission.
19209616Sjfv
20209616Sjfv  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31209616Sjfv
32209616Sjfv******************************************************************************/
33209616Sjfv/*$FreeBSD: releng/10.2/sys/dev/e1000/e1000_mbx.h 269196 2014-07-28 21:11:18Z jfv $*/
34209616Sjfv
35209616Sjfv#ifndef _E1000_MBX_H_
36209616Sjfv#define _E1000_MBX_H_
37209616Sjfv
38209616Sjfv#include "e1000_api.h"
39209616Sjfv
40209616Sjfv/* Define mailbox register bits */
41269196Sjfv#define E1000_V2PMAILBOX_REQ	0x00000001 /* Request for PF Ready bit */
42269196Sjfv#define E1000_V2PMAILBOX_ACK	0x00000002 /* Ack PF message received */
43269196Sjfv#define E1000_V2PMAILBOX_VFU	0x00000004 /* VF owns the mailbox buffer */
44269196Sjfv#define E1000_V2PMAILBOX_PFU	0x00000008 /* PF owns the mailbox buffer */
45269196Sjfv#define E1000_V2PMAILBOX_PFSTS	0x00000010 /* PF wrote a message in the MB */
46269196Sjfv#define E1000_V2PMAILBOX_PFACK	0x00000020 /* PF ack the previous VF msg */
47269196Sjfv#define E1000_V2PMAILBOX_RSTI	0x00000040 /* PF has reset indication */
48269196Sjfv#define E1000_V2PMAILBOX_RSTD	0x00000080 /* PF has indicated reset done */
49209616Sjfv#define E1000_V2PMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */
50209616Sjfv
51269196Sjfv#define E1000_P2VMAILBOX_STS	0x00000001 /* Initiate message send to VF */
52269196Sjfv#define E1000_P2VMAILBOX_ACK	0x00000002 /* Ack message recv'd from VF */
53269196Sjfv#define E1000_P2VMAILBOX_VFU	0x00000004 /* VF owns the mailbox buffer */
54269196Sjfv#define E1000_P2VMAILBOX_PFU	0x00000008 /* PF owns the mailbox buffer */
55269196Sjfv#define E1000_P2VMAILBOX_RVFU	0x00000010 /* Reset VFU - used when VF stuck */
56209616Sjfv
57209616Sjfv#define E1000_MBVFICR_VFREQ_MASK 0x000000FF /* bits for VF messages */
58269196Sjfv#define E1000_MBVFICR_VFREQ_VF1	0x00000001 /* bit for VF 1 message */
59209616Sjfv#define E1000_MBVFICR_VFACK_MASK 0x00FF0000 /* bits for VF acks */
60269196Sjfv#define E1000_MBVFICR_VFACK_VF1	0x00010000 /* bit for VF 1 ack */
61209616Sjfv
62269196Sjfv#define E1000_VFMAILBOX_SIZE	16 /* 16 32 bit words - 64 bytes */
63209616Sjfv
64209616Sjfv/* If it's a E1000_VF_* msg then it originates in the VF and is sent to the
65209616Sjfv * PF.  The reverse is TRUE if it is E1000_PF_*.
66209616Sjfv * Message ACK's are the value or'd with 0xF0000000
67209616Sjfv */
68269196Sjfv/* Msgs below or'd with this are the ACK */
69269196Sjfv#define E1000_VT_MSGTYPE_ACK	0x80000000
70269196Sjfv/* Msgs below or'd with this are the NACK */
71269196Sjfv#define E1000_VT_MSGTYPE_NACK	0x40000000
72269196Sjfv/* Indicates that VF is still clear to send requests */
73269196Sjfv#define E1000_VT_MSGTYPE_CTS	0x20000000
74269196Sjfv#define E1000_VT_MSGINFO_SHIFT	16
75269196Sjfv/* bits 23:16 are used for extra info for certain messages */
76269196Sjfv#define E1000_VT_MSGINFO_MASK	(0xFF << E1000_VT_MSGINFO_SHIFT)
77209616Sjfv
78269196Sjfv#define E1000_VF_RESET			0x01 /* VF requests reset */
79269196Sjfv#define E1000_VF_SET_MAC_ADDR		0x02 /* VF requests to set MAC addr */
80269196Sjfv#define E1000_VF_SET_MULTICAST		0x03 /* VF requests to set MC addr */
81209616Sjfv#define E1000_VF_SET_MULTICAST_COUNT_MASK (0x1F << E1000_VT_MSGINFO_SHIFT)
82269196Sjfv#define E1000_VF_SET_MULTICAST_OVERFLOW	(0x80 << E1000_VT_MSGINFO_SHIFT)
83269196Sjfv#define E1000_VF_SET_VLAN		0x04 /* VF requests to set VLAN */
84269196Sjfv#define E1000_VF_SET_VLAN_ADD		(0x01 << E1000_VT_MSGINFO_SHIFT)
85269196Sjfv#define E1000_VF_SET_LPE		0x05 /* reqs to set VMOLR.LPE */
86269196Sjfv#define E1000_VF_SET_PROMISC		0x06 /* reqs to clear VMOLR.ROPE/MPME*/
87269196Sjfv#define E1000_VF_SET_PROMISC_UNICAST	(0x01 << E1000_VT_MSGINFO_SHIFT)
88269196Sjfv#define E1000_VF_SET_PROMISC_MULTICAST	(0x02 << E1000_VT_MSGINFO_SHIFT)
89209616Sjfv
90269196Sjfv#define E1000_PF_CONTROL_MSG		0x0100 /* PF control message */
91209616Sjfv
92269196Sjfv#define E1000_VF_MBX_INIT_TIMEOUT	2000 /* number of retries on mailbox */
93269196Sjfv#define E1000_VF_MBX_INIT_DELAY		500  /* microseconds between retries */
94209616Sjfv
95209616Sjfvs32 e1000_read_mbx(struct e1000_hw *, u32 *, u16, u16);
96209616Sjfvs32 e1000_write_mbx(struct e1000_hw *, u32 *, u16, u16);
97209616Sjfvs32 e1000_read_posted_mbx(struct e1000_hw *, u32 *, u16, u16);
98209616Sjfvs32 e1000_write_posted_mbx(struct e1000_hw *, u32 *, u16, u16);
99209616Sjfvs32 e1000_check_for_msg(struct e1000_hw *, u16);
100209616Sjfvs32 e1000_check_for_ack(struct e1000_hw *, u16);
101209616Sjfvs32 e1000_check_for_rst(struct e1000_hw *, u16);
102209616Sjfvvoid e1000_init_mbx_ops_generic(struct e1000_hw *hw);
103209616Sjfvs32 e1000_init_mbx_params_vf(struct e1000_hw *);
104209616Sjfvs32 e1000_init_mbx_params_pf(struct e1000_hw *);
105209616Sjfv
106209616Sjfv#endif /* _E1000_MBX_H_ */
107