e1000_mac.c revision 169248
1217309Snwhitehorn/******************************************************************************* 2217309Snwhitehorn 3217309Snwhitehorn Copyright (c) 2001-2007, Intel Corporation 4217309Snwhitehorn All rights reserved. 5217309Snwhitehorn 6217309Snwhitehorn Redistribution and use in source and binary forms, with or without 7217309Snwhitehorn modification, are permitted provided that the following conditions are met: 8217309Snwhitehorn 9217309Snwhitehorn 1. Redistributions of source code must retain the above copyright notice, 10217309Snwhitehorn this list of conditions and the following disclaimer. 11217309Snwhitehorn 12217309Snwhitehorn 2. Redistributions in binary form must reproduce the above copyright 13217309Snwhitehorn notice, this list of conditions and the following disclaimer in the 14217309Snwhitehorn documentation and/or other materials provided with the distribution. 15217309Snwhitehorn 16217309Snwhitehorn 3. Neither the name of the Intel Corporation nor the names of its 17217309Snwhitehorn contributors may be used to endorse or promote products derived from 18217309Snwhitehorn this software without specific prior written permission. 19217309Snwhitehorn 20217309Snwhitehorn THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21217309Snwhitehorn AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22217309Snwhitehorn IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23217309Snwhitehorn ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32*******************************************************************************/ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/em/e1000_mac.c 169248 2007-05-04 13:30:44Z rwatson $"); 36 37 38#include "e1000_mac.h" 39 40/** 41 * e1000_remove_device_generic - Free device specific structure 42 * @hw - pointer to the HW structure 43 * 44 * If a device specific structure was allocated, this function will 45 * free it. 46 **/ 47void 48e1000_remove_device_generic(struct e1000_hw *hw) 49{ 50 DEBUGFUNC("e1000_remove_device_generic"); 51 52 /* Freeing the dev_spec member of e1000_hw structure */ 53 e1000_free_dev_spec_struct(hw); 54} 55 56/** 57 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information 58 * @hw - pointer to the HW structure 59 * 60 * Determines and stores the system bus information for a particular 61 * network interface. The following bus information is determined and stored: 62 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function. 63 **/ 64s32 65e1000_get_bus_info_pci_generic(struct e1000_hw *hw) 66{ 67 struct e1000_bus_info *bus = &hw->bus; 68 u32 status = E1000_READ_REG(hw, E1000_STATUS); 69 s32 ret_val = E1000_SUCCESS; 70 u16 pci_header_type; 71 72 DEBUGFUNC("e1000_get_bus_info_pci_generic"); 73 74 /* PCI or PCI-X? */ 75 bus->type = (status & E1000_STATUS_PCIX_MODE) 76 ? e1000_bus_type_pcix 77 : e1000_bus_type_pci; 78 79 /* Bus speed */ 80 if (bus->type == e1000_bus_type_pci) { 81 bus->speed = (status & E1000_STATUS_PCI66) 82 ? e1000_bus_speed_66 83 : e1000_bus_speed_33; 84 } else { 85 switch (status & E1000_STATUS_PCIX_SPEED) { 86 case E1000_STATUS_PCIX_SPEED_66: 87 bus->speed = e1000_bus_speed_66; 88 break; 89 case E1000_STATUS_PCIX_SPEED_100: 90 bus->speed = e1000_bus_speed_100; 91 break; 92 case E1000_STATUS_PCIX_SPEED_133: 93 bus->speed = e1000_bus_speed_133; 94 break; 95 default: 96 bus->speed = e1000_bus_speed_reserved; 97 break; 98 } 99 } 100 101 /* Bus width */ 102 bus->width = (status & E1000_STATUS_BUS64) 103 ? e1000_bus_width_64 104 : e1000_bus_width_32; 105 106 /* Which PCI(-X) function? */ 107 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 108 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) 109 bus->func = (status & E1000_STATUS_FUNC_MASK) 110 >> E1000_STATUS_FUNC_SHIFT; 111 else 112 bus->func = 0; 113 114 return ret_val; 115} 116 117/** 118 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 119 * @hw - pointer to the HW structure 120 * 121 * Determines and stores the system bus information for a particular 122 * network interface. The following bus information is determined and stored: 123 * bus speed, bus width, type (PCIe), and PCIe function. 124 **/ 125s32 126e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 127{ 128 struct e1000_bus_info *bus = &hw->bus; 129 s32 ret_val; 130 u32 status; 131 u16 pcie_link_status, pci_header_type; 132 133 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 134 135 bus->type = e1000_bus_type_pci_express; 136 bus->speed = e1000_bus_speed_2500; 137 138 ret_val = e1000_read_pcie_cap_reg(hw, 139 PCIE_LINK_STATUS, 140 &pcie_link_status); 141 if (ret_val) 142 bus->width = e1000_bus_width_unknown; 143 else 144 bus->width = (e1000_bus_width)((pcie_link_status & 145 PCIE_LINK_WIDTH_MASK) >> 146 PCIE_LINK_WIDTH_SHIFT); 147 148 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 149 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 150 status = E1000_READ_REG(hw, E1000_STATUS); 151 bus->func = (status & E1000_STATUS_FUNC_MASK) 152 >> E1000_STATUS_FUNC_SHIFT; 153 } else 154 bus->func = 0; 155 156 return E1000_SUCCESS; 157} 158 159/** 160 * e1000_clear_vfta_generic - Clear VLAN filter table 161 * @hw - pointer to the HW structure 162 * 163 * Clears the register array which contains the VLAN filter table by 164 * setting all the values to 0. 165 **/ 166void 167e1000_clear_vfta_generic(struct e1000_hw *hw) 168{ 169 u32 offset; 170 171 DEBUGFUNC("e1000_clear_vfta_generic"); 172 173 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 174 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 175 E1000_WRITE_FLUSH(hw); 176 } 177} 178 179/** 180 * e1000_write_vfta_generic - Write value to VLAN filter table 181 * @hw - pointer to the HW structure 182 * @offset - register offset in VLAN filter table 183 * @value - register value written to VLAN filter table 184 * 185 * Writes value at the given offset in the register array which stores 186 * the VLAN filter table. 187 **/ 188void 189e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 190{ 191 DEBUGFUNC("e1000_write_vfta_generic"); 192 193 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 194 E1000_WRITE_FLUSH(hw); 195} 196 197/** 198 * e1000_init_rx_addrs_generic - Initialize receive address's 199 * @hw - pointer to the HW structure 200 * @rar_count - receive address registers 201 * 202 * Setups the receive address registers by setting the base receive address 203 * register to the devices MAC address and clearing all the other receive 204 * address registers to 0. 205 **/ 206void 207e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 208{ 209 u32 i; 210 211 DEBUGFUNC("e1000_init_rx_addrs_generic"); 212 213 /* Setup the receive address */ 214 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 215 216 e1000_rar_set_generic(hw, hw->mac.addr, 0); 217 218 /* Zero out the other (rar_entry_count - 1) receive addresses */ 219 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 220 for (i = 1; i < rar_count; i++) { 221 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0); 222 E1000_WRITE_FLUSH(hw); 223 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0); 224 E1000_WRITE_FLUSH(hw); 225 } 226} 227 228/** 229 * e1000_rar_set_generic - Set receive address register 230 * @hw - pointer to the HW structure 231 * @addr - pointer to the receive address 232 * @index - receive address array register 233 * 234 * Sets the receive address array register at index to the address passed 235 * in by addr. 236 **/ 237void 238e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 239{ 240 u32 rar_low, rar_high; 241 242 DEBUGFUNC("e1000_rar_set_generic"); 243 244 /* HW expects these in little endian so we reverse the byte order 245 * from network order (big endian) to little endian 246 */ 247 rar_low = ((u32) addr[0] | 248 ((u32) addr[1] << 8) | 249 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 250 251 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 252 253 if (!hw->mac.disable_av) 254 rar_high |= E1000_RAH_AV; 255 256 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 257 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 258} 259 260/** 261 * e1000_mta_set_generic - Set multicast filter table address 262 * @hw - pointer to the HW structure 263 * @hash_value - determines the MTA register and bit to set 264 * 265 * The multicast table address is a register array of 32-bit registers. 266 * The hash_value is used to determine what register the bit is in, the 267 * current value is read, the new bit is OR'd in and the new value is 268 * written back into the register. 269 **/ 270void 271e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 272{ 273 u32 hash_bit, hash_reg, mta; 274 275 DEBUGFUNC("e1000_mta_set_generic"); 276 /* The MTA is a register array of 32-bit registers. It is 277 * treated like an array of (32*mta_reg_count) bits. We want to 278 * set bit BitArray[hash_value]. So we figure out what register 279 * the bit is in, read it, OR in the new bit, then write 280 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 281 * mask to bits 31:5 of the hash value which gives us the 282 * register we're modifying. The hash bit within that register 283 * is determined by the lower 5 bits of the hash value. 284 */ 285 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 286 hash_bit = hash_value & 0x1F; 287 288 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 289 290 mta |= (1 << hash_bit); 291 292 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 293 E1000_WRITE_FLUSH(hw); 294} 295 296/** 297 * e1000_mc_addr_list_update_generic - Update Multicast addresses 298 * @hw - pointer to the HW structure 299 * @mc_addr_list - array of multicast addresses to program 300 * @mc_addr_count - number of multicast addresses to program 301 * @rar_used_count - the first RAR register free to program 302 * @rar_count - total number of supported Receive Address Registers 303 * 304 * Updates the Receive Address Registers and Multicast Table Array. 305 * The caller must have a packed mc_addr_list of multicast addresses. 306 * The parameter rar_count will usually be hw->mac.rar_entry_count 307 * unless there are workarounds that change this. 308 **/ 309void 310e1000_mc_addr_list_update_generic(struct e1000_hw *hw, 311 u8 *mc_addr_list, u32 mc_addr_count, 312 u32 rar_used_count, u32 rar_count) 313{ 314 u32 hash_value; 315 u32 i; 316 317 DEBUGFUNC("e1000_mc_addr_list_update_generic"); 318 319 /* Load the first set of multicast addresses into the exact 320 * filters (RAR). If there are not enough to fill the RAR 321 * array, clear the filters. 322 */ 323 for (i = rar_used_count; i < rar_count; i++) { 324 if (mc_addr_count) { 325 e1000_rar_set(hw, mc_addr_list, i); 326 mc_addr_count--; 327 mc_addr_list += ETH_ADDR_LEN; 328 } else { 329 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0); 330 E1000_WRITE_FLUSH(hw); 331 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0); 332 E1000_WRITE_FLUSH(hw); 333 } 334 } 335 336 /* Clear the old settings from the MTA */ 337 DEBUGOUT("Clearing MTA\n"); 338 for (i = 0; i < hw->mac.mta_reg_count; i++) { 339 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 340 E1000_WRITE_FLUSH(hw); 341 } 342 343 /* Load any remaining multicast addresses into the hash table. */ 344 for (; mc_addr_count > 0; mc_addr_count--) { 345 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 346 DEBUGOUT1("Hash value = 0x%03X\n", hash_value); 347 e1000_mta_set(hw, hash_value); 348 mc_addr_list += ETH_ADDR_LEN; 349 } 350} 351 352/** 353 * e1000_hash_mc_addr_generic - Generate a multicast hash value 354 * @hw - pointer to the HW structure 355 * @mc_addr - pointer to a multicast address 356 * 357 * Generates a multicast address hash value which is used to determine 358 * the multicast filter table array address and new table value. See 359 * e1000_mta_set_generic() 360 **/ 361u32 362e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 363{ 364 u32 hash_value, hash_mask; 365 u8 bit_shift = 0; 366 367 DEBUGFUNC("e1000_hash_mc_addr_generic"); 368 369 /* Register count multiplied by bits per register */ 370 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 371 372 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts 373 * where 0xFF would still fall within the hash mask. */ 374 while (hash_mask >> bit_shift != 0xFF) 375 bit_shift++; 376 377 /* The portion of the address that is used for the hash table 378 * is determined by the mc_filter_type setting. 379 * The algorithm is such that there is a total of 8 bits of shifting. 380 * The bit_shift for a mc_filter_type of 0 represents the number of 381 * left-shifts where the MSB of mc_addr[5] would still fall within 382 * the hash_mask. Case 0 does this exactly. Since there are a total 383 * of 8 bits of shifting, then mc_addr[4] will shift right the 384 * remaining number of bits. Thus 8 - bit_shift. The rest of the 385 * cases are a variation of this algorithm...essentially raising the 386 * number of bits to shift mc_addr[5] left, while still keeping the 387 * 8-bit shifting total. 388 */ 389 /* For example, given the following Destination MAC Address and an 390 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 391 * we can see that the bit_shift for case 0 is 4. These are the hash 392 * values resulting from each mc_filter_type... 393 * [0] [1] [2] [3] [4] [5] 394 * 01 AA 00 12 34 56 395 * LSB MSB 396 * 397 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 398 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 399 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 400 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 401 */ 402 switch (hw->mac.mc_filter_type) { 403 default: 404 case 0: 405 break; 406 case 1: 407 bit_shift += 1; 408 break; 409 case 2: 410 bit_shift += 2; 411 break; 412 case 3: 413 bit_shift += 4; 414 break; 415 } 416 417 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 418 (((u16) mc_addr[5]) << bit_shift))); 419 420 return hash_value; 421} 422 423/** 424 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value 425 * @hw - pointer to the HW structure 426 * 427 * In certain situations, a system BIOS may report that the PCIx maximum 428 * memory read byte count (MMRBC) value is higher than than the actual 429 * value. We check the PCIx command regsiter with the current PCIx status 430 * regsiter. 431 **/ 432void 433e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw) 434{ 435 u16 cmd_mmrbc; 436 u16 pcix_cmd; 437 u16 pcix_stat_hi_word; 438 u16 stat_mmrbc; 439 440 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 441 442 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 443 if (hw->bus.type != e1000_bus_type_pcix) 444 return; 445 446 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 447 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 448 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 449 PCIX_COMMAND_MMRBC_SHIFT; 450 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 451 PCIX_STATUS_HI_MMRBC_SHIFT; 452 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 453 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 454 if (cmd_mmrbc > stat_mmrbc) { 455 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 456 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 457 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 458 } 459} 460 461/** 462 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 463 * @hw - pointer to the HW structure 464 * 465 * Clears the base hardware counters by reading the counter registers. 466 **/ 467void 468e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 469{ 470 volatile u32 temp; 471 472 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 473 474 temp = E1000_READ_REG(hw, E1000_CRCERRS); 475 temp = E1000_READ_REG(hw, E1000_SYMERRS); 476 temp = E1000_READ_REG(hw, E1000_MPC); 477 temp = E1000_READ_REG(hw, E1000_SCC); 478 temp = E1000_READ_REG(hw, E1000_ECOL); 479 temp = E1000_READ_REG(hw, E1000_MCC); 480 temp = E1000_READ_REG(hw, E1000_LATECOL); 481 temp = E1000_READ_REG(hw, E1000_COLC); 482 temp = E1000_READ_REG(hw, E1000_DC); 483 temp = E1000_READ_REG(hw, E1000_SEC); 484 temp = E1000_READ_REG(hw, E1000_RLEC); 485 temp = E1000_READ_REG(hw, E1000_XONRXC); 486 temp = E1000_READ_REG(hw, E1000_XONTXC); 487 temp = E1000_READ_REG(hw, E1000_XOFFRXC); 488 temp = E1000_READ_REG(hw, E1000_XOFFTXC); 489 temp = E1000_READ_REG(hw, E1000_FCRUC); 490 temp = E1000_READ_REG(hw, E1000_GPRC); 491 temp = E1000_READ_REG(hw, E1000_BPRC); 492 temp = E1000_READ_REG(hw, E1000_MPRC); 493 temp = E1000_READ_REG(hw, E1000_GPTC); 494 temp = E1000_READ_REG(hw, E1000_GORCL); 495 temp = E1000_READ_REG(hw, E1000_GORCH); 496 temp = E1000_READ_REG(hw, E1000_GOTCL); 497 temp = E1000_READ_REG(hw, E1000_GOTCH); 498 temp = E1000_READ_REG(hw, E1000_RNBC); 499 temp = E1000_READ_REG(hw, E1000_RUC); 500 temp = E1000_READ_REG(hw, E1000_RFC); 501 temp = E1000_READ_REG(hw, E1000_ROC); 502 temp = E1000_READ_REG(hw, E1000_RJC); 503 temp = E1000_READ_REG(hw, E1000_TORL); 504 temp = E1000_READ_REG(hw, E1000_TORH); 505 temp = E1000_READ_REG(hw, E1000_TOTL); 506 temp = E1000_READ_REG(hw, E1000_TOTH); 507 temp = E1000_READ_REG(hw, E1000_TPR); 508 temp = E1000_READ_REG(hw, E1000_TPT); 509 temp = E1000_READ_REG(hw, E1000_MPTC); 510 temp = E1000_READ_REG(hw, E1000_BPTC); 511} 512 513/** 514 * e1000_check_for_copper_link_generic - Check for link (Copper) 515 * @hw - pointer to the HW structure 516 * 517 * Checks to see of the link status of the hardware has changed. If a 518 * change in link status has been detected, then we read the PHY registers 519 * to get the current speed/duplex if link exists. 520 **/ 521s32 522e1000_check_for_copper_link_generic(struct e1000_hw *hw) 523{ 524 struct e1000_mac_info *mac = &hw->mac; 525 s32 ret_val; 526 boolean_t link; 527 528 DEBUGFUNC("e1000_check_for_copper_link"); 529 530 /* We only want to go out to the PHY registers to see if Auto-Neg 531 * has completed and/or if our link status has changed. The 532 * get_link_status flag is set upon receiving a Link Status 533 * Change or Rx Sequence Error interrupt. 534 */ 535 if (!mac->get_link_status) { 536 ret_val = E1000_SUCCESS; 537 goto out; 538 } 539 540 /* First we want to see if the MII Status Register reports 541 * link. If so, then we want to get the current speed/duplex 542 * of the PHY. 543 */ 544 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 545 if (ret_val) 546 goto out; 547 548 if (!link) 549 goto out; /* No link detected */ 550 551 mac->get_link_status = FALSE; 552 553 /* Check if there was DownShift, must be checked 554 * immediately after link-up */ 555 e1000_check_downshift_generic(hw); 556 557 /* If we are forcing speed/duplex, then we simply return since 558 * we have already determined whether we have link or not. 559 */ 560 if (!mac->autoneg) { 561 ret_val = -E1000_ERR_CONFIG; 562 goto out; 563 } 564 565 /* Auto-Neg is enabled. Auto Speed Detection takes care 566 * of MAC speed/duplex configuration. So we only need to 567 * configure Collision Distance in the MAC. 568 */ 569 e1000_config_collision_dist_generic(hw); 570 571 /* Configure Flow Control now that Auto-Neg has completed. 572 * First, we need to restore the desired flow control 573 * settings because we may have had to re-autoneg with a 574 * different link partner. 575 */ 576 ret_val = e1000_config_fc_after_link_up_generic(hw); 577 if (ret_val) { 578 DEBUGOUT("Error configuring flow control\n"); 579 } 580 581out: 582 return ret_val; 583} 584 585/** 586 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 587 * @hw - pointer to the HW structure 588 * 589 * Checks for link up on the hardware. If link is not up and we have 590 * a signal, then we need to force link up. 591 **/ 592s32 593e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 594{ 595 struct e1000_mac_info *mac = &hw->mac; 596 u32 rxcw; 597 u32 ctrl; 598 u32 status; 599 s32 ret_val = E1000_SUCCESS; 600 601 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 602 603 ctrl = E1000_READ_REG(hw, E1000_CTRL); 604 status = E1000_READ_REG(hw, E1000_STATUS); 605 rxcw = E1000_READ_REG(hw, E1000_RXCW); 606 607 /* If we don't have link (auto-negotiation failed or link partner 608 * cannot auto-negotiate), the cable is plugged in (we have signal), 609 * and our link partner is not trying to auto-negotiate with us (we 610 * are receiving idles or data), we need to force link up. We also 611 * need to give auto-negotiation time to complete, in case the cable 612 * was just plugged in. The autoneg_failed flag does this. 613 */ 614 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 615 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 616 (!(rxcw & E1000_RXCW_C))) { 617 if (mac->autoneg_failed == 0) { 618 mac->autoneg_failed = 1; 619 goto out; 620 } 621 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 622 623 /* Disable auto-negotiation in the TXCW register */ 624 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 625 626 /* Force link-up and also force full-duplex. */ 627 ctrl = E1000_READ_REG(hw, E1000_CTRL); 628 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 629 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 630 631 /* Configure Flow Control after forcing link up. */ 632 ret_val = e1000_config_fc_after_link_up_generic(hw); 633 if (ret_val) { 634 DEBUGOUT("Error configuring flow control\n"); 635 goto out; 636 } 637 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 638 /* If we are forcing link and we are receiving /C/ ordered 639 * sets, re-enable auto-negotiation in the TXCW register 640 * and disable forced link in the Device Control register 641 * in an attempt to auto-negotiate with our link partner. 642 */ 643 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 644 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 645 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 646 647 mac->serdes_has_link = TRUE; 648 } 649 650out: 651 return ret_val; 652} 653 654/** 655 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 656 * @hw - pointer to the HW structure 657 * 658 * Checks for link up on the hardware. If link is not up and we have 659 * a signal, then we need to force link up. 660 **/ 661s32 662e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 663{ 664 struct e1000_mac_info *mac = &hw->mac; 665 u32 rxcw; 666 u32 ctrl; 667 u32 status; 668 s32 ret_val = E1000_SUCCESS; 669 670 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 671 672 ctrl = E1000_READ_REG(hw, E1000_CTRL); 673 status = E1000_READ_REG(hw, E1000_STATUS); 674 rxcw = E1000_READ_REG(hw, E1000_RXCW); 675 676 /* If we don't have link (auto-negotiation failed or link partner 677 * cannot auto-negotiate), and our link partner is not trying to 678 * auto-negotiate with us (we are receiving idles or data), 679 * we need to force link up. We also need to give auto-negotiation 680 * time to complete. 681 */ 682 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 683 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 684 if (mac->autoneg_failed == 0) { 685 mac->autoneg_failed = 1; 686 goto out; 687 } 688 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 689 690 /* Disable auto-negotiation in the TXCW register */ 691 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 692 693 /* Force link-up and also force full-duplex. */ 694 ctrl = E1000_READ_REG(hw, E1000_CTRL); 695 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 696 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 697 698 /* Configure Flow Control after forcing link up. */ 699 ret_val = e1000_config_fc_after_link_up_generic(hw); 700 if (ret_val) { 701 DEBUGOUT("Error configuring flow control\n"); 702 goto out; 703 } 704 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 705 /* If we are forcing link and we are receiving /C/ ordered 706 * sets, re-enable auto-negotiation in the TXCW register 707 * and disable forced link in the Device Control register 708 * in an attempt to auto-negotiate with our link partner. 709 */ 710 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 711 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 712 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 713 714 mac->serdes_has_link = TRUE; 715 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 716 /* If we force link for non-auto-negotiation switch, check 717 * link status based on MAC synchronization for internal 718 * serdes media type. 719 */ 720 /* SYNCH bit and IV bit are sticky. */ 721 usec_delay(10); 722 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) { 723 if (!(rxcw & E1000_RXCW_IV)) { 724 mac->serdes_has_link = TRUE; 725 DEBUGOUT("SERDES: Link is up.\n"); 726 } 727 } else { 728 mac->serdes_has_link = FALSE; 729 DEBUGOUT("SERDES: Link is down.\n"); 730 } 731 } 732 733 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 734 status = E1000_READ_REG(hw, E1000_STATUS); 735 mac->serdes_has_link = (status & E1000_STATUS_LU) 736 ? TRUE 737 : FALSE; 738 } 739 740out: 741 return ret_val; 742} 743 744/** 745 * e1000_setup_link_generic - Setup flow control and link settings 746 * @hw - pointer to the HW structure 747 * 748 * Determines which flow control settings to use, then configures flow 749 * control. Calls the appropriate media-specific link configuration 750 * function. Assuming the adapter has a valid link partner, a valid link 751 * should be established. Assumes the hardware has previously been reset 752 * and the transmitter and receiver are not enabled. 753 **/ 754s32 755e1000_setup_link_generic(struct e1000_hw *hw) 756{ 757 struct e1000_mac_info *mac = &hw->mac; 758 struct e1000_functions *func = &hw->func; 759 s32 ret_val = E1000_SUCCESS; 760 761 DEBUGFUNC("e1000_setup_link_generic"); 762 763 /* In the case of the phy reset being blocked, we already have a link. 764 * We do not need to set it up again. 765 */ 766 if (e1000_check_reset_block(hw)) 767 goto out; 768 769 ret_val = e1000_set_default_fc_generic(hw); 770 if (ret_val) 771 goto out; 772 773 /* We want to save off the original Flow Control configuration just 774 * in case we get disconnected and then reconnected into a different 775 * hub or switch with different Flow Control capabilities. 776 */ 777 mac->original_fc = mac->fc; 778 779 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", mac->fc); 780 781 /* Call the necessary media_type subroutine to configure the link. */ 782 ret_val = func->setup_physical_interface(hw); 783 if (ret_val) 784 goto out; 785 786 /* Initialize the flow control address, type, and PAUSE timer 787 * registers to their default values. This is done even if flow 788 * control is disabled, because it does not hurt anything to 789 * initialize these registers. 790 */ 791 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 792 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 793 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 794 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 795 796 E1000_WRITE_REG(hw, E1000_FCTTV, mac->fc_pause_time); 797 798 ret_val = e1000_set_fc_watermarks_generic(hw); 799 800out: 801 return ret_val; 802} 803 804/** 805 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 806 * @hw - pointer to the HW structure 807 * 808 * Configures collision distance and flow control for fiber and serdes 809 * links. Upon successful setup, poll for link. 810 **/ 811s32 812e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 813{ 814 u32 ctrl; 815 s32 ret_val = E1000_SUCCESS; 816 817 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 818 819 ctrl = E1000_READ_REG(hw, E1000_CTRL); 820 821 /* Take the link out of reset */ 822 ctrl &= ~E1000_CTRL_LRST; 823 824 e1000_config_collision_dist_generic(hw); 825 826 ret_val = e1000_commit_fc_settings_generic(hw); 827 if (ret_val) 828 goto out; 829 830 /* Since auto-negotiation is enabled, take the link out of reset (the 831 * link will be in reset, because we previously reset the chip). This 832 * will restart auto-negotiation. If auto-negotiation is successful 833 * then the link-up status bit will be set and the flow control enable 834 * bits (RFCE and TFCE) will be set according to their negotiated value. 835 */ 836 DEBUGOUT("Auto-negotiation enabled\n"); 837 838 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 839 E1000_WRITE_FLUSH(hw); 840 msec_delay(1); 841 842 /* For these adapters, the SW defineable pin 1 is set when the optics 843 * detect a signal. If we have a signal, then poll for a "Link-Up" 844 * indication. 845 */ 846 if (hw->media_type == e1000_media_type_internal_serdes || 847 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 848 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 849 } else { 850 DEBUGOUT("No signal detected\n"); 851 } 852 853out: 854 return ret_val; 855} 856 857/** 858 * e1000_config_collision_dist_generic - Configure collision distance 859 * @hw - pointer to the HW structure 860 * 861 * Configures the collision distance to the default value and is used 862 * during link setup. Currently no func pointer exists and all 863 * implementations are handled in the generic version of this function. 864 **/ 865void 866e1000_config_collision_dist_generic(struct e1000_hw *hw) 867{ 868 u32 tctl; 869 870 DEBUGFUNC("e1000_config_collision_dist_generic"); 871 872 tctl = E1000_READ_REG(hw, E1000_TCTL); 873 874 tctl &= ~E1000_TCTL_COLD; 875 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 876 877 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 878 E1000_WRITE_FLUSH(hw); 879} 880 881/** 882 * e1000_poll_fiber_serdes_link_generic - Poll for link up 883 * @hw - pointer to the HW structure 884 * 885 * Polls for link up by reading the status register, if link fails to come 886 * up with auto-negotiation, then the link is forced if a signal is detected. 887 **/ 888s32 889e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 890{ 891 struct e1000_mac_info *mac = &hw->mac; 892 u32 i, status; 893 s32 ret_val = E1000_SUCCESS; 894 895 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 896 897 /* If we have a signal (the cable is plugged in, or assumed true for 898 * serdes media) then poll for a "Link-Up" indication in the Device 899 * Status Register. Time-out if a link isn't seen in 500 milliseconds 900 * seconds (Auto-negotiation should complete in less than 500 901 * milliseconds even if the other end is doing it in SW). 902 */ 903 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 904 msec_delay(10); 905 status = E1000_READ_REG(hw, E1000_STATUS); 906 if (status & E1000_STATUS_LU) 907 break; 908 } 909 if (i == FIBER_LINK_UP_LIMIT) { 910 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 911 mac->autoneg_failed = 1; 912 /* AutoNeg failed to achieve a link, so we'll call 913 * mac->check_for_link. This routine will force the 914 * link up if we detect a signal. This will allow us to 915 * communicate with non-autonegotiating link partners. 916 */ 917 ret_val = e1000_check_for_link(hw); 918 if (ret_val) { 919 DEBUGOUT("Error while checking for link\n"); 920 goto out; 921 } 922 mac->autoneg_failed = 0; 923 } else { 924 mac->autoneg_failed = 0; 925 DEBUGOUT("Valid Link Found\n"); 926 } 927 928out: 929 return ret_val; 930} 931 932/** 933 * e1000_commit_fc_settings_generic - Configure flow control 934 * @hw - pointer to the HW structure 935 * 936 * Write the flow control settings to the Transmit Config Word Register (TXCW) 937 * base on the flow control settings in e1000_mac_info. 938 **/ 939s32 940e1000_commit_fc_settings_generic(struct e1000_hw *hw) 941{ 942 struct e1000_mac_info *mac = &hw->mac; 943 u32 txcw; 944 s32 ret_val = E1000_SUCCESS; 945 946 DEBUGFUNC("e1000_commit_fc_settings_generic"); 947 948 /* Check for a software override of the flow control settings, and 949 * setup the device accordingly. If auto-negotiation is enabled, then 950 * software will have to set the "PAUSE" bits to the correct value in 951 * the Transmit Config Word Register (TXCW) and re-start auto- 952 * negotiation. However, if auto-negotiation is disabled, then 953 * software will have to manually configure the two flow control enable 954 * bits in the CTRL register. 955 * 956 * The possible values of the "fc" parameter are: 957 * 0: Flow control is completely disabled 958 * 1: Rx flow control is enabled (we can receive pause frames, 959 * but not send pause frames). 960 * 2: Tx flow control is enabled (we can send pause frames but we 961 * do not support receiving pause frames). 962 * 3: Both Rx and TX flow control (symmetric) are enabled. 963 */ 964 switch (mac->fc) { 965 case e1000_fc_none: 966 /* Flow control completely disabled by a software over-ride. */ 967 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 968 break; 969 case e1000_fc_rx_pause: 970 /* RX Flow control is enabled and TX Flow control is disabled 971 * by a software over-ride. Since there really isn't a way to 972 * advertise that we are capable of RX Pause ONLY, we will 973 * advertise that we support both symmetric and asymmetric RX 974 * PAUSE. Later, we will disable the adapter's ability to send 975 * PAUSE frames. 976 */ 977 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 978 break; 979 case e1000_fc_tx_pause: 980 /* TX Flow control is enabled, and RX Flow control is disabled, 981 * by a software over-ride. 982 */ 983 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 984 break; 985 case e1000_fc_full: 986 /* Flow control (both RX and TX) is enabled by a software 987 * over-ride. 988 */ 989 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 990 break; 991 default: 992 DEBUGOUT("Flow control param set incorrectly\n"); 993 ret_val = -E1000_ERR_CONFIG; 994 goto out; 995 break; 996 } 997 998 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 999 mac->txcw = txcw; 1000 1001out: 1002 return ret_val; 1003} 1004 1005/** 1006 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1007 * @hw - pointer to the HW structure 1008 * 1009 * Sets the flow control high/low threshold (watermark) registers. If 1010 * flow control XON frame transmission is enabled, then set XON frame 1011 * tansmission as well. 1012 **/ 1013s32 1014e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1015{ 1016 struct e1000_mac_info *mac = &hw->mac; 1017 s32 ret_val = E1000_SUCCESS; 1018 u32 fcrtl = 0, fcrth = 0; 1019 1020 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1021 1022 /* Set the flow control receive threshold registers. Normally, 1023 * these registers will be set to a default threshold that may be 1024 * adjusted later by the driver's runtime code. However, if the 1025 * ability to transmit pause frames is not enabled, then these 1026 * registers will be set to 0. 1027 */ 1028 if (mac->fc & e1000_fc_tx_pause) { 1029 /* We need to set up the Receive Threshold high and low water 1030 * marks as well as (optionally) enabling the transmission of 1031 * XON frames. 1032 */ 1033 fcrtl = mac->fc_low_water; 1034 if (mac->fc_send_xon) 1035 fcrtl |= E1000_FCRTL_XONE; 1036 1037 fcrth = mac->fc_high_water; 1038 } 1039 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1040 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1041 1042 return ret_val; 1043} 1044 1045/** 1046 * e1000_set_default_fc_generic - Set flow control default values 1047 * @hw - pointer to the HW structure 1048 * 1049 * Read the EEPROM for the default values for flow control and store the 1050 * values. 1051 **/ 1052s32 1053e1000_set_default_fc_generic(struct e1000_hw *hw) 1054{ 1055 struct e1000_mac_info *mac = &hw->mac; 1056 s32 ret_val = E1000_SUCCESS; 1057 u16 nvm_data; 1058 1059 DEBUGFUNC("e1000_set_default_fc_generic"); 1060 1061 if (mac->fc != e1000_fc_default) 1062 goto out; 1063 1064 /* Read and store word 0x0F of the EEPROM. This word contains bits 1065 * that determine the hardware's default PAUSE (flow control) mode, 1066 * a bit that determines whether the HW defaults to enabling or 1067 * disabling auto-negotiation, and the direction of the 1068 * SW defined pins. If there is no SW over-ride of the flow 1069 * control setting, then the variable hw->fc will 1070 * be initialized based on a value in the EEPROM. 1071 */ 1072 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1073 1074 if (ret_val) { 1075 DEBUGOUT("NVM Read Error\n"); 1076 goto out; 1077 } 1078 1079 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1080 mac->fc = e1000_fc_none; 1081 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1082 NVM_WORD0F_ASM_DIR) 1083 mac->fc = e1000_fc_tx_pause; 1084 else 1085 mac->fc = e1000_fc_full; 1086 1087out: 1088 return ret_val; 1089} 1090 1091/** 1092 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1093 * @hw - pointer to the HW structure 1094 * 1095 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1096 * device control register to reflect the adapter settings. TFCE and RFCE 1097 * need to be explicitly set by software when a copper PHY is used because 1098 * autonegotiation is managed by the PHY rather than the MAC. Software must 1099 * also configure these bits when link is forced on a fiber connection. 1100 **/ 1101s32 1102e1000_force_mac_fc_generic(struct e1000_hw *hw) 1103{ 1104 struct e1000_mac_info *mac = &hw->mac; 1105 u32 ctrl; 1106 s32 ret_val = E1000_SUCCESS; 1107 1108 DEBUGFUNC("e1000_force_mac_fc_generic"); 1109 1110 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1111 1112 /* Because we didn't get link via the internal auto-negotiation 1113 * mechanism (we either forced link or we got link via PHY 1114 * auto-neg), we have to manually enable/disable transmit an 1115 * receive flow control. 1116 * 1117 * The "Case" statement below enables/disable flow control 1118 * according to the "mac->fc" parameter. 1119 * 1120 * The possible values of the "fc" parameter are: 1121 * 0: Flow control is completely disabled 1122 * 1: Rx flow control is enabled (we can receive pause 1123 * frames but not send pause frames). 1124 * 2: Tx flow control is enabled (we can send pause frames 1125 * frames but we do not receive pause frames). 1126 * 3: Both Rx and TX flow control (symmetric) is enabled. 1127 * other: No other values should be possible at this point. 1128 */ 1129 DEBUGOUT1("mac->fc = %u\n", mac->fc); 1130 1131 switch (mac->fc) { 1132 case e1000_fc_none: 1133 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1134 break; 1135 case e1000_fc_rx_pause: 1136 ctrl &= (~E1000_CTRL_TFCE); 1137 ctrl |= E1000_CTRL_RFCE; 1138 break; 1139 case e1000_fc_tx_pause: 1140 ctrl &= (~E1000_CTRL_RFCE); 1141 ctrl |= E1000_CTRL_TFCE; 1142 break; 1143 case e1000_fc_full: 1144 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1145 break; 1146 default: 1147 DEBUGOUT("Flow control param set incorrectly\n"); 1148 ret_val = -E1000_ERR_CONFIG; 1149 goto out; 1150 } 1151 1152 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1153 1154out: 1155 return ret_val; 1156} 1157 1158/** 1159 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1160 * @hw - pointer to the HW structure 1161 * 1162 * Checks the status of auto-negotiation after link up to ensure that the 1163 * speed and duplex were not forced. If the link needed to be forced, then 1164 * flow control needs to be forced also. If auto-negotiation is enabled 1165 * and did not fail, then we configure flow control based on our link 1166 * partner. 1167 **/ 1168s32 1169e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1170{ 1171 struct e1000_mac_info *mac = &hw->mac; 1172 s32 ret_val = E1000_SUCCESS; 1173 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1174 u16 speed, duplex; 1175 1176 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1177 1178 /* Check for the case where we have fiber media and auto-neg failed 1179 * so we had to force link. In this case, we need to force the 1180 * configuration of the MAC to match the "fc" parameter. 1181 */ 1182 if (mac->autoneg_failed) { 1183 if (hw->media_type == e1000_media_type_fiber || 1184 hw->media_type == e1000_media_type_internal_serdes) 1185 ret_val = e1000_force_mac_fc_generic(hw); 1186 } else { 1187 if (hw->media_type == e1000_media_type_copper) 1188 ret_val = e1000_force_mac_fc_generic(hw); 1189 } 1190 1191 if (ret_val) { 1192 DEBUGOUT("Error forcing flow control settings\n"); 1193 goto out; 1194 } 1195 1196 /* Check for the case where we have copper media and auto-neg is 1197 * enabled. In this case, we need to check and see if Auto-Neg 1198 * has completed, and if so, how the PHY and link partner has 1199 * flow control configured. 1200 */ 1201 if ((hw->media_type == e1000_media_type_copper) && mac->autoneg) { 1202 /* Read the MII Status Register and check to see if AutoNeg 1203 * has completed. We read this twice because this reg has 1204 * some "sticky" (latched) bits. 1205 */ 1206 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1207 if (ret_val) 1208 goto out; 1209 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); 1210 if (ret_val) 1211 goto out; 1212 1213 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1214 DEBUGOUT("Copper PHY and Auto Neg " 1215 "has not completed.\n"); 1216 goto out; 1217 } 1218 1219 /* The AutoNeg process has completed, so we now need to 1220 * read both the Auto Negotiation Advertisement 1221 * Register (Address 4) and the Auto_Negotiation Base 1222 * Page Ability Register (Address 5) to determine how 1223 * flow control was negotiated. 1224 */ 1225 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 1226 &mii_nway_adv_reg); 1227 if (ret_val) 1228 goto out; 1229 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, 1230 &mii_nway_lp_ability_reg); 1231 if (ret_val) 1232 goto out; 1233 1234 /* Two bits in the Auto Negotiation Advertisement Register 1235 * (Address 4) and two bits in the Auto Negotiation Base 1236 * Page Ability Register (Address 5) determine flow control 1237 * for both the PHY and the link partner. The following 1238 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1239 * 1999, describes these PAUSE resolution bits and how flow 1240 * control is determined based upon these settings. 1241 * NOTE: DC = Don't Care 1242 * 1243 * LOCAL DEVICE | LINK PARTNER 1244 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1245 *-------|---------|-------|---------|-------------------- 1246 * 0 | 0 | DC | DC | e1000_fc_none 1247 * 0 | 1 | 0 | DC | e1000_fc_none 1248 * 0 | 1 | 1 | 0 | e1000_fc_none 1249 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1250 * 1 | 0 | 0 | DC | e1000_fc_none 1251 * 1 | DC | 1 | DC | e1000_fc_full 1252 * 1 | 1 | 0 | 0 | e1000_fc_none 1253 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1254 * 1255 */ 1256 /* Are both PAUSE bits set to 1? If so, this implies 1257 * Symmetric Flow Control is enabled at both ends. The 1258 * ASM_DIR bits are irrelevant per the spec. 1259 * 1260 * For Symmetric Flow Control: 1261 * 1262 * LOCAL DEVICE | LINK PARTNER 1263 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1264 *-------|---------|-------|---------|-------------------- 1265 * 1 | DC | 1 | DC | E1000_fc_full 1266 * 1267 */ 1268 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1269 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1270 /* Now we need to check if the user selected RX ONLY 1271 * of pause frames. In this case, we had to advertise 1272 * FULL flow control because we could not advertise RX 1273 * ONLY. Hence, we must now check to see if we need to 1274 * turn OFF the TRANSMISSION of PAUSE frames. 1275 */ 1276 if (mac->original_fc == e1000_fc_full) { 1277 mac->fc = e1000_fc_full; 1278 DEBUGOUT("Flow Control = FULL.\r\n"); 1279 } else { 1280 mac->fc = e1000_fc_rx_pause; 1281 DEBUGOUT("Flow Control = " 1282 "RX PAUSE frames only.\r\n"); 1283 } 1284 } 1285 /* For receiving PAUSE frames ONLY. 1286 * 1287 * LOCAL DEVICE | LINK PARTNER 1288 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1289 *-------|---------|-------|---------|-------------------- 1290 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1291 * 1292 */ 1293 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1294 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1295 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1296 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1297 mac->fc = e1000_fc_tx_pause; 1298 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1299 } 1300 /* For transmitting PAUSE frames ONLY. 1301 * 1302 * LOCAL DEVICE | LINK PARTNER 1303 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1304 *-------|---------|-------|---------|-------------------- 1305 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1306 * 1307 */ 1308 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1309 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1310 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1311 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1312 mac->fc = e1000_fc_rx_pause; 1313 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1314 } 1315 /* Per the IEEE spec, at this point flow control should be 1316 * disabled. However, we want to consider that we could 1317 * be connected to a legacy switch that doesn't advertise 1318 * desired flow control, but can be forced on the link 1319 * partner. So if we advertised no flow control, that is 1320 * what we will resolve to. If we advertised some kind of 1321 * receive capability (Rx Pause Only or Full Flow Control) 1322 * and the link partner advertised none, we will configure 1323 * ourselves to enable Rx Flow Control only. We can do 1324 * this safely for two reasons: If the link partner really 1325 * didn't want flow control enabled, and we enable Rx, no 1326 * harm done since we won't be receiving any PAUSE frames 1327 * anyway. If the intent on the link partner was to have 1328 * flow control enabled, then by us enabling RX only, we 1329 * can at least receive pause frames and process them. 1330 * This is a good idea because in most cases, since we are 1331 * predominantly a server NIC, more times than not we will 1332 * be asked to delay transmission of packets than asking 1333 * our link partner to pause transmission of frames. 1334 */ 1335 else if ((mac->original_fc == e1000_fc_none || 1336 mac->original_fc == e1000_fc_tx_pause) || 1337 mac->fc_strict_ieee) { 1338 mac->fc = e1000_fc_none; 1339 DEBUGOUT("Flow Control = NONE.\r\n"); 1340 } else { 1341 mac->fc = e1000_fc_rx_pause; 1342 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1343 } 1344 1345 /* Now we need to do one last check... If we auto- 1346 * negotiated to HALF DUPLEX, flow control should not be 1347 * enabled per IEEE 802.3 spec. 1348 */ 1349 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); 1350 if (ret_val) { 1351 DEBUGOUT("Error getting link speed and duplex\n"); 1352 goto out; 1353 } 1354 1355 if (duplex == HALF_DUPLEX) 1356 mac->fc = e1000_fc_none; 1357 1358 /* Now we call a subroutine to actually force the MAC 1359 * controller to use the correct flow control settings. 1360 */ 1361 ret_val = e1000_force_mac_fc_generic(hw); 1362 if (ret_val) { 1363 DEBUGOUT("Error forcing flow control settings\n"); 1364 goto out; 1365 } 1366 } 1367 1368out: 1369 return ret_val; 1370} 1371 1372/** 1373 * e1000_get_speed_and_duplex_copper_generic - Retreive current speed/duplex 1374 * @hw - pointer to the HW structure 1375 * @speed - stores the current speed 1376 * @duplex - stores the current duplex 1377 * 1378 * Read the status register for the current speed/duplex and store the current 1379 * speed and duplex for copper connections. 1380 **/ 1381s32 1382e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1383 u16 *duplex) 1384{ 1385 u32 status; 1386 1387 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1388 1389 status = E1000_READ_REG(hw, E1000_STATUS); 1390 if (status & E1000_STATUS_SPEED_1000) { 1391 *speed = SPEED_1000; 1392 DEBUGOUT("1000 Mbs, "); 1393 } else if (status & E1000_STATUS_SPEED_100) { 1394 *speed = SPEED_100; 1395 DEBUGOUT("100 Mbs, "); 1396 } else { 1397 *speed = SPEED_10; 1398 DEBUGOUT("10 Mbs, "); 1399 } 1400 1401 if (status & E1000_STATUS_FD) { 1402 *duplex = FULL_DUPLEX; 1403 DEBUGOUT("Full Duplex\n"); 1404 } else { 1405 *duplex = HALF_DUPLEX; 1406 DEBUGOUT("Half Duplex\n"); 1407 } 1408 1409 return E1000_SUCCESS; 1410} 1411 1412/** 1413 * e1000_get_speed_and_duplex_fiber_generic - Retreive current speed/duplex 1414 * @hw - pointer to the HW structure 1415 * @speed - stores the current speed 1416 * @duplex - stores the current duplex 1417 * 1418 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1419 * for fiber/serdes links. 1420 **/ 1421s32 1422e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, u16 *speed, 1423 u16 *duplex) 1424{ 1425 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1426 1427 *speed = SPEED_1000; 1428 *duplex = FULL_DUPLEX; 1429 1430 return E1000_SUCCESS; 1431} 1432 1433/** 1434 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1435 * @hw - pointer to the HW structure 1436 * 1437 * Request a hardware semaphore by setting the firmware semaphore bit, once 1438 * bit has been set, semaphore has been acquired. 1439 **/ 1440s32 1441e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1442{ 1443 u32 swsm; 1444 s32 ret_val = E1000_SUCCESS; 1445 s32 timeout = hw->nvm.word_size + 1; 1446 s32 i = 0; 1447 1448 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1449 1450 /* Get the FW semaphore. */ 1451 for (i = 0; i < timeout; i++) { 1452 swsm = E1000_READ_REG(hw, E1000_SWSM); 1453 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1454 1455 /* Semaphore acquired if bit latched */ 1456 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1457 break; 1458 1459 usec_delay(50); 1460 } 1461 1462 if (i == timeout) { 1463 /* Release semaphores */ 1464 e1000_put_hw_semaphore_generic(hw); 1465 DEBUGOUT("Driver can't access the NVM\n"); 1466 ret_val = -E1000_ERR_NVM; 1467 goto out; 1468 } 1469 1470out: 1471 return ret_val; 1472} 1473 1474/** 1475 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1476 * @hw - pointer to the HW structure 1477 * 1478 * Release hardware semaphore by clearing in the firmware semaphore bit. 1479 **/ 1480void 1481e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1482{ 1483 u32 swsm; 1484 1485 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1486 1487 swsm = E1000_READ_REG(hw, E1000_SWSM); 1488 1489 swsm &= ~E1000_SWSM_SWESMBI; 1490 1491 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1492} 1493 1494/** 1495 * e1000_get_auto_rd_done_generic - Check for auto read completion 1496 * @hw - pointer to the HW structure 1497 * 1498 * Check EEPROM for Auto Read done bit. 1499 **/ 1500s32 1501e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1502{ 1503 s32 i = 0; 1504 s32 ret_val = E1000_SUCCESS; 1505 1506 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1507 1508 while (i < AUTO_READ_DONE_TIMEOUT) { 1509 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1510 break; 1511 msec_delay(1); 1512 i++; 1513 } 1514 1515 if (i == AUTO_READ_DONE_TIMEOUT) { 1516 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1517 ret_val = -E1000_ERR_RESET; 1518 goto out; 1519 } 1520 1521out: 1522 return ret_val; 1523} 1524 1525/** 1526 * e1000_valid_led_default_generic - Verify a valid default LED config 1527 * @hw - pointer to the HW structure 1528 * @data - pointer to the NVM (EEPROM) 1529 * 1530 * Read the EEPROM for the current default LED configuration. If the 1531 * LED configuration is not valid, set to a valid LED configuration. 1532 **/ 1533s32 1534e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1535{ 1536 s32 ret_val; 1537 1538 DEBUGFUNC("e1000_valid_led_default_generic"); 1539 1540 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1541 if (ret_val) { 1542 DEBUGOUT("NVM Read Error\n"); 1543 goto out; 1544 } 1545 1546 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1547 *data = ID_LED_DEFAULT; 1548 1549out: 1550 return ret_val; 1551} 1552 1553/** 1554 * e1000_id_led_init_generic - 1555 * @hw - pointer to the HW structure 1556 * 1557 **/ 1558s32 1559e1000_id_led_init_generic(struct e1000_hw * hw) 1560{ 1561 struct e1000_mac_info *mac = &hw->mac; 1562 s32 ret_val; 1563 const u32 ledctl_mask = 0x000000FF; 1564 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1565 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1566 u16 data, i, temp; 1567 const u16 led_mask = 0x0F; 1568 1569 DEBUGFUNC("e1000_id_led_init_generic"); 1570 1571 ret_val = hw->func.valid_led_default(hw, &data); 1572 if (ret_val) 1573 goto out; 1574 1575 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1576 mac->ledctl_mode1 = mac->ledctl_default; 1577 mac->ledctl_mode2 = mac->ledctl_default; 1578 1579 for (i = 0; i < 4; i++) { 1580 temp = (data >> (i << 2)) & led_mask; 1581 switch (temp) { 1582 case ID_LED_ON1_DEF2: 1583 case ID_LED_ON1_ON2: 1584 case ID_LED_ON1_OFF2: 1585 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1586 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1587 break; 1588 case ID_LED_OFF1_DEF2: 1589 case ID_LED_OFF1_ON2: 1590 case ID_LED_OFF1_OFF2: 1591 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1592 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1593 break; 1594 default: 1595 /* Do nothing */ 1596 break; 1597 } 1598 switch (temp) { 1599 case ID_LED_DEF1_ON2: 1600 case ID_LED_ON1_ON2: 1601 case ID_LED_OFF1_ON2: 1602 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1603 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1604 break; 1605 case ID_LED_DEF1_OFF2: 1606 case ID_LED_ON1_OFF2: 1607 case ID_LED_OFF1_OFF2: 1608 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1609 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1610 break; 1611 default: 1612 /* Do nothing */ 1613 break; 1614 } 1615 } 1616 1617out: 1618 return ret_val; 1619} 1620 1621/** 1622 * e1000_setup_led_generic - Configures SW controllable LED 1623 * @hw - pointer to the HW structure 1624 * 1625 * This prepares the SW controllable LED for use and saves the current state 1626 * of the LED so it can be later restored. 1627 **/ 1628s32 1629e1000_setup_led_generic(struct e1000_hw *hw) 1630{ 1631 u32 ledctl; 1632 s32 ret_val = E1000_SUCCESS; 1633 1634 DEBUGFUNC("e1000_setup_led_generic"); 1635 1636 if (hw->func.setup_led != e1000_setup_led_generic) { 1637 ret_val = -E1000_ERR_CONFIG; 1638 goto out; 1639 } 1640 1641 if (hw->media_type == e1000_media_type_fiber) { 1642 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1643 hw->mac.ledctl_default = ledctl; 1644 /* Turn off LED0 */ 1645 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1646 E1000_LEDCTL_LED0_BLINK | 1647 E1000_LEDCTL_LED0_MODE_MASK); 1648 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1649 E1000_LEDCTL_LED0_MODE_SHIFT); 1650 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1651 } else if (hw->media_type == e1000_media_type_copper) { 1652 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1653 } 1654 1655out: 1656 return ret_val; 1657} 1658 1659/** 1660 * e1000_cleanup_led_generic - Set LED config to default operation 1661 * @hw - pointer to the HW structure 1662 * 1663 * Remove the current LED configuration and set the LED configuration 1664 * to the default value, saved from the EEPROM. 1665 **/ 1666s32 1667e1000_cleanup_led_generic(struct e1000_hw *hw) 1668{ 1669 s32 ret_val = E1000_SUCCESS; 1670 1671 DEBUGFUNC("e1000_cleanup_led_generic"); 1672 1673 if (hw->func.cleanup_led != e1000_cleanup_led_generic) { 1674 ret_val = -E1000_ERR_CONFIG; 1675 goto out; 1676 } 1677 1678 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1679 1680out: 1681 return ret_val; 1682} 1683 1684/** 1685 * e1000_blink_led_generic - Blink LED 1686 * @hw - pointer to the HW structure 1687 * 1688 * Blink the led's which are set to be on. 1689 **/ 1690s32 1691e1000_blink_led_generic(struct e1000_hw *hw) 1692{ 1693 u32 ledctl_blink = 0; 1694 u32 i; 1695 1696 DEBUGFUNC("e1000_blink_led_generic"); 1697 1698 if (hw->media_type == e1000_media_type_fiber) { 1699 /* always blink LED0 for PCI-E fiber */ 1700 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1701 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1702 } else { 1703 /* set the blink bit for each LED that's "on" (0x0E) 1704 * in ledctl_mode2 */ 1705 ledctl_blink = hw->mac.ledctl_mode2; 1706 for (i = 0; i < 4; i++) 1707 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1708 E1000_LEDCTL_MODE_LED_ON) 1709 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1710 (i * 8)); 1711 } 1712 1713 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1714 1715 return E1000_SUCCESS; 1716} 1717 1718/** 1719 * e1000_led_on_generic - Turn LED on 1720 * @hw - pointer to the HW structure 1721 * 1722 * Turn LED on. 1723 **/ 1724s32 1725e1000_led_on_generic(struct e1000_hw *hw) 1726{ 1727 u32 ctrl; 1728 1729 DEBUGFUNC("e1000_led_on_generic"); 1730 1731 switch (hw->media_type) { 1732 case e1000_media_type_fiber: 1733 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1734 ctrl &= ~E1000_CTRL_SWDPIN0; 1735 ctrl |= E1000_CTRL_SWDPIO0; 1736 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1737 break; 1738 case e1000_media_type_copper: 1739 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1740 break; 1741 default: 1742 break; 1743 } 1744 1745 return E1000_SUCCESS; 1746} 1747 1748/** 1749 * e1000_led_off_generic - Turn LED off 1750 * @hw - pointer to the HW structure 1751 * 1752 * Turn LED off. 1753 **/ 1754s32 1755e1000_led_off_generic(struct e1000_hw *hw) 1756{ 1757 u32 ctrl; 1758 1759 DEBUGFUNC("e1000_led_off_generic"); 1760 1761 switch (hw->media_type) { 1762 case e1000_media_type_fiber: 1763 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1764 ctrl |= E1000_CTRL_SWDPIN0; 1765 ctrl |= E1000_CTRL_SWDPIO0; 1766 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1767 break; 1768 case e1000_media_type_copper: 1769 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1770 break; 1771 default: 1772 break; 1773 } 1774 1775 return E1000_SUCCESS; 1776} 1777 1778/** 1779 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1780 * @hw - pointer to the HW structure 1781 * @no_snoop - bitmap of snoop events 1782 * 1783 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1784 **/ 1785void 1786e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1787{ 1788 u32 gcr; 1789 1790 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1791 1792 if (hw->bus.type != e1000_bus_type_pci_express) 1793 goto out; 1794 1795 if (no_snoop) { 1796 gcr = E1000_READ_REG(hw, E1000_GCR); 1797 gcr &= ~(PCIE_NO_SNOOP_ALL); 1798 gcr |= no_snoop; 1799 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1800 } 1801out: 1802 return; 1803} 1804 1805/** 1806 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1807 * @hw - pointer to the HW structure 1808 * 1809 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1810 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued 1811 * the master requests to be disabled. 1812 * 1813 * Disables PCI-Express master access and verifies there are no pending 1814 * requests. 1815 **/ 1816s32 1817e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1818{ 1819 u32 ctrl; 1820 s32 timeout = MASTER_DISABLE_TIMEOUT; 1821 s32 ret_val = E1000_SUCCESS; 1822 1823 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1824 1825 if (hw->bus.type != e1000_bus_type_pci_express) 1826 goto out; 1827 1828 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1829 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1830 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1831 1832 while (timeout) { 1833 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1834 E1000_STATUS_GIO_MASTER_ENABLE)) 1835 break; 1836 usec_delay(100); 1837 timeout--; 1838 } 1839 1840 if (!timeout) { 1841 DEBUGOUT("Master requests are pending.\n"); 1842 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1843 goto out; 1844 } 1845 1846out: 1847 return ret_val; 1848} 1849 1850/** 1851 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 1852 * @hw - pointer to the HW structure 1853 * 1854 * Reset the Adaptive Interframe Spacing throttle to default values. 1855 **/ 1856void 1857e1000_reset_adaptive_generic(struct e1000_hw *hw) 1858{ 1859 struct e1000_mac_info *mac = &hw->mac; 1860 1861 DEBUGFUNC("e1000_reset_adaptive_generic"); 1862 1863 if (!mac->adaptive_ifs) { 1864 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1865 goto out; 1866 } 1867 1868 if (!mac->ifs_params_forced) { 1869 mac->current_ifs_val = 0; 1870 mac->ifs_min_val = IFS_MIN; 1871 mac->ifs_max_val = IFS_MAX; 1872 mac->ifs_step_size = IFS_STEP; 1873 mac->ifs_ratio = IFS_RATIO; 1874 } 1875 1876 mac->in_ifs_mode = FALSE; 1877 E1000_WRITE_REG(hw, E1000_AIT, 0); 1878out: 1879 return; 1880} 1881 1882/** 1883 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 1884 * @hw - pointer to the HW structure 1885 * 1886 * Update the Adaptive Interframe Spacing Throttle value based on the 1887 * time between transmitted packets and time between collisions. 1888 **/ 1889void 1890e1000_update_adaptive_generic(struct e1000_hw *hw) 1891{ 1892 struct e1000_mac_info *mac = &hw->mac; 1893 1894 DEBUGFUNC("e1000_update_adaptive_generic"); 1895 1896 if (!mac->adaptive_ifs) { 1897 DEBUGOUT("Not in Adaptive IFS mode!\n"); 1898 goto out; 1899 } 1900 1901 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1902 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1903 mac->in_ifs_mode = TRUE; 1904 if (mac->current_ifs_val < mac->ifs_max_val) { 1905 if (!mac->current_ifs_val) 1906 mac->current_ifs_val = mac->ifs_min_val; 1907 else 1908 mac->current_ifs_val += 1909 mac->ifs_step_size; 1910 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 1911 } 1912 } 1913 } else { 1914 if (mac->in_ifs_mode && 1915 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 1916 mac->current_ifs_val = 0; 1917 mac->in_ifs_mode = FALSE; 1918 E1000_WRITE_REG(hw, E1000_AIT, 0); 1919 } 1920 } 1921out: 1922 return; 1923} 1924 1925/** 1926 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 1927 * @hw - pointer to the HW structure 1928 * 1929 * Verify that when not using auto-negotitation that MDI/MDIx is correctly 1930 * set, which is forced to MDI mode only. 1931 **/ 1932s32 1933e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 1934{ 1935 s32 ret_val = E1000_SUCCESS; 1936 1937 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 1938 1939 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 1940 DEBUGOUT("Invalid MDI setting detected\n"); 1941 hw->phy.mdix = 1; 1942 ret_val = -E1000_ERR_CONFIG; 1943 goto out; 1944 } 1945 1946out: 1947 return ret_val; 1948} 1949 1950/** 1951 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 1952 * @hw - pointer to the HW structure 1953 * @reg - 32bit register offset such as E1000_SCTL 1954 * @offset - register offset to write to 1955 * @data - data to write at register offset 1956 * 1957 * Writes an address/data control type register. There are several of these 1958 * and they all have the format address << 8 | data and bit 31 is polled for 1959 * completion. 1960 **/ 1961s32 1962e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 1963 u32 offset, u8 data) 1964{ 1965 u32 i, regvalue = 0; 1966 s32 ret_val = E1000_SUCCESS; 1967 1968 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 1969 1970 /* Set up the address and data */ 1971 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 1972 E1000_WRITE_REG(hw, reg, regvalue); 1973 1974 /* Poll the ready bit to see if the MDI read completed */ 1975 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 1976 usec_delay(5); 1977 regvalue = E1000_READ_REG(hw, reg); 1978 if (regvalue & E1000_GEN_CTL_READY) 1979 break; 1980 } 1981 if (!(regvalue & E1000_GEN_CTL_READY)) { 1982 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 1983 ret_val = -E1000_ERR_PHY; 1984 goto out; 1985 } 1986 1987out: 1988 return ret_val; 1989} 1990