e1000_82575.c revision 205869
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 205869 2010-03-29 23:36:34Z jfv $*/ 34 35/* 36 * 82575EB Gigabit Network Connection 37 * 82575EB Gigabit Backplane Connection 38 * 82575GB Gigabit Network Connection 39 * 82575GB Gigabit Network Connection 40 * 82576 Gigabit Network Connection 41 * 82576 Quad Port Gigabit Mezzanine Adapter 42 */ 43 44#include "e1000_api.h" 45 46static s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 47static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); 48static s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 49static s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 50static void e1000_release_phy_82575(struct e1000_hw *hw); 51static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 52static void e1000_release_nvm_82575(struct e1000_hw *hw); 53static s32 e1000_check_for_link_82575(struct e1000_hw *hw); 54static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 55static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 56 u16 *duplex); 57static s32 e1000_init_hw_82575(struct e1000_hw *hw); 58static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 59static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 60 u16 *data); 61static s32 e1000_reset_hw_82575(struct e1000_hw *hw); 62static s32 e1000_reset_hw_82580(struct e1000_hw *hw); 63static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 64 u32 offset, u16 *data); 65static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 66 u32 offset, u16 data); 67static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 68 bool active); 69static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 70static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 71static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 72static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 73 u32 offset, u16 data); 74static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 75static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 76static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 77 u16 *speed, u16 *duplex); 78static s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 79static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 80static bool e1000_sgmii_active_82575(struct e1000_hw *hw); 81static s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 82static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 83static void e1000_config_collision_dist_82575(struct e1000_hw *hw); 84static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 85static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 86static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 87static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 88 89static const u16 e1000_82580_rxpbs_table[] = 90 { 36, 72, 144, 1, 2, 4, 8, 16, 91 35, 70, 140 }; 92#define E1000_82580_RXPBS_TABLE_SIZE \ 93 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 94 95/** 96 * e1000_init_phy_params_82575 - Init PHY func ptrs. 97 * @hw: pointer to the HW structure 98 **/ 99static s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 100{ 101 struct e1000_phy_info *phy = &hw->phy; 102 s32 ret_val = E1000_SUCCESS; 103 104 DEBUGFUNC("e1000_init_phy_params_82575"); 105 106 if (hw->phy.media_type != e1000_media_type_copper) { 107 phy->type = e1000_phy_none; 108 goto out; 109 } 110 111 phy->ops.power_up = e1000_power_up_phy_copper; 112 phy->ops.power_down = e1000_power_down_phy_copper_82575; 113 114 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 115 phy->reset_delay_us = 100; 116 117 phy->ops.acquire = e1000_acquire_phy_82575; 118 phy->ops.check_reset_block = e1000_check_reset_block_generic; 119 phy->ops.commit = e1000_phy_sw_reset_generic; 120 phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 121 phy->ops.release = e1000_release_phy_82575; 122 123 if (e1000_sgmii_active_82575(hw)) { 124 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 125 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 126 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 127 } else if (hw->mac.type >= e1000_82580) { 128 phy->ops.reset = e1000_phy_hw_reset_generic; 129 phy->ops.read_reg = e1000_read_phy_reg_82580; 130 phy->ops.write_reg = e1000_write_phy_reg_82580; 131 } else { 132 phy->ops.reset = e1000_phy_hw_reset_generic; 133 phy->ops.read_reg = e1000_read_phy_reg_igp; 134 phy->ops.write_reg = e1000_write_phy_reg_igp; 135 } 136 137 /* Set phy->phy_addr and phy->id. */ 138 ret_val = e1000_get_phy_id_82575(hw); 139 140 /* Verify phy id and set remaining function pointers */ 141 switch (phy->id) { 142 case M88E1111_I_PHY_ID: 143 phy->type = e1000_phy_m88; 144 phy->ops.check_polarity = e1000_check_polarity_m88; 145 phy->ops.get_info = e1000_get_phy_info_m88; 146 phy->ops.get_cable_length = e1000_get_cable_length_m88; 147 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 148 break; 149 case IGP03E1000_E_PHY_ID: 150 case IGP04E1000_E_PHY_ID: 151 phy->type = e1000_phy_igp_3; 152 phy->ops.check_polarity = e1000_check_polarity_igp; 153 phy->ops.get_info = e1000_get_phy_info_igp; 154 phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 155 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 156 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 157 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 158 break; 159 case I82580_I_PHY_ID: 160 phy->type = e1000_phy_82580; 161 phy->ops.check_polarity = e1000_check_polarity_82577; 162 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; 163 phy->ops.get_cable_length = e1000_get_cable_length_82577; 164 phy->ops.get_info = e1000_get_phy_info_82577; 165 break; 166 default: 167 ret_val = -E1000_ERR_PHY; 168 goto out; 169 } 170 171out: 172 return ret_val; 173} 174 175/** 176 * e1000_init_nvm_params_82575 - Init NVM func ptrs. 177 * @hw: pointer to the HW structure 178 **/ 179static s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 180{ 181 struct e1000_nvm_info *nvm = &hw->nvm; 182 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 183 u16 size; 184 185 DEBUGFUNC("e1000_init_nvm_params_82575"); 186 187 nvm->opcode_bits = 8; 188 nvm->delay_usec = 1; 189 switch (nvm->override) { 190 case e1000_nvm_override_spi_large: 191 nvm->page_size = 32; 192 nvm->address_bits = 16; 193 break; 194 case e1000_nvm_override_spi_small: 195 nvm->page_size = 8; 196 nvm->address_bits = 8; 197 break; 198 default: 199 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 200 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 201 break; 202 } 203 204 nvm->type = e1000_nvm_eeprom_spi; 205 206 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 207 E1000_EECD_SIZE_EX_SHIFT); 208 209 /* 210 * Added to a constant, "size" becomes the left-shift value 211 * for setting word_size. 212 */ 213 size += NVM_WORD_SIZE_BASE_SHIFT; 214 215 /* EEPROM access above 16k is unsupported */ 216 if (size > 14) 217 size = 14; 218 nvm->word_size = 1 << size; 219 220 /* Function Pointers */ 221 nvm->ops.acquire = e1000_acquire_nvm_82575; 222 nvm->ops.read = e1000_read_nvm_eerd; 223 nvm->ops.release = e1000_release_nvm_82575; 224 nvm->ops.update = e1000_update_nvm_checksum_generic; 225 nvm->ops.valid_led_default = e1000_valid_led_default_82575; 226 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 227 nvm->ops.write = e1000_write_nvm_spi; 228 229 return E1000_SUCCESS; 230} 231 232/** 233 * e1000_init_mac_params_82575 - Init MAC func ptrs. 234 * @hw: pointer to the HW structure 235 **/ 236static s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 237{ 238 struct e1000_mac_info *mac = &hw->mac; 239 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 240 u32 ctrl_ext = 0; 241 242 DEBUGFUNC("e1000_init_mac_params_82575"); 243 244 /* Set media type */ 245 /* 246 * The 82575 uses bits 22:23 for link mode. The mode can be changed 247 * based on the EEPROM. We cannot rely upon device ID. There 248 * is no distinguishable difference between fiber and internal 249 * SerDes mode on the 82575. There can be an external PHY attached 250 * on the SGMII interface. For this, we'll set sgmii_active to TRUE. 251 */ 252 hw->phy.media_type = e1000_media_type_copper; 253 dev_spec->sgmii_active = FALSE; 254 255 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 256 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 257 case E1000_CTRL_EXT_LINK_MODE_SGMII: 258 dev_spec->sgmii_active = TRUE; 259 ctrl_ext |= E1000_CTRL_I2C_ENA; 260 break; 261 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 262 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 263 hw->phy.media_type = e1000_media_type_internal_serdes; 264 ctrl_ext |= E1000_CTRL_I2C_ENA; 265 break; 266 default: 267 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 268 break; 269 } 270 271 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 272 273 /* 274 * if using i2c make certain the MDICNFG register is cleared to prevent 275 * communications from being misrouted to the mdic registers 276 */ 277 if ((ctrl_ext & E1000_CTRL_I2C_ENA) && (hw->mac.type == e1000_82580)) 278 E1000_WRITE_REG(hw, E1000_MDICNFG, 0); 279 280 /* Set mta register count */ 281 mac->mta_reg_count = 128; 282 /* Set uta register count */ 283 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 284 /* Set rar entry count */ 285 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 286 if (mac->type == e1000_82576) 287 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 288 if (mac->type == e1000_82580) 289 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 290 /* Set if part includes ASF firmware */ 291 mac->asf_firmware_present = TRUE; 292 /* FWSM register */ 293 mac->has_fwsm = TRUE; 294 /* ARC supported; valid only if manageability features are enabled. */ 295 mac->arc_subsystem_valid = 296 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 297 ? TRUE : FALSE; 298 299 /* Function pointers */ 300 301 /* bus type/speed/width */ 302 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 303 /* reset */ 304 if (mac->type >= e1000_82580) 305 mac->ops.reset_hw = e1000_reset_hw_82580; 306 else 307 mac->ops.reset_hw = e1000_reset_hw_82575; 308 /* hw initialization */ 309 mac->ops.init_hw = e1000_init_hw_82575; 310 /* link setup */ 311 mac->ops.setup_link = e1000_setup_link_generic; 312 /* physical interface link setup */ 313 mac->ops.setup_physical_interface = 314 (hw->phy.media_type == e1000_media_type_copper) 315 ? e1000_setup_copper_link_82575 316 : e1000_setup_serdes_link_82575; 317 /* physical interface shutdown */ 318 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 319 /* physical interface power up */ 320 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 321 /* check for link */ 322 mac->ops.check_for_link = e1000_check_for_link_82575; 323 /* receive address register setting */ 324 mac->ops.rar_set = e1000_rar_set_generic; 325 /* read mac address */ 326 mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 327 /* configure collision distance */ 328 mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 329 /* multicast address update */ 330 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 331 /* writing VFTA */ 332 mac->ops.write_vfta = e1000_write_vfta_generic; 333 /* clearing VFTA */ 334 mac->ops.clear_vfta = e1000_clear_vfta_generic; 335 /* ID LED init */ 336 mac->ops.id_led_init = e1000_id_led_init_generic; 337 /* blink LED */ 338 mac->ops.blink_led = e1000_blink_led_generic; 339 /* setup LED */ 340 mac->ops.setup_led = e1000_setup_led_generic; 341 /* cleanup LED */ 342 mac->ops.cleanup_led = e1000_cleanup_led_generic; 343 /* turn on/off LED */ 344 mac->ops.led_on = e1000_led_on_generic; 345 mac->ops.led_off = e1000_led_off_generic; 346 /* clear hardware counters */ 347 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 348 /* link info */ 349 mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 350 351 /* set lan id for port to determine which phy lock to use */ 352 hw->mac.ops.set_lan_id(hw); 353 354 return E1000_SUCCESS; 355} 356 357/** 358 * e1000_init_function_pointers_82575 - Init func ptrs. 359 * @hw: pointer to the HW structure 360 * 361 * Called to initialize all function pointers and parameters. 362 **/ 363void e1000_init_function_pointers_82575(struct e1000_hw *hw) 364{ 365 DEBUGFUNC("e1000_init_function_pointers_82575"); 366 367 hw->mac.ops.init_params = e1000_init_mac_params_82575; 368 hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 369 hw->phy.ops.init_params = e1000_init_phy_params_82575; 370} 371 372/** 373 * e1000_acquire_phy_82575 - Acquire rights to access PHY 374 * @hw: pointer to the HW structure 375 * 376 * Acquire access rights to the correct PHY. 377 **/ 378static s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 379{ 380 u16 mask = E1000_SWFW_PHY0_SM; 381 382 DEBUGFUNC("e1000_acquire_phy_82575"); 383 384 if (hw->bus.func == E1000_FUNC_1) 385 mask = E1000_SWFW_PHY1_SM; 386 else if (hw->bus.func == E1000_FUNC_2) 387 mask = E1000_SWFW_PHY2_SM; 388 else if (hw->bus.func == E1000_FUNC_3) 389 mask = E1000_SWFW_PHY3_SM; 390 391 return e1000_acquire_swfw_sync_82575(hw, mask); 392} 393 394/** 395 * e1000_release_phy_82575 - Release rights to access PHY 396 * @hw: pointer to the HW structure 397 * 398 * A wrapper to release access rights to the correct PHY. 399 **/ 400static void e1000_release_phy_82575(struct e1000_hw *hw) 401{ 402 u16 mask = E1000_SWFW_PHY0_SM; 403 404 DEBUGFUNC("e1000_release_phy_82575"); 405 406 if (hw->bus.func == E1000_FUNC_1) 407 mask = E1000_SWFW_PHY1_SM; 408 else if (hw->bus.func == E1000_FUNC_2) 409 mask = E1000_SWFW_PHY2_SM; 410 else if (hw->bus.func == E1000_FUNC_3) 411 mask = E1000_SWFW_PHY3_SM; 412 413 e1000_release_swfw_sync_82575(hw, mask); 414} 415 416/** 417 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 418 * @hw: pointer to the HW structure 419 * @offset: register offset to be read 420 * @data: pointer to the read data 421 * 422 * Reads the PHY register at offset using the serial gigabit media independent 423 * interface and stores the retrieved information in data. 424 **/ 425static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 426 u16 *data) 427{ 428 s32 ret_val = -E1000_ERR_PARAM; 429 430 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 431 432 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 433 DEBUGOUT1("PHY Address %u is out of range\n", offset); 434 goto out; 435 } 436 437 ret_val = hw->phy.ops.acquire(hw); 438 if (ret_val) 439 goto out; 440 441 ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 442 443 hw->phy.ops.release(hw); 444 445out: 446 return ret_val; 447} 448 449/** 450 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 451 * @hw: pointer to the HW structure 452 * @offset: register offset to write to 453 * @data: data to write at register offset 454 * 455 * Writes the data to PHY register at the offset using the serial gigabit 456 * media independent interface. 457 **/ 458static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 459 u16 data) 460{ 461 s32 ret_val = -E1000_ERR_PARAM; 462 463 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 464 465 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 466 DEBUGOUT1("PHY Address %d is out of range\n", offset); 467 goto out; 468 } 469 470 ret_val = hw->phy.ops.acquire(hw); 471 if (ret_val) 472 goto out; 473 474 ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 475 476 hw->phy.ops.release(hw); 477 478out: 479 return ret_val; 480} 481 482/** 483 * e1000_get_phy_id_82575 - Retrieve PHY addr and id 484 * @hw: pointer to the HW structure 485 * 486 * Retrieves the PHY address and ID for both PHY's which do and do not use 487 * sgmi interface. 488 **/ 489static s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 490{ 491 struct e1000_phy_info *phy = &hw->phy; 492 s32 ret_val = E1000_SUCCESS; 493 u16 phy_id; 494 u32 ctrl_ext; 495 496 DEBUGFUNC("e1000_get_phy_id_82575"); 497 498 /* 499 * For SGMII PHYs, we try the list of possible addresses until 500 * we find one that works. For non-SGMII PHYs 501 * (e.g. integrated copper PHYs), an address of 1 should 502 * work. The result of this function should mean phy->phy_addr 503 * and phy->id are set correctly. 504 */ 505 if (!e1000_sgmii_active_82575(hw)) { 506 phy->addr = 1; 507 ret_val = e1000_get_phy_id(hw); 508 goto out; 509 } 510 511 /* Power on sgmii phy if it is disabled */ 512 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 513 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 514 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 515 E1000_WRITE_FLUSH(hw); 516 msec_delay(300); 517 518 /* 519 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 520 * Therefore, we need to test 1-7 521 */ 522 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 523 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 524 if (ret_val == E1000_SUCCESS) { 525 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 526 phy_id, 527 phy->addr); 528 /* 529 * At the time of this writing, The M88 part is 530 * the only supported SGMII PHY product. 531 */ 532 if (phy_id == M88_VENDOR) 533 break; 534 } else { 535 DEBUGOUT1("PHY address %u was unreadable\n", 536 phy->addr); 537 } 538 } 539 540 /* A valid PHY type couldn't be found. */ 541 if (phy->addr == 8) { 542 phy->addr = 0; 543 ret_val = -E1000_ERR_PHY; 544 } else { 545 ret_val = e1000_get_phy_id(hw); 546 } 547 548 /* restore previous sfp cage power state */ 549 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 550 551out: 552 return ret_val; 553} 554 555/** 556 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 557 * @hw: pointer to the HW structure 558 * 559 * Resets the PHY using the serial gigabit media independent interface. 560 **/ 561static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 562{ 563 s32 ret_val = E1000_SUCCESS; 564 565 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 566 567 /* 568 * This isn't a TRUE "hard" reset, but is the only reset 569 * available to us at this time. 570 */ 571 572 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 573 574 if (!(hw->phy.ops.write_reg)) 575 goto out; 576 577 /* 578 * SFP documentation requires the following to configure the SPF module 579 * to work on SGMII. No further documentation is given. 580 */ 581 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 582 if (ret_val) 583 goto out; 584 585 ret_val = hw->phy.ops.commit(hw); 586 587out: 588 return ret_val; 589} 590 591/** 592 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 593 * @hw: pointer to the HW structure 594 * @active: TRUE to enable LPLU, FALSE to disable 595 * 596 * Sets the LPLU D0 state according to the active flag. When 597 * activating LPLU this function also disables smart speed 598 * and vice versa. LPLU will not be activated unless the 599 * device autonegotiation advertisement meets standards of 600 * either 10 or 10/100 or 10/100/1000 at all duplexes. 601 * This is a function pointer entry point only called by 602 * PHY setup routines. 603 **/ 604static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 605{ 606 struct e1000_phy_info *phy = &hw->phy; 607 s32 ret_val = E1000_SUCCESS; 608 u16 data; 609 610 DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 611 612 if (!(hw->phy.ops.read_reg)) 613 goto out; 614 615 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 616 if (ret_val) 617 goto out; 618 619 if (active) { 620 data |= IGP02E1000_PM_D0_LPLU; 621 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 622 data); 623 if (ret_val) 624 goto out; 625 626 /* When LPLU is enabled, we should disable SmartSpeed */ 627 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 628 &data); 629 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 630 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 631 data); 632 if (ret_val) 633 goto out; 634 } else { 635 data &= ~IGP02E1000_PM_D0_LPLU; 636 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 637 data); 638 /* 639 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 640 * during Dx states where the power conservation is most 641 * important. During driver activity we should enable 642 * SmartSpeed, so performance is maintained. 643 */ 644 if (phy->smart_speed == e1000_smart_speed_on) { 645 ret_val = phy->ops.read_reg(hw, 646 IGP01E1000_PHY_PORT_CONFIG, 647 &data); 648 if (ret_val) 649 goto out; 650 651 data |= IGP01E1000_PSCFR_SMART_SPEED; 652 ret_val = phy->ops.write_reg(hw, 653 IGP01E1000_PHY_PORT_CONFIG, 654 data); 655 if (ret_val) 656 goto out; 657 } else if (phy->smart_speed == e1000_smart_speed_off) { 658 ret_val = phy->ops.read_reg(hw, 659 IGP01E1000_PHY_PORT_CONFIG, 660 &data); 661 if (ret_val) 662 goto out; 663 664 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 665 ret_val = phy->ops.write_reg(hw, 666 IGP01E1000_PHY_PORT_CONFIG, 667 data); 668 if (ret_val) 669 goto out; 670 } 671 } 672 673out: 674 return ret_val; 675} 676 677/** 678 * e1000_acquire_nvm_82575 - Request for access to EEPROM 679 * @hw: pointer to the HW structure 680 * 681 * Acquire the necessary semaphores for exclusive access to the EEPROM. 682 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 683 * Return successful if access grant bit set, else clear the request for 684 * EEPROM access and return -E1000_ERR_NVM (-1). 685 **/ 686static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 687{ 688 s32 ret_val; 689 690 DEBUGFUNC("e1000_acquire_nvm_82575"); 691 692 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 693 if (ret_val) 694 goto out; 695 696 ret_val = e1000_acquire_nvm_generic(hw); 697 698 if (ret_val) 699 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 700 701out: 702 return ret_val; 703} 704 705/** 706 * e1000_release_nvm_82575 - Release exclusive access to EEPROM 707 * @hw: pointer to the HW structure 708 * 709 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 710 * then release the semaphores acquired. 711 **/ 712static void e1000_release_nvm_82575(struct e1000_hw *hw) 713{ 714 DEBUGFUNC("e1000_release_nvm_82575"); 715 716 e1000_release_nvm_generic(hw); 717 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 718} 719 720/** 721 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 722 * @hw: pointer to the HW structure 723 * @mask: specifies which semaphore to acquire 724 * 725 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 726 * will also specify which port we're acquiring the lock for. 727 **/ 728static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 729{ 730 u32 swfw_sync; 731 u32 swmask = mask; 732 u32 fwmask = mask << 16; 733 s32 ret_val = E1000_SUCCESS; 734 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 735 736 DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 737 738 while (i < timeout) { 739 if (e1000_get_hw_semaphore_generic(hw)) { 740 ret_val = -E1000_ERR_SWFW_SYNC; 741 goto out; 742 } 743 744 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 745 if (!(swfw_sync & (fwmask | swmask))) 746 break; 747 748 /* 749 * Firmware currently using resource (fwmask) 750 * or other software thread using resource (swmask) 751 */ 752 e1000_put_hw_semaphore_generic(hw); 753 msec_delay_irq(5); 754 i++; 755 } 756 757 if (i == timeout) { 758 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 759 ret_val = -E1000_ERR_SWFW_SYNC; 760 goto out; 761 } 762 763 swfw_sync |= swmask; 764 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 765 766 e1000_put_hw_semaphore_generic(hw); 767 768out: 769 return ret_val; 770} 771 772/** 773 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 774 * @hw: pointer to the HW structure 775 * @mask: specifies which semaphore to acquire 776 * 777 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 778 * will also specify which port we're releasing the lock for. 779 **/ 780static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 781{ 782 u32 swfw_sync; 783 784 DEBUGFUNC("e1000_release_swfw_sync_82575"); 785 786 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 787 /* Empty */ 788 789 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 790 swfw_sync &= ~mask; 791 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 792 793 e1000_put_hw_semaphore_generic(hw); 794} 795 796/** 797 * e1000_get_cfg_done_82575 - Read config done bit 798 * @hw: pointer to the HW structure 799 * 800 * Read the management control register for the config done bit for 801 * completion status. NOTE: silicon which is EEPROM-less will fail trying 802 * to read the config done bit, so an error is *ONLY* logged and returns 803 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 804 * would not be able to be reset or change link. 805 **/ 806static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 807{ 808 s32 timeout = PHY_CFG_TIMEOUT; 809 s32 ret_val = E1000_SUCCESS; 810 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 811 812 DEBUGFUNC("e1000_get_cfg_done_82575"); 813 814 if (hw->bus.func == E1000_FUNC_1) 815 mask = E1000_NVM_CFG_DONE_PORT_1; 816 else if (hw->bus.func == E1000_FUNC_2) 817 mask = E1000_NVM_CFG_DONE_PORT_2; 818 else if (hw->bus.func == E1000_FUNC_3) 819 mask = E1000_NVM_CFG_DONE_PORT_3; 820 while (timeout) { 821 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 822 break; 823 msec_delay(1); 824 timeout--; 825 } 826 if (!timeout) 827 DEBUGOUT("MNG configuration cycle has not completed.\n"); 828 829 /* If EEPROM is not marked present, init the PHY manually */ 830 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 831 (hw->phy.type == e1000_phy_igp_3)) 832 e1000_phy_init_script_igp3(hw); 833 834 return ret_val; 835} 836 837/** 838 * e1000_get_link_up_info_82575 - Get link speed/duplex info 839 * @hw: pointer to the HW structure 840 * @speed: stores the current speed 841 * @duplex: stores the current duplex 842 * 843 * This is a wrapper function, if using the serial gigabit media independent 844 * interface, use PCS to retrieve the link speed and duplex information. 845 * Otherwise, use the generic function to get the link speed and duplex info. 846 **/ 847static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 848 u16 *duplex) 849{ 850 s32 ret_val; 851 852 DEBUGFUNC("e1000_get_link_up_info_82575"); 853 854 if (hw->phy.media_type != e1000_media_type_copper) 855 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 856 duplex); 857 else 858 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 859 duplex); 860 861 return ret_val; 862} 863 864/** 865 * e1000_check_for_link_82575 - Check for link 866 * @hw: pointer to the HW structure 867 * 868 * If sgmii is enabled, then use the pcs register to determine link, otherwise 869 * use the generic interface for determining link. 870 **/ 871static s32 e1000_check_for_link_82575(struct e1000_hw *hw) 872{ 873 s32 ret_val; 874 u16 speed, duplex; 875 876 DEBUGFUNC("e1000_check_for_link_82575"); 877 878 if (hw->phy.media_type != e1000_media_type_copper) { 879 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 880 &duplex); 881 /* 882 * Use this flag to determine if link needs to be checked or 883 * not. If we have link clear the flag so that we do not 884 * continue to check for link. 885 */ 886 hw->mac.get_link_status = !hw->mac.serdes_has_link; 887 } else { 888 ret_val = e1000_check_for_copper_link_generic(hw); 889 } 890 891 return ret_val; 892} 893 894/** 895 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 896 * @hw: pointer to the HW structure 897 **/ 898static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 899{ 900 u32 reg; 901 902 DEBUGFUNC("e1000_power_up_serdes_link_82575"); 903 904 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 905 !e1000_sgmii_active_82575(hw)) 906 return; 907 908 /* Enable PCS to turn on link */ 909 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 910 reg |= E1000_PCS_CFG_PCS_EN; 911 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 912 913 /* Power up the laser */ 914 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 915 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 916 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 917 918 /* flush the write to verify completion */ 919 E1000_WRITE_FLUSH(hw); 920 msec_delay(1); 921} 922 923/** 924 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 925 * @hw: pointer to the HW structure 926 * @speed: stores the current speed 927 * @duplex: stores the current duplex 928 * 929 * Using the physical coding sub-layer (PCS), retrieve the current speed and 930 * duplex, then store the values in the pointers provided. 931 **/ 932static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 933 u16 *speed, u16 *duplex) 934{ 935 struct e1000_mac_info *mac = &hw->mac; 936 u32 pcs; 937 938 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 939 940 /* Set up defaults for the return values of this function */ 941 mac->serdes_has_link = FALSE; 942 *speed = 0; 943 *duplex = 0; 944 945 /* 946 * Read the PCS Status register for link state. For non-copper mode, 947 * the status register is not accurate. The PCS status register is 948 * used instead. 949 */ 950 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 951 952 /* 953 * The link up bit determines when link is up on autoneg. The sync ok 954 * gets set once both sides sync up and agree upon link. Stable link 955 * can be determined by checking for both link up and link sync ok 956 */ 957 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 958 mac->serdes_has_link = TRUE; 959 960 /* Detect and store PCS speed */ 961 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 962 *speed = SPEED_1000; 963 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 964 *speed = SPEED_100; 965 } else { 966 *speed = SPEED_10; 967 } 968 969 /* Detect and store PCS duplex */ 970 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 971 *duplex = FULL_DUPLEX; 972 } else { 973 *duplex = HALF_DUPLEX; 974 } 975 } 976 977 return E1000_SUCCESS; 978} 979 980/** 981 * e1000_shutdown_serdes_link_82575 - Remove link during power down 982 * @hw: pointer to the HW structure 983 * 984 * In the case of serdes shut down sfp and PCS on driver unload 985 * when management pass thru is not enabled. 986 **/ 987void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 988{ 989 u32 reg; 990 991 DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 992 993 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 994 !e1000_sgmii_active_82575(hw)) 995 return; 996 997 if (!e1000_enable_mng_pass_thru(hw)) { 998 /* Disable PCS to turn off link */ 999 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1000 reg &= ~E1000_PCS_CFG_PCS_EN; 1001 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1002 1003 /* shutdown the laser */ 1004 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1005 reg |= E1000_CTRL_EXT_SDP3_DATA; 1006 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1007 1008 /* flush the write to verify completion */ 1009 E1000_WRITE_FLUSH(hw); 1010 msec_delay(1); 1011 } 1012 1013 return; 1014} 1015 1016/** 1017 * e1000_reset_hw_82575 - Reset hardware 1018 * @hw: pointer to the HW structure 1019 * 1020 * This resets the hardware into a known state. 1021 **/ 1022static s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1023{ 1024 u32 ctrl, icr; 1025 s32 ret_val; 1026 1027 DEBUGFUNC("e1000_reset_hw_82575"); 1028 1029 /* 1030 * Prevent the PCI-E bus from sticking if there is no TLP connection 1031 * on the last TLP read/write transaction when MAC is reset. 1032 */ 1033 ret_val = e1000_disable_pcie_master_generic(hw); 1034 if (ret_val) { 1035 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1036 } 1037 1038 /* set the completion timeout for interface */ 1039 ret_val = e1000_set_pcie_completion_timeout(hw); 1040 if (ret_val) { 1041 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1042 } 1043 1044 DEBUGOUT("Masking off all interrupts\n"); 1045 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1046 1047 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1048 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1049 E1000_WRITE_FLUSH(hw); 1050 1051 msec_delay(10); 1052 1053 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1054 1055 DEBUGOUT("Issuing a global reset to MAC\n"); 1056 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1057 1058 ret_val = e1000_get_auto_rd_done_generic(hw); 1059 if (ret_val) { 1060 /* 1061 * When auto config read does not complete, do not 1062 * return with an error. This can happen in situations 1063 * where there is no eeprom and prevents getting link. 1064 */ 1065 DEBUGOUT("Auto Read Done did not complete\n"); 1066 } 1067 1068 /* If EEPROM is not present, run manual init scripts */ 1069 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1070 e1000_reset_init_script_82575(hw); 1071 1072 /* Clear any pending interrupt events. */ 1073 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1074 icr = E1000_READ_REG(hw, E1000_ICR); 1075 1076 /* Install any alternate MAC address into RAR0 */ 1077 ret_val = e1000_check_alt_mac_addr_generic(hw); 1078 1079 return ret_val; 1080} 1081 1082/** 1083 * e1000_init_hw_82575 - Initialize hardware 1084 * @hw: pointer to the HW structure 1085 * 1086 * This inits the hardware readying it for operation. 1087 **/ 1088static s32 e1000_init_hw_82575(struct e1000_hw *hw) 1089{ 1090 struct e1000_mac_info *mac = &hw->mac; 1091 s32 ret_val; 1092 u16 i, rar_count = mac->rar_entry_count; 1093 1094 DEBUGFUNC("e1000_init_hw_82575"); 1095 1096 /* Initialize identification LED */ 1097 ret_val = mac->ops.id_led_init(hw); 1098 if (ret_val) { 1099 DEBUGOUT("Error initializing identification LED\n"); 1100 /* This is not fatal and we should not stop init due to this */ 1101 } 1102 1103 /* Disabling VLAN filtering */ 1104 DEBUGOUT("Initializing the IEEE VLAN\n"); 1105 mac->ops.clear_vfta(hw); 1106 1107 /* Setup the receive address */ 1108 e1000_init_rx_addrs_generic(hw, rar_count); 1109 1110 /* Zero out the Multicast HASH table */ 1111 DEBUGOUT("Zeroing the MTA\n"); 1112 for (i = 0; i < mac->mta_reg_count; i++) 1113 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1114 1115 /* Zero out the Unicast HASH table */ 1116 DEBUGOUT("Zeroing the UTA\n"); 1117 for (i = 0; i < mac->uta_reg_count; i++) 1118 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1119 1120 /* Setup link and flow control */ 1121 ret_val = mac->ops.setup_link(hw); 1122 1123 /* 1124 * Clear all of the statistics registers (clear on read). It is 1125 * important that we do this after we have tried to establish link 1126 * because the symbol error count will increment wildly if there 1127 * is no link. 1128 */ 1129 e1000_clear_hw_cntrs_82575(hw); 1130 1131 return ret_val; 1132} 1133 1134/** 1135 * e1000_setup_copper_link_82575 - Configure copper link settings 1136 * @hw: pointer to the HW structure 1137 * 1138 * Configures the link for auto-neg or forced speed and duplex. Then we check 1139 * for link, once link is established calls to configure collision distance 1140 * and flow control are called. 1141 **/ 1142static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1143{ 1144 u32 ctrl; 1145 s32 ret_val; 1146 1147 DEBUGFUNC("e1000_setup_copper_link_82575"); 1148 1149 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1150 ctrl |= E1000_CTRL_SLU; 1151 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1152 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1153 1154 ret_val = e1000_setup_serdes_link_82575(hw); 1155 if (ret_val) 1156 goto out; 1157 1158 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1159 /* allow time for SFP cage time to power up phy */ 1160 msec_delay(300); 1161 1162 ret_val = hw->phy.ops.reset(hw); 1163 if (ret_val) { 1164 DEBUGOUT("Error resetting the PHY.\n"); 1165 goto out; 1166 } 1167 } 1168 switch (hw->phy.type) { 1169 case e1000_phy_m88: 1170 ret_val = e1000_copper_link_setup_m88(hw); 1171 break; 1172 case e1000_phy_igp_3: 1173 ret_val = e1000_copper_link_setup_igp(hw); 1174 break; 1175 case e1000_phy_82580: 1176 ret_val = e1000_copper_link_setup_82577(hw); 1177 break; 1178 default: 1179 ret_val = -E1000_ERR_PHY; 1180 break; 1181 } 1182 1183 if (ret_val) 1184 goto out; 1185 1186 ret_val = e1000_setup_copper_link_generic(hw); 1187out: 1188 return ret_val; 1189} 1190 1191/** 1192 * e1000_setup_serdes_link_82575 - Setup link for serdes 1193 * @hw: pointer to the HW structure 1194 * 1195 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1196 * used on copper connections where the serialized gigabit media independent 1197 * interface (sgmii), or serdes fiber is being used. Configures the link 1198 * for auto-negotiation or forces speed/duplex. 1199 **/ 1200static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1201{ 1202 u32 ctrl_ext, ctrl_reg, reg; 1203 bool pcs_autoneg; 1204 1205 DEBUGFUNC("e1000_setup_serdes_link_82575"); 1206 1207 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1208 !e1000_sgmii_active_82575(hw)) 1209 return E1000_SUCCESS; 1210 1211 /* 1212 * On the 82575, SerDes loopback mode persists until it is 1213 * explicitly turned off or a power cycle is performed. A read to 1214 * the register does not indicate its status. Therefore, we ensure 1215 * loopback mode is disabled during initialization. 1216 */ 1217 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1218 1219 /* power on the sfp cage if present */ 1220 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1221 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1222 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1223 1224 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1225 ctrl_reg |= E1000_CTRL_SLU; 1226 1227 /* set both sw defined pins on 82575/82576*/ 1228 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1229 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1230 1231 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1232 1233 /* default pcs_autoneg to the same setting as mac autoneg */ 1234 pcs_autoneg = hw->mac.autoneg; 1235 1236 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1237 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1238 /* sgmii mode lets the phy handle forcing speed/duplex */ 1239 pcs_autoneg = TRUE; 1240 /* autoneg time out should be disabled for SGMII mode */ 1241 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1242 break; 1243 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1244 /* disable PCS autoneg and support parallel detect only */ 1245 pcs_autoneg = FALSE; 1246 default: 1247 /* 1248 * non-SGMII modes only supports a speed of 1000/Full for the 1249 * link so it is best to just force the MAC and let the pcs 1250 * link either autoneg or be forced to 1000/Full 1251 */ 1252 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1253 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1254 1255 /* set speed of 1000/Full if speed/duplex is forced */ 1256 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1257 break; 1258 } 1259 1260 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1261 1262 /* 1263 * New SerDes mode allows for forcing speed or autonegotiating speed 1264 * at 1gb. Autoneg should be default set by most drivers. This is the 1265 * mode that will be compatible with older link partners and switches. 1266 * However, both are supported by the hardware and some drivers/tools. 1267 */ 1268 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1269 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1270 1271 /* 1272 * We force flow control to prevent the CTRL register values from being 1273 * overwritten by the autonegotiated flow control values 1274 */ 1275 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1276 1277 if (pcs_autoneg) { 1278 /* Set PCS register for autoneg */ 1279 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1280 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1281 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1282 } else { 1283 /* Set PCS register for forced link */ 1284 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1285 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1286 } 1287 1288 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1289 1290 if (!e1000_sgmii_active_82575(hw)) 1291 e1000_force_mac_fc_generic(hw); 1292 1293 return E1000_SUCCESS; 1294} 1295 1296/** 1297 * e1000_valid_led_default_82575 - Verify a valid default LED config 1298 * @hw: pointer to the HW structure 1299 * @data: pointer to the NVM (EEPROM) 1300 * 1301 * Read the EEPROM for the current default LED configuration. If the 1302 * LED configuration is not valid, set to a valid LED configuration. 1303 **/ 1304static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1305{ 1306 s32 ret_val; 1307 1308 DEBUGFUNC("e1000_valid_led_default_82575"); 1309 1310 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1311 if (ret_val) { 1312 DEBUGOUT("NVM Read Error\n"); 1313 goto out; 1314 } 1315 1316 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1317 switch(hw->phy.media_type) { 1318 case e1000_media_type_internal_serdes: 1319 *data = ID_LED_DEFAULT_82575_SERDES; 1320 break; 1321 case e1000_media_type_copper: 1322 default: 1323 *data = ID_LED_DEFAULT; 1324 break; 1325 } 1326 } 1327out: 1328 return ret_val; 1329} 1330 1331/** 1332 * e1000_sgmii_active_82575 - Return sgmii state 1333 * @hw: pointer to the HW structure 1334 * 1335 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1336 * which can be enabled for use in the embedded applications. Simply 1337 * return the current state of the sgmii interface. 1338 **/ 1339static bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1340{ 1341 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1342 return dev_spec->sgmii_active; 1343} 1344 1345/** 1346 * e1000_reset_init_script_82575 - Inits HW defaults after reset 1347 * @hw: pointer to the HW structure 1348 * 1349 * Inits recommended HW defaults after a reset when there is no EEPROM 1350 * detected. This is only for the 82575. 1351 **/ 1352static s32 e1000_reset_init_script_82575(struct e1000_hw* hw) 1353{ 1354 DEBUGFUNC("e1000_reset_init_script_82575"); 1355 1356 if (hw->mac.type == e1000_82575) { 1357 DEBUGOUT("Running reset init script for 82575\n"); 1358 /* SerDes configuration via SERDESCTRL */ 1359 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1360 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1361 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1362 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1363 1364 /* CCM configuration via CCMCTL register */ 1365 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1366 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1367 1368 /* PCIe lanes configuration */ 1369 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1370 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1371 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1372 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1373 1374 /* PCIe PLL Configuration */ 1375 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1376 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1377 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1378 } 1379 1380 return E1000_SUCCESS; 1381} 1382 1383/** 1384 * e1000_read_mac_addr_82575 - Read device MAC address 1385 * @hw: pointer to the HW structure 1386 **/ 1387static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1388{ 1389 s32 ret_val = E1000_SUCCESS; 1390 1391 DEBUGFUNC("e1000_read_mac_addr_82575"); 1392 1393 /* 1394 * If there's an alternate MAC address place it in RAR0 1395 * so that it will override the Si installed default perm 1396 * address. 1397 */ 1398 ret_val = e1000_check_alt_mac_addr_generic(hw); 1399 if (ret_val) 1400 goto out; 1401 1402 ret_val = e1000_read_mac_addr_generic(hw); 1403 1404out: 1405 return ret_val; 1406} 1407 1408/** 1409 * e1000_config_collision_dist_82575 - Configure collision distance 1410 * @hw: pointer to the HW structure 1411 * 1412 * Configures the collision distance to the default value and is used 1413 * during link setup. 1414 **/ 1415static void e1000_config_collision_dist_82575(struct e1000_hw *hw) 1416{ 1417 u32 tctl_ext; 1418 1419 DEBUGFUNC("e1000_config_collision_dist_82575"); 1420 1421 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 1422 1423 tctl_ext &= ~E1000_TCTL_EXT_COLD; 1424 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 1425 1426 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 1427 E1000_WRITE_FLUSH(hw); 1428} 1429 1430/** 1431 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 1432 * @hw: pointer to the HW structure 1433 * 1434 * In the case of a PHY power down to save power, or to turn off link during a 1435 * driver unload, or wake on lan is not enabled, remove the link. 1436 **/ 1437static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 1438{ 1439 struct e1000_phy_info *phy = &hw->phy; 1440 1441 if (!(phy->ops.check_reset_block)) 1442 return; 1443 1444 /* If the management interface is not enabled, then power down */ 1445 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 1446 e1000_power_down_phy_copper(hw); 1447 1448 return; 1449} 1450 1451/** 1452 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 1453 * @hw: pointer to the HW structure 1454 * 1455 * Clears the hardware counters by reading the counter registers. 1456 **/ 1457static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 1458{ 1459 DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 1460 1461 e1000_clear_hw_cntrs_base_generic(hw); 1462 1463 E1000_READ_REG(hw, E1000_PRC64); 1464 E1000_READ_REG(hw, E1000_PRC127); 1465 E1000_READ_REG(hw, E1000_PRC255); 1466 E1000_READ_REG(hw, E1000_PRC511); 1467 E1000_READ_REG(hw, E1000_PRC1023); 1468 E1000_READ_REG(hw, E1000_PRC1522); 1469 E1000_READ_REG(hw, E1000_PTC64); 1470 E1000_READ_REG(hw, E1000_PTC127); 1471 E1000_READ_REG(hw, E1000_PTC255); 1472 E1000_READ_REG(hw, E1000_PTC511); 1473 E1000_READ_REG(hw, E1000_PTC1023); 1474 E1000_READ_REG(hw, E1000_PTC1522); 1475 1476 E1000_READ_REG(hw, E1000_ALGNERRC); 1477 E1000_READ_REG(hw, E1000_RXERRC); 1478 E1000_READ_REG(hw, E1000_TNCRS); 1479 E1000_READ_REG(hw, E1000_CEXTERR); 1480 E1000_READ_REG(hw, E1000_TSCTC); 1481 E1000_READ_REG(hw, E1000_TSCTFC); 1482 1483 E1000_READ_REG(hw, E1000_MGTPRC); 1484 E1000_READ_REG(hw, E1000_MGTPDC); 1485 E1000_READ_REG(hw, E1000_MGTPTC); 1486 1487 E1000_READ_REG(hw, E1000_IAC); 1488 E1000_READ_REG(hw, E1000_ICRXOC); 1489 1490 E1000_READ_REG(hw, E1000_ICRXPTC); 1491 E1000_READ_REG(hw, E1000_ICRXATC); 1492 E1000_READ_REG(hw, E1000_ICTXPTC); 1493 E1000_READ_REG(hw, E1000_ICTXATC); 1494 E1000_READ_REG(hw, E1000_ICTXQEC); 1495 E1000_READ_REG(hw, E1000_ICTXQMTC); 1496 E1000_READ_REG(hw, E1000_ICRXDMTC); 1497 1498 E1000_READ_REG(hw, E1000_CBTMPC); 1499 E1000_READ_REG(hw, E1000_HTDPMC); 1500 E1000_READ_REG(hw, E1000_CBRMPC); 1501 E1000_READ_REG(hw, E1000_RPTHC); 1502 E1000_READ_REG(hw, E1000_HGPTC); 1503 E1000_READ_REG(hw, E1000_HTCBDPC); 1504 E1000_READ_REG(hw, E1000_HGORCL); 1505 E1000_READ_REG(hw, E1000_HGORCH); 1506 E1000_READ_REG(hw, E1000_HGOTCL); 1507 E1000_READ_REG(hw, E1000_HGOTCH); 1508 E1000_READ_REG(hw, E1000_LENERRS); 1509 1510 /* This register should not be read in copper configurations */ 1511 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 1512 e1000_sgmii_active_82575(hw)) 1513 E1000_READ_REG(hw, E1000_SCVPC); 1514} 1515 1516/** 1517 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1518 * @hw: pointer to the HW structure 1519 * 1520 * After rx enable if managability is enabled then there is likely some 1521 * bad data at the start of the fifo and possibly in the DMA fifo. This 1522 * function clears the fifos and flushes any packets that came in as rx was 1523 * being enabled. 1524 **/ 1525void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 1526{ 1527 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1528 int i, ms_wait; 1529 1530 DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 1531 if (hw->mac.type != e1000_82575 || 1532 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1533 return; 1534 1535 /* Disable all RX queues */ 1536 for (i = 0; i < 4; i++) { 1537 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 1538 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 1539 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1540 } 1541 /* Poll all queues to verify they have shut down */ 1542 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1543 msec_delay(1); 1544 rx_enabled = 0; 1545 for (i = 0; i < 4; i++) 1546 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 1547 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1548 break; 1549 } 1550 1551 if (ms_wait == 10) 1552 DEBUGOUT("Queue disable timed out after 10ms\n"); 1553 1554 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1555 * incoming packets are rejected. Set enable and wait 2ms so that 1556 * any packet that was coming in as RCTL.EN was set is flushed 1557 */ 1558 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 1559 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1560 1561 rlpml = E1000_READ_REG(hw, E1000_RLPML); 1562 E1000_WRITE_REG(hw, E1000_RLPML, 0); 1563 1564 rctl = E1000_READ_REG(hw, E1000_RCTL); 1565 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1566 temp_rctl |= E1000_RCTL_LPE; 1567 1568 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 1569 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1570 E1000_WRITE_FLUSH(hw); 1571 msec_delay(2); 1572 1573 /* Enable RX queues that were previously enabled and restore our 1574 * previous state 1575 */ 1576 for (i = 0; i < 4; i++) 1577 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 1578 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 1579 E1000_WRITE_FLUSH(hw); 1580 1581 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 1582 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 1583 1584 /* Flush receive errors generated by workaround */ 1585 E1000_READ_REG(hw, E1000_ROC); 1586 E1000_READ_REG(hw, E1000_RNBC); 1587 E1000_READ_REG(hw, E1000_MPC); 1588} 1589 1590/** 1591 * e1000_set_pcie_completion_timeout - set pci-e completion timeout 1592 * @hw: pointer to the HW structure 1593 * 1594 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1595 * however the hardware default for these parts is 500us to 1ms which is less 1596 * than the 10ms recommended by the pci-e spec. To address this we need to 1597 * increase the value to either 10ms to 200ms for capability version 1 config, 1598 * or 16ms to 55ms for version 2. 1599 **/ 1600static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 1601{ 1602 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 1603 s32 ret_val = E1000_SUCCESS; 1604 u16 pcie_devctl2; 1605 1606 /* only take action if timeout value is defaulted to 0 */ 1607 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1608 goto out; 1609 1610 /* 1611 * if capababilities version is type 1 we can write the 1612 * timeout of 10ms to 200ms through the GCR register 1613 */ 1614 if (!(gcr & E1000_GCR_CAP_VER2)) { 1615 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 1616 goto out; 1617 } 1618 1619 /* 1620 * for version 2 capabilities we need to write the config space 1621 * directly in order to set the completion timeout value for 1622 * 16ms to 55ms 1623 */ 1624 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1625 &pcie_devctl2); 1626 if (ret_val) 1627 goto out; 1628 1629 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 1630 1631 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1632 &pcie_devctl2); 1633out: 1634 /* disable completion timeout resend */ 1635 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 1636 1637 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1638 return ret_val; 1639} 1640 1641/** 1642 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 1643 * @hw: pointer to the hardware struct 1644 * @enable: state to enter, either enabled or disabled 1645 * 1646 * enables/disables L2 switch loopback functionality. 1647 **/ 1648void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 1649{ 1650 u32 dtxswc; 1651 1652 switch (hw->mac.type) { 1653 case e1000_82576: 1654 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 1655 if (enable) 1656 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1657 else 1658 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1659 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 1660 break; 1661 default: 1662 /* Currently no other hardware supports loopback */ 1663 break; 1664 } 1665 1666 1667} 1668 1669/** 1670 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 1671 * @hw: pointer to the hardware struct 1672 * @enable: state to enter, either enabled or disabled 1673 * 1674 * enables/disables replication of packets across multiple pools. 1675 **/ 1676void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 1677{ 1678 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 1679 1680 if (enable) 1681 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 1682 else 1683 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 1684 1685 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 1686} 1687 1688/** 1689 * e1000_read_phy_reg_82580 - Read 82580 MDI control register 1690 * @hw: pointer to the HW structure 1691 * @offset: register offset to be read 1692 * @data: pointer to the read data 1693 * 1694 * Reads the MDI control register in the PHY at offset and stores the 1695 * information read to data. 1696 **/ 1697static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 1698{ 1699 s32 ret_val; 1700 1701 DEBUGFUNC("e1000_read_phy_reg_82580"); 1702 1703 ret_val = hw->phy.ops.acquire(hw); 1704 if (ret_val) 1705 goto out; 1706 1707 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 1708 1709 hw->phy.ops.release(hw); 1710 1711out: 1712 return ret_val; 1713} 1714 1715/** 1716 * e1000_write_phy_reg_82580 - Write 82580 MDI control register 1717 * @hw: pointer to the HW structure 1718 * @offset: register offset to write to 1719 * @data: data to write to register at offset 1720 * 1721 * Writes data to MDI control register in the PHY at offset. 1722 **/ 1723static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 1724{ 1725 s32 ret_val; 1726 1727 DEBUGFUNC("e1000_write_phy_reg_82580"); 1728 1729 ret_val = hw->phy.ops.acquire(hw); 1730 if (ret_val) 1731 goto out; 1732 1733 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 1734 1735 hw->phy.ops.release(hw); 1736 1737out: 1738 return ret_val; 1739} 1740 1741/** 1742 * e1000_reset_hw_82580 - Reset hardware 1743 * @hw: pointer to the HW structure 1744 * 1745 * This resets function or entire device (all ports, etc.) 1746 * to a known state. 1747 **/ 1748static s32 e1000_reset_hw_82580(struct e1000_hw *hw) 1749{ 1750 s32 ret_val = E1000_SUCCESS; 1751 /* BH SW mailbox bit in SW_FW_SYNC */ 1752 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 1753 u32 ctrl, icr; 1754 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 1755 1756 DEBUGFUNC("e1000_reset_hw_82580"); 1757 1758 hw->dev_spec._82575.global_device_reset = FALSE; 1759 1760 /* Get current control state. */ 1761 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1762 1763 /* 1764 * Prevent the PCI-E bus from sticking if there is no TLP connection 1765 * on the last TLP read/write transaction when MAC is reset. 1766 */ 1767 ret_val = e1000_disable_pcie_master_generic(hw); 1768 if (ret_val) 1769 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1770 1771 DEBUGOUT("Masking off all interrupts\n"); 1772 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1773 E1000_WRITE_REG(hw, E1000_RCTL, 0); 1774 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1775 E1000_WRITE_FLUSH(hw); 1776 1777 msec_delay(10); 1778 1779 /* Determine whether or not a global dev reset is requested */ 1780 if (global_device_reset && 1781 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask)) 1782 global_device_reset = FALSE; 1783 1784 if (global_device_reset && 1785 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 1786 ctrl |= E1000_CTRL_DEV_RST; 1787 else 1788 ctrl |= E1000_CTRL_RST; 1789 1790 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1791 1792 /* Add delay to insure DEV_RST has time to complete */ 1793 if (global_device_reset) 1794 msec_delay(5); 1795 1796 ret_val = e1000_get_auto_rd_done_generic(hw); 1797 if (ret_val) { 1798 /* 1799 * When auto config read does not complete, do not 1800 * return with an error. This can happen in situations 1801 * where there is no eeprom and prevents getting link. 1802 */ 1803 DEBUGOUT("Auto Read Done did not complete\n"); 1804 } 1805 1806 /* If EEPROM is not present, run manual init scripts */ 1807 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 1808 e1000_reset_init_script_82575(hw); 1809 1810 /* clear global device reset status bit */ 1811 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 1812 1813 /* Clear any pending interrupt events. */ 1814 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1815 icr = E1000_READ_REG(hw, E1000_ICR); 1816 1817 /* Install any alternate MAC address into RAR0 */ 1818 ret_val = e1000_check_alt_mac_addr_generic(hw); 1819 1820 /* Release semaphore */ 1821 if (global_device_reset) 1822 e1000_release_swfw_sync_82575(hw, swmbsw_mask); 1823 1824 return ret_val; 1825} 1826 1827/** 1828 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 1829 * @data: data received by reading RXPBS register 1830 * 1831 * The 82580 uses a table based approach for packet buffer allocation sizes. 1832 * This function converts the retrieved value into the correct table value 1833 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 1834 * 0x0 36 72 144 1 2 4 8 16 1835 * 0x8 35 70 140 rsv rsv rsv rsv rsv 1836 */ 1837u16 e1000_rxpbs_adjust_82580(u32 data) 1838{ 1839 u16 ret_val = 0; 1840 1841 if (data < E1000_82580_RXPBS_TABLE_SIZE) 1842 ret_val = e1000_82580_rxpbs_table[data]; 1843 1844 return ret_val; 1845} 1846