1176667Sjfv/****************************************************************************** 2176667Sjfv 3269196Sjfv Copyright (c) 2001-2014, Intel Corporation 4176667Sjfv All rights reserved. 5176667Sjfv 6176667Sjfv Redistribution and use in source and binary forms, with or without 7176667Sjfv modification, are permitted provided that the following conditions are met: 8176667Sjfv 9176667Sjfv 1. Redistributions of source code must retain the above copyright notice, 10176667Sjfv this list of conditions and the following disclaimer. 11176667Sjfv 12176667Sjfv 2. Redistributions in binary form must reproduce the above copyright 13176667Sjfv notice, this list of conditions and the following disclaimer in the 14176667Sjfv documentation and/or other materials provided with the distribution. 15176667Sjfv 16176667Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17176667Sjfv contributors may be used to endorse or promote products derived from 18176667Sjfv this software without specific prior written permission. 19176667Sjfv 20176667Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21176667Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22176667Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23176667Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24176667Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25176667Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26176667Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27176667Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28176667Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29176667Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30176667Sjfv POSSIBILITY OF SUCH DAMAGE. 31176667Sjfv 32176667Sjfv******************************************************************************/ 33176667Sjfv/*$FreeBSD: releng/10.2/sys/dev/e1000/e1000_82575.c 269196 2014-07-28 21:11:18Z jfv $*/ 34176667Sjfv 35185353Sjfv/* 36185353Sjfv * 82575EB Gigabit Network Connection 37185353Sjfv * 82575EB Gigabit Backplane Connection 38185353Sjfv * 82575GB Gigabit Network Connection 39185353Sjfv * 82576 Gigabit Network Connection 40194865Sjfv * 82576 Quad Port Gigabit Mezzanine Adapter 41238148Sjfv * 82580 Gigabit Network Connection 42238148Sjfv * I350 Gigabit Network Connection 43176667Sjfv */ 44176667Sjfv 45176667Sjfv#include "e1000_api.h" 46238148Sjfv#include "e1000_i210.h" 47176667Sjfv 48176667Sjfvstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw); 49176667Sjfvstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw); 50176667Sjfvstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw); 51176667Sjfvstatic void e1000_release_phy_82575(struct e1000_hw *hw); 52176667Sjfvstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); 53176667Sjfvstatic void e1000_release_nvm_82575(struct e1000_hw *hw); 54176667Sjfvstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw); 55256200Sjfvstatic s32 e1000_check_for_link_media_swap(struct e1000_hw *hw); 56176667Sjfvstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw); 57176667Sjfvstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 58228386Sjfv u16 *duplex); 59176667Sjfvstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); 60176667Sjfvstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 61228386Sjfv u16 *data); 62176667Sjfvstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw); 63200243Sjfvstatic s32 e1000_reset_hw_82580(struct e1000_hw *hw); 64218530Sjfvstatic s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, 65228386Sjfv u32 offset, u16 *data); 66218530Sjfvstatic s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, 67228386Sjfv u32 offset, u16 data); 68218530Sjfvstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, 69228386Sjfv bool active); 70218530Sjfvstatic s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, 71228386Sjfv bool active); 72176667Sjfvstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, 73228386Sjfv bool active); 74176667Sjfvstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw); 75200243Sjfvstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw); 76228386Sjfvstatic s32 e1000_get_media_type_82575(struct e1000_hw *hw); 77228386Sjfvstatic s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw); 78181027Sjfvstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data); 79176667Sjfvstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, 80228386Sjfv u32 offset, u16 data); 81176667Sjfvstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw); 82176667Sjfvstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 83176667Sjfvstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 84228386Sjfv u16 *speed, u16 *duplex); 85176667Sjfvstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw); 86176667Sjfvstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); 87176667Sjfvstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw); 88176667Sjfvstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw); 89176667Sjfvstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); 90203049Sjfvstatic void e1000_config_collision_dist_82575(struct e1000_hw *hw); 91176667Sjfvstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); 92200243Sjfvstatic void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); 93203049Sjfvstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); 94194865Sjfvstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); 95213234Sjfvstatic s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw); 96218530Sjfvstatic s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw); 97218530Sjfvstatic s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw); 98218530Sjfvstatic s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, 99228386Sjfv u16 offset); 100218530Sjfvstatic s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 101228386Sjfv u16 offset); 102218530Sjfvstatic s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw); 103218530Sjfvstatic s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw); 104228386Sjfvstatic void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value); 105228386Sjfvstatic void e1000_clear_vfta_i350(struct e1000_hw *hw); 106176667Sjfv 107228386Sjfvstatic void e1000_i2c_start(struct e1000_hw *hw); 108228386Sjfvstatic void e1000_i2c_stop(struct e1000_hw *hw); 109228386Sjfvstatic s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data); 110228386Sjfvstatic s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data); 111228386Sjfvstatic s32 e1000_get_i2c_ack(struct e1000_hw *hw); 112228386Sjfvstatic s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data); 113228386Sjfvstatic s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data); 114228386Sjfvstatic void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 115228386Sjfvstatic void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl); 116228386Sjfvstatic s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data); 117228386Sjfvstatic bool e1000_get_i2c_data(u32 *i2cctl); 118228386Sjfv 119228386Sjfvstatic const u16 e1000_82580_rxpbs_table[] = { 120228386Sjfv 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 121200243Sjfv#define E1000_82580_RXPBS_TABLE_SIZE \ 122269196Sjfv (sizeof(e1000_82580_rxpbs_table) / \ 123269196Sjfv sizeof(e1000_82580_rxpbs_table[0])) 124200243Sjfv 125213234Sjfv 126176667Sjfv/** 127213234Sjfv * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 128213234Sjfv * @hw: pointer to the HW structure 129213234Sjfv * 130213234Sjfv * Called to determine if the I2C pins are being used for I2C or as an 131213234Sjfv * external MDIO interface since the two options are mutually exclusive. 132213234Sjfv **/ 133213234Sjfvstatic bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) 134213234Sjfv{ 135213234Sjfv u32 reg = 0; 136213234Sjfv bool ext_mdio = FALSE; 137213234Sjfv 138213234Sjfv DEBUGFUNC("e1000_sgmii_uses_mdio_82575"); 139213234Sjfv 140213234Sjfv switch (hw->mac.type) { 141213234Sjfv case e1000_82575: 142213234Sjfv case e1000_82576: 143213234Sjfv reg = E1000_READ_REG(hw, E1000_MDIC); 144213234Sjfv ext_mdio = !!(reg & E1000_MDIC_DEST); 145213234Sjfv break; 146213234Sjfv case e1000_82580: 147218530Sjfv case e1000_i350: 148256200Sjfv case e1000_i354: 149247064Sjfv case e1000_i210: 150247064Sjfv case e1000_i211: 151213234Sjfv reg = E1000_READ_REG(hw, E1000_MDICNFG); 152213234Sjfv ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 153213234Sjfv break; 154213234Sjfv default: 155213234Sjfv break; 156213234Sjfv } 157213234Sjfv return ext_mdio; 158213234Sjfv} 159213234Sjfv 160213234Sjfv/** 161176667Sjfv * e1000_init_phy_params_82575 - Init PHY func ptrs. 162176667Sjfv * @hw: pointer to the HW structure 163176667Sjfv **/ 164176667Sjfvstatic s32 e1000_init_phy_params_82575(struct e1000_hw *hw) 165176667Sjfv{ 166176667Sjfv struct e1000_phy_info *phy = &hw->phy; 167176667Sjfv s32 ret_val = E1000_SUCCESS; 168213234Sjfv u32 ctrl_ext; 169176667Sjfv 170176667Sjfv DEBUGFUNC("e1000_init_phy_params_82575"); 171176667Sjfv 172238148Sjfv phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; 173238148Sjfv phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; 174238148Sjfv 175176667Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 176176667Sjfv phy->type = e1000_phy_none; 177176667Sjfv goto out; 178176667Sjfv } 179176667Sjfv 180200243Sjfv phy->ops.power_up = e1000_power_up_phy_copper; 181200243Sjfv phy->ops.power_down = e1000_power_down_phy_copper_82575; 182200243Sjfv 183228386Sjfv phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 184228386Sjfv phy->reset_delay_us = 100; 185176667Sjfv 186228386Sjfv phy->ops.acquire = e1000_acquire_phy_82575; 187228386Sjfv phy->ops.check_reset_block = e1000_check_reset_block_generic; 188228386Sjfv phy->ops.commit = e1000_phy_sw_reset_generic; 189228386Sjfv phy->ops.get_cfg_done = e1000_get_cfg_done_82575; 190228386Sjfv phy->ops.release = e1000_release_phy_82575; 191176667Sjfv 192213234Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 193213234Sjfv 194176667Sjfv if (e1000_sgmii_active_82575(hw)) { 195228386Sjfv phy->ops.reset = e1000_phy_hw_reset_sgmii_82575; 196213234Sjfv ctrl_ext |= E1000_CTRL_I2C_ENA; 197213234Sjfv } else { 198228386Sjfv phy->ops.reset = e1000_phy_hw_reset_generic; 199213234Sjfv ctrl_ext &= ~E1000_CTRL_I2C_ENA; 200213234Sjfv } 201213234Sjfv 202213234Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 203213234Sjfv e1000_reset_mdicnfg_82580(hw); 204218530Sjfv 205213234Sjfv if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) { 206228386Sjfv phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575; 207228386Sjfv phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575; 208176667Sjfv } else { 209238148Sjfv switch (hw->mac.type) { 210238148Sjfv case e1000_82580: 211238148Sjfv case e1000_i350: 212256200Sjfv case e1000_i354: 213238148Sjfv phy->ops.read_reg = e1000_read_phy_reg_82580; 214238148Sjfv phy->ops.write_reg = e1000_write_phy_reg_82580; 215238148Sjfv break; 216238148Sjfv case e1000_i210: 217238148Sjfv case e1000_i211: 218238148Sjfv phy->ops.read_reg = e1000_read_phy_reg_gs40g; 219238148Sjfv phy->ops.write_reg = e1000_write_phy_reg_gs40g; 220238148Sjfv break; 221238148Sjfv default: 222238148Sjfv phy->ops.read_reg = e1000_read_phy_reg_igp; 223238148Sjfv phy->ops.write_reg = e1000_write_phy_reg_igp; 224238148Sjfv } 225176667Sjfv } 226176667Sjfv 227176667Sjfv /* Set phy->phy_addr and phy->id. */ 228176667Sjfv ret_val = e1000_get_phy_id_82575(hw); 229176667Sjfv 230176667Sjfv /* Verify phy id and set remaining function pointers */ 231176667Sjfv switch (phy->id) { 232256200Sjfv case M88E1543_E_PHY_ID: 233256200Sjfv case M88E1512_E_PHY_ID: 234218530Sjfv case I347AT4_E_PHY_ID: 235218530Sjfv case M88E1112_E_PHY_ID: 236219753Sjfv case M88E1340M_E_PHY_ID: 237176667Sjfv case M88E1111_I_PHY_ID: 238228386Sjfv phy->type = e1000_phy_m88; 239228386Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 240228386Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 241218530Sjfv if (phy->id == I347AT4_E_PHY_ID || 242219753Sjfv phy->id == M88E1112_E_PHY_ID || 243219753Sjfv phy->id == M88E1340M_E_PHY_ID) 244228386Sjfv phy->ops.get_cable_length = 245228386Sjfv e1000_get_cable_length_m88_gen2; 246256200Sjfv else if (phy->id == M88E1543_E_PHY_ID || 247256200Sjfv phy->id == M88E1512_E_PHY_ID) 248256200Sjfv phy->ops.get_cable_length = 249256200Sjfv e1000_get_cable_length_m88_gen2; 250218530Sjfv else 251218530Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88; 252176667Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 253256200Sjfv /* Check if this PHY is confgured for media swap. */ 254256200Sjfv if (phy->id == M88E1112_E_PHY_ID) { 255256200Sjfv u16 data; 256256200Sjfv 257256200Sjfv ret_val = phy->ops.write_reg(hw, 258256200Sjfv E1000_M88E1112_PAGE_ADDR, 259256200Sjfv 2); 260256200Sjfv if (ret_val) 261256200Sjfv goto out; 262256200Sjfv 263256200Sjfv ret_val = phy->ops.read_reg(hw, 264256200Sjfv E1000_M88E1112_MAC_CTRL_1, 265256200Sjfv &data); 266256200Sjfv if (ret_val) 267256200Sjfv goto out; 268256200Sjfv 269256200Sjfv data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 270256200Sjfv E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 271256200Sjfv if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 272256200Sjfv data == E1000_M88E1112_AUTO_COPPER_BASEX) 273256200Sjfv hw->mac.ops.check_for_link = 274256200Sjfv e1000_check_for_link_media_swap; 275256200Sjfv } 276269196Sjfv if (phy->id == M88E1512_E_PHY_ID) { 277269196Sjfv ret_val = e1000_initialize_M88E1512_phy(hw); 278269196Sjfv if (ret_val) 279269196Sjfv goto out; 280269196Sjfv } 281176667Sjfv break; 282176667Sjfv case IGP03E1000_E_PHY_ID: 283181027Sjfv case IGP04E1000_E_PHY_ID: 284228386Sjfv phy->type = e1000_phy_igp_3; 285228386Sjfv phy->ops.check_polarity = e1000_check_polarity_igp; 286228386Sjfv phy->ops.get_info = e1000_get_phy_info_igp; 287228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_igp_2; 288176667Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 289228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; 290228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 291176667Sjfv break; 292200243Sjfv case I82580_I_PHY_ID: 293218530Sjfv case I350_I_PHY_ID: 294228386Sjfv phy->type = e1000_phy_82580; 295228386Sjfv phy->ops.check_polarity = e1000_check_polarity_82577; 296228386Sjfv phy->ops.force_speed_duplex = 297228386Sjfv e1000_phy_force_speed_duplex_82577; 298228386Sjfv phy->ops.get_cable_length = e1000_get_cable_length_82577; 299228386Sjfv phy->ops.get_info = e1000_get_phy_info_82577; 300228386Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 301228386Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 302200243Sjfv break; 303238148Sjfv case I210_I_PHY_ID: 304238148Sjfv phy->type = e1000_phy_i210; 305238148Sjfv phy->ops.check_polarity = e1000_check_polarity_m88; 306238148Sjfv phy->ops.get_info = e1000_get_phy_info_m88; 307238148Sjfv phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; 308238148Sjfv phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; 309238148Sjfv phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; 310238148Sjfv phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; 311238148Sjfv break; 312176667Sjfv default: 313176667Sjfv ret_val = -E1000_ERR_PHY; 314176667Sjfv goto out; 315176667Sjfv } 316176667Sjfv 317176667Sjfvout: 318176667Sjfv return ret_val; 319176667Sjfv} 320176667Sjfv 321176667Sjfv/** 322176667Sjfv * e1000_init_nvm_params_82575 - Init NVM func ptrs. 323176667Sjfv * @hw: pointer to the HW structure 324176667Sjfv **/ 325219753Sjfvs32 e1000_init_nvm_params_82575(struct e1000_hw *hw) 326176667Sjfv{ 327176667Sjfv struct e1000_nvm_info *nvm = &hw->nvm; 328176667Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 329176667Sjfv u16 size; 330176667Sjfv 331176667Sjfv DEBUGFUNC("e1000_init_nvm_params_82575"); 332176667Sjfv 333218530Sjfv size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 334228386Sjfv E1000_EECD_SIZE_EX_SHIFT); 335218530Sjfv /* 336218530Sjfv * Added to a constant, "size" becomes the left-shift value 337218530Sjfv * for setting word_size. 338218530Sjfv */ 339218530Sjfv size += NVM_WORD_SIZE_BASE_SHIFT; 340218530Sjfv 341228386Sjfv /* Just in case size is out of range, cap it to the largest 342228386Sjfv * EEPROM size supported 343228386Sjfv */ 344228386Sjfv if (size > 15) 345228386Sjfv size = 15; 346228386Sjfv 347218530Sjfv nvm->word_size = 1 << size; 348238148Sjfv if (hw->mac.type < e1000_i210) { 349238148Sjfv nvm->opcode_bits = 8; 350238148Sjfv nvm->delay_usec = 1; 351176667Sjfv 352238148Sjfv switch (nvm->override) { 353238148Sjfv case e1000_nvm_override_spi_large: 354238148Sjfv nvm->page_size = 32; 355238148Sjfv nvm->address_bits = 16; 356238148Sjfv break; 357238148Sjfv case e1000_nvm_override_spi_small: 358238148Sjfv nvm->page_size = 8; 359238148Sjfv nvm->address_bits = 8; 360238148Sjfv break; 361238148Sjfv default: 362238148Sjfv nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 363238148Sjfv nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 364238148Sjfv 16 : 8; 365238148Sjfv break; 366238148Sjfv } 367238148Sjfv if (nvm->word_size == (1 << 15)) 368238148Sjfv nvm->page_size = 128; 369176667Sjfv 370238148Sjfv nvm->type = e1000_nvm_eeprom_spi; 371238148Sjfv } else { 372238148Sjfv nvm->type = e1000_nvm_flash_hw; 373238148Sjfv } 374247064Sjfv 375219753Sjfv /* Function Pointers */ 376228386Sjfv nvm->ops.acquire = e1000_acquire_nvm_82575; 377228386Sjfv nvm->ops.release = e1000_release_nvm_82575; 378219753Sjfv if (nvm->word_size < (1 << 15)) 379228386Sjfv nvm->ops.read = e1000_read_nvm_eerd; 380219753Sjfv else 381228386Sjfv nvm->ops.read = e1000_read_nvm_spi; 382176667Sjfv 383228386Sjfv nvm->ops.write = e1000_write_nvm_spi; 384228386Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_generic; 385228386Sjfv nvm->ops.update = e1000_update_nvm_checksum_generic; 386228386Sjfv nvm->ops.valid_led_default = e1000_valid_led_default_82575; 387219753Sjfv 388238148Sjfv /* override generic family function pointers for specific descendants */ 389218530Sjfv switch (hw->mac.type) { 390218530Sjfv case e1000_82580: 391218530Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_82580; 392218530Sjfv nvm->ops.update = e1000_update_nvm_checksum_82580; 393218530Sjfv break; 394218530Sjfv case e1000_i350: 395256200Sjfv case e1000_i354: 396218530Sjfv nvm->ops.validate = e1000_validate_nvm_checksum_i350; 397218530Sjfv nvm->ops.update = e1000_update_nvm_checksum_i350; 398218530Sjfv break; 399218530Sjfv default: 400219753Sjfv break; 401218530Sjfv } 402176667Sjfv 403176667Sjfv return E1000_SUCCESS; 404176667Sjfv} 405176667Sjfv 406176667Sjfv/** 407176667Sjfv * e1000_init_mac_params_82575 - Init MAC func ptrs. 408176667Sjfv * @hw: pointer to the HW structure 409176667Sjfv **/ 410176667Sjfvstatic s32 e1000_init_mac_params_82575(struct e1000_hw *hw) 411176667Sjfv{ 412176667Sjfv struct e1000_mac_info *mac = &hw->mac; 413185353Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 414176667Sjfv 415176667Sjfv DEBUGFUNC("e1000_init_mac_params_82575"); 416176667Sjfv 417228386Sjfv /* Derives media type */ 418228386Sjfv e1000_get_media_type_82575(hw); 419176667Sjfv /* Set mta register count */ 420176667Sjfv mac->mta_reg_count = 128; 421200243Sjfv /* Set uta register count */ 422200243Sjfv mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 423176667Sjfv /* Set rar entry count */ 424176667Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 425181027Sjfv if (mac->type == e1000_82576) 426181027Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 427203049Sjfv if (mac->type == e1000_82580) 428200243Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 429256200Sjfv if (mac->type == e1000_i350 || mac->type == e1000_i354) 430218530Sjfv mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 431247064Sjfv 432247064Sjfv /* Enable EEE default settings for EEE supported devices */ 433247064Sjfv if (mac->type >= e1000_i350) 434218530Sjfv dev_spec->eee_disable = FALSE; 435218530Sjfv 436247064Sjfv /* Allow a single clear of the SW semaphore on I210 and newer */ 437247064Sjfv if (mac->type >= e1000_i210) 438247064Sjfv dev_spec->clear_semaphore_once = TRUE; 439247064Sjfv 440176667Sjfv /* Set if part includes ASF firmware */ 441176667Sjfv mac->asf_firmware_present = TRUE; 442205869Sjfv /* FWSM register */ 443205869Sjfv mac->has_fwsm = TRUE; 444205869Sjfv /* ARC supported; valid only if manageability features are enabled. */ 445176667Sjfv mac->arc_subsystem_valid = 446238148Sjfv !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK); 447176667Sjfv 448176667Sjfv /* Function pointers */ 449176667Sjfv 450176667Sjfv /* bus type/speed/width */ 451176667Sjfv mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 452176667Sjfv /* reset */ 453203049Sjfv if (mac->type >= e1000_82580) 454200243Sjfv mac->ops.reset_hw = e1000_reset_hw_82580; 455200243Sjfv else 456176667Sjfv mac->ops.reset_hw = e1000_reset_hw_82575; 457176667Sjfv /* hw initialization */ 458269196Sjfv if ((mac->type == e1000_i210) || (mac->type == e1000_i211)) 459269196Sjfv mac->ops.init_hw = e1000_init_hw_i210; 460269196Sjfv else 461176667Sjfv mac->ops.init_hw = e1000_init_hw_82575; 462176667Sjfv /* link setup */ 463176667Sjfv mac->ops.setup_link = e1000_setup_link_generic; 464176667Sjfv /* physical interface link setup */ 465176667Sjfv mac->ops.setup_physical_interface = 466228386Sjfv (hw->phy.media_type == e1000_media_type_copper) 467228386Sjfv ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575; 468181027Sjfv /* physical interface shutdown */ 469200243Sjfv mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575; 470203049Sjfv /* physical interface power up */ 471203049Sjfv mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575; 472176667Sjfv /* check for link */ 473176667Sjfv mac->ops.check_for_link = e1000_check_for_link_82575; 474176667Sjfv /* read mac address */ 475176667Sjfv mac->ops.read_mac_addr = e1000_read_mac_addr_82575; 476203049Sjfv /* configure collision distance */ 477203049Sjfv mac->ops.config_collision_dist = e1000_config_collision_dist_82575; 478176667Sjfv /* multicast address update */ 479190872Sjfv mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 480256200Sjfv if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) { 481228386Sjfv /* writing VFTA */ 482228386Sjfv mac->ops.write_vfta = e1000_write_vfta_i350; 483228386Sjfv /* clearing VFTA */ 484228386Sjfv mac->ops.clear_vfta = e1000_clear_vfta_i350; 485228386Sjfv } else { 486228386Sjfv /* writing VFTA */ 487228386Sjfv mac->ops.write_vfta = e1000_write_vfta_generic; 488228386Sjfv /* clearing VFTA */ 489228386Sjfv mac->ops.clear_vfta = e1000_clear_vfta_generic; 490228386Sjfv } 491247064Sjfv if (hw->mac.type >= e1000_82580) 492247064Sjfv mac->ops.validate_mdi_setting = 493247064Sjfv e1000_validate_mdi_setting_crossover_generic; 494190872Sjfv /* ID LED init */ 495190872Sjfv mac->ops.id_led_init = e1000_id_led_init_generic; 496176667Sjfv /* blink LED */ 497176667Sjfv mac->ops.blink_led = e1000_blink_led_generic; 498176667Sjfv /* setup LED */ 499176667Sjfv mac->ops.setup_led = e1000_setup_led_generic; 500176667Sjfv /* cleanup LED */ 501176667Sjfv mac->ops.cleanup_led = e1000_cleanup_led_generic; 502176667Sjfv /* turn on/off LED */ 503176667Sjfv mac->ops.led_on = e1000_led_on_generic; 504176667Sjfv mac->ops.led_off = e1000_led_off_generic; 505176667Sjfv /* clear hardware counters */ 506176667Sjfv mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575; 507176667Sjfv /* link info */ 508176667Sjfv mac->ops.get_link_up_info = e1000_get_link_up_info_82575; 509238148Sjfv /* acquire SW_FW sync */ 510238148Sjfv mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575; 511238148Sjfv mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575; 512238148Sjfv if (mac->type >= e1000_i210) { 513238148Sjfv mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210; 514238148Sjfv mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210; 515238148Sjfv } 516176667Sjfv 517200243Sjfv /* set lan id for port to determine which phy lock to use */ 518200243Sjfv hw->mac.ops.set_lan_id(hw); 519200243Sjfv 520185353Sjfv return E1000_SUCCESS; 521176667Sjfv} 522176667Sjfv 523176667Sjfv/** 524176667Sjfv * e1000_init_function_pointers_82575 - Init func ptrs. 525176667Sjfv * @hw: pointer to the HW structure 526176667Sjfv * 527185353Sjfv * Called to initialize all function pointers and parameters. 528176667Sjfv **/ 529176667Sjfvvoid e1000_init_function_pointers_82575(struct e1000_hw *hw) 530176667Sjfv{ 531176667Sjfv DEBUGFUNC("e1000_init_function_pointers_82575"); 532176667Sjfv 533176667Sjfv hw->mac.ops.init_params = e1000_init_mac_params_82575; 534176667Sjfv hw->nvm.ops.init_params = e1000_init_nvm_params_82575; 535176667Sjfv hw->phy.ops.init_params = e1000_init_phy_params_82575; 536213234Sjfv hw->mbx.ops.init_params = e1000_init_mbx_params_pf; 537176667Sjfv} 538176667Sjfv 539176667Sjfv/** 540176667Sjfv * e1000_acquire_phy_82575 - Acquire rights to access PHY 541176667Sjfv * @hw: pointer to the HW structure 542176667Sjfv * 543185353Sjfv * Acquire access rights to the correct PHY. 544176667Sjfv **/ 545176667Sjfvstatic s32 e1000_acquire_phy_82575(struct e1000_hw *hw) 546176667Sjfv{ 547194865Sjfv u16 mask = E1000_SWFW_PHY0_SM; 548176667Sjfv 549176667Sjfv DEBUGFUNC("e1000_acquire_phy_82575"); 550176667Sjfv 551194865Sjfv if (hw->bus.func == E1000_FUNC_1) 552194865Sjfv mask = E1000_SWFW_PHY1_SM; 553200243Sjfv else if (hw->bus.func == E1000_FUNC_2) 554200243Sjfv mask = E1000_SWFW_PHY2_SM; 555200243Sjfv else if (hw->bus.func == E1000_FUNC_3) 556200243Sjfv mask = E1000_SWFW_PHY3_SM; 557176667Sjfv 558238148Sjfv return hw->mac.ops.acquire_swfw_sync(hw, mask); 559176667Sjfv} 560176667Sjfv 561176667Sjfv/** 562176667Sjfv * e1000_release_phy_82575 - Release rights to access PHY 563176667Sjfv * @hw: pointer to the HW structure 564176667Sjfv * 565185353Sjfv * A wrapper to release access rights to the correct PHY. 566176667Sjfv **/ 567176667Sjfvstatic void e1000_release_phy_82575(struct e1000_hw *hw) 568176667Sjfv{ 569194865Sjfv u16 mask = E1000_SWFW_PHY0_SM; 570176667Sjfv 571176667Sjfv DEBUGFUNC("e1000_release_phy_82575"); 572176667Sjfv 573194865Sjfv if (hw->bus.func == E1000_FUNC_1) 574194865Sjfv mask = E1000_SWFW_PHY1_SM; 575200243Sjfv else if (hw->bus.func == E1000_FUNC_2) 576200243Sjfv mask = E1000_SWFW_PHY2_SM; 577200243Sjfv else if (hw->bus.func == E1000_FUNC_3) 578200243Sjfv mask = E1000_SWFW_PHY3_SM; 579194865Sjfv 580238148Sjfv hw->mac.ops.release_swfw_sync(hw, mask); 581176667Sjfv} 582176667Sjfv 583176667Sjfv/** 584176667Sjfv * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 585176667Sjfv * @hw: pointer to the HW structure 586176667Sjfv * @offset: register offset to be read 587176667Sjfv * @data: pointer to the read data 588176667Sjfv * 589176667Sjfv * Reads the PHY register at offset using the serial gigabit media independent 590176667Sjfv * interface and stores the retrieved information in data. 591176667Sjfv **/ 592176667Sjfvstatic s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 593228386Sjfv u16 *data) 594176667Sjfv{ 595200243Sjfv s32 ret_val = -E1000_ERR_PARAM; 596176667Sjfv 597176667Sjfv DEBUGFUNC("e1000_read_phy_reg_sgmii_82575"); 598176667Sjfv 599176667Sjfv if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 600176667Sjfv DEBUGOUT1("PHY Address %u is out of range\n", offset); 601200243Sjfv goto out; 602176667Sjfv } 603176667Sjfv 604200243Sjfv ret_val = hw->phy.ops.acquire(hw); 605200243Sjfv if (ret_val) 606200243Sjfv goto out; 607176667Sjfv 608200243Sjfv ret_val = e1000_read_phy_reg_i2c(hw, offset, data); 609176667Sjfv 610200243Sjfv hw->phy.ops.release(hw); 611176667Sjfv 612200243Sjfvout: 613200243Sjfv return ret_val; 614176667Sjfv} 615176667Sjfv 616176667Sjfv/** 617176667Sjfv * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 618176667Sjfv * @hw: pointer to the HW structure 619176667Sjfv * @offset: register offset to write to 620176667Sjfv * @data: data to write at register offset 621176667Sjfv * 622176667Sjfv * Writes the data to PHY register at the offset using the serial gigabit 623176667Sjfv * media independent interface. 624176667Sjfv **/ 625176667Sjfvstatic s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 626228386Sjfv u16 data) 627176667Sjfv{ 628200243Sjfv s32 ret_val = -E1000_ERR_PARAM; 629176667Sjfv 630176667Sjfv DEBUGFUNC("e1000_write_phy_reg_sgmii_82575"); 631176667Sjfv 632176667Sjfv if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 633176667Sjfv DEBUGOUT1("PHY Address %d is out of range\n", offset); 634200243Sjfv goto out; 635176667Sjfv } 636176667Sjfv 637200243Sjfv ret_val = hw->phy.ops.acquire(hw); 638200243Sjfv if (ret_val) 639200243Sjfv goto out; 640176667Sjfv 641200243Sjfv ret_val = e1000_write_phy_reg_i2c(hw, offset, data); 642176667Sjfv 643200243Sjfv hw->phy.ops.release(hw); 644176667Sjfv 645200243Sjfvout: 646200243Sjfv return ret_val; 647176667Sjfv} 648176667Sjfv 649176667Sjfv/** 650176667Sjfv * e1000_get_phy_id_82575 - Retrieve PHY addr and id 651176667Sjfv * @hw: pointer to the HW structure 652176667Sjfv * 653176667Sjfv * Retrieves the PHY address and ID for both PHY's which do and do not use 654176667Sjfv * sgmi interface. 655176667Sjfv **/ 656176667Sjfvstatic s32 e1000_get_phy_id_82575(struct e1000_hw *hw) 657176667Sjfv{ 658176667Sjfv struct e1000_phy_info *phy = &hw->phy; 659176667Sjfv s32 ret_val = E1000_SUCCESS; 660176667Sjfv u16 phy_id; 661200243Sjfv u32 ctrl_ext; 662213234Sjfv u32 mdic; 663176667Sjfv 664176667Sjfv DEBUGFUNC("e1000_get_phy_id_82575"); 665176667Sjfv 666256200Sjfv /* some i354 devices need an extra read for phy id */ 667256200Sjfv if (hw->mac.type == e1000_i354) 668256200Sjfv e1000_get_phy_id(hw); 669256200Sjfv 670176667Sjfv /* 671176667Sjfv * For SGMII PHYs, we try the list of possible addresses until 672176667Sjfv * we find one that works. For non-SGMII PHYs 673176667Sjfv * (e.g. integrated copper PHYs), an address of 1 should 674176667Sjfv * work. The result of this function should mean phy->phy_addr 675176667Sjfv * and phy->id are set correctly. 676176667Sjfv */ 677200243Sjfv if (!e1000_sgmii_active_82575(hw)) { 678176667Sjfv phy->addr = 1; 679176667Sjfv ret_val = e1000_get_phy_id(hw); 680176667Sjfv goto out; 681176667Sjfv } 682176667Sjfv 683213234Sjfv if (e1000_sgmii_uses_mdio_82575(hw)) { 684213234Sjfv switch (hw->mac.type) { 685213234Sjfv case e1000_82575: 686213234Sjfv case e1000_82576: 687213234Sjfv mdic = E1000_READ_REG(hw, E1000_MDIC); 688213234Sjfv mdic &= E1000_MDIC_PHY_MASK; 689213234Sjfv phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 690213234Sjfv break; 691213234Sjfv case e1000_82580: 692218530Sjfv case e1000_i350: 693256200Sjfv case e1000_i354: 694247064Sjfv case e1000_i210: 695247064Sjfv case e1000_i211: 696213234Sjfv mdic = E1000_READ_REG(hw, E1000_MDICNFG); 697213234Sjfv mdic &= E1000_MDICNFG_PHY_MASK; 698213234Sjfv phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 699213234Sjfv break; 700213234Sjfv default: 701213234Sjfv ret_val = -E1000_ERR_PHY; 702213234Sjfv goto out; 703213234Sjfv break; 704213234Sjfv } 705213234Sjfv ret_val = e1000_get_phy_id(hw); 706213234Sjfv goto out; 707213234Sjfv } 708213234Sjfv 709200243Sjfv /* Power on sgmii phy if it is disabled */ 710200243Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 711200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, 712228386Sjfv ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 713200243Sjfv E1000_WRITE_FLUSH(hw); 714200243Sjfv msec_delay(300); 715200243Sjfv 716176667Sjfv /* 717176667Sjfv * The address field in the I2CCMD register is 3 bits and 0 is invalid. 718176667Sjfv * Therefore, we need to test 1-7 719176667Sjfv */ 720176667Sjfv for (phy->addr = 1; phy->addr < 8; phy->addr++) { 721176667Sjfv ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 722176667Sjfv if (ret_val == E1000_SUCCESS) { 723176667Sjfv DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 724228386Sjfv phy_id, phy->addr); 725176667Sjfv /* 726176667Sjfv * At the time of this writing, The M88 part is 727176667Sjfv * the only supported SGMII PHY product. 728176667Sjfv */ 729176667Sjfv if (phy_id == M88_VENDOR) 730176667Sjfv break; 731176667Sjfv } else { 732176667Sjfv DEBUGOUT1("PHY address %u was unreadable\n", 733228386Sjfv phy->addr); 734176667Sjfv } 735176667Sjfv } 736176667Sjfv 737176667Sjfv /* A valid PHY type couldn't be found. */ 738176667Sjfv if (phy->addr == 8) { 739176667Sjfv phy->addr = 0; 740176667Sjfv ret_val = -E1000_ERR_PHY; 741200243Sjfv } else { 742200243Sjfv ret_val = e1000_get_phy_id(hw); 743176667Sjfv } 744176667Sjfv 745200243Sjfv /* restore previous sfp cage power state */ 746200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 747176667Sjfv 748176667Sjfvout: 749176667Sjfv return ret_val; 750176667Sjfv} 751176667Sjfv 752176667Sjfv/** 753176667Sjfv * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset 754176667Sjfv * @hw: pointer to the HW structure 755176667Sjfv * 756176667Sjfv * Resets the PHY using the serial gigabit media independent interface. 757176667Sjfv **/ 758176667Sjfvstatic s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 759176667Sjfv{ 760176667Sjfv s32 ret_val = E1000_SUCCESS; 761269196Sjfv struct e1000_phy_info *phy = &hw->phy; 762176667Sjfv 763176667Sjfv DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575"); 764176667Sjfv 765176667Sjfv /* 766178523Sjfv * This isn't a TRUE "hard" reset, but is the only reset 767176667Sjfv * available to us at this time. 768176667Sjfv */ 769176667Sjfv 770176667Sjfv DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 771176667Sjfv 772176667Sjfv if (!(hw->phy.ops.write_reg)) 773176667Sjfv goto out; 774176667Sjfv 775176667Sjfv /* 776176667Sjfv * SFP documentation requires the following to configure the SPF module 777176667Sjfv * to work on SGMII. No further documentation is given. 778176667Sjfv */ 779176667Sjfv ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 780176667Sjfv if (ret_val) 781176667Sjfv goto out; 782176667Sjfv 783176667Sjfv ret_val = hw->phy.ops.commit(hw); 784269196Sjfv if (ret_val) 785269196Sjfv goto out; 786176667Sjfv 787269196Sjfv if (phy->id == M88E1512_E_PHY_ID) 788269196Sjfv ret_val = e1000_initialize_M88E1512_phy(hw); 789176667Sjfvout: 790176667Sjfv return ret_val; 791176667Sjfv} 792176667Sjfv 793176667Sjfv/** 794176667Sjfv * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 795176667Sjfv * @hw: pointer to the HW structure 796176667Sjfv * @active: TRUE to enable LPLU, FALSE to disable 797176667Sjfv * 798176667Sjfv * Sets the LPLU D0 state according to the active flag. When 799176667Sjfv * activating LPLU this function also disables smart speed 800176667Sjfv * and vice versa. LPLU will not be activated unless the 801176667Sjfv * device autonegotiation advertisement meets standards of 802176667Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 803176667Sjfv * This is a function pointer entry point only called by 804176667Sjfv * PHY setup routines. 805176667Sjfv **/ 806176667Sjfvstatic s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 807176667Sjfv{ 808176667Sjfv struct e1000_phy_info *phy = &hw->phy; 809176667Sjfv s32 ret_val = E1000_SUCCESS; 810176667Sjfv u16 data; 811176667Sjfv 812176667Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82575"); 813176667Sjfv 814176667Sjfv if (!(hw->phy.ops.read_reg)) 815176667Sjfv goto out; 816176667Sjfv 817176667Sjfv ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 818176667Sjfv if (ret_val) 819176667Sjfv goto out; 820176667Sjfv 821176667Sjfv if (active) { 822176667Sjfv data |= IGP02E1000_PM_D0_LPLU; 823176667Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 824228386Sjfv data); 825176667Sjfv if (ret_val) 826176667Sjfv goto out; 827176667Sjfv 828176667Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 829176667Sjfv ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 830228386Sjfv &data); 831176667Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 832176667Sjfv ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 833228386Sjfv data); 834176667Sjfv if (ret_val) 835176667Sjfv goto out; 836176667Sjfv } else { 837176667Sjfv data &= ~IGP02E1000_PM_D0_LPLU; 838176667Sjfv ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 839228386Sjfv data); 840176667Sjfv /* 841176667Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 842176667Sjfv * during Dx states where the power conservation is most 843176667Sjfv * important. During driver activity we should enable 844176667Sjfv * SmartSpeed, so performance is maintained. 845176667Sjfv */ 846176667Sjfv if (phy->smart_speed == e1000_smart_speed_on) { 847176667Sjfv ret_val = phy->ops.read_reg(hw, 848228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 849228386Sjfv &data); 850176667Sjfv if (ret_val) 851176667Sjfv goto out; 852176667Sjfv 853176667Sjfv data |= IGP01E1000_PSCFR_SMART_SPEED; 854176667Sjfv ret_val = phy->ops.write_reg(hw, 855228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 856228386Sjfv data); 857176667Sjfv if (ret_val) 858176667Sjfv goto out; 859176667Sjfv } else if (phy->smart_speed == e1000_smart_speed_off) { 860176667Sjfv ret_val = phy->ops.read_reg(hw, 861228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 862228386Sjfv &data); 863176667Sjfv if (ret_val) 864176667Sjfv goto out; 865176667Sjfv 866176667Sjfv data &= ~IGP01E1000_PSCFR_SMART_SPEED; 867176667Sjfv ret_val = phy->ops.write_reg(hw, 868228386Sjfv IGP01E1000_PHY_PORT_CONFIG, 869228386Sjfv data); 870176667Sjfv if (ret_val) 871176667Sjfv goto out; 872176667Sjfv } 873176667Sjfv } 874176667Sjfv 875176667Sjfvout: 876176667Sjfv return ret_val; 877176667Sjfv} 878176667Sjfv 879176667Sjfv/** 880218530Sjfv * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 881218530Sjfv * @hw: pointer to the HW structure 882218530Sjfv * @active: TRUE to enable LPLU, FALSE to disable 883218530Sjfv * 884218530Sjfv * Sets the LPLU D0 state according to the active flag. When 885218530Sjfv * activating LPLU this function also disables smart speed 886218530Sjfv * and vice versa. LPLU will not be activated unless the 887218530Sjfv * device autonegotiation advertisement meets standards of 888218530Sjfv * either 10 or 10/100 or 10/100/1000 at all duplexes. 889218530Sjfv * This is a function pointer entry point only called by 890218530Sjfv * PHY setup routines. 891218530Sjfv **/ 892218530Sjfvstatic s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 893218530Sjfv{ 894218530Sjfv struct e1000_phy_info *phy = &hw->phy; 895238148Sjfv u32 data; 896218530Sjfv 897218530Sjfv DEBUGFUNC("e1000_set_d0_lplu_state_82580"); 898218530Sjfv 899218530Sjfv data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 900218530Sjfv 901218530Sjfv if (active) { 902218530Sjfv data |= E1000_82580_PM_D0_LPLU; 903218530Sjfv 904218530Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 905218530Sjfv data &= ~E1000_82580_PM_SPD; 906218530Sjfv } else { 907218530Sjfv data &= ~E1000_82580_PM_D0_LPLU; 908218530Sjfv 909218530Sjfv /* 910218530Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 911218530Sjfv * during Dx states where the power conservation is most 912218530Sjfv * important. During driver activity we should enable 913218530Sjfv * SmartSpeed, so performance is maintained. 914218530Sjfv */ 915228386Sjfv if (phy->smart_speed == e1000_smart_speed_on) 916218530Sjfv data |= E1000_82580_PM_SPD; 917228386Sjfv else if (phy->smart_speed == e1000_smart_speed_off) 918218530Sjfv data &= ~E1000_82580_PM_SPD; 919218530Sjfv } 920218530Sjfv 921218530Sjfv E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 922269196Sjfv return E1000_SUCCESS; 923218530Sjfv} 924218530Sjfv 925218530Sjfv/** 926218530Sjfv * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3 927218530Sjfv * @hw: pointer to the HW structure 928218530Sjfv * @active: boolean used to enable/disable lplu 929218530Sjfv * 930218530Sjfv * Success returns 0, Failure returns 1 931218530Sjfv * 932218530Sjfv * The low power link up (lplu) state is set to the power management level D3 933218530Sjfv * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 934218530Sjfv * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 935218530Sjfv * is used during Dx states where the power conservation is most important. 936218530Sjfv * During driver activity, SmartSpeed should be enabled so performance is 937218530Sjfv * maintained. 938218530Sjfv **/ 939218530Sjfvs32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 940218530Sjfv{ 941218530Sjfv struct e1000_phy_info *phy = &hw->phy; 942238148Sjfv u32 data; 943218530Sjfv 944218530Sjfv DEBUGFUNC("e1000_set_d3_lplu_state_82580"); 945218530Sjfv 946218530Sjfv data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 947218530Sjfv 948218530Sjfv if (!active) { 949218530Sjfv data &= ~E1000_82580_PM_D3_LPLU; 950218530Sjfv /* 951218530Sjfv * LPLU and SmartSpeed are mutually exclusive. LPLU is used 952218530Sjfv * during Dx states where the power conservation is most 953218530Sjfv * important. During driver activity we should enable 954218530Sjfv * SmartSpeed, so performance is maintained. 955218530Sjfv */ 956228386Sjfv if (phy->smart_speed == e1000_smart_speed_on) 957218530Sjfv data |= E1000_82580_PM_SPD; 958228386Sjfv else if (phy->smart_speed == e1000_smart_speed_off) 959218530Sjfv data &= ~E1000_82580_PM_SPD; 960218530Sjfv } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 961228386Sjfv (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 962228386Sjfv (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 963218530Sjfv data |= E1000_82580_PM_D3_LPLU; 964218530Sjfv /* When LPLU is enabled, we should disable SmartSpeed */ 965218530Sjfv data &= ~E1000_82580_PM_SPD; 966218530Sjfv } 967218530Sjfv 968218530Sjfv E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data); 969269196Sjfv return E1000_SUCCESS; 970218530Sjfv} 971218530Sjfv 972218530Sjfv/** 973176667Sjfv * e1000_acquire_nvm_82575 - Request for access to EEPROM 974176667Sjfv * @hw: pointer to the HW structure 975176667Sjfv * 976176667Sjfv * Acquire the necessary semaphores for exclusive access to the EEPROM. 977176667Sjfv * Set the EEPROM access request bit and wait for EEPROM access grant bit. 978176667Sjfv * Return successful if access grant bit set, else clear the request for 979176667Sjfv * EEPROM access and return -E1000_ERR_NVM (-1). 980176667Sjfv **/ 981176667Sjfvstatic s32 e1000_acquire_nvm_82575(struct e1000_hw *hw) 982176667Sjfv{ 983269196Sjfv s32 ret_val = E1000_SUCCESS; 984176667Sjfv 985176667Sjfv DEBUGFUNC("e1000_acquire_nvm_82575"); 986176667Sjfv 987176667Sjfv ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 988176667Sjfv if (ret_val) 989176667Sjfv goto out; 990228386Sjfv 991228386Sjfv /* 992228386Sjfv * Check if there is some access 993228386Sjfv * error this access may hook on 994228386Sjfv */ 995228386Sjfv if (hw->mac.type == e1000_i350) { 996228386Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 997228386Sjfv if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT | 998228386Sjfv E1000_EECD_TIMEOUT)) { 999228386Sjfv /* Clear all access error flags */ 1000228386Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd | 1001228386Sjfv E1000_EECD_ERROR_CLR); 1002228386Sjfv DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 1003228386Sjfv } 1004228386Sjfv } 1005269196Sjfv 1006228386Sjfv if (hw->mac.type == e1000_82580) { 1007228386Sjfv u32 eecd = E1000_READ_REG(hw, E1000_EECD); 1008228386Sjfv if (eecd & E1000_EECD_BLOCKED) { 1009228386Sjfv /* Clear access error flag */ 1010228386Sjfv E1000_WRITE_REG(hw, E1000_EECD, eecd | 1011228386Sjfv E1000_EECD_BLOCKED); 1012228386Sjfv DEBUGOUT("Nvm bit banging access error detected and cleared.\n"); 1013228386Sjfv } 1014228386Sjfv } 1015228386Sjfv 1016238148Sjfv ret_val = e1000_acquire_nvm_generic(hw); 1017176667Sjfv if (ret_val) 1018176667Sjfv e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 1019176667Sjfv 1020176667Sjfvout: 1021176667Sjfv return ret_val; 1022176667Sjfv} 1023176667Sjfv 1024176667Sjfv/** 1025176667Sjfv * e1000_release_nvm_82575 - Release exclusive access to EEPROM 1026176667Sjfv * @hw: pointer to the HW structure 1027176667Sjfv * 1028176667Sjfv * Stop any current commands to the EEPROM and clear the EEPROM request bit, 1029176667Sjfv * then release the semaphores acquired. 1030176667Sjfv **/ 1031176667Sjfvstatic void e1000_release_nvm_82575(struct e1000_hw *hw) 1032176667Sjfv{ 1033176667Sjfv DEBUGFUNC("e1000_release_nvm_82575"); 1034176667Sjfv 1035238148Sjfv e1000_release_nvm_generic(hw); 1036238148Sjfv 1037176667Sjfv e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 1038176667Sjfv} 1039176667Sjfv 1040176667Sjfv/** 1041176667Sjfv * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1042176667Sjfv * @hw: pointer to the HW structure 1043176667Sjfv * @mask: specifies which semaphore to acquire 1044176667Sjfv * 1045176667Sjfv * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1046176667Sjfv * will also specify which port we're acquiring the lock for. 1047176667Sjfv **/ 1048176667Sjfvstatic s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1049176667Sjfv{ 1050176667Sjfv u32 swfw_sync; 1051176667Sjfv u32 swmask = mask; 1052176667Sjfv u32 fwmask = mask << 16; 1053176667Sjfv s32 ret_val = E1000_SUCCESS; 1054176667Sjfv s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 1055176667Sjfv 1056176667Sjfv DEBUGFUNC("e1000_acquire_swfw_sync_82575"); 1057176667Sjfv 1058176667Sjfv while (i < timeout) { 1059176667Sjfv if (e1000_get_hw_semaphore_generic(hw)) { 1060176667Sjfv ret_val = -E1000_ERR_SWFW_SYNC; 1061176667Sjfv goto out; 1062176667Sjfv } 1063176667Sjfv 1064176667Sjfv swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1065176667Sjfv if (!(swfw_sync & (fwmask | swmask))) 1066176667Sjfv break; 1067176667Sjfv 1068176667Sjfv /* 1069176667Sjfv * Firmware currently using resource (fwmask) 1070176667Sjfv * or other software thread using resource (swmask) 1071176667Sjfv */ 1072176667Sjfv e1000_put_hw_semaphore_generic(hw); 1073176667Sjfv msec_delay_irq(5); 1074176667Sjfv i++; 1075176667Sjfv } 1076176667Sjfv 1077176667Sjfv if (i == timeout) { 1078176667Sjfv DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1079176667Sjfv ret_val = -E1000_ERR_SWFW_SYNC; 1080176667Sjfv goto out; 1081176667Sjfv } 1082176667Sjfv 1083176667Sjfv swfw_sync |= swmask; 1084176667Sjfv E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1085176667Sjfv 1086176667Sjfv e1000_put_hw_semaphore_generic(hw); 1087176667Sjfv 1088176667Sjfvout: 1089176667Sjfv return ret_val; 1090176667Sjfv} 1091176667Sjfv 1092176667Sjfv/** 1093176667Sjfv * e1000_release_swfw_sync_82575 - Release SW/FW semaphore 1094176667Sjfv * @hw: pointer to the HW structure 1095176667Sjfv * @mask: specifies which semaphore to acquire 1096176667Sjfv * 1097176667Sjfv * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1098176667Sjfv * will also specify which port we're releasing the lock for. 1099176667Sjfv **/ 1100176667Sjfvstatic void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1101176667Sjfv{ 1102176667Sjfv u32 swfw_sync; 1103176667Sjfv 1104176667Sjfv DEBUGFUNC("e1000_release_swfw_sync_82575"); 1105176667Sjfv 1106228386Sjfv while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 1107228386Sjfv ; /* Empty */ 1108176667Sjfv 1109176667Sjfv swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 1110176667Sjfv swfw_sync &= ~mask; 1111176667Sjfv E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 1112176667Sjfv 1113176667Sjfv e1000_put_hw_semaphore_generic(hw); 1114176667Sjfv} 1115176667Sjfv 1116176667Sjfv/** 1117176667Sjfv * e1000_get_cfg_done_82575 - Read config done bit 1118176667Sjfv * @hw: pointer to the HW structure 1119176667Sjfv * 1120176667Sjfv * Read the management control register for the config done bit for 1121176667Sjfv * completion status. NOTE: silicon which is EEPROM-less will fail trying 1122176667Sjfv * to read the config done bit, so an error is *ONLY* logged and returns 1123176667Sjfv * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon 1124176667Sjfv * would not be able to be reset or change link. 1125176667Sjfv **/ 1126176667Sjfvstatic s32 e1000_get_cfg_done_82575(struct e1000_hw *hw) 1127176667Sjfv{ 1128176667Sjfv s32 timeout = PHY_CFG_TIMEOUT; 1129176667Sjfv u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1130176667Sjfv 1131176667Sjfv DEBUGFUNC("e1000_get_cfg_done_82575"); 1132176667Sjfv 1133194865Sjfv if (hw->bus.func == E1000_FUNC_1) 1134176667Sjfv mask = E1000_NVM_CFG_DONE_PORT_1; 1135200243Sjfv else if (hw->bus.func == E1000_FUNC_2) 1136200243Sjfv mask = E1000_NVM_CFG_DONE_PORT_2; 1137200243Sjfv else if (hw->bus.func == E1000_FUNC_3) 1138200243Sjfv mask = E1000_NVM_CFG_DONE_PORT_3; 1139176667Sjfv while (timeout) { 1140176667Sjfv if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 1141176667Sjfv break; 1142176667Sjfv msec_delay(1); 1143176667Sjfv timeout--; 1144176667Sjfv } 1145200243Sjfv if (!timeout) 1146176667Sjfv DEBUGOUT("MNG configuration cycle has not completed.\n"); 1147176667Sjfv 1148176667Sjfv /* If EEPROM is not marked present, init the PHY manually */ 1149238148Sjfv if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) && 1150200243Sjfv (hw->phy.type == e1000_phy_igp_3)) 1151176667Sjfv e1000_phy_init_script_igp3(hw); 1152176667Sjfv 1153269196Sjfv return E1000_SUCCESS; 1154176667Sjfv} 1155176667Sjfv 1156176667Sjfv/** 1157176667Sjfv * e1000_get_link_up_info_82575 - Get link speed/duplex info 1158176667Sjfv * @hw: pointer to the HW structure 1159176667Sjfv * @speed: stores the current speed 1160176667Sjfv * @duplex: stores the current duplex 1161176667Sjfv * 1162176667Sjfv * This is a wrapper function, if using the serial gigabit media independent 1163176667Sjfv * interface, use PCS to retrieve the link speed and duplex information. 1164176667Sjfv * Otherwise, use the generic function to get the link speed and duplex info. 1165176667Sjfv **/ 1166176667Sjfvstatic s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1167228386Sjfv u16 *duplex) 1168176667Sjfv{ 1169176667Sjfv s32 ret_val; 1170176667Sjfv 1171176667Sjfv DEBUGFUNC("e1000_get_link_up_info_82575"); 1172176667Sjfv 1173200243Sjfv if (hw->phy.media_type != e1000_media_type_copper) 1174176667Sjfv ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed, 1175228386Sjfv duplex); 1176200243Sjfv else 1177176667Sjfv ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 1178228386Sjfv duplex); 1179176667Sjfv 1180176667Sjfv return ret_val; 1181176667Sjfv} 1182176667Sjfv 1183176667Sjfv/** 1184176667Sjfv * e1000_check_for_link_82575 - Check for link 1185176667Sjfv * @hw: pointer to the HW structure 1186176667Sjfv * 1187176667Sjfv * If sgmii is enabled, then use the pcs register to determine link, otherwise 1188176667Sjfv * use the generic interface for determining link. 1189176667Sjfv **/ 1190176667Sjfvstatic s32 e1000_check_for_link_82575(struct e1000_hw *hw) 1191176667Sjfv{ 1192176667Sjfv s32 ret_val; 1193176667Sjfv u16 speed, duplex; 1194176667Sjfv 1195176667Sjfv DEBUGFUNC("e1000_check_for_link_82575"); 1196176667Sjfv 1197200243Sjfv if (hw->phy.media_type != e1000_media_type_copper) { 1198176667Sjfv ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed, 1199228386Sjfv &duplex); 1200190872Sjfv /* 1201190872Sjfv * Use this flag to determine if link needs to be checked or 1202190872Sjfv * not. If we have link clear the flag so that we do not 1203190872Sjfv * continue to check for link. 1204190872Sjfv */ 1205190872Sjfv hw->mac.get_link_status = !hw->mac.serdes_has_link; 1206238148Sjfv 1207247064Sjfv /* 1208247064Sjfv * Configure Flow Control now that Auto-Neg has completed. 1209247064Sjfv * First, we need to restore the desired flow control 1210247064Sjfv * settings because we may have had to re-autoneg with a 1211247064Sjfv * different link partner. 1212247064Sjfv */ 1213247064Sjfv ret_val = e1000_config_fc_after_link_up_generic(hw); 1214247064Sjfv if (ret_val) 1215247064Sjfv DEBUGOUT("Error configuring flow control\n"); 1216190872Sjfv } else { 1217176667Sjfv ret_val = e1000_check_for_copper_link_generic(hw); 1218190872Sjfv } 1219176667Sjfv 1220176667Sjfv return ret_val; 1221176667Sjfv} 1222176667Sjfv 1223176667Sjfv/** 1224256200Sjfv * e1000_check_for_link_media_swap - Check which M88E1112 interface linked 1225256200Sjfv * @hw: pointer to the HW structure 1226256200Sjfv * 1227256200Sjfv * Poll the M88E1112 interfaces to see which interface achieved link. 1228256200Sjfv */ 1229256200Sjfvstatic s32 e1000_check_for_link_media_swap(struct e1000_hw *hw) 1230256200Sjfv{ 1231256200Sjfv struct e1000_phy_info *phy = &hw->phy; 1232256200Sjfv s32 ret_val; 1233256200Sjfv u16 data; 1234256200Sjfv u8 port = 0; 1235256200Sjfv 1236256200Sjfv DEBUGFUNC("e1000_check_for_link_media_swap"); 1237256200Sjfv 1238256200Sjfv /* Check the copper medium. */ 1239256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1240256200Sjfv if (ret_val) 1241256200Sjfv return ret_val; 1242256200Sjfv 1243256200Sjfv ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 1244256200Sjfv if (ret_val) 1245256200Sjfv return ret_val; 1246256200Sjfv 1247256200Sjfv if (data & E1000_M88E1112_STATUS_LINK) 1248256200Sjfv port = E1000_MEDIA_PORT_COPPER; 1249256200Sjfv 1250256200Sjfv /* Check the other medium. */ 1251256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 1252256200Sjfv if (ret_val) 1253256200Sjfv return ret_val; 1254256200Sjfv 1255256200Sjfv ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 1256256200Sjfv if (ret_val) 1257256200Sjfv return ret_val; 1258256200Sjfv 1259256200Sjfv /* reset page to 0 */ 1260256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 1261256200Sjfv if (ret_val) 1262256200Sjfv return ret_val; 1263256200Sjfv 1264256200Sjfv if (data & E1000_M88E1112_STATUS_LINK) 1265256200Sjfv port = E1000_MEDIA_PORT_OTHER; 1266256200Sjfv 1267256200Sjfv /* Determine if a swap needs to happen. */ 1268256200Sjfv if (port && (hw->dev_spec._82575.media_port != port)) { 1269256200Sjfv hw->dev_spec._82575.media_port = port; 1270256200Sjfv hw->dev_spec._82575.media_changed = TRUE; 1271256200Sjfv } else { 1272256200Sjfv ret_val = e1000_check_for_link_82575(hw); 1273256200Sjfv } 1274256200Sjfv 1275256200Sjfv return E1000_SUCCESS; 1276256200Sjfv} 1277256200Sjfv 1278256200Sjfv/** 1279203049Sjfv * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1280203049Sjfv * @hw: pointer to the HW structure 1281203049Sjfv **/ 1282203049Sjfvstatic void e1000_power_up_serdes_link_82575(struct e1000_hw *hw) 1283203049Sjfv{ 1284203049Sjfv u32 reg; 1285203049Sjfv 1286203049Sjfv DEBUGFUNC("e1000_power_up_serdes_link_82575"); 1287203049Sjfv 1288203049Sjfv if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1289203049Sjfv !e1000_sgmii_active_82575(hw)) 1290203049Sjfv return; 1291203049Sjfv 1292203049Sjfv /* Enable PCS to turn on link */ 1293203049Sjfv reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1294203049Sjfv reg |= E1000_PCS_CFG_PCS_EN; 1295203049Sjfv E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1296203049Sjfv 1297203049Sjfv /* Power up the laser */ 1298203049Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1299203049Sjfv reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1300203049Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1301203049Sjfv 1302203049Sjfv /* flush the write to verify completion */ 1303203049Sjfv E1000_WRITE_FLUSH(hw); 1304203049Sjfv msec_delay(1); 1305203049Sjfv} 1306203049Sjfv 1307203049Sjfv/** 1308176667Sjfv * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1309176667Sjfv * @hw: pointer to the HW structure 1310176667Sjfv * @speed: stores the current speed 1311176667Sjfv * @duplex: stores the current duplex 1312176667Sjfv * 1313176667Sjfv * Using the physical coding sub-layer (PCS), retrieve the current speed and 1314176667Sjfv * duplex, then store the values in the pointers provided. 1315176667Sjfv **/ 1316176667Sjfvstatic s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, 1317228386Sjfv u16 *speed, u16 *duplex) 1318176667Sjfv{ 1319176667Sjfv struct e1000_mac_info *mac = &hw->mac; 1320176667Sjfv u32 pcs; 1321256200Sjfv u32 status; 1322176667Sjfv 1323176667Sjfv DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575"); 1324176667Sjfv 1325176667Sjfv /* 1326176667Sjfv * Read the PCS Status register for link state. For non-copper mode, 1327176667Sjfv * the status register is not accurate. The PCS status register is 1328176667Sjfv * used instead. 1329176667Sjfv */ 1330176667Sjfv pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 1331176667Sjfv 1332176667Sjfv /* 1333238148Sjfv * The link up bit determines when link is up on autoneg. 1334176667Sjfv */ 1335238148Sjfv if (pcs & E1000_PCS_LSTS_LINK_OK) { 1336176667Sjfv mac->serdes_has_link = TRUE; 1337176667Sjfv 1338176667Sjfv /* Detect and store PCS speed */ 1339228386Sjfv if (pcs & E1000_PCS_LSTS_SPEED_1000) 1340176667Sjfv *speed = SPEED_1000; 1341228386Sjfv else if (pcs & E1000_PCS_LSTS_SPEED_100) 1342176667Sjfv *speed = SPEED_100; 1343228386Sjfv else 1344176667Sjfv *speed = SPEED_10; 1345176667Sjfv 1346176667Sjfv /* Detect and store PCS duplex */ 1347228386Sjfv if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1348176667Sjfv *duplex = FULL_DUPLEX; 1349228386Sjfv else 1350176667Sjfv *duplex = HALF_DUPLEX; 1351247064Sjfv 1352256200Sjfv /* Check if it is an I354 2.5Gb backplane connection. */ 1353256200Sjfv if (mac->type == e1000_i354) { 1354256200Sjfv status = E1000_READ_REG(hw, E1000_STATUS); 1355256200Sjfv if ((status & E1000_STATUS_2P5_SKU) && 1356256200Sjfv !(status & E1000_STATUS_2P5_SKU_OVER)) { 1357256200Sjfv *speed = SPEED_2500; 1358256200Sjfv *duplex = FULL_DUPLEX; 1359256200Sjfv DEBUGOUT("2500 Mbs, "); 1360256200Sjfv DEBUGOUT("Full Duplex\n"); 1361256200Sjfv } 1362256200Sjfv } 1363256200Sjfv 1364238148Sjfv } else { 1365238148Sjfv mac->serdes_has_link = FALSE; 1366238148Sjfv *speed = 0; 1367238148Sjfv *duplex = 0; 1368176667Sjfv } 1369176667Sjfv 1370176667Sjfv return E1000_SUCCESS; 1371176667Sjfv} 1372176667Sjfv 1373176667Sjfv/** 1374200243Sjfv * e1000_shutdown_serdes_link_82575 - Remove link during power down 1375181027Sjfv * @hw: pointer to the HW structure 1376181027Sjfv * 1377200243Sjfv * In the case of serdes shut down sfp and PCS on driver unload 1378181027Sjfv * when management pass thru is not enabled. 1379181027Sjfv **/ 1380200243Sjfvvoid e1000_shutdown_serdes_link_82575(struct e1000_hw *hw) 1381181027Sjfv{ 1382181027Sjfv u32 reg; 1383181027Sjfv 1384203049Sjfv DEBUGFUNC("e1000_shutdown_serdes_link_82575"); 1385203049Sjfv 1386200243Sjfv if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1387200243Sjfv !e1000_sgmii_active_82575(hw)) 1388181027Sjfv return; 1389181027Sjfv 1390203049Sjfv if (!e1000_enable_mng_pass_thru(hw)) { 1391181027Sjfv /* Disable PCS to turn off link */ 1392181027Sjfv reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 1393181027Sjfv reg &= ~E1000_PCS_CFG_PCS_EN; 1394181027Sjfv E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 1395181027Sjfv 1396181027Sjfv /* shutdown the laser */ 1397181027Sjfv reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1398200243Sjfv reg |= E1000_CTRL_EXT_SDP3_DATA; 1399181027Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1400181027Sjfv 1401200243Sjfv /* flush the write to verify completion */ 1402181027Sjfv E1000_WRITE_FLUSH(hw); 1403181027Sjfv msec_delay(1); 1404181027Sjfv } 1405181027Sjfv 1406181027Sjfv return; 1407181027Sjfv} 1408181027Sjfv 1409181027Sjfv/** 1410176667Sjfv * e1000_reset_hw_82575 - Reset hardware 1411176667Sjfv * @hw: pointer to the HW structure 1412176667Sjfv * 1413185353Sjfv * This resets the hardware into a known state. 1414176667Sjfv **/ 1415176667Sjfvstatic s32 e1000_reset_hw_82575(struct e1000_hw *hw) 1416176667Sjfv{ 1417218530Sjfv u32 ctrl; 1418176667Sjfv s32 ret_val; 1419176667Sjfv 1420176667Sjfv DEBUGFUNC("e1000_reset_hw_82575"); 1421176667Sjfv 1422176667Sjfv /* 1423176667Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 1424176667Sjfv * on the last TLP read/write transaction when MAC is reset. 1425176667Sjfv */ 1426176667Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 1427228386Sjfv if (ret_val) 1428176667Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 1429176667Sjfv 1430194865Sjfv /* set the completion timeout for interface */ 1431194865Sjfv ret_val = e1000_set_pcie_completion_timeout(hw); 1432228386Sjfv if (ret_val) 1433194865Sjfv DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 1434194865Sjfv 1435176667Sjfv DEBUGOUT("Masking off all interrupts\n"); 1436176667Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1437176667Sjfv 1438176667Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 1439176667Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 1440176667Sjfv E1000_WRITE_FLUSH(hw); 1441176667Sjfv 1442176667Sjfv msec_delay(10); 1443176667Sjfv 1444176667Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1445176667Sjfv 1446176667Sjfv DEBUGOUT("Issuing a global reset to MAC\n"); 1447176667Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 1448176667Sjfv 1449176667Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 1450176667Sjfv if (ret_val) { 1451176667Sjfv /* 1452176667Sjfv * When auto config read does not complete, do not 1453176667Sjfv * return with an error. This can happen in situations 1454176667Sjfv * where there is no eeprom and prevents getting link. 1455176667Sjfv */ 1456176667Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 1457176667Sjfv } 1458176667Sjfv 1459176667Sjfv /* If EEPROM is not present, run manual init scripts */ 1460238148Sjfv if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES)) 1461176667Sjfv e1000_reset_init_script_82575(hw); 1462176667Sjfv 1463176667Sjfv /* Clear any pending interrupt events. */ 1464176667Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 1465218530Sjfv E1000_READ_REG(hw, E1000_ICR); 1466176667Sjfv 1467190872Sjfv /* Install any alternate MAC address into RAR0 */ 1468190872Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 1469176667Sjfv 1470176667Sjfv return ret_val; 1471176667Sjfv} 1472176667Sjfv 1473176667Sjfv/** 1474176667Sjfv * e1000_init_hw_82575 - Initialize hardware 1475176667Sjfv * @hw: pointer to the HW structure 1476176667Sjfv * 1477176667Sjfv * This inits the hardware readying it for operation. 1478176667Sjfv **/ 1479269196Sjfvs32 e1000_init_hw_82575(struct e1000_hw *hw) 1480176667Sjfv{ 1481176667Sjfv struct e1000_mac_info *mac = &hw->mac; 1482176667Sjfv s32 ret_val; 1483176667Sjfv u16 i, rar_count = mac->rar_entry_count; 1484176667Sjfv 1485176667Sjfv DEBUGFUNC("e1000_init_hw_82575"); 1486176667Sjfv 1487176667Sjfv /* Initialize identification LED */ 1488190872Sjfv ret_val = mac->ops.id_led_init(hw); 1489176667Sjfv if (ret_val) { 1490176667Sjfv DEBUGOUT("Error initializing identification LED\n"); 1491176667Sjfv /* This is not fatal and we should not stop init due to this */ 1492176667Sjfv } 1493176667Sjfv 1494176667Sjfv /* Disabling VLAN filtering */ 1495176667Sjfv DEBUGOUT("Initializing the IEEE VLAN\n"); 1496176667Sjfv mac->ops.clear_vfta(hw); 1497176667Sjfv 1498176667Sjfv /* Setup the receive address */ 1499190872Sjfv e1000_init_rx_addrs_generic(hw, rar_count); 1500190872Sjfv 1501176667Sjfv /* Zero out the Multicast HASH table */ 1502176667Sjfv DEBUGOUT("Zeroing the MTA\n"); 1503176667Sjfv for (i = 0; i < mac->mta_reg_count; i++) 1504176667Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 1505176667Sjfv 1506200243Sjfv /* Zero out the Unicast HASH table */ 1507200243Sjfv DEBUGOUT("Zeroing the UTA\n"); 1508200243Sjfv for (i = 0; i < mac->uta_reg_count; i++) 1509200243Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 1510200243Sjfv 1511176667Sjfv /* Setup link and flow control */ 1512176667Sjfv ret_val = mac->ops.setup_link(hw); 1513176667Sjfv 1514228386Sjfv /* Set the default MTU size */ 1515228386Sjfv hw->dev_spec._82575.mtu = 1500; 1516228386Sjfv 1517176667Sjfv /* 1518176667Sjfv * Clear all of the statistics registers (clear on read). It is 1519176667Sjfv * important that we do this after we have tried to establish link 1520176667Sjfv * because the symbol error count will increment wildly if there 1521176667Sjfv * is no link. 1522176667Sjfv */ 1523176667Sjfv e1000_clear_hw_cntrs_82575(hw); 1524176667Sjfv 1525176667Sjfv return ret_val; 1526176667Sjfv} 1527176667Sjfv 1528176667Sjfv/** 1529176667Sjfv * e1000_setup_copper_link_82575 - Configure copper link settings 1530176667Sjfv * @hw: pointer to the HW structure 1531176667Sjfv * 1532176667Sjfv * Configures the link for auto-neg or forced speed and duplex. Then we check 1533176667Sjfv * for link, once link is established calls to configure collision distance 1534176667Sjfv * and flow control are called. 1535176667Sjfv **/ 1536176667Sjfvstatic s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) 1537176667Sjfv{ 1538194865Sjfv u32 ctrl; 1539247064Sjfv s32 ret_val; 1540247064Sjfv u32 phpm_reg; 1541176667Sjfv 1542176667Sjfv DEBUGFUNC("e1000_setup_copper_link_82575"); 1543176667Sjfv 1544176667Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 1545176667Sjfv ctrl |= E1000_CTRL_SLU; 1546176667Sjfv ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1547176667Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1548176667Sjfv 1549256200Sjfv /* Clear Go Link Disconnect bit on supported devices */ 1550256200Sjfv switch (hw->mac.type) { 1551256200Sjfv case e1000_82580: 1552256200Sjfv case e1000_i350: 1553256200Sjfv case e1000_i210: 1554256200Sjfv case e1000_i211: 1555247064Sjfv phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT); 1556247064Sjfv phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1557247064Sjfv E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg); 1558256200Sjfv break; 1559256200Sjfv default: 1560256200Sjfv break; 1561247064Sjfv } 1562247064Sjfv 1563200243Sjfv ret_val = e1000_setup_serdes_link_82575(hw); 1564200243Sjfv if (ret_val) 1565200243Sjfv goto out; 1566200243Sjfv 1567228386Sjfv if (e1000_sgmii_active_82575(hw)) { 1568200243Sjfv /* allow time for SFP cage time to power up phy */ 1569200243Sjfv msec_delay(300); 1570200243Sjfv 1571200243Sjfv ret_val = hw->phy.ops.reset(hw); 1572200243Sjfv if (ret_val) { 1573200243Sjfv DEBUGOUT("Error resetting the PHY.\n"); 1574200243Sjfv goto out; 1575200243Sjfv } 1576200243Sjfv } 1577176667Sjfv switch (hw->phy.type) { 1578238148Sjfv case e1000_phy_i210: 1579176667Sjfv case e1000_phy_m88: 1580247064Sjfv switch (hw->phy.id) { 1581247064Sjfv case I347AT4_E_PHY_ID: 1582247064Sjfv case M88E1112_E_PHY_ID: 1583247064Sjfv case M88E1340M_E_PHY_ID: 1584256200Sjfv case M88E1543_E_PHY_ID: 1585256200Sjfv case M88E1512_E_PHY_ID: 1586247064Sjfv case I210_I_PHY_ID: 1587218530Sjfv ret_val = e1000_copper_link_setup_m88_gen2(hw); 1588247064Sjfv break; 1589247064Sjfv default: 1590218530Sjfv ret_val = e1000_copper_link_setup_m88(hw); 1591247064Sjfv break; 1592247064Sjfv } 1593176667Sjfv break; 1594176667Sjfv case e1000_phy_igp_3: 1595176667Sjfv ret_val = e1000_copper_link_setup_igp(hw); 1596176667Sjfv break; 1597200243Sjfv case e1000_phy_82580: 1598200243Sjfv ret_val = e1000_copper_link_setup_82577(hw); 1599200243Sjfv break; 1600176667Sjfv default: 1601176667Sjfv ret_val = -E1000_ERR_PHY; 1602176667Sjfv break; 1603176667Sjfv } 1604176667Sjfv 1605176667Sjfv if (ret_val) 1606176667Sjfv goto out; 1607176667Sjfv 1608200243Sjfv ret_val = e1000_setup_copper_link_generic(hw); 1609176667Sjfvout: 1610176667Sjfv return ret_val; 1611176667Sjfv} 1612176667Sjfv 1613176667Sjfv/** 1614200243Sjfv * e1000_setup_serdes_link_82575 - Setup link for serdes 1615176667Sjfv * @hw: pointer to the HW structure 1616176667Sjfv * 1617200243Sjfv * Configure the physical coding sub-layer (PCS) link. The PCS link is 1618200243Sjfv * used on copper connections where the serialized gigabit media independent 1619200243Sjfv * interface (sgmii), or serdes fiber is being used. Configures the link 1620200243Sjfv * for auto-negotiation or forces speed/duplex. 1621176667Sjfv **/ 1622200243Sjfvstatic s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) 1623176667Sjfv{ 1624247064Sjfv u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1625200243Sjfv bool pcs_autoneg; 1626228386Sjfv s32 ret_val = E1000_SUCCESS; 1627228386Sjfv u16 data; 1628176667Sjfv 1629200243Sjfv DEBUGFUNC("e1000_setup_serdes_link_82575"); 1630176667Sjfv 1631200243Sjfv if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1632200243Sjfv !e1000_sgmii_active_82575(hw)) 1633228386Sjfv return ret_val; 1634200243Sjfv 1635176667Sjfv /* 1636176667Sjfv * On the 82575, SerDes loopback mode persists until it is 1637176667Sjfv * explicitly turned off or a power cycle is performed. A read to 1638176667Sjfv * the register does not indicate its status. Therefore, we ensure 1639176667Sjfv * loopback mode is disabled during initialization. 1640176667Sjfv */ 1641176667Sjfv E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1642176667Sjfv 1643200243Sjfv /* power on the sfp cage if present */ 1644200243Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1645200243Sjfv ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1646200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1647200243Sjfv 1648200243Sjfv ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 1649200243Sjfv ctrl_reg |= E1000_CTRL_SLU; 1650200243Sjfv 1651203049Sjfv /* set both sw defined pins on 82575/82576*/ 1652203049Sjfv if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) 1653200243Sjfv ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1654200243Sjfv 1655200243Sjfv reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 1656200243Sjfv 1657200243Sjfv /* default pcs_autoneg to the same setting as mac autoneg */ 1658200243Sjfv pcs_autoneg = hw->mac.autoneg; 1659200243Sjfv 1660200243Sjfv switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1661200243Sjfv case E1000_CTRL_EXT_LINK_MODE_SGMII: 1662200243Sjfv /* sgmii mode lets the phy handle forcing speed/duplex */ 1663200243Sjfv pcs_autoneg = TRUE; 1664200243Sjfv /* autoneg time out should be disabled for SGMII mode */ 1665200243Sjfv reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1666200243Sjfv break; 1667200243Sjfv case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1668200243Sjfv /* disable PCS autoneg and support parallel detect only */ 1669200243Sjfv pcs_autoneg = FALSE; 1670213234Sjfv /* fall through to default case */ 1671200243Sjfv default: 1672228386Sjfv if (hw->mac.type == e1000_82575 || 1673228386Sjfv hw->mac.type == e1000_82576) { 1674228386Sjfv ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1675228386Sjfv if (ret_val) { 1676228386Sjfv DEBUGOUT("NVM Read Error\n"); 1677228386Sjfv return ret_val; 1678228386Sjfv } 1679228386Sjfv 1680228386Sjfv if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1681228386Sjfv pcs_autoneg = FALSE; 1682228386Sjfv } 1683228386Sjfv 1684200243Sjfv /* 1685200243Sjfv * non-SGMII modes only supports a speed of 1000/Full for the 1686200243Sjfv * link so it is best to just force the MAC and let the pcs 1687200243Sjfv * link either autoneg or be forced to 1000/Full 1688200243Sjfv */ 1689200243Sjfv ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1690228386Sjfv E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1691200243Sjfv 1692200243Sjfv /* set speed of 1000/Full if speed/duplex is forced */ 1693200243Sjfv reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1694200243Sjfv break; 1695181027Sjfv } 1696181027Sjfv 1697200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 1698176667Sjfv 1699176667Sjfv /* 1700176667Sjfv * New SerDes mode allows for forcing speed or autonegotiating speed 1701176667Sjfv * at 1gb. Autoneg should be default set by most drivers. This is the 1702176667Sjfv * mode that will be compatible with older link partners and switches. 1703176667Sjfv * However, both are supported by the hardware and some drivers/tools. 1704176667Sjfv */ 1705176667Sjfv reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1706228386Sjfv E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1707176667Sjfv 1708200243Sjfv if (pcs_autoneg) { 1709176667Sjfv /* Set PCS register for autoneg */ 1710200243Sjfv reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1711200243Sjfv E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1712247064Sjfv 1713247064Sjfv /* Disable force flow control for autoneg */ 1714247064Sjfv reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1715247064Sjfv 1716247064Sjfv /* Configure flow control advertisement for autoneg */ 1717247064Sjfv anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV); 1718247064Sjfv anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1719247064Sjfv 1720247064Sjfv switch (hw->fc.requested_mode) { 1721247064Sjfv case e1000_fc_full: 1722247064Sjfv case e1000_fc_rx_pause: 1723247064Sjfv anadv_reg |= E1000_TXCW_ASM_DIR; 1724247064Sjfv anadv_reg |= E1000_TXCW_PAUSE; 1725247064Sjfv break; 1726247064Sjfv case e1000_fc_tx_pause: 1727247064Sjfv anadv_reg |= E1000_TXCW_ASM_DIR; 1728247064Sjfv break; 1729247064Sjfv default: 1730247064Sjfv break; 1731247064Sjfv } 1732247064Sjfv 1733247064Sjfv E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg); 1734247064Sjfv 1735200243Sjfv DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1736176667Sjfv } else { 1737200243Sjfv /* Set PCS register for forced link */ 1738228386Sjfv reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1739247064Sjfv 1740247064Sjfv /* Force flow control for forced link */ 1741247064Sjfv reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1742247064Sjfv 1743200243Sjfv DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1744181027Sjfv } 1745181027Sjfv 1746176667Sjfv E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 1747176667Sjfv 1748247064Sjfv if (!pcs_autoneg && !e1000_sgmii_active_82575(hw)) 1749200243Sjfv e1000_force_mac_fc_generic(hw); 1750200243Sjfv 1751228386Sjfv return ret_val; 1752176667Sjfv} 1753176667Sjfv 1754176667Sjfv/** 1755228386Sjfv * e1000_get_media_type_82575 - derives current media type. 1756228386Sjfv * @hw: pointer to the HW structure 1757228386Sjfv * 1758228386Sjfv * The media type is chosen reflecting few settings. 1759228386Sjfv * The following are taken into account: 1760228386Sjfv * - link mode set in the current port Init Control Word #3 1761228386Sjfv * - current link mode settings in CSR register 1762228386Sjfv * - MDIO vs. I2C PHY control interface chosen 1763228386Sjfv * - SFP module media type 1764228386Sjfv **/ 1765228386Sjfvstatic s32 e1000_get_media_type_82575(struct e1000_hw *hw) 1766228386Sjfv{ 1767228386Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1768247064Sjfv s32 ret_val = E1000_SUCCESS; 1769228386Sjfv u32 ctrl_ext = 0; 1770247064Sjfv u32 link_mode = 0; 1771228386Sjfv 1772228386Sjfv /* Set internal phy as default */ 1773228386Sjfv dev_spec->sgmii_active = FALSE; 1774228386Sjfv dev_spec->module_plugged = FALSE; 1775228386Sjfv 1776228386Sjfv /* Get CSR setting */ 1777228386Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1778228386Sjfv 1779247064Sjfv /* extract link mode setting */ 1780247064Sjfv link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 1781228386Sjfv 1782247064Sjfv switch (link_mode) { 1783228386Sjfv case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1784228386Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 1785228386Sjfv break; 1786228386Sjfv case E1000_CTRL_EXT_LINK_MODE_GMII: 1787228386Sjfv hw->phy.media_type = e1000_media_type_copper; 1788228386Sjfv break; 1789228386Sjfv case E1000_CTRL_EXT_LINK_MODE_SGMII: 1790228386Sjfv /* Get phy control interface type set (MDIO vs. I2C)*/ 1791228386Sjfv if (e1000_sgmii_uses_mdio_82575(hw)) { 1792228386Sjfv hw->phy.media_type = e1000_media_type_copper; 1793228386Sjfv dev_spec->sgmii_active = TRUE; 1794247064Sjfv break; 1795247064Sjfv } 1796247064Sjfv /* fall through for I2C based SGMII */ 1797247064Sjfv case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 1798247064Sjfv /* read media type from SFP EEPROM */ 1799247064Sjfv ret_val = e1000_set_sfp_media_type_82575(hw); 1800247064Sjfv if ((ret_val != E1000_SUCCESS) || 1801247064Sjfv (hw->phy.media_type == e1000_media_type_unknown)) { 1802247064Sjfv /* 1803247064Sjfv * If media type was not identified then return media 1804247064Sjfv * type defined by the CTRL_EXT settings. 1805247064Sjfv */ 1806247064Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 1807247064Sjfv 1808247064Sjfv if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 1809247064Sjfv hw->phy.media_type = e1000_media_type_copper; 1810247064Sjfv dev_spec->sgmii_active = TRUE; 1811228386Sjfv } 1812247064Sjfv 1813247064Sjfv break; 1814228386Sjfv } 1815247064Sjfv 1816247064Sjfv /* do not change link mode for 100BaseFX */ 1817247064Sjfv if (dev_spec->eth_flags.e100_base_fx) 1818247064Sjfv break; 1819247064Sjfv 1820247064Sjfv /* change current link mode setting */ 1821228386Sjfv ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 1822228386Sjfv 1823247064Sjfv if (hw->phy.media_type == e1000_media_type_copper) 1824247064Sjfv ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 1825228386Sjfv else 1826247064Sjfv ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1827247064Sjfv 1828247064Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1829247064Sjfv 1830247064Sjfv break; 1831228386Sjfv } 1832228386Sjfv 1833228386Sjfv return ret_val; 1834228386Sjfv} 1835228386Sjfv 1836228386Sjfv/** 1837228386Sjfv * e1000_set_sfp_media_type_82575 - derives SFP module media type. 1838228386Sjfv * @hw: pointer to the HW structure 1839228386Sjfv * 1840228386Sjfv * The media type is chosen based on SFP module. 1841228386Sjfv * compatibility flags retrieved from SFP ID EEPROM. 1842228386Sjfv **/ 1843228386Sjfvstatic s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw) 1844228386Sjfv{ 1845228386Sjfv s32 ret_val = E1000_ERR_CONFIG; 1846228386Sjfv u32 ctrl_ext = 0; 1847228386Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1848247064Sjfv struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags; 1849228386Sjfv u8 tranceiver_type = 0; 1850247064Sjfv s32 timeout = 3; 1851228386Sjfv 1852247064Sjfv /* Turn I2C interface ON and power on sfp cage */ 1853228386Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1854247064Sjfv ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1855228386Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 1856228386Sjfv 1857247064Sjfv E1000_WRITE_FLUSH(hw); 1858247064Sjfv 1859228386Sjfv /* Read SFP module data */ 1860247064Sjfv while (timeout) { 1861247064Sjfv ret_val = e1000_read_sfp_data_byte(hw, 1862228386Sjfv E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 1863228386Sjfv &tranceiver_type); 1864247064Sjfv if (ret_val == E1000_SUCCESS) 1865247064Sjfv break; 1866247064Sjfv msec_delay(100); 1867247064Sjfv timeout--; 1868247064Sjfv } 1869228386Sjfv if (ret_val != E1000_SUCCESS) 1870228386Sjfv goto out; 1871247064Sjfv 1872228386Sjfv ret_val = e1000_read_sfp_data_byte(hw, 1873228386Sjfv E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 1874247064Sjfv (u8 *)eth_flags); 1875228386Sjfv if (ret_val != E1000_SUCCESS) 1876228386Sjfv goto out; 1877247064Sjfv 1878247064Sjfv /* Check if there is some SFP module plugged and powered */ 1879228386Sjfv if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 1880228386Sjfv (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 1881228386Sjfv dev_spec->module_plugged = TRUE; 1882247064Sjfv if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 1883228386Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 1884247064Sjfv } else if (eth_flags->e100_base_fx) { 1885228386Sjfv dev_spec->sgmii_active = TRUE; 1886247064Sjfv hw->phy.media_type = e1000_media_type_internal_serdes; 1887247064Sjfv } else if (eth_flags->e1000_base_t) { 1888247064Sjfv dev_spec->sgmii_active = TRUE; 1889228386Sjfv hw->phy.media_type = e1000_media_type_copper; 1890228386Sjfv } else { 1891247064Sjfv hw->phy.media_type = e1000_media_type_unknown; 1892247064Sjfv DEBUGOUT("PHY module has not been recognized\n"); 1893247064Sjfv goto out; 1894228386Sjfv } 1895228386Sjfv } else { 1896228386Sjfv hw->phy.media_type = e1000_media_type_unknown; 1897228386Sjfv } 1898228386Sjfv ret_val = E1000_SUCCESS; 1899228386Sjfvout: 1900228386Sjfv /* Restore I2C interface setting */ 1901228386Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1902228386Sjfv return ret_val; 1903228386Sjfv} 1904228386Sjfv 1905228386Sjfv/** 1906181027Sjfv * e1000_valid_led_default_82575 - Verify a valid default LED config 1907181027Sjfv * @hw: pointer to the HW structure 1908181027Sjfv * @data: pointer to the NVM (EEPROM) 1909181027Sjfv * 1910181027Sjfv * Read the EEPROM for the current default LED configuration. If the 1911181027Sjfv * LED configuration is not valid, set to a valid LED configuration. 1912181027Sjfv **/ 1913181027Sjfvstatic s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data) 1914181027Sjfv{ 1915181027Sjfv s32 ret_val; 1916181027Sjfv 1917181027Sjfv DEBUGFUNC("e1000_valid_led_default_82575"); 1918181027Sjfv 1919181027Sjfv ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1920181027Sjfv if (ret_val) { 1921181027Sjfv DEBUGOUT("NVM Read Error\n"); 1922181027Sjfv goto out; 1923181027Sjfv } 1924181027Sjfv 1925181027Sjfv if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 1926228386Sjfv switch (hw->phy.media_type) { 1927181027Sjfv case e1000_media_type_internal_serdes: 1928181027Sjfv *data = ID_LED_DEFAULT_82575_SERDES; 1929181027Sjfv break; 1930181027Sjfv case e1000_media_type_copper: 1931181027Sjfv default: 1932181027Sjfv *data = ID_LED_DEFAULT; 1933181027Sjfv break; 1934181027Sjfv } 1935181027Sjfv } 1936181027Sjfvout: 1937181027Sjfv return ret_val; 1938181027Sjfv} 1939181027Sjfv 1940181027Sjfv/** 1941176667Sjfv * e1000_sgmii_active_82575 - Return sgmii state 1942176667Sjfv * @hw: pointer to the HW structure 1943176667Sjfv * 1944176667Sjfv * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1945176667Sjfv * which can be enabled for use in the embedded applications. Simply 1946176667Sjfv * return the current state of the sgmii interface. 1947176667Sjfv **/ 1948176667Sjfvstatic bool e1000_sgmii_active_82575(struct e1000_hw *hw) 1949176667Sjfv{ 1950185353Sjfv struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1951185353Sjfv return dev_spec->sgmii_active; 1952176667Sjfv} 1953176667Sjfv 1954176667Sjfv/** 1955176667Sjfv * e1000_reset_init_script_82575 - Inits HW defaults after reset 1956176667Sjfv * @hw: pointer to the HW structure 1957176667Sjfv * 1958176667Sjfv * Inits recommended HW defaults after a reset when there is no EEPROM 1959176667Sjfv * detected. This is only for the 82575. 1960176667Sjfv **/ 1961228386Sjfvstatic s32 e1000_reset_init_script_82575(struct e1000_hw *hw) 1962176667Sjfv{ 1963176667Sjfv DEBUGFUNC("e1000_reset_init_script_82575"); 1964176667Sjfv 1965176667Sjfv if (hw->mac.type == e1000_82575) { 1966176667Sjfv DEBUGOUT("Running reset init script for 82575\n"); 1967176667Sjfv /* SerDes configuration via SERDESCTRL */ 1968178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 1969178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 1970178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 1971178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 1972176667Sjfv 1973176667Sjfv /* CCM configuration via CCMCTL register */ 1974178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 1975178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 1976176667Sjfv 1977176667Sjfv /* PCIe lanes configuration */ 1978178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 1979178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 1980178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 1981178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 1982176667Sjfv 1983176667Sjfv /* PCIe PLL Configuration */ 1984178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 1985178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 1986178523Sjfv e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 1987176667Sjfv } 1988176667Sjfv 1989176667Sjfv return E1000_SUCCESS; 1990176667Sjfv} 1991176667Sjfv 1992176667Sjfv/** 1993176667Sjfv * e1000_read_mac_addr_82575 - Read device MAC address 1994176667Sjfv * @hw: pointer to the HW structure 1995176667Sjfv **/ 1996176667Sjfvstatic s32 e1000_read_mac_addr_82575(struct e1000_hw *hw) 1997176667Sjfv{ 1998269196Sjfv s32 ret_val; 1999176667Sjfv 2000176667Sjfv DEBUGFUNC("e1000_read_mac_addr_82575"); 2001176667Sjfv 2002190872Sjfv /* 2003190872Sjfv * If there's an alternate MAC address place it in RAR0 2004190872Sjfv * so that it will override the Si installed default perm 2005190872Sjfv * address. 2006190872Sjfv */ 2007190872Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 2008190872Sjfv if (ret_val) 2009190872Sjfv goto out; 2010190872Sjfv 2011190872Sjfv ret_val = e1000_read_mac_addr_generic(hw); 2012190872Sjfv 2013190872Sjfvout: 2014176667Sjfv return ret_val; 2015176667Sjfv} 2016176667Sjfv 2017176667Sjfv/** 2018203049Sjfv * e1000_config_collision_dist_82575 - Configure collision distance 2019203049Sjfv * @hw: pointer to the HW structure 2020203049Sjfv * 2021203049Sjfv * Configures the collision distance to the default value and is used 2022203049Sjfv * during link setup. 2023203049Sjfv **/ 2024203049Sjfvstatic void e1000_config_collision_dist_82575(struct e1000_hw *hw) 2025203049Sjfv{ 2026203049Sjfv u32 tctl_ext; 2027203049Sjfv 2028203049Sjfv DEBUGFUNC("e1000_config_collision_dist_82575"); 2029203049Sjfv 2030203049Sjfv tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT); 2031203049Sjfv 2032203049Sjfv tctl_ext &= ~E1000_TCTL_EXT_COLD; 2033203049Sjfv tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT; 2034203049Sjfv 2035203049Sjfv E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext); 2036203049Sjfv E1000_WRITE_FLUSH(hw); 2037203049Sjfv} 2038203049Sjfv 2039203049Sjfv/** 2040176667Sjfv * e1000_power_down_phy_copper_82575 - Remove link during PHY power down 2041176667Sjfv * @hw: pointer to the HW structure 2042176667Sjfv * 2043176667Sjfv * In the case of a PHY power down to save power, or to turn off link during a 2044176667Sjfv * driver unload, or wake on lan is not enabled, remove the link. 2045176667Sjfv **/ 2046176667Sjfvstatic void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) 2047176667Sjfv{ 2048176667Sjfv struct e1000_phy_info *phy = &hw->phy; 2049176667Sjfv 2050176667Sjfv if (!(phy->ops.check_reset_block)) 2051176667Sjfv return; 2052176667Sjfv 2053176667Sjfv /* If the management interface is not enabled, then power down */ 2054205869Sjfv if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) 2055176667Sjfv e1000_power_down_phy_copper(hw); 2056176667Sjfv 2057176667Sjfv return; 2058176667Sjfv} 2059176667Sjfv 2060176667Sjfv/** 2061176667Sjfv * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters 2062176667Sjfv * @hw: pointer to the HW structure 2063176667Sjfv * 2064176667Sjfv * Clears the hardware counters by reading the counter registers. 2065176667Sjfv **/ 2066176667Sjfvstatic void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) 2067176667Sjfv{ 2068176667Sjfv DEBUGFUNC("e1000_clear_hw_cntrs_82575"); 2069176667Sjfv 2070176667Sjfv e1000_clear_hw_cntrs_base_generic(hw); 2071176667Sjfv 2072185353Sjfv E1000_READ_REG(hw, E1000_PRC64); 2073185353Sjfv E1000_READ_REG(hw, E1000_PRC127); 2074185353Sjfv E1000_READ_REG(hw, E1000_PRC255); 2075185353Sjfv E1000_READ_REG(hw, E1000_PRC511); 2076185353Sjfv E1000_READ_REG(hw, E1000_PRC1023); 2077185353Sjfv E1000_READ_REG(hw, E1000_PRC1522); 2078185353Sjfv E1000_READ_REG(hw, E1000_PTC64); 2079185353Sjfv E1000_READ_REG(hw, E1000_PTC127); 2080185353Sjfv E1000_READ_REG(hw, E1000_PTC255); 2081185353Sjfv E1000_READ_REG(hw, E1000_PTC511); 2082185353Sjfv E1000_READ_REG(hw, E1000_PTC1023); 2083185353Sjfv E1000_READ_REG(hw, E1000_PTC1522); 2084176667Sjfv 2085185353Sjfv E1000_READ_REG(hw, E1000_ALGNERRC); 2086185353Sjfv E1000_READ_REG(hw, E1000_RXERRC); 2087185353Sjfv E1000_READ_REG(hw, E1000_TNCRS); 2088185353Sjfv E1000_READ_REG(hw, E1000_CEXTERR); 2089185353Sjfv E1000_READ_REG(hw, E1000_TSCTC); 2090185353Sjfv E1000_READ_REG(hw, E1000_TSCTFC); 2091176667Sjfv 2092185353Sjfv E1000_READ_REG(hw, E1000_MGTPRC); 2093185353Sjfv E1000_READ_REG(hw, E1000_MGTPDC); 2094185353Sjfv E1000_READ_REG(hw, E1000_MGTPTC); 2095176667Sjfv 2096185353Sjfv E1000_READ_REG(hw, E1000_IAC); 2097185353Sjfv E1000_READ_REG(hw, E1000_ICRXOC); 2098176667Sjfv 2099185353Sjfv E1000_READ_REG(hw, E1000_ICRXPTC); 2100185353Sjfv E1000_READ_REG(hw, E1000_ICRXATC); 2101185353Sjfv E1000_READ_REG(hw, E1000_ICTXPTC); 2102185353Sjfv E1000_READ_REG(hw, E1000_ICTXATC); 2103185353Sjfv E1000_READ_REG(hw, E1000_ICTXQEC); 2104185353Sjfv E1000_READ_REG(hw, E1000_ICTXQMTC); 2105185353Sjfv E1000_READ_REG(hw, E1000_ICRXDMTC); 2106176667Sjfv 2107185353Sjfv E1000_READ_REG(hw, E1000_CBTMPC); 2108185353Sjfv E1000_READ_REG(hw, E1000_HTDPMC); 2109185353Sjfv E1000_READ_REG(hw, E1000_CBRMPC); 2110185353Sjfv E1000_READ_REG(hw, E1000_RPTHC); 2111185353Sjfv E1000_READ_REG(hw, E1000_HGPTC); 2112185353Sjfv E1000_READ_REG(hw, E1000_HTCBDPC); 2113185353Sjfv E1000_READ_REG(hw, E1000_HGORCL); 2114185353Sjfv E1000_READ_REG(hw, E1000_HGORCH); 2115185353Sjfv E1000_READ_REG(hw, E1000_HGOTCL); 2116185353Sjfv E1000_READ_REG(hw, E1000_HGOTCH); 2117185353Sjfv E1000_READ_REG(hw, E1000_LENERRS); 2118176667Sjfv 2119176667Sjfv /* This register should not be read in copper configurations */ 2120200243Sjfv if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 2121200243Sjfv e1000_sgmii_active_82575(hw)) 2122185353Sjfv E1000_READ_REG(hw, E1000_SCVPC); 2123176667Sjfv} 2124194865Sjfv 2125181027Sjfv/** 2126218530Sjfv * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable 2127181027Sjfv * @hw: pointer to the HW structure 2128181027Sjfv * 2129181027Sjfv * After rx enable if managability is enabled then there is likely some 2130181027Sjfv * bad data at the start of the fifo and possibly in the DMA fifo. This 2131181027Sjfv * function clears the fifos and flushes any packets that came in as rx was 2132181027Sjfv * being enabled. 2133181027Sjfv **/ 2134181027Sjfvvoid e1000_rx_fifo_flush_82575(struct e1000_hw *hw) 2135181027Sjfv{ 2136181027Sjfv u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 2137181027Sjfv int i, ms_wait; 2138181027Sjfv 2139181027Sjfv DEBUGFUNC("e1000_rx_fifo_workaround_82575"); 2140181027Sjfv if (hw->mac.type != e1000_82575 || 2141181027Sjfv !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 2142181027Sjfv return; 2143181027Sjfv 2144218530Sjfv /* Disable all Rx queues */ 2145181027Sjfv for (i = 0; i < 4; i++) { 2146181027Sjfv rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 2147181027Sjfv E1000_WRITE_REG(hw, E1000_RXDCTL(i), 2148228386Sjfv rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 2149181027Sjfv } 2150181027Sjfv /* Poll all queues to verify they have shut down */ 2151181027Sjfv for (ms_wait = 0; ms_wait < 10; ms_wait++) { 2152181027Sjfv msec_delay(1); 2153181027Sjfv rx_enabled = 0; 2154181027Sjfv for (i = 0; i < 4; i++) 2155181027Sjfv rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 2156181027Sjfv if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 2157181027Sjfv break; 2158181027Sjfv } 2159181027Sjfv 2160181027Sjfv if (ms_wait == 10) 2161181027Sjfv DEBUGOUT("Queue disable timed out after 10ms\n"); 2162181027Sjfv 2163181027Sjfv /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 2164181027Sjfv * incoming packets are rejected. Set enable and wait 2ms so that 2165181027Sjfv * any packet that was coming in as RCTL.EN was set is flushed 2166181027Sjfv */ 2167181027Sjfv rfctl = E1000_READ_REG(hw, E1000_RFCTL); 2168181027Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 2169181027Sjfv 2170181027Sjfv rlpml = E1000_READ_REG(hw, E1000_RLPML); 2171181027Sjfv E1000_WRITE_REG(hw, E1000_RLPML, 0); 2172181027Sjfv 2173181027Sjfv rctl = E1000_READ_REG(hw, E1000_RCTL); 2174181027Sjfv temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 2175181027Sjfv temp_rctl |= E1000_RCTL_LPE; 2176181027Sjfv 2177181027Sjfv E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 2178181027Sjfv E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 2179181027Sjfv E1000_WRITE_FLUSH(hw); 2180181027Sjfv msec_delay(2); 2181181027Sjfv 2182218530Sjfv /* Enable Rx queues that were previously enabled and restore our 2183181027Sjfv * previous state 2184181027Sjfv */ 2185181027Sjfv for (i = 0; i < 4; i++) 2186181027Sjfv E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 2187181027Sjfv E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2188181027Sjfv E1000_WRITE_FLUSH(hw); 2189181027Sjfv 2190181027Sjfv E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 2191181027Sjfv E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 2192181027Sjfv 2193181027Sjfv /* Flush receive errors generated by workaround */ 2194181027Sjfv E1000_READ_REG(hw, E1000_ROC); 2195181027Sjfv E1000_READ_REG(hw, E1000_RNBC); 2196181027Sjfv E1000_READ_REG(hw, E1000_MPC); 2197181027Sjfv} 2198185353Sjfv 2199194865Sjfv/** 2200194865Sjfv * e1000_set_pcie_completion_timeout - set pci-e completion timeout 2201194865Sjfv * @hw: pointer to the HW structure 2202194865Sjfv * 2203194865Sjfv * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2204194865Sjfv * however the hardware default for these parts is 500us to 1ms which is less 2205194865Sjfv * than the 10ms recommended by the pci-e spec. To address this we need to 2206194865Sjfv * increase the value to either 10ms to 200ms for capability version 1 config, 2207194865Sjfv * or 16ms to 55ms for version 2. 2208194865Sjfv **/ 2209194865Sjfvstatic s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw) 2210194865Sjfv{ 2211194865Sjfv u32 gcr = E1000_READ_REG(hw, E1000_GCR); 2212194865Sjfv s32 ret_val = E1000_SUCCESS; 2213194865Sjfv u16 pcie_devctl2; 2214194865Sjfv 2215194865Sjfv /* only take action if timeout value is defaulted to 0 */ 2216194865Sjfv if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2217194865Sjfv goto out; 2218194865Sjfv 2219194865Sjfv /* 2220194865Sjfv * if capababilities version is type 1 we can write the 2221194865Sjfv * timeout of 10ms to 200ms through the GCR register 2222194865Sjfv */ 2223194865Sjfv if (!(gcr & E1000_GCR_CAP_VER2)) { 2224194865Sjfv gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2225194865Sjfv goto out; 2226194865Sjfv } 2227194865Sjfv 2228194865Sjfv /* 2229194865Sjfv * for version 2 capabilities we need to write the config space 2230194865Sjfv * directly in order to set the completion timeout value for 2231194865Sjfv * 16ms to 55ms 2232194865Sjfv */ 2233194865Sjfv ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2234228386Sjfv &pcie_devctl2); 2235194865Sjfv if (ret_val) 2236194865Sjfv goto out; 2237194865Sjfv 2238194865Sjfv pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2239194865Sjfv 2240194865Sjfv ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2241228386Sjfv &pcie_devctl2); 2242194865Sjfvout: 2243194865Sjfv /* disable completion timeout resend */ 2244194865Sjfv gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2245194865Sjfv 2246194865Sjfv E1000_WRITE_REG(hw, E1000_GCR, gcr); 2247194865Sjfv return ret_val; 2248194865Sjfv} 2249194865Sjfv 2250200243Sjfv/** 2251213234Sjfv * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2252213234Sjfv * @hw: pointer to the hardware struct 2253213234Sjfv * @enable: state to enter, either enabled or disabled 2254213234Sjfv * @pf: Physical Function pool - do not set anti-spoofing for the PF 2255213234Sjfv * 2256213234Sjfv * enables/disables L2 switch anti-spoofing functionality. 2257213234Sjfv **/ 2258213234Sjfvvoid e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2259213234Sjfv{ 2260256200Sjfv u32 reg_val, reg_offset; 2261213234Sjfv 2262213234Sjfv switch (hw->mac.type) { 2263213234Sjfv case e1000_82576: 2264256200Sjfv reg_offset = E1000_DTXSWC; 2265213234Sjfv break; 2266228386Sjfv case e1000_i350: 2267256200Sjfv case e1000_i354: 2268256200Sjfv reg_offset = E1000_TXSWC; 2269256200Sjfv break; 2270213234Sjfv default: 2271256200Sjfv return; 2272213234Sjfv } 2273256200Sjfv 2274256200Sjfv reg_val = E1000_READ_REG(hw, reg_offset); 2275256200Sjfv if (enable) { 2276256200Sjfv reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2277256200Sjfv E1000_DTXSWC_VLAN_SPOOF_MASK); 2278256200Sjfv /* The PF can spoof - it has to in order to 2279256200Sjfv * support emulation mode NICs 2280256200Sjfv */ 2281256200Sjfv reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 2282256200Sjfv } else { 2283256200Sjfv reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2284256200Sjfv E1000_DTXSWC_VLAN_SPOOF_MASK); 2285256200Sjfv } 2286256200Sjfv E1000_WRITE_REG(hw, reg_offset, reg_val); 2287213234Sjfv} 2288213234Sjfv 2289213234Sjfv/** 2290200243Sjfv * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback 2291200243Sjfv * @hw: pointer to the hardware struct 2292200243Sjfv * @enable: state to enter, either enabled or disabled 2293200243Sjfv * 2294200243Sjfv * enables/disables L2 switch loopback functionality. 2295200243Sjfv **/ 2296200243Sjfvvoid e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2297200243Sjfv{ 2298205869Sjfv u32 dtxswc; 2299200243Sjfv 2300205869Sjfv switch (hw->mac.type) { 2301205869Sjfv case e1000_82576: 2302205869Sjfv dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 2303205869Sjfv if (enable) 2304205869Sjfv dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2305205869Sjfv else 2306205869Sjfv dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2307205869Sjfv E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 2308205869Sjfv break; 2309218530Sjfv case e1000_i350: 2310256200Sjfv case e1000_i354: 2311218530Sjfv dtxswc = E1000_READ_REG(hw, E1000_TXSWC); 2312218530Sjfv if (enable) 2313218530Sjfv dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2314218530Sjfv else 2315218530Sjfv dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2316218530Sjfv E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc); 2317218530Sjfv break; 2318205869Sjfv default: 2319205869Sjfv /* Currently no other hardware supports loopback */ 2320205869Sjfv break; 2321205869Sjfv } 2322200243Sjfv 2323205869Sjfv 2324200243Sjfv} 2325200243Sjfv 2326200243Sjfv/** 2327200243Sjfv * e1000_vmdq_set_replication_pf - enable or disable vmdq replication 2328200243Sjfv * @hw: pointer to the hardware struct 2329200243Sjfv * @enable: state to enter, either enabled or disabled 2330200243Sjfv * 2331200243Sjfv * enables/disables replication of packets across multiple pools. 2332200243Sjfv **/ 2333200243Sjfvvoid e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2334200243Sjfv{ 2335200243Sjfv u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 2336200243Sjfv 2337200243Sjfv if (enable) 2338200243Sjfv vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2339200243Sjfv else 2340200243Sjfv vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2341200243Sjfv 2342200243Sjfv E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 2343200243Sjfv} 2344200243Sjfv 2345200243Sjfv/** 2346200243Sjfv * e1000_read_phy_reg_82580 - Read 82580 MDI control register 2347200243Sjfv * @hw: pointer to the HW structure 2348200243Sjfv * @offset: register offset to be read 2349200243Sjfv * @data: pointer to the read data 2350200243Sjfv * 2351200243Sjfv * Reads the MDI control register in the PHY at offset and stores the 2352200243Sjfv * information read to data. 2353200243Sjfv **/ 2354200243Sjfvstatic s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2355200243Sjfv{ 2356200243Sjfv s32 ret_val; 2357200243Sjfv 2358200243Sjfv DEBUGFUNC("e1000_read_phy_reg_82580"); 2359200243Sjfv 2360200243Sjfv ret_val = hw->phy.ops.acquire(hw); 2361200243Sjfv if (ret_val) 2362200243Sjfv goto out; 2363200243Sjfv 2364200243Sjfv ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 2365200243Sjfv 2366200243Sjfv hw->phy.ops.release(hw); 2367200243Sjfv 2368200243Sjfvout: 2369200243Sjfv return ret_val; 2370200243Sjfv} 2371200243Sjfv 2372200243Sjfv/** 2373200243Sjfv * e1000_write_phy_reg_82580 - Write 82580 MDI control register 2374200243Sjfv * @hw: pointer to the HW structure 2375200243Sjfv * @offset: register offset to write to 2376200243Sjfv * @data: data to write to register at offset 2377200243Sjfv * 2378200243Sjfv * Writes data to MDI control register in the PHY at offset. 2379200243Sjfv **/ 2380200243Sjfvstatic s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2381200243Sjfv{ 2382200243Sjfv s32 ret_val; 2383200243Sjfv 2384200243Sjfv DEBUGFUNC("e1000_write_phy_reg_82580"); 2385200243Sjfv 2386200243Sjfv ret_val = hw->phy.ops.acquire(hw); 2387200243Sjfv if (ret_val) 2388200243Sjfv goto out; 2389200243Sjfv 2390200243Sjfv ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 2391200243Sjfv 2392200243Sjfv hw->phy.ops.release(hw); 2393200243Sjfv 2394200243Sjfvout: 2395200243Sjfv return ret_val; 2396200243Sjfv} 2397203049Sjfv 2398200243Sjfv/** 2399213234Sjfv * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2400213234Sjfv * @hw: pointer to the HW structure 2401213234Sjfv * 2402247064Sjfv * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2403213234Sjfv * the values found in the EEPROM. This addresses an issue in which these 2404213234Sjfv * bits are not restored from EEPROM after reset. 2405213234Sjfv **/ 2406213234Sjfvstatic s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw) 2407213234Sjfv{ 2408213234Sjfv s32 ret_val = E1000_SUCCESS; 2409213234Sjfv u32 mdicnfg; 2410218530Sjfv u16 nvm_data = 0; 2411213234Sjfv 2412213234Sjfv DEBUGFUNC("e1000_reset_mdicnfg_82580"); 2413213234Sjfv 2414213234Sjfv if (hw->mac.type != e1000_82580) 2415213234Sjfv goto out; 2416213234Sjfv if (!e1000_sgmii_active_82575(hw)) 2417213234Sjfv goto out; 2418213234Sjfv 2419213234Sjfv ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2420228386Sjfv NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2421228386Sjfv &nvm_data); 2422213234Sjfv if (ret_val) { 2423213234Sjfv DEBUGOUT("NVM Read Error\n"); 2424213234Sjfv goto out; 2425213234Sjfv } 2426213234Sjfv 2427213234Sjfv mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG); 2428213234Sjfv if (nvm_data & NVM_WORD24_EXT_MDIO) 2429213234Sjfv mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2430213234Sjfv if (nvm_data & NVM_WORD24_COM_MDIO) 2431213234Sjfv mdicnfg |= E1000_MDICNFG_COM_MDIO; 2432213234Sjfv E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg); 2433213234Sjfvout: 2434213234Sjfv return ret_val; 2435213234Sjfv} 2436213234Sjfv 2437213234Sjfv/** 2438200243Sjfv * e1000_reset_hw_82580 - Reset hardware 2439200243Sjfv * @hw: pointer to the HW structure 2440200243Sjfv * 2441200243Sjfv * This resets function or entire device (all ports, etc.) 2442200243Sjfv * to a known state. 2443200243Sjfv **/ 2444200243Sjfvstatic s32 e1000_reset_hw_82580(struct e1000_hw *hw) 2445200243Sjfv{ 2446200243Sjfv s32 ret_val = E1000_SUCCESS; 2447200243Sjfv /* BH SW mailbox bit in SW_FW_SYNC */ 2448200243Sjfv u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2449218530Sjfv u32 ctrl; 2450200243Sjfv bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2451200243Sjfv 2452200243Sjfv DEBUGFUNC("e1000_reset_hw_82580"); 2453200243Sjfv 2454200243Sjfv hw->dev_spec._82575.global_device_reset = FALSE; 2455200243Sjfv 2456247064Sjfv /* 82580 does not reliably do global_device_reset due to hw errata */ 2457247064Sjfv if (hw->mac.type == e1000_82580) 2458247064Sjfv global_device_reset = FALSE; 2459247064Sjfv 2460200243Sjfv /* Get current control state. */ 2461200243Sjfv ctrl = E1000_READ_REG(hw, E1000_CTRL); 2462200243Sjfv 2463200243Sjfv /* 2464200243Sjfv * Prevent the PCI-E bus from sticking if there is no TLP connection 2465200243Sjfv * on the last TLP read/write transaction when MAC is reset. 2466200243Sjfv */ 2467200243Sjfv ret_val = e1000_disable_pcie_master_generic(hw); 2468200243Sjfv if (ret_val) 2469200243Sjfv DEBUGOUT("PCI-E Master disable polling has failed.\n"); 2470200243Sjfv 2471200243Sjfv DEBUGOUT("Masking off all interrupts\n"); 2472200243Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2473200243Sjfv E1000_WRITE_REG(hw, E1000_RCTL, 0); 2474200243Sjfv E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 2475200243Sjfv E1000_WRITE_FLUSH(hw); 2476200243Sjfv 2477200243Sjfv msec_delay(10); 2478200243Sjfv 2479200243Sjfv /* Determine whether or not a global dev reset is requested */ 2480238148Sjfv if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw, 2481228386Sjfv swmbsw_mask)) 2482200243Sjfv global_device_reset = FALSE; 2483200243Sjfv 2484228386Sjfv if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) & 2485228386Sjfv E1000_STAT_DEV_RST_SET)) 2486200243Sjfv ctrl |= E1000_CTRL_DEV_RST; 2487200243Sjfv else 2488200243Sjfv ctrl |= E1000_CTRL_RST; 2489200243Sjfv 2490200243Sjfv E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2491200243Sjfv 2492269196Sjfv switch (hw->device_id) { 2493269196Sjfv case E1000_DEV_ID_DH89XXCC_SGMII: 2494269196Sjfv break; 2495269196Sjfv default: 2496269196Sjfv E1000_WRITE_FLUSH(hw); 2497269196Sjfv break; 2498269196Sjfv } 2499200243Sjfv 2500269196Sjfv /* Add delay to insure DEV_RST or RST has time to complete */ 2501269196Sjfv msec_delay(5); 2502269196Sjfv 2503200243Sjfv ret_val = e1000_get_auto_rd_done_generic(hw); 2504200243Sjfv if (ret_val) { 2505200243Sjfv /* 2506200243Sjfv * When auto config read does not complete, do not 2507200243Sjfv * return with an error. This can happen in situations 2508200243Sjfv * where there is no eeprom and prevents getting link. 2509200243Sjfv */ 2510200243Sjfv DEBUGOUT("Auto Read Done did not complete\n"); 2511200243Sjfv } 2512200243Sjfv 2513200243Sjfv /* clear global device reset status bit */ 2514200243Sjfv E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET); 2515200243Sjfv 2516200243Sjfv /* Clear any pending interrupt events. */ 2517200243Sjfv E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2518218530Sjfv E1000_READ_REG(hw, E1000_ICR); 2519200243Sjfv 2520213234Sjfv ret_val = e1000_reset_mdicnfg_82580(hw); 2521213234Sjfv if (ret_val) 2522213234Sjfv DEBUGOUT("Could not reset MDICNFG based on EEPROM\n"); 2523213234Sjfv 2524200243Sjfv /* Install any alternate MAC address into RAR0 */ 2525200243Sjfv ret_val = e1000_check_alt_mac_addr_generic(hw); 2526200243Sjfv 2527200243Sjfv /* Release semaphore */ 2528200243Sjfv if (global_device_reset) 2529238148Sjfv hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2530200243Sjfv 2531200243Sjfv return ret_val; 2532200243Sjfv} 2533200243Sjfv 2534200243Sjfv/** 2535218530Sjfv * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size 2536200243Sjfv * @data: data received by reading RXPBS register 2537200243Sjfv * 2538200243Sjfv * The 82580 uses a table based approach for packet buffer allocation sizes. 2539200243Sjfv * This function converts the retrieved value into the correct table value 2540200243Sjfv * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2541200243Sjfv * 0x0 36 72 144 1 2 4 8 16 2542200243Sjfv * 0x8 35 70 140 rsv rsv rsv rsv rsv 2543200243Sjfv */ 2544200243Sjfvu16 e1000_rxpbs_adjust_82580(u32 data) 2545200243Sjfv{ 2546200243Sjfv u16 ret_val = 0; 2547200243Sjfv 2548200243Sjfv if (data < E1000_82580_RXPBS_TABLE_SIZE) 2549200243Sjfv ret_val = e1000_82580_rxpbs_table[data]; 2550200243Sjfv 2551200243Sjfv return ret_val; 2552200243Sjfv} 2553218530Sjfv 2554218530Sjfv/** 2555218530Sjfv * e1000_validate_nvm_checksum_with_offset - Validate EEPROM 2556218530Sjfv * checksum 2557218530Sjfv * @hw: pointer to the HW structure 2558218530Sjfv * @offset: offset in words of the checksum protected region 2559218530Sjfv * 2560218530Sjfv * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2561218530Sjfv * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2562218530Sjfv **/ 2563218530Sjfvs32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2564218530Sjfv{ 2565218530Sjfv s32 ret_val = E1000_SUCCESS; 2566218530Sjfv u16 checksum = 0; 2567218530Sjfv u16 i, nvm_data; 2568218530Sjfv 2569218530Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_with_offset"); 2570218530Sjfv 2571218530Sjfv for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2572218530Sjfv ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2573218530Sjfv if (ret_val) { 2574218530Sjfv DEBUGOUT("NVM Read Error\n"); 2575218530Sjfv goto out; 2576218530Sjfv } 2577218530Sjfv checksum += nvm_data; 2578218530Sjfv } 2579218530Sjfv 2580218530Sjfv if (checksum != (u16) NVM_SUM) { 2581218530Sjfv DEBUGOUT("NVM Checksum Invalid\n"); 2582218530Sjfv ret_val = -E1000_ERR_NVM; 2583218530Sjfv goto out; 2584218530Sjfv } 2585218530Sjfv 2586218530Sjfvout: 2587218530Sjfv return ret_val; 2588218530Sjfv} 2589218530Sjfv 2590218530Sjfv/** 2591218530Sjfv * e1000_update_nvm_checksum_with_offset - Update EEPROM 2592218530Sjfv * checksum 2593218530Sjfv * @hw: pointer to the HW structure 2594218530Sjfv * @offset: offset in words of the checksum protected region 2595218530Sjfv * 2596218530Sjfv * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2597218530Sjfv * up to the checksum. Then calculates the EEPROM checksum and writes the 2598218530Sjfv * value to the EEPROM. 2599218530Sjfv **/ 2600218530Sjfvs32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2601218530Sjfv{ 2602218530Sjfv s32 ret_val; 2603218530Sjfv u16 checksum = 0; 2604218530Sjfv u16 i, nvm_data; 2605218530Sjfv 2606218530Sjfv DEBUGFUNC("e1000_update_nvm_checksum_with_offset"); 2607218530Sjfv 2608218530Sjfv for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2609218530Sjfv ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2610218530Sjfv if (ret_val) { 2611218530Sjfv DEBUGOUT("NVM Read Error while updating checksum.\n"); 2612218530Sjfv goto out; 2613218530Sjfv } 2614218530Sjfv checksum += nvm_data; 2615218530Sjfv } 2616218530Sjfv checksum = (u16) NVM_SUM - checksum; 2617218530Sjfv ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2618228386Sjfv &checksum); 2619218530Sjfv if (ret_val) 2620218530Sjfv DEBUGOUT("NVM Write Error while updating checksum.\n"); 2621218530Sjfv 2622218530Sjfvout: 2623218530Sjfv return ret_val; 2624218530Sjfv} 2625218530Sjfv 2626218530Sjfv/** 2627218530Sjfv * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum 2628218530Sjfv * @hw: pointer to the HW structure 2629218530Sjfv * 2630218530Sjfv * Calculates the EEPROM section checksum by reading/adding each word of 2631218530Sjfv * the EEPROM and then verifies that the sum of the EEPROM is 2632218530Sjfv * equal to 0xBABA. 2633218530Sjfv **/ 2634218530Sjfvstatic s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw) 2635218530Sjfv{ 2636269196Sjfv s32 ret_val; 2637218530Sjfv u16 eeprom_regions_count = 1; 2638218530Sjfv u16 j, nvm_data; 2639218530Sjfv u16 nvm_offset; 2640218530Sjfv 2641218530Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_82580"); 2642218530Sjfv 2643218530Sjfv ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2644218530Sjfv if (ret_val) { 2645218530Sjfv DEBUGOUT("NVM Read Error\n"); 2646218530Sjfv goto out; 2647218530Sjfv } 2648218530Sjfv 2649218530Sjfv if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2650218530Sjfv /* if chekcsums compatibility bit is set validate checksums 2651218530Sjfv * for all 4 ports. */ 2652218530Sjfv eeprom_regions_count = 4; 2653218530Sjfv } 2654218530Sjfv 2655218530Sjfv for (j = 0; j < eeprom_regions_count; j++) { 2656218530Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2657218530Sjfv ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2658228386Sjfv nvm_offset); 2659218530Sjfv if (ret_val != E1000_SUCCESS) 2660218530Sjfv goto out; 2661218530Sjfv } 2662218530Sjfv 2663218530Sjfvout: 2664218530Sjfv return ret_val; 2665218530Sjfv} 2666218530Sjfv 2667218530Sjfv/** 2668218530Sjfv * e1000_update_nvm_checksum_82580 - Update EEPROM checksum 2669218530Sjfv * @hw: pointer to the HW structure 2670218530Sjfv * 2671218530Sjfv * Updates the EEPROM section checksums for all 4 ports by reading/adding 2672218530Sjfv * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2673218530Sjfv * checksum and writes the value to the EEPROM. 2674218530Sjfv **/ 2675218530Sjfvstatic s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw) 2676218530Sjfv{ 2677218530Sjfv s32 ret_val; 2678218530Sjfv u16 j, nvm_data; 2679218530Sjfv u16 nvm_offset; 2680218530Sjfv 2681218530Sjfv DEBUGFUNC("e1000_update_nvm_checksum_82580"); 2682218530Sjfv 2683218530Sjfv ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2684218530Sjfv if (ret_val) { 2685228386Sjfv DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n"); 2686218530Sjfv goto out; 2687218530Sjfv } 2688218530Sjfv 2689238148Sjfv if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) { 2690218530Sjfv /* set compatibility bit to validate checksums appropriately */ 2691218530Sjfv nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2692218530Sjfv ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2693228386Sjfv &nvm_data); 2694218530Sjfv if (ret_val) { 2695228386Sjfv DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n"); 2696218530Sjfv goto out; 2697218530Sjfv } 2698218530Sjfv } 2699218530Sjfv 2700218530Sjfv for (j = 0; j < 4; j++) { 2701218530Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2702218530Sjfv ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2703228386Sjfv if (ret_val) 2704218530Sjfv goto out; 2705218530Sjfv } 2706218530Sjfv 2707218530Sjfvout: 2708218530Sjfv return ret_val; 2709218530Sjfv} 2710218530Sjfv 2711218530Sjfv/** 2712218530Sjfv * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum 2713218530Sjfv * @hw: pointer to the HW structure 2714218530Sjfv * 2715218530Sjfv * Calculates the EEPROM section checksum by reading/adding each word of 2716218530Sjfv * the EEPROM and then verifies that the sum of the EEPROM is 2717218530Sjfv * equal to 0xBABA. 2718218530Sjfv **/ 2719218530Sjfvstatic s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw) 2720218530Sjfv{ 2721218530Sjfv s32 ret_val = E1000_SUCCESS; 2722218530Sjfv u16 j; 2723218530Sjfv u16 nvm_offset; 2724218530Sjfv 2725218530Sjfv DEBUGFUNC("e1000_validate_nvm_checksum_i350"); 2726218530Sjfv 2727218530Sjfv for (j = 0; j < 4; j++) { 2728218530Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2729218530Sjfv ret_val = e1000_validate_nvm_checksum_with_offset(hw, 2730228386Sjfv nvm_offset); 2731218530Sjfv if (ret_val != E1000_SUCCESS) 2732218530Sjfv goto out; 2733218530Sjfv } 2734218530Sjfv 2735218530Sjfvout: 2736218530Sjfv return ret_val; 2737218530Sjfv} 2738218530Sjfv 2739218530Sjfv/** 2740218530Sjfv * e1000_update_nvm_checksum_i350 - Update EEPROM checksum 2741218530Sjfv * @hw: pointer to the HW structure 2742218530Sjfv * 2743218530Sjfv * Updates the EEPROM section checksums for all 4 ports by reading/adding 2744218530Sjfv * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2745218530Sjfv * checksum and writes the value to the EEPROM. 2746218530Sjfv **/ 2747218530Sjfvstatic s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw) 2748218530Sjfv{ 2749218530Sjfv s32 ret_val = E1000_SUCCESS; 2750218530Sjfv u16 j; 2751218530Sjfv u16 nvm_offset; 2752218530Sjfv 2753218530Sjfv DEBUGFUNC("e1000_update_nvm_checksum_i350"); 2754218530Sjfv 2755218530Sjfv for (j = 0; j < 4; j++) { 2756218530Sjfv nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2757218530Sjfv ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset); 2758218530Sjfv if (ret_val != E1000_SUCCESS) 2759218530Sjfv goto out; 2760218530Sjfv } 2761218530Sjfv 2762218530Sjfvout: 2763218530Sjfv return ret_val; 2764218530Sjfv} 2765218530Sjfv 2766218530Sjfv/** 2767256200Sjfv * __e1000_access_emi_reg - Read/write EMI register 2768256200Sjfv * @hw: pointer to the HW structure 2769256200Sjfv * @addr: EMI address to program 2770256200Sjfv * @data: pointer to value to read/write from/to the EMI address 2771256200Sjfv * @read: boolean flag to indicate read or write 2772256200Sjfv **/ 2773256200Sjfvstatic s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address, 2774256200Sjfv u16 *data, bool read) 2775256200Sjfv{ 2776269196Sjfv s32 ret_val; 2777256200Sjfv 2778256200Sjfv DEBUGFUNC("__e1000_access_emi_reg"); 2779256200Sjfv 2780256200Sjfv ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2781256200Sjfv if (ret_val) 2782256200Sjfv return ret_val; 2783256200Sjfv 2784256200Sjfv if (read) 2785256200Sjfv ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2786256200Sjfv else 2787256200Sjfv ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2788256200Sjfv 2789256200Sjfv return ret_val; 2790256200Sjfv} 2791256200Sjfv 2792256200Sjfv/** 2793256200Sjfv * e1000_read_emi_reg - Read Extended Management Interface register 2794256200Sjfv * @hw: pointer to the HW structure 2795256200Sjfv * @addr: EMI address to program 2796256200Sjfv * @data: value to be read from the EMI address 2797256200Sjfv **/ 2798256200Sjfvs32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2799256200Sjfv{ 2800256200Sjfv DEBUGFUNC("e1000_read_emi_reg"); 2801256200Sjfv 2802256200Sjfv return __e1000_access_emi_reg(hw, addr, data, TRUE); 2803256200Sjfv} 2804256200Sjfv 2805256200Sjfv/** 2806269196Sjfv * e1000_initialize_M88E1512_phy - Initialize M88E1512 PHY 2807269196Sjfv * @hw: pointer to the HW structure 2808269196Sjfv * 2809269196Sjfv * Initialize Marverl 1512 to work correctly with Avoton. 2810269196Sjfv **/ 2811269196Sjfvs32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw) 2812269196Sjfv{ 2813269196Sjfv struct e1000_phy_info *phy = &hw->phy; 2814269196Sjfv s32 ret_val = E1000_SUCCESS; 2815269196Sjfv 2816269196Sjfv DEBUGFUNC("e1000_initialize_M88E1512_phy"); 2817269196Sjfv 2818269196Sjfv /* Check if this is correct PHY. */ 2819269196Sjfv if (phy->id != M88E1512_E_PHY_ID) 2820269196Sjfv goto out; 2821269196Sjfv 2822269196Sjfv /* Switch to PHY page 0xFF. */ 2823269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2824269196Sjfv if (ret_val) 2825269196Sjfv goto out; 2826269196Sjfv 2827269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2828269196Sjfv if (ret_val) 2829269196Sjfv goto out; 2830269196Sjfv 2831269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2832269196Sjfv if (ret_val) 2833269196Sjfv goto out; 2834269196Sjfv 2835269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2836269196Sjfv if (ret_val) 2837269196Sjfv goto out; 2838269196Sjfv 2839269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2840269196Sjfv if (ret_val) 2841269196Sjfv goto out; 2842269196Sjfv 2843269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2844269196Sjfv if (ret_val) 2845269196Sjfv goto out; 2846269196Sjfv 2847269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2848269196Sjfv if (ret_val) 2849269196Sjfv goto out; 2850269196Sjfv 2851269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C); 2852269196Sjfv if (ret_val) 2853269196Sjfv goto out; 2854269196Sjfv 2855269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2856269196Sjfv if (ret_val) 2857269196Sjfv goto out; 2858269196Sjfv 2859269196Sjfv /* Switch to PHY page 0xFB. */ 2860269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2861269196Sjfv if (ret_val) 2862269196Sjfv goto out; 2863269196Sjfv 2864269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D); 2865269196Sjfv if (ret_val) 2866269196Sjfv goto out; 2867269196Sjfv 2868269196Sjfv /* Switch to PHY page 0x12. */ 2869269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2870269196Sjfv if (ret_val) 2871269196Sjfv goto out; 2872269196Sjfv 2873269196Sjfv /* Change mode to SGMII-to-Copper */ 2874269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2875269196Sjfv if (ret_val) 2876269196Sjfv goto out; 2877269196Sjfv 2878269196Sjfv /* Return the PHY to page 0. */ 2879269196Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2880269196Sjfv if (ret_val) 2881269196Sjfv goto out; 2882269196Sjfv 2883269196Sjfv ret_val = phy->ops.commit(hw); 2884269196Sjfv if (ret_val) { 2885269196Sjfv DEBUGOUT("Error committing the PHY changes\n"); 2886269196Sjfv return ret_val; 2887269196Sjfv } 2888269196Sjfv 2889269196Sjfv msec_delay(1000); 2890269196Sjfvout: 2891269196Sjfv return ret_val; 2892269196Sjfv} 2893269196Sjfv 2894269196Sjfv/** 2895218530Sjfv * e1000_set_eee_i350 - Enable/disable EEE support 2896218530Sjfv * @hw: pointer to the HW structure 2897218530Sjfv * 2898218530Sjfv * Enable/disable EEE based on setting in dev_spec structure. 2899218530Sjfv * 2900218530Sjfv **/ 2901218530Sjfvs32 e1000_set_eee_i350(struct e1000_hw *hw) 2902218530Sjfv{ 2903228386Sjfv u32 ipcnfg, eeer; 2904218530Sjfv 2905218530Sjfv DEBUGFUNC("e1000_set_eee_i350"); 2906218530Sjfv 2907228386Sjfv if ((hw->mac.type < e1000_i350) || 2908228386Sjfv (hw->phy.media_type != e1000_media_type_copper)) 2909218530Sjfv goto out; 2910218530Sjfv ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG); 2911218530Sjfv eeer = E1000_READ_REG(hw, E1000_EEER); 2912218530Sjfv 2913218530Sjfv /* enable or disable per user setting */ 2914218530Sjfv if (!(hw->dev_spec._82575.eee_disable)) { 2915247064Sjfv u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU); 2916247064Sjfv 2917228386Sjfv ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2918228386Sjfv eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2919228386Sjfv E1000_EEER_LPI_FC); 2920218530Sjfv 2921247064Sjfv /* This bit should not be set in normal operation. */ 2922247064Sjfv if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2923247064Sjfv DEBUGOUT("LPI Clock Stop Bit should not be set!\n"); 2924218530Sjfv } else { 2925228386Sjfv ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN); 2926228386Sjfv eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2927228386Sjfv E1000_EEER_LPI_FC); 2928218530Sjfv } 2929218530Sjfv E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg); 2930218530Sjfv E1000_WRITE_REG(hw, E1000_EEER, eeer); 2931228386Sjfv E1000_READ_REG(hw, E1000_IPCNFG); 2932228386Sjfv E1000_READ_REG(hw, E1000_EEER); 2933218530Sjfvout: 2934218530Sjfv 2935269196Sjfv return E1000_SUCCESS; 2936218530Sjfv} 2937228386Sjfv 2938256200Sjfv/** 2939256200Sjfv * e1000_set_eee_i354 - Enable/disable EEE support 2940256200Sjfv * @hw: pointer to the HW structure 2941256200Sjfv * 2942256200Sjfv * Enable/disable EEE legacy mode based on setting in dev_spec structure. 2943256200Sjfv * 2944256200Sjfv **/ 2945256200Sjfvs32 e1000_set_eee_i354(struct e1000_hw *hw) 2946256200Sjfv{ 2947256200Sjfv struct e1000_phy_info *phy = &hw->phy; 2948256200Sjfv s32 ret_val = E1000_SUCCESS; 2949256200Sjfv u16 phy_data; 2950256200Sjfv 2951256200Sjfv DEBUGFUNC("e1000_set_eee_i354"); 2952256200Sjfv 2953256200Sjfv if ((hw->phy.media_type != e1000_media_type_copper) || 2954256200Sjfv ((phy->id != M88E1543_E_PHY_ID) && 2955256200Sjfv (phy->id != M88E1512_E_PHY_ID))) 2956256200Sjfv goto out; 2957256200Sjfv 2958256200Sjfv if (!hw->dev_spec._82575.eee_disable) { 2959256200Sjfv /* Switch to PHY page 18. */ 2960256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 2961256200Sjfv if (ret_val) 2962256200Sjfv goto out; 2963256200Sjfv 2964256200Sjfv ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2965256200Sjfv &phy_data); 2966256200Sjfv if (ret_val) 2967256200Sjfv goto out; 2968256200Sjfv 2969256200Sjfv phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2970256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2971256200Sjfv phy_data); 2972256200Sjfv if (ret_val) 2973256200Sjfv goto out; 2974256200Sjfv 2975256200Sjfv /* Return the PHY to page 0. */ 2976256200Sjfv ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2977256200Sjfv if (ret_val) 2978256200Sjfv goto out; 2979256200Sjfv 2980256200Sjfv /* Turn on EEE advertisement. */ 2981256200Sjfv ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2982256200Sjfv E1000_EEE_ADV_DEV_I354, 2983256200Sjfv &phy_data); 2984256200Sjfv if (ret_val) 2985256200Sjfv goto out; 2986256200Sjfv 2987256200Sjfv phy_data |= E1000_EEE_ADV_100_SUPPORTED | 2988256200Sjfv E1000_EEE_ADV_1000_SUPPORTED; 2989256200Sjfv ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2990256200Sjfv E1000_EEE_ADV_DEV_I354, 2991256200Sjfv phy_data); 2992256200Sjfv } else { 2993256200Sjfv /* Turn off EEE advertisement. */ 2994256200Sjfv ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2995256200Sjfv E1000_EEE_ADV_DEV_I354, 2996256200Sjfv &phy_data); 2997256200Sjfv if (ret_val) 2998256200Sjfv goto out; 2999256200Sjfv 3000256200Sjfv phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 3001256200Sjfv E1000_EEE_ADV_1000_SUPPORTED); 3002256200Sjfv ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 3003256200Sjfv E1000_EEE_ADV_DEV_I354, 3004256200Sjfv phy_data); 3005256200Sjfv } 3006256200Sjfv 3007256200Sjfvout: 3008256200Sjfv return ret_val; 3009256200Sjfv} 3010256200Sjfv 3011256200Sjfv/** 3012256200Sjfv * e1000_get_eee_status_i354 - Get EEE status 3013256200Sjfv * @hw: pointer to the HW structure 3014256200Sjfv * @status: EEE status 3015256200Sjfv * 3016256200Sjfv * Get EEE status by guessing based on whether Tx or Rx LPI indications have 3017256200Sjfv * been received. 3018256200Sjfv **/ 3019256200Sjfvs32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status) 3020256200Sjfv{ 3021256200Sjfv struct e1000_phy_info *phy = &hw->phy; 3022256200Sjfv s32 ret_val = E1000_SUCCESS; 3023256200Sjfv u16 phy_data; 3024256200Sjfv 3025256200Sjfv DEBUGFUNC("e1000_get_eee_status_i354"); 3026256200Sjfv 3027256200Sjfv /* Check if EEE is supported on this device. */ 3028256200Sjfv if ((hw->phy.media_type != e1000_media_type_copper) || 3029256200Sjfv ((phy->id != M88E1543_E_PHY_ID) && 3030256200Sjfv (phy->id != M88E1512_E_PHY_ID))) 3031256200Sjfv goto out; 3032256200Sjfv 3033256200Sjfv ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 3034256200Sjfv E1000_PCS_STATUS_DEV_I354, 3035256200Sjfv &phy_data); 3036256200Sjfv if (ret_val) 3037256200Sjfv goto out; 3038256200Sjfv 3039256200Sjfv *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 3040256200Sjfv E1000_PCS_STATUS_RX_LPI_RCVD) ? TRUE : FALSE; 3041256200Sjfv 3042256200Sjfvout: 3043256200Sjfv return ret_val; 3044256200Sjfv} 3045256200Sjfv 3046228386Sjfv/* Due to a hw errata, if the host tries to configure the VFTA register 3047228386Sjfv * while performing queries from the BMC or DMA, then the VFTA in some 3048228386Sjfv * cases won't be written. 3049228386Sjfv */ 3050228386Sjfv 3051228386Sjfv/** 3052228386Sjfv * e1000_clear_vfta_i350 - Clear VLAN filter table 3053228386Sjfv * @hw: pointer to the HW structure 3054228386Sjfv * 3055228386Sjfv * Clears the register array which contains the VLAN filter table by 3056228386Sjfv * setting all the values to 0. 3057228386Sjfv **/ 3058228386Sjfvvoid e1000_clear_vfta_i350(struct e1000_hw *hw) 3059228386Sjfv{ 3060228386Sjfv u32 offset; 3061228386Sjfv int i; 3062228386Sjfv 3063228386Sjfv DEBUGFUNC("e1000_clear_vfta_350"); 3064228386Sjfv 3065228386Sjfv for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 3066228386Sjfv for (i = 0; i < 10; i++) 3067228386Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 3068228386Sjfv 3069228386Sjfv E1000_WRITE_FLUSH(hw); 3070228386Sjfv } 3071228386Sjfv} 3072228386Sjfv 3073228386Sjfv/** 3074228386Sjfv * e1000_write_vfta_i350 - Write value to VLAN filter table 3075228386Sjfv * @hw: pointer to the HW structure 3076228386Sjfv * @offset: register offset in VLAN filter table 3077228386Sjfv * @value: register value written to VLAN filter table 3078228386Sjfv * 3079228386Sjfv * Writes value at the given offset in the register array which stores 3080228386Sjfv * the VLAN filter table. 3081228386Sjfv **/ 3082228386Sjfvvoid e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 3083228386Sjfv{ 3084228386Sjfv int i; 3085228386Sjfv 3086228386Sjfv DEBUGFUNC("e1000_write_vfta_350"); 3087228386Sjfv 3088228386Sjfv for (i = 0; i < 10; i++) 3089228386Sjfv E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 3090228386Sjfv 3091228386Sjfv E1000_WRITE_FLUSH(hw); 3092228386Sjfv} 3093228386Sjfv 3094228386Sjfv 3095228386Sjfv/** 3096228386Sjfv * e1000_set_i2c_bb - Enable I2C bit-bang 3097228386Sjfv * @hw: pointer to the HW structure 3098228386Sjfv * 3099228386Sjfv * Enable I2C bit-bang interface 3100228386Sjfv * 3101228386Sjfv **/ 3102228386Sjfvs32 e1000_set_i2c_bb(struct e1000_hw *hw) 3103228386Sjfv{ 3104228386Sjfv s32 ret_val = E1000_SUCCESS; 3105228386Sjfv u32 ctrl_ext, i2cparams; 3106228386Sjfv 3107228386Sjfv DEBUGFUNC("e1000_set_i2c_bb"); 3108228386Sjfv 3109228386Sjfv ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3110228386Sjfv ctrl_ext |= E1000_CTRL_I2C_ENA; 3111228386Sjfv E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3112228386Sjfv E1000_WRITE_FLUSH(hw); 3113228386Sjfv 3114228386Sjfv i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS); 3115228386Sjfv i2cparams |= E1000_I2CBB_EN; 3116228386Sjfv i2cparams |= E1000_I2C_DATA_OE_N; 3117228386Sjfv i2cparams |= E1000_I2C_CLK_OE_N; 3118228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams); 3119228386Sjfv E1000_WRITE_FLUSH(hw); 3120228386Sjfv 3121228386Sjfv return ret_val; 3122228386Sjfv} 3123228386Sjfv 3124228386Sjfv/** 3125228386Sjfv * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C 3126228386Sjfv * @hw: pointer to hardware structure 3127228386Sjfv * @byte_offset: byte offset to read 3128238148Sjfv * @dev_addr: device address 3129228386Sjfv * @data: value read 3130228386Sjfv * 3131228386Sjfv * Performs byte read operation over I2C interface at 3132228386Sjfv * a specified device address. 3133228386Sjfv **/ 3134228386Sjfvs32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 3135228386Sjfv u8 dev_addr, u8 *data) 3136228386Sjfv{ 3137228386Sjfv s32 status = E1000_SUCCESS; 3138228386Sjfv u32 max_retry = 10; 3139228386Sjfv u32 retry = 1; 3140228386Sjfv u16 swfw_mask = 0; 3141228386Sjfv 3142238148Sjfv bool nack = TRUE; 3143228386Sjfv 3144228386Sjfv DEBUGFUNC("e1000_read_i2c_byte_generic"); 3145228386Sjfv 3146228386Sjfv swfw_mask = E1000_SWFW_PHY0_SM; 3147228386Sjfv 3148228386Sjfv do { 3149238148Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 3150228386Sjfv != E1000_SUCCESS) { 3151228386Sjfv status = E1000_ERR_SWFW_SYNC; 3152228386Sjfv goto read_byte_out; 3153228386Sjfv } 3154228386Sjfv 3155228386Sjfv e1000_i2c_start(hw); 3156228386Sjfv 3157228386Sjfv /* Device Address and write indication */ 3158228386Sjfv status = e1000_clock_out_i2c_byte(hw, dev_addr); 3159228386Sjfv if (status != E1000_SUCCESS) 3160228386Sjfv goto fail; 3161228386Sjfv 3162228386Sjfv status = e1000_get_i2c_ack(hw); 3163228386Sjfv if (status != E1000_SUCCESS) 3164228386Sjfv goto fail; 3165228386Sjfv 3166228386Sjfv status = e1000_clock_out_i2c_byte(hw, byte_offset); 3167228386Sjfv if (status != E1000_SUCCESS) 3168228386Sjfv goto fail; 3169228386Sjfv 3170228386Sjfv status = e1000_get_i2c_ack(hw); 3171228386Sjfv if (status != E1000_SUCCESS) 3172228386Sjfv goto fail; 3173228386Sjfv 3174228386Sjfv e1000_i2c_start(hw); 3175228386Sjfv 3176228386Sjfv /* Device Address and read indication */ 3177228386Sjfv status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 3178228386Sjfv if (status != E1000_SUCCESS) 3179228386Sjfv goto fail; 3180228386Sjfv 3181228386Sjfv status = e1000_get_i2c_ack(hw); 3182228386Sjfv if (status != E1000_SUCCESS) 3183228386Sjfv goto fail; 3184228386Sjfv 3185228386Sjfv status = e1000_clock_in_i2c_byte(hw, data); 3186228386Sjfv if (status != E1000_SUCCESS) 3187228386Sjfv goto fail; 3188228386Sjfv 3189228386Sjfv status = e1000_clock_out_i2c_bit(hw, nack); 3190228386Sjfv if (status != E1000_SUCCESS) 3191228386Sjfv goto fail; 3192228386Sjfv 3193228386Sjfv e1000_i2c_stop(hw); 3194228386Sjfv break; 3195228386Sjfv 3196228386Sjfvfail: 3197238148Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3198228386Sjfv msec_delay(100); 3199228386Sjfv e1000_i2c_bus_clear(hw); 3200228386Sjfv retry++; 3201228386Sjfv if (retry < max_retry) 3202228386Sjfv DEBUGOUT("I2C byte read error - Retrying.\n"); 3203228386Sjfv else 3204228386Sjfv DEBUGOUT("I2C byte read error.\n"); 3205228386Sjfv 3206228386Sjfv } while (retry < max_retry); 3207228386Sjfv 3208238148Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3209228386Sjfv 3210228386Sjfvread_byte_out: 3211228386Sjfv 3212228386Sjfv return status; 3213228386Sjfv} 3214228386Sjfv 3215228386Sjfv/** 3216228386Sjfv * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C 3217228386Sjfv * @hw: pointer to hardware structure 3218228386Sjfv * @byte_offset: byte offset to write 3219238148Sjfv * @dev_addr: device address 3220228386Sjfv * @data: value to write 3221228386Sjfv * 3222228386Sjfv * Performs byte write operation over I2C interface at 3223228386Sjfv * a specified device address. 3224228386Sjfv **/ 3225228386Sjfvs32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset, 3226228386Sjfv u8 dev_addr, u8 data) 3227228386Sjfv{ 3228228386Sjfv s32 status = E1000_SUCCESS; 3229228386Sjfv u32 max_retry = 1; 3230228386Sjfv u32 retry = 0; 3231228386Sjfv u16 swfw_mask = 0; 3232228386Sjfv 3233228386Sjfv DEBUGFUNC("e1000_write_i2c_byte_generic"); 3234228386Sjfv 3235228386Sjfv swfw_mask = E1000_SWFW_PHY0_SM; 3236228386Sjfv 3237238148Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) { 3238228386Sjfv status = E1000_ERR_SWFW_SYNC; 3239228386Sjfv goto write_byte_out; 3240228386Sjfv } 3241228386Sjfv 3242228386Sjfv do { 3243228386Sjfv e1000_i2c_start(hw); 3244228386Sjfv 3245228386Sjfv status = e1000_clock_out_i2c_byte(hw, dev_addr); 3246228386Sjfv if (status != E1000_SUCCESS) 3247228386Sjfv goto fail; 3248228386Sjfv 3249228386Sjfv status = e1000_get_i2c_ack(hw); 3250228386Sjfv if (status != E1000_SUCCESS) 3251228386Sjfv goto fail; 3252228386Sjfv 3253228386Sjfv status = e1000_clock_out_i2c_byte(hw, byte_offset); 3254228386Sjfv if (status != E1000_SUCCESS) 3255228386Sjfv goto fail; 3256228386Sjfv 3257228386Sjfv status = e1000_get_i2c_ack(hw); 3258228386Sjfv if (status != E1000_SUCCESS) 3259228386Sjfv goto fail; 3260228386Sjfv 3261228386Sjfv status = e1000_clock_out_i2c_byte(hw, data); 3262228386Sjfv if (status != E1000_SUCCESS) 3263228386Sjfv goto fail; 3264228386Sjfv 3265228386Sjfv status = e1000_get_i2c_ack(hw); 3266228386Sjfv if (status != E1000_SUCCESS) 3267228386Sjfv goto fail; 3268228386Sjfv 3269228386Sjfv e1000_i2c_stop(hw); 3270228386Sjfv break; 3271228386Sjfv 3272228386Sjfvfail: 3273228386Sjfv e1000_i2c_bus_clear(hw); 3274228386Sjfv retry++; 3275228386Sjfv if (retry < max_retry) 3276228386Sjfv DEBUGOUT("I2C byte write error - Retrying.\n"); 3277228386Sjfv else 3278228386Sjfv DEBUGOUT("I2C byte write error.\n"); 3279228386Sjfv } while (retry < max_retry); 3280228386Sjfv 3281238148Sjfv hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3282228386Sjfv 3283228386Sjfvwrite_byte_out: 3284228386Sjfv 3285228386Sjfv return status; 3286228386Sjfv} 3287228386Sjfv 3288228386Sjfv/** 3289228386Sjfv * e1000_i2c_start - Sets I2C start condition 3290228386Sjfv * @hw: pointer to hardware structure 3291228386Sjfv * 3292228386Sjfv * Sets I2C start condition (High -> Low on SDA while SCL is High) 3293228386Sjfv **/ 3294228386Sjfvstatic void e1000_i2c_start(struct e1000_hw *hw) 3295228386Sjfv{ 3296228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3297228386Sjfv 3298228386Sjfv DEBUGFUNC("e1000_i2c_start"); 3299228386Sjfv 3300228386Sjfv /* Start condition must begin with data and clock high */ 3301228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 1); 3302228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3303228386Sjfv 3304228386Sjfv /* Setup time for start condition (4.7us) */ 3305228386Sjfv usec_delay(E1000_I2C_T_SU_STA); 3306228386Sjfv 3307228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 0); 3308228386Sjfv 3309228386Sjfv /* Hold time for start condition (4us) */ 3310228386Sjfv usec_delay(E1000_I2C_T_HD_STA); 3311228386Sjfv 3312228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3313228386Sjfv 3314228386Sjfv /* Minimum low period of clock is 4.7 us */ 3315228386Sjfv usec_delay(E1000_I2C_T_LOW); 3316228386Sjfv 3317228386Sjfv} 3318228386Sjfv 3319228386Sjfv/** 3320228386Sjfv * e1000_i2c_stop - Sets I2C stop condition 3321228386Sjfv * @hw: pointer to hardware structure 3322228386Sjfv * 3323228386Sjfv * Sets I2C stop condition (Low -> High on SDA while SCL is High) 3324228386Sjfv **/ 3325228386Sjfvstatic void e1000_i2c_stop(struct e1000_hw *hw) 3326228386Sjfv{ 3327228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3328228386Sjfv 3329228386Sjfv DEBUGFUNC("e1000_i2c_stop"); 3330228386Sjfv 3331228386Sjfv /* Stop condition must begin with data low and clock high */ 3332228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 0); 3333228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3334228386Sjfv 3335228386Sjfv /* Setup time for stop condition (4us) */ 3336228386Sjfv usec_delay(E1000_I2C_T_SU_STO); 3337228386Sjfv 3338228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 1); 3339228386Sjfv 3340228386Sjfv /* bus free time between stop and start (4.7us)*/ 3341228386Sjfv usec_delay(E1000_I2C_T_BUF); 3342228386Sjfv} 3343228386Sjfv 3344228386Sjfv/** 3345228386Sjfv * e1000_clock_in_i2c_byte - Clocks in one byte via I2C 3346228386Sjfv * @hw: pointer to hardware structure 3347228386Sjfv * @data: data byte to clock in 3348228386Sjfv * 3349228386Sjfv * Clocks in one byte data via I2C data/clock 3350228386Sjfv **/ 3351228386Sjfvstatic s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data) 3352228386Sjfv{ 3353228386Sjfv s32 i; 3354228386Sjfv bool bit = 0; 3355228386Sjfv 3356228386Sjfv DEBUGFUNC("e1000_clock_in_i2c_byte"); 3357228386Sjfv 3358228386Sjfv *data = 0; 3359228386Sjfv for (i = 7; i >= 0; i--) { 3360228386Sjfv e1000_clock_in_i2c_bit(hw, &bit); 3361228386Sjfv *data |= bit << i; 3362228386Sjfv } 3363228386Sjfv 3364228386Sjfv return E1000_SUCCESS; 3365228386Sjfv} 3366228386Sjfv 3367228386Sjfv/** 3368228386Sjfv * e1000_clock_out_i2c_byte - Clocks out one byte via I2C 3369228386Sjfv * @hw: pointer to hardware structure 3370228386Sjfv * @data: data byte clocked out 3371228386Sjfv * 3372228386Sjfv * Clocks out one byte data via I2C data/clock 3373228386Sjfv **/ 3374228386Sjfvstatic s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data) 3375228386Sjfv{ 3376228386Sjfv s32 status = E1000_SUCCESS; 3377228386Sjfv s32 i; 3378228386Sjfv u32 i2cctl; 3379228386Sjfv bool bit = 0; 3380228386Sjfv 3381228386Sjfv DEBUGFUNC("e1000_clock_out_i2c_byte"); 3382228386Sjfv 3383228386Sjfv for (i = 7; i >= 0; i--) { 3384228386Sjfv bit = (data >> i) & 0x1; 3385228386Sjfv status = e1000_clock_out_i2c_bit(hw, bit); 3386228386Sjfv 3387228386Sjfv if (status != E1000_SUCCESS) 3388228386Sjfv break; 3389228386Sjfv } 3390228386Sjfv 3391228386Sjfv /* Release SDA line (set high) */ 3392228386Sjfv i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3393228386Sjfv 3394228386Sjfv i2cctl |= E1000_I2C_DATA_OE_N; 3395228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl); 3396228386Sjfv E1000_WRITE_FLUSH(hw); 3397228386Sjfv 3398228386Sjfv return status; 3399228386Sjfv} 3400228386Sjfv 3401228386Sjfv/** 3402228386Sjfv * e1000_get_i2c_ack - Polls for I2C ACK 3403228386Sjfv * @hw: pointer to hardware structure 3404228386Sjfv * 3405228386Sjfv * Clocks in/out one bit via I2C data/clock 3406228386Sjfv **/ 3407228386Sjfvstatic s32 e1000_get_i2c_ack(struct e1000_hw *hw) 3408228386Sjfv{ 3409228386Sjfv s32 status = E1000_SUCCESS; 3410228386Sjfv u32 i = 0; 3411228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3412228386Sjfv u32 timeout = 10; 3413238148Sjfv bool ack = TRUE; 3414228386Sjfv 3415228386Sjfv DEBUGFUNC("e1000_get_i2c_ack"); 3416228386Sjfv 3417228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3418228386Sjfv 3419228386Sjfv /* Minimum high period of clock is 4us */ 3420228386Sjfv usec_delay(E1000_I2C_T_HIGH); 3421228386Sjfv 3422228386Sjfv /* Wait until SCL returns high */ 3423228386Sjfv for (i = 0; i < timeout; i++) { 3424228386Sjfv usec_delay(1); 3425228386Sjfv i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3426228386Sjfv if (i2cctl & E1000_I2C_CLK_IN) 3427228386Sjfv break; 3428228386Sjfv } 3429228386Sjfv if (!(i2cctl & E1000_I2C_CLK_IN)) 3430228386Sjfv return E1000_ERR_I2C; 3431228386Sjfv 3432228386Sjfv ack = e1000_get_i2c_data(&i2cctl); 3433238148Sjfv if (ack) { 3434228386Sjfv DEBUGOUT("I2C ack was not received.\n"); 3435228386Sjfv status = E1000_ERR_I2C; 3436228386Sjfv } 3437228386Sjfv 3438228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3439228386Sjfv 3440228386Sjfv /* Minimum low period of clock is 4.7 us */ 3441228386Sjfv usec_delay(E1000_I2C_T_LOW); 3442228386Sjfv 3443228386Sjfv return status; 3444228386Sjfv} 3445228386Sjfv 3446228386Sjfv/** 3447228386Sjfv * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 3448228386Sjfv * @hw: pointer to hardware structure 3449228386Sjfv * @data: read data value 3450228386Sjfv * 3451228386Sjfv * Clocks in one bit via I2C data/clock 3452228386Sjfv **/ 3453228386Sjfvstatic s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data) 3454228386Sjfv{ 3455228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3456228386Sjfv 3457228386Sjfv DEBUGFUNC("e1000_clock_in_i2c_bit"); 3458228386Sjfv 3459228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3460228386Sjfv 3461228386Sjfv /* Minimum high period of clock is 4us */ 3462228386Sjfv usec_delay(E1000_I2C_T_HIGH); 3463228386Sjfv 3464228386Sjfv i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3465228386Sjfv *data = e1000_get_i2c_data(&i2cctl); 3466228386Sjfv 3467228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3468228386Sjfv 3469228386Sjfv /* Minimum low period of clock is 4.7 us */ 3470228386Sjfv usec_delay(E1000_I2C_T_LOW); 3471228386Sjfv 3472228386Sjfv return E1000_SUCCESS; 3473228386Sjfv} 3474228386Sjfv 3475228386Sjfv/** 3476228386Sjfv * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 3477228386Sjfv * @hw: pointer to hardware structure 3478228386Sjfv * @data: data value to write 3479228386Sjfv * 3480228386Sjfv * Clocks out one bit via I2C data/clock 3481228386Sjfv **/ 3482228386Sjfvstatic s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data) 3483228386Sjfv{ 3484228386Sjfv s32 status; 3485228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3486228386Sjfv 3487228386Sjfv DEBUGFUNC("e1000_clock_out_i2c_bit"); 3488228386Sjfv 3489228386Sjfv status = e1000_set_i2c_data(hw, &i2cctl, data); 3490228386Sjfv if (status == E1000_SUCCESS) { 3491228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3492228386Sjfv 3493228386Sjfv /* Minimum high period of clock is 4us */ 3494228386Sjfv usec_delay(E1000_I2C_T_HIGH); 3495228386Sjfv 3496228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3497228386Sjfv 3498228386Sjfv /* Minimum low period of clock is 4.7 us. 3499228386Sjfv * This also takes care of the data hold time. 3500228386Sjfv */ 3501228386Sjfv usec_delay(E1000_I2C_T_LOW); 3502228386Sjfv } else { 3503228386Sjfv status = E1000_ERR_I2C; 3504228386Sjfv DEBUGOUT1("I2C data was not set to %X\n", data); 3505228386Sjfv } 3506228386Sjfv 3507228386Sjfv return status; 3508228386Sjfv} 3509228386Sjfv/** 3510228386Sjfv * e1000_raise_i2c_clk - Raises the I2C SCL clock 3511228386Sjfv * @hw: pointer to hardware structure 3512228386Sjfv * @i2cctl: Current value of I2CCTL register 3513228386Sjfv * 3514228386Sjfv * Raises the I2C clock line '0'->'1' 3515228386Sjfv **/ 3516228386Sjfvstatic void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3517228386Sjfv{ 3518228386Sjfv DEBUGFUNC("e1000_raise_i2c_clk"); 3519228386Sjfv 3520228386Sjfv *i2cctl |= E1000_I2C_CLK_OUT; 3521228386Sjfv *i2cctl &= ~E1000_I2C_CLK_OE_N; 3522228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3523228386Sjfv E1000_WRITE_FLUSH(hw); 3524228386Sjfv 3525228386Sjfv /* SCL rise time (1000ns) */ 3526228386Sjfv usec_delay(E1000_I2C_T_RISE); 3527228386Sjfv} 3528228386Sjfv 3529228386Sjfv/** 3530228386Sjfv * e1000_lower_i2c_clk - Lowers the I2C SCL clock 3531228386Sjfv * @hw: pointer to hardware structure 3532228386Sjfv * @i2cctl: Current value of I2CCTL register 3533228386Sjfv * 3534228386Sjfv * Lowers the I2C clock line '1'->'0' 3535228386Sjfv **/ 3536228386Sjfvstatic void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl) 3537228386Sjfv{ 3538228386Sjfv 3539228386Sjfv DEBUGFUNC("e1000_lower_i2c_clk"); 3540228386Sjfv 3541228386Sjfv *i2cctl &= ~E1000_I2C_CLK_OUT; 3542228386Sjfv *i2cctl &= ~E1000_I2C_CLK_OE_N; 3543228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3544228386Sjfv E1000_WRITE_FLUSH(hw); 3545228386Sjfv 3546228386Sjfv /* SCL fall time (300ns) */ 3547228386Sjfv usec_delay(E1000_I2C_T_FALL); 3548228386Sjfv} 3549228386Sjfv 3550228386Sjfv/** 3551228386Sjfv * e1000_set_i2c_data - Sets the I2C data bit 3552228386Sjfv * @hw: pointer to hardware structure 3553228386Sjfv * @i2cctl: Current value of I2CCTL register 3554228386Sjfv * @data: I2C data value (0 or 1) to set 3555228386Sjfv * 3556228386Sjfv * Sets the I2C data bit 3557228386Sjfv **/ 3558228386Sjfvstatic s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data) 3559228386Sjfv{ 3560228386Sjfv s32 status = E1000_SUCCESS; 3561228386Sjfv 3562228386Sjfv DEBUGFUNC("e1000_set_i2c_data"); 3563228386Sjfv 3564228386Sjfv if (data) 3565228386Sjfv *i2cctl |= E1000_I2C_DATA_OUT; 3566228386Sjfv else 3567228386Sjfv *i2cctl &= ~E1000_I2C_DATA_OUT; 3568228386Sjfv 3569228386Sjfv *i2cctl &= ~E1000_I2C_DATA_OE_N; 3570228386Sjfv *i2cctl |= E1000_I2C_CLK_OE_N; 3571228386Sjfv E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl); 3572228386Sjfv E1000_WRITE_FLUSH(hw); 3573228386Sjfv 3574228386Sjfv /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 3575228386Sjfv usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA); 3576228386Sjfv 3577228386Sjfv *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3578228386Sjfv if (data != e1000_get_i2c_data(i2cctl)) { 3579228386Sjfv status = E1000_ERR_I2C; 3580228386Sjfv DEBUGOUT1("Error - I2C data was not set to %X.\n", data); 3581228386Sjfv } 3582228386Sjfv 3583228386Sjfv return status; 3584228386Sjfv} 3585228386Sjfv 3586228386Sjfv/** 3587228386Sjfv * e1000_get_i2c_data - Reads the I2C SDA data bit 3588228386Sjfv * @hw: pointer to hardware structure 3589228386Sjfv * @i2cctl: Current value of I2CCTL register 3590228386Sjfv * 3591228386Sjfv * Returns the I2C data bit value 3592228386Sjfv **/ 3593228386Sjfvstatic bool e1000_get_i2c_data(u32 *i2cctl) 3594228386Sjfv{ 3595228386Sjfv bool data; 3596228386Sjfv 3597228386Sjfv DEBUGFUNC("e1000_get_i2c_data"); 3598228386Sjfv 3599228386Sjfv if (*i2cctl & E1000_I2C_DATA_IN) 3600228386Sjfv data = 1; 3601228386Sjfv else 3602228386Sjfv data = 0; 3603228386Sjfv 3604228386Sjfv return data; 3605228386Sjfv} 3606228386Sjfv 3607228386Sjfv/** 3608228386Sjfv * e1000_i2c_bus_clear - Clears the I2C bus 3609228386Sjfv * @hw: pointer to hardware structure 3610228386Sjfv * 3611228386Sjfv * Clears the I2C bus by sending nine clock pulses. 3612228386Sjfv * Used when data line is stuck low. 3613228386Sjfv **/ 3614228386Sjfvvoid e1000_i2c_bus_clear(struct e1000_hw *hw) 3615228386Sjfv{ 3616228386Sjfv u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS); 3617228386Sjfv u32 i; 3618228386Sjfv 3619228386Sjfv DEBUGFUNC("e1000_i2c_bus_clear"); 3620228386Sjfv 3621228386Sjfv e1000_i2c_start(hw); 3622228386Sjfv 3623228386Sjfv e1000_set_i2c_data(hw, &i2cctl, 1); 3624228386Sjfv 3625228386Sjfv for (i = 0; i < 9; i++) { 3626228386Sjfv e1000_raise_i2c_clk(hw, &i2cctl); 3627228386Sjfv 3628228386Sjfv /* Min high period of clock is 4us */ 3629228386Sjfv usec_delay(E1000_I2C_T_HIGH); 3630228386Sjfv 3631228386Sjfv e1000_lower_i2c_clk(hw, &i2cctl); 3632228386Sjfv 3633228386Sjfv /* Min low period of clock is 4.7us*/ 3634228386Sjfv usec_delay(E1000_I2C_T_LOW); 3635228386Sjfv } 3636228386Sjfv 3637228386Sjfv e1000_i2c_start(hw); 3638228386Sjfv 3639228386Sjfv /* Put the i2c bus back to default state */ 3640228386Sjfv e1000_i2c_stop(hw); 3641228386Sjfv} 3642228386Sjfv 3643