1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell#ifndef __RV515D_H__ 29254885Sdumbbell#define __RV515D_H__ 30254885Sdumbbell 31254885Sdumbbell#include <sys/cdefs.h> 32254885Sdumbbell__FBSDID("$FreeBSD: releng/10.2/sys/dev/drm2/radeon/rv515d.h 254885 2013-08-25 19:37:15Z dumbbell $"); 33254885Sdumbbell 34254885Sdumbbell/* 35254885Sdumbbell * RV515 registers 36254885Sdumbbell */ 37254885Sdumbbell#define PCIE_INDEX 0x0030 38254885Sdumbbell#define PCIE_DATA 0x0034 39254885Sdumbbell#define MC_IND_INDEX 0x0070 40254885Sdumbbell#define MC_IND_WR_EN (1 << 24) 41254885Sdumbbell#define MC_IND_DATA 0x0074 42254885Sdumbbell#define RBBM_SOFT_RESET 0x00F0 43254885Sdumbbell#define CONFIG_MEMSIZE 0x00F8 44254885Sdumbbell#define HDP_FB_LOCATION 0x0134 45254885Sdumbbell#define CP_CSQ_CNTL 0x0740 46254885Sdumbbell#define CP_CSQ_MODE 0x0744 47254885Sdumbbell#define CP_CSQ_ADDR 0x07F0 48254885Sdumbbell#define CP_CSQ_DATA 0x07F4 49254885Sdumbbell#define CP_CSQ_STAT 0x07F8 50254885Sdumbbell#define CP_CSQ2_STAT 0x07FC 51254885Sdumbbell#define RBBM_STATUS 0x0E40 52254885Sdumbbell#define DST_PIPE_CONFIG 0x170C 53254885Sdumbbell#define WAIT_UNTIL 0x1720 54254885Sdumbbell#define WAIT_2D_IDLE (1 << 14) 55254885Sdumbbell#define WAIT_3D_IDLE (1 << 15) 56254885Sdumbbell#define WAIT_2D_IDLECLEAN (1 << 16) 57254885Sdumbbell#define WAIT_3D_IDLECLEAN (1 << 17) 58254885Sdumbbell#define ISYNC_CNTL 0x1724 59254885Sdumbbell#define ISYNC_ANY2D_IDLE3D (1 << 0) 60254885Sdumbbell#define ISYNC_ANY3D_IDLE2D (1 << 1) 61254885Sdumbbell#define ISYNC_TRIG2D_IDLE3D (1 << 2) 62254885Sdumbbell#define ISYNC_TRIG3D_IDLE2D (1 << 3) 63254885Sdumbbell#define ISYNC_WAIT_IDLEGUI (1 << 4) 64254885Sdumbbell#define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 65254885Sdumbbell#define VAP_INDEX_OFFSET 0x208C 66254885Sdumbbell#define VAP_PVS_STATE_FLUSH_REG 0x2284 67254885Sdumbbell#define GB_ENABLE 0x4008 68254885Sdumbbell#define GB_MSPOS0 0x4010 69254885Sdumbbell#define MS_X0_SHIFT 0 70254885Sdumbbell#define MS_Y0_SHIFT 4 71254885Sdumbbell#define MS_X1_SHIFT 8 72254885Sdumbbell#define MS_Y1_SHIFT 12 73254885Sdumbbell#define MS_X2_SHIFT 16 74254885Sdumbbell#define MS_Y2_SHIFT 20 75254885Sdumbbell#define MSBD0_Y_SHIFT 24 76254885Sdumbbell#define MSBD0_X_SHIFT 28 77254885Sdumbbell#define GB_MSPOS1 0x4014 78254885Sdumbbell#define MS_X3_SHIFT 0 79254885Sdumbbell#define MS_Y3_SHIFT 4 80254885Sdumbbell#define MS_X4_SHIFT 8 81254885Sdumbbell#define MS_Y4_SHIFT 12 82254885Sdumbbell#define MS_X5_SHIFT 16 83254885Sdumbbell#define MS_Y5_SHIFT 20 84254885Sdumbbell#define MSBD1_SHIFT 24 85254885Sdumbbell#define GB_TILE_CONFIG 0x4018 86254885Sdumbbell#define ENABLE_TILING (1 << 0) 87254885Sdumbbell#define PIPE_COUNT_MASK 0x0000000E 88254885Sdumbbell#define PIPE_COUNT_SHIFT 1 89254885Sdumbbell#define TILE_SIZE_8 (0 << 4) 90254885Sdumbbell#define TILE_SIZE_16 (1 << 4) 91254885Sdumbbell#define TILE_SIZE_32 (2 << 4) 92254885Sdumbbell#define SUBPIXEL_1_12 (0 << 16) 93254885Sdumbbell#define SUBPIXEL_1_16 (1 << 16) 94254885Sdumbbell#define GB_SELECT 0x401C 95254885Sdumbbell#define GB_AA_CONFIG 0x4020 96254885Sdumbbell#define GB_PIPE_SELECT 0x402C 97254885Sdumbbell#define GA_ENHANCE 0x4274 98254885Sdumbbell#define GA_DEADLOCK_CNTL (1 << 0) 99254885Sdumbbell#define GA_FASTSYNC_CNTL (1 << 1) 100254885Sdumbbell#define GA_POLY_MODE 0x4288 101254885Sdumbbell#define FRONT_PTYPE_POINT (0 << 4) 102254885Sdumbbell#define FRONT_PTYPE_LINE (1 << 4) 103254885Sdumbbell#define FRONT_PTYPE_TRIANGE (2 << 4) 104254885Sdumbbell#define BACK_PTYPE_POINT (0 << 7) 105254885Sdumbbell#define BACK_PTYPE_LINE (1 << 7) 106254885Sdumbbell#define BACK_PTYPE_TRIANGE (2 << 7) 107254885Sdumbbell#define GA_ROUND_MODE 0x428C 108254885Sdumbbell#define GEOMETRY_ROUND_TRUNC (0 << 0) 109254885Sdumbbell#define GEOMETRY_ROUND_NEAREST (1 << 0) 110254885Sdumbbell#define COLOR_ROUND_TRUNC (0 << 2) 111254885Sdumbbell#define COLOR_ROUND_NEAREST (1 << 2) 112254885Sdumbbell#define SU_REG_DEST 0x42C8 113254885Sdumbbell#define RB3D_DSTCACHE_CTLSTAT 0x4E4C 114254885Sdumbbell#define RB3D_DC_FLUSH (2 << 0) 115254885Sdumbbell#define RB3D_DC_FREE (2 << 2) 116254885Sdumbbell#define RB3D_DC_FINISH (1 << 4) 117254885Sdumbbell#define ZB_ZCACHE_CTLSTAT 0x4F18 118254885Sdumbbell#define ZC_FLUSH (1 << 0) 119254885Sdumbbell#define ZC_FREE (1 << 1) 120254885Sdumbbell#define DC_LB_MEMORY_SPLIT 0x6520 121254885Sdumbbell#define DC_LB_MEMORY_SPLIT_MASK 0x00000003 122254885Sdumbbell#define DC_LB_MEMORY_SPLIT_SHIFT 0 123254885Sdumbbell#define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 124254885Sdumbbell#define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 125254885Sdumbbell#define DC_LB_MEMORY_SPLIT_D1_ONLY 2 126254885Sdumbbell#define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 127254885Sdumbbell#define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) 128254885Sdumbbell#define DC_LB_DISP1_END_ADR_SHIFT 4 129254885Sdumbbell#define DC_LB_DISP1_END_ADR_MASK 0x00007FF0 130254885Sdumbbell#define D1MODE_PRIORITY_A_CNT 0x6548 131254885Sdumbbell#define MODE_PRIORITY_MARK_MASK 0x00007FFF 132254885Sdumbbell#define MODE_PRIORITY_OFF (1 << 16) 133254885Sdumbbell#define MODE_PRIORITY_ALWAYS_ON (1 << 20) 134254885Sdumbbell#define MODE_PRIORITY_FORCE_MASK (1 << 24) 135254885Sdumbbell#define D1MODE_PRIORITY_B_CNT 0x654C 136254885Sdumbbell#define LB_MAX_REQ_OUTSTANDING 0x6D58 137254885Sdumbbell#define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F 138254885Sdumbbell#define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0 139254885Sdumbbell#define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000 140254885Sdumbbell#define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16 141254885Sdumbbell#define D2MODE_PRIORITY_A_CNT 0x6D48 142254885Sdumbbell#define D2MODE_PRIORITY_B_CNT 0x6D4C 143254885Sdumbbell 144254885Sdumbbell/* ix[MC] registers */ 145254885Sdumbbell#define MC_FB_LOCATION 0x01 146254885Sdumbbell#define MC_FB_START_MASK 0x0000FFFF 147254885Sdumbbell#define MC_FB_START_SHIFT 0 148254885Sdumbbell#define MC_FB_TOP_MASK 0xFFFF0000 149254885Sdumbbell#define MC_FB_TOP_SHIFT 16 150254885Sdumbbell#define MC_AGP_LOCATION 0x02 151254885Sdumbbell#define MC_AGP_START_MASK 0x0000FFFF 152254885Sdumbbell#define MC_AGP_START_SHIFT 0 153254885Sdumbbell#define MC_AGP_TOP_MASK 0xFFFF0000 154254885Sdumbbell#define MC_AGP_TOP_SHIFT 16 155254885Sdumbbell#define MC_AGP_BASE 0x03 156254885Sdumbbell#define MC_AGP_BASE_2 0x04 157254885Sdumbbell#define MC_CNTL 0x5 158254885Sdumbbell#define MEM_NUM_CHANNELS_MASK 0x00000003 159254885Sdumbbell#define MC_STATUS 0x08 160254885Sdumbbell#define MC_STATUS_IDLE (1 << 4) 161254885Sdumbbell#define MC_MISC_LAT_TIMER 0x09 162254885Sdumbbell#define MC_CPR_INIT_LAT_MASK 0x0000000F 163254885Sdumbbell#define MC_VF_INIT_LAT_MASK 0x000000F0 164254885Sdumbbell#define MC_DISP0R_INIT_LAT_MASK 0x00000F00 165254885Sdumbbell#define MC_DISP0R_INIT_LAT_SHIFT 8 166254885Sdumbbell#define MC_DISP1R_INIT_LAT_MASK 0x0000F000 167254885Sdumbbell#define MC_DISP1R_INIT_LAT_SHIFT 12 168254885Sdumbbell#define MC_FIXED_INIT_LAT_MASK 0x000F0000 169254885Sdumbbell#define MC_E2R_INIT_LAT_MASK 0x00F00000 170254885Sdumbbell#define SAME_PAGE_PRIO_MASK 0x0F000000 171254885Sdumbbell#define MC_GLOBW_INIT_LAT_MASK 0xF0000000 172254885Sdumbbell 173254885Sdumbbell 174254885Sdumbbell/* 175254885Sdumbbell * PM4 packet 176254885Sdumbbell */ 177254885Sdumbbell#define CP_PACKET0 0x00000000 178254885Sdumbbell#define PACKET0_BASE_INDEX_SHIFT 0 179254885Sdumbbell#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 180254885Sdumbbell#define PACKET0_COUNT_SHIFT 16 181254885Sdumbbell#define PACKET0_COUNT_MASK (0x3fff << 16) 182254885Sdumbbell#define CP_PACKET1 0x40000000 183254885Sdumbbell#define CP_PACKET2 0x80000000 184254885Sdumbbell#define PACKET2_PAD_SHIFT 0 185254885Sdumbbell#define PACKET2_PAD_MASK (0x3fffffff << 0) 186254885Sdumbbell#define CP_PACKET3 0xC0000000 187254885Sdumbbell#define PACKET3_IT_OPCODE_SHIFT 8 188254885Sdumbbell#define PACKET3_IT_OPCODE_MASK (0xff << 8) 189254885Sdumbbell#define PACKET3_COUNT_SHIFT 16 190254885Sdumbbell#define PACKET3_COUNT_MASK (0x3fff << 16) 191254885Sdumbbell/* PACKET3 op code */ 192254885Sdumbbell#define PACKET3_NOP 0x10 193254885Sdumbbell#define PACKET3_3D_DRAW_VBUF 0x28 194254885Sdumbbell#define PACKET3_3D_DRAW_IMMD 0x29 195254885Sdumbbell#define PACKET3_3D_DRAW_INDX 0x2A 196254885Sdumbbell#define PACKET3_3D_LOAD_VBPNTR 0x2F 197254885Sdumbbell#define PACKET3_INDX_BUFFER 0x33 198254885Sdumbbell#define PACKET3_3D_DRAW_VBUF_2 0x34 199254885Sdumbbell#define PACKET3_3D_DRAW_IMMD_2 0x35 200254885Sdumbbell#define PACKET3_3D_DRAW_INDX_2 0x36 201254885Sdumbbell#define PACKET3_BITBLT_MULTI 0x9B 202254885Sdumbbell 203254885Sdumbbell#define PACKET0(reg, n) (CP_PACKET0 | \ 204254885Sdumbbell REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 205254885Sdumbbell REG_SET(PACKET0_COUNT, (n))) 206254885Sdumbbell#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 207254885Sdumbbell#define PACKET3(op, n) (CP_PACKET3 | \ 208254885Sdumbbell REG_SET(PACKET3_IT_OPCODE, (op)) | \ 209254885Sdumbbell REG_SET(PACKET3_COUNT, (n))) 210254885Sdumbbell 211254885Sdumbbell#define PACKET_TYPE0 0 212254885Sdumbbell#define PACKET_TYPE1 1 213254885Sdumbbell#define PACKET_TYPE2 2 214254885Sdumbbell#define PACKET_TYPE3 3 215254885Sdumbbell 216254885Sdumbbell#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 217254885Sdumbbell#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 218254885Sdumbbell#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) 219254885Sdumbbell#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 220254885Sdumbbell#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 221254885Sdumbbell 222254885Sdumbbell/* Registers */ 223254885Sdumbbell#define R_0000F0_RBBM_SOFT_RESET 0x0000F0 224254885Sdumbbell#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 225254885Sdumbbell#define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 226254885Sdumbbell#define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 227254885Sdumbbell#define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 228254885Sdumbbell#define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 229254885Sdumbbell#define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 230254885Sdumbbell#define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) 231254885Sdumbbell#define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) 232254885Sdumbbell#define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB 233254885Sdumbbell#define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 234254885Sdumbbell#define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 235254885Sdumbbell#define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 236254885Sdumbbell#define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 237254885Sdumbbell#define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 238254885Sdumbbell#define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 239254885Sdumbbell#define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 240254885Sdumbbell#define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 241254885Sdumbbell#define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 242254885Sdumbbell#define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 243254885Sdumbbell#define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 244254885Sdumbbell#define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 245254885Sdumbbell#define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 246254885Sdumbbell#define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 247254885Sdumbbell#define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 248254885Sdumbbell#define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 249254885Sdumbbell#define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 250254885Sdumbbell#define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 251254885Sdumbbell#define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 252254885Sdumbbell#define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 253254885Sdumbbell#define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 254254885Sdumbbell#define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 255254885Sdumbbell#define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 256254885Sdumbbell#define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 257254885Sdumbbell#define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 258254885Sdumbbell#define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 259254885Sdumbbell#define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 260254885Sdumbbell#define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 261254885Sdumbbell#define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 262254885Sdumbbell#define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 263254885Sdumbbell#define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) 264254885Sdumbbell#define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) 265254885Sdumbbell#define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF 266254885Sdumbbell#define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) 267254885Sdumbbell#define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) 268254885Sdumbbell#define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF 269254885Sdumbbell#define R_0000F8_CONFIG_MEMSIZE 0x0000F8 270254885Sdumbbell#define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0) 271254885Sdumbbell#define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF) 272254885Sdumbbell#define C_0000F8_CONFIG_MEMSIZE 0x00000000 273254885Sdumbbell#define R_000134_HDP_FB_LOCATION 0x000134 274254885Sdumbbell#define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) 275254885Sdumbbell#define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) 276254885Sdumbbell#define C_000134_HDP_FB_START 0xFFFF0000 277254885Sdumbbell#define R_000300_VGA_RENDER_CONTROL 0x000300 278254885Sdumbbell#define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0) 279254885Sdumbbell#define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F) 280254885Sdumbbell#define C_000300_VGA_BLINK_RATE 0xFFFFFFE0 281254885Sdumbbell#define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5) 282254885Sdumbbell#define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3) 283254885Sdumbbell#define C_000300_VGA_BLINK_MODE 0xFFFFFF9F 284254885Sdumbbell#define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7) 285254885Sdumbbell#define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1) 286254885Sdumbbell#define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F 287254885Sdumbbell#define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8) 288254885Sdumbbell#define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1) 289254885Sdumbbell#define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF 290254885Sdumbbell#define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16) 291254885Sdumbbell#define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3) 292254885Sdumbbell#define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF 293254885Sdumbbell#define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24) 294254885Sdumbbell#define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1) 295254885Sdumbbell#define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF 296254885Sdumbbell#define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25) 297254885Sdumbbell#define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1) 298254885Sdumbbell#define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF 299254885Sdumbbell#define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310 300254885Sdumbbell#define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 301254885Sdumbbell#define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 302254885Sdumbbell#define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000 303254885Sdumbbell#define R_000328_VGA_HDP_CONTROL 0x000328 304254885Sdumbbell#define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0) 305254885Sdumbbell#define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1) 306254885Sdumbbell#define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE 307254885Sdumbbell#define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8) 308254885Sdumbbell#define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1) 309254885Sdumbbell#define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF 310254885Sdumbbell#define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16) 311254885Sdumbbell#define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1) 312254885Sdumbbell#define C_000328_VGA_SOFT_RESET 0xFFFEFFFF 313254885Sdumbbell#define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24) 314254885Sdumbbell#define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1) 315254885Sdumbbell#define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF 316254885Sdumbbell#define R_000330_D1VGA_CONTROL 0x000330 317254885Sdumbbell#define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) 318254885Sdumbbell#define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) 319254885Sdumbbell#define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE 320254885Sdumbbell#define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) 321254885Sdumbbell#define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) 322254885Sdumbbell#define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF 323254885Sdumbbell#define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) 324254885Sdumbbell#define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) 325254885Sdumbbell#define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF 326254885Sdumbbell#define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) 327254885Sdumbbell#define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) 328254885Sdumbbell#define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF 329254885Sdumbbell#define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) 330254885Sdumbbell#define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) 331254885Sdumbbell#define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF 332254885Sdumbbell#define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24) 333254885Sdumbbell#define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3) 334254885Sdumbbell#define C_000330_D1VGA_ROTATE 0xFCFFFFFF 335254885Sdumbbell#define R_000338_D2VGA_CONTROL 0x000338 336254885Sdumbbell#define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0) 337254885Sdumbbell#define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1) 338254885Sdumbbell#define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE 339254885Sdumbbell#define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8) 340254885Sdumbbell#define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1) 341254885Sdumbbell#define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF 342254885Sdumbbell#define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9) 343254885Sdumbbell#define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1) 344254885Sdumbbell#define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF 345254885Sdumbbell#define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10) 346254885Sdumbbell#define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1) 347254885Sdumbbell#define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF 348254885Sdumbbell#define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16) 349254885Sdumbbell#define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1) 350254885Sdumbbell#define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF 351254885Sdumbbell#define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24) 352254885Sdumbbell#define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3) 353254885Sdumbbell#define C_000338_D2VGA_ROTATE 0xFCFFFFFF 354254885Sdumbbell#define R_0007C0_CP_STAT 0x0007C0 355254885Sdumbbell#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 356254885Sdumbbell#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 357254885Sdumbbell#define C_0007C0_MRU_BUSY 0xFFFFFFFE 358254885Sdumbbell#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 359254885Sdumbbell#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 360254885Sdumbbell#define C_0007C0_MWU_BUSY 0xFFFFFFFD 361254885Sdumbbell#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 362254885Sdumbbell#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 363254885Sdumbbell#define C_0007C0_RSIU_BUSY 0xFFFFFFFB 364254885Sdumbbell#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 365254885Sdumbbell#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 366254885Sdumbbell#define C_0007C0_RCIU_BUSY 0xFFFFFFF7 367254885Sdumbbell#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 368254885Sdumbbell#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 369254885Sdumbbell#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 370254885Sdumbbell#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 371254885Sdumbbell#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 372254885Sdumbbell#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 373254885Sdumbbell#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 374254885Sdumbbell#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 375254885Sdumbbell#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 376254885Sdumbbell#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 377254885Sdumbbell#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 378254885Sdumbbell#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 379254885Sdumbbell#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 380254885Sdumbbell#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 381254885Sdumbbell#define C_0007C0_CSI_BUSY 0xFFFFDFFF 382254885Sdumbbell#define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) 383254885Sdumbbell#define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) 384254885Sdumbbell#define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF 385254885Sdumbbell#define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) 386254885Sdumbbell#define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) 387254885Sdumbbell#define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF 388254885Sdumbbell#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 389254885Sdumbbell#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 390254885Sdumbbell#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 391254885Sdumbbell#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 392254885Sdumbbell#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 393254885Sdumbbell#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 394254885Sdumbbell#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 395254885Sdumbbell#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 396254885Sdumbbell#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 397254885Sdumbbell#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 398254885Sdumbbell#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 399254885Sdumbbell#define C_0007C0_CP_BUSY 0x7FFFFFFF 400254885Sdumbbell#define R_000E40_RBBM_STATUS 0x000E40 401254885Sdumbbell#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 402254885Sdumbbell#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 403254885Sdumbbell#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 404254885Sdumbbell#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 405254885Sdumbbell#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 406254885Sdumbbell#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 407254885Sdumbbell#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 408254885Sdumbbell#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 409254885Sdumbbell#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 410254885Sdumbbell#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 411254885Sdumbbell#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 412254885Sdumbbell#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 413254885Sdumbbell#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 414254885Sdumbbell#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 415254885Sdumbbell#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 416254885Sdumbbell#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 417254885Sdumbbell#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 418254885Sdumbbell#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 419254885Sdumbbell#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 420254885Sdumbbell#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 421254885Sdumbbell#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 422254885Sdumbbell#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 423254885Sdumbbell#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 424254885Sdumbbell#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 425254885Sdumbbell#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 426254885Sdumbbell#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 427254885Sdumbbell#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 428254885Sdumbbell#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 429254885Sdumbbell#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 430254885Sdumbbell#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 431254885Sdumbbell#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 432254885Sdumbbell#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 433254885Sdumbbell#define C_000E40_E2_BUSY 0xFFFDFFFF 434254885Sdumbbell#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 435254885Sdumbbell#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 436254885Sdumbbell#define C_000E40_RB2D_BUSY 0xFFFBFFFF 437254885Sdumbbell#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 438254885Sdumbbell#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 439254885Sdumbbell#define C_000E40_RB3D_BUSY 0xFFF7FFFF 440254885Sdumbbell#define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) 441254885Sdumbbell#define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) 442254885Sdumbbell#define C_000E40_VAP_BUSY 0xFFEFFFFF 443254885Sdumbbell#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 444254885Sdumbbell#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 445254885Sdumbbell#define C_000E40_RE_BUSY 0xFFDFFFFF 446254885Sdumbbell#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 447254885Sdumbbell#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 448254885Sdumbbell#define C_000E40_TAM_BUSY 0xFFBFFFFF 449254885Sdumbbell#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 450254885Sdumbbell#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 451254885Sdumbbell#define C_000E40_TDM_BUSY 0xFF7FFFFF 452254885Sdumbbell#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 453254885Sdumbbell#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 454254885Sdumbbell#define C_000E40_PB_BUSY 0xFEFFFFFF 455254885Sdumbbell#define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) 456254885Sdumbbell#define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) 457254885Sdumbbell#define C_000E40_TIM_BUSY 0xFDFFFFFF 458254885Sdumbbell#define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) 459254885Sdumbbell#define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) 460254885Sdumbbell#define C_000E40_GA_BUSY 0xFBFFFFFF 461254885Sdumbbell#define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) 462254885Sdumbbell#define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) 463254885Sdumbbell#define C_000E40_CBA2D_BUSY 0xF7FFFFFF 464254885Sdumbbell#define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28) 465254885Sdumbbell#define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1) 466254885Sdumbbell#define C_000E40_RBBM_HIBUSY 0xEFFFFFFF 467254885Sdumbbell#define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29) 468254885Sdumbbell#define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1) 469254885Sdumbbell#define C_000E40_SKID_CFBUSY 0xDFFFFFFF 470254885Sdumbbell#define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30) 471254885Sdumbbell#define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1) 472254885Sdumbbell#define C_000E40_VAP_VF_BUSY 0xBFFFFFFF 473254885Sdumbbell#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 474254885Sdumbbell#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 475254885Sdumbbell#define C_000E40_GUI_ACTIVE 0x7FFFFFFF 476254885Sdumbbell#define R_006080_D1CRTC_CONTROL 0x006080 477254885Sdumbbell#define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0) 478254885Sdumbbell#define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) 479254885Sdumbbell#define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE 480254885Sdumbbell#define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) 481254885Sdumbbell#define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) 482254885Sdumbbell#define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF 483254885Sdumbbell#define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) 484254885Sdumbbell#define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) 485254885Sdumbbell#define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF 486254885Sdumbbell#define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) 487254885Sdumbbell#define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) 488254885Sdumbbell#define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF 489254885Sdumbbell#define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) 490254885Sdumbbell#define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) 491254885Sdumbbell#define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF 492254885Sdumbbell#define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8 493254885Sdumbbell#define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) 494254885Sdumbbell#define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) 495254885Sdumbbell#define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE 496254885Sdumbbell#define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110 497254885Sdumbbell#define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 498254885Sdumbbell#define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 499254885Sdumbbell#define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 500254885Sdumbbell#define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118 501254885Sdumbbell#define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 502254885Sdumbbell#define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 503254885Sdumbbell#define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 504254885Sdumbbell#define R_006880_D2CRTC_CONTROL 0x006880 505254885Sdumbbell#define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0) 506254885Sdumbbell#define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1) 507254885Sdumbbell#define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE 508254885Sdumbbell#define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4) 509254885Sdumbbell#define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1) 510254885Sdumbbell#define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF 511254885Sdumbbell#define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8) 512254885Sdumbbell#define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3) 513254885Sdumbbell#define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF 514254885Sdumbbell#define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16) 515254885Sdumbbell#define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1) 516254885Sdumbbell#define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF 517254885Sdumbbell#define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24) 518254885Sdumbbell#define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1) 519254885Sdumbbell#define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF 520254885Sdumbbell#define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8 521254885Sdumbbell#define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0) 522254885Sdumbbell#define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1) 523254885Sdumbbell#define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE 524254885Sdumbbell#define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910 525254885Sdumbbell#define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 526254885Sdumbbell#define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 527254885Sdumbbell#define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000 528254885Sdumbbell#define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918 529254885Sdumbbell#define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0) 530254885Sdumbbell#define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF) 531254885Sdumbbell#define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000 532254885Sdumbbell 533254885Sdumbbell 534254885Sdumbbell#define R_000001_MC_FB_LOCATION 0x000001 535254885Sdumbbell#define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0) 536254885Sdumbbell#define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 537254885Sdumbbell#define C_000001_MC_FB_START 0xFFFF0000 538254885Sdumbbell#define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 539254885Sdumbbell#define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 540254885Sdumbbell#define C_000001_MC_FB_TOP 0x0000FFFF 541254885Sdumbbell#define R_000002_MC_AGP_LOCATION 0x000002 542254885Sdumbbell#define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 543254885Sdumbbell#define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 544254885Sdumbbell#define C_000002_MC_AGP_START 0xFFFF0000 545254885Sdumbbell#define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 546254885Sdumbbell#define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 547254885Sdumbbell#define C_000002_MC_AGP_TOP 0x0000FFFF 548254885Sdumbbell#define R_000003_MC_AGP_BASE 0x000003 549254885Sdumbbell#define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 550254885Sdumbbell#define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 551254885Sdumbbell#define C_000003_AGP_BASE_ADDR 0x00000000 552254885Sdumbbell#define R_000004_MC_AGP_BASE_2 0x000004 553254885Sdumbbell#define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) 554254885Sdumbbell#define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) 555254885Sdumbbell#define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0 556254885Sdumbbell 557254885Sdumbbell 558254885Sdumbbell#define R_00000F_CP_DYN_CNTL 0x00000F 559254885Sdumbbell#define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0) 560254885Sdumbbell#define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1) 561254885Sdumbbell#define C_00000F_CP_FORCEON 0xFFFFFFFE 562254885Sdumbbell#define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) 563254885Sdumbbell#define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) 564254885Sdumbbell#define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD 565254885Sdumbbell#define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2) 566254885Sdumbbell#define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1) 567254885Sdumbbell#define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB 568254885Sdumbbell#define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3) 569254885Sdumbbell#define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) 570254885Sdumbbell#define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7 571254885Sdumbbell#define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) 572254885Sdumbbell#define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) 573254885Sdumbbell#define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F 574254885Sdumbbell#define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) 575254885Sdumbbell#define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) 576254885Sdumbbell#define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF 577254885Sdumbbell#define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) 578254885Sdumbbell#define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) 579254885Sdumbbell#define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF 580254885Sdumbbell#define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) 581254885Sdumbbell#define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) 582254885Sdumbbell#define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF 583254885Sdumbbell#define S_00000F_SPARE(x) (((x) & 0x3) << 22) 584254885Sdumbbell#define G_00000F_SPARE(x) (((x) >> 22) & 0x3) 585254885Sdumbbell#define C_00000F_SPARE 0xFF3FFFFF 586254885Sdumbbell#define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) 587254885Sdumbbell#define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) 588254885Sdumbbell#define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF 589254885Sdumbbell#define R_000011_E2_DYN_CNTL 0x000011 590254885Sdumbbell#define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0) 591254885Sdumbbell#define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1) 592254885Sdumbbell#define C_000011_E2_FORCEON 0xFFFFFFFE 593254885Sdumbbell#define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) 594254885Sdumbbell#define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) 595254885Sdumbbell#define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD 596254885Sdumbbell#define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2) 597254885Sdumbbell#define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1) 598254885Sdumbbell#define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB 599254885Sdumbbell#define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3) 600254885Sdumbbell#define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) 601254885Sdumbbell#define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7 602254885Sdumbbell#define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) 603254885Sdumbbell#define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) 604254885Sdumbbell#define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F 605254885Sdumbbell#define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) 606254885Sdumbbell#define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) 607254885Sdumbbell#define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF 608254885Sdumbbell#define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) 609254885Sdumbbell#define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) 610254885Sdumbbell#define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF 611254885Sdumbbell#define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) 612254885Sdumbbell#define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) 613254885Sdumbbell#define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF 614254885Sdumbbell#define S_000011_SPARE(x) (((x) & 0x3) << 22) 615254885Sdumbbell#define G_000011_SPARE(x) (((x) >> 22) & 0x3) 616254885Sdumbbell#define C_000011_SPARE 0xFF3FFFFF 617254885Sdumbbell#define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) 618254885Sdumbbell#define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) 619254885Sdumbbell#define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF 620254885Sdumbbell#define R_000013_IDCT_DYN_CNTL 0x000013 621254885Sdumbbell#define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0) 622254885Sdumbbell#define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1) 623254885Sdumbbell#define C_000013_IDCT_FORCEON 0xFFFFFFFE 624254885Sdumbbell#define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1) 625254885Sdumbbell#define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1) 626254885Sdumbbell#define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD 627254885Sdumbbell#define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2) 628254885Sdumbbell#define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1) 629254885Sdumbbell#define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB 630254885Sdumbbell#define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3) 631254885Sdumbbell#define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1) 632254885Sdumbbell#define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7 633254885Sdumbbell#define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4) 634254885Sdumbbell#define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF) 635254885Sdumbbell#define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F 636254885Sdumbbell#define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12) 637254885Sdumbbell#define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF) 638254885Sdumbbell#define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF 639254885Sdumbbell#define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20) 640254885Sdumbbell#define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1) 641254885Sdumbbell#define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF 642254885Sdumbbell#define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21) 643254885Sdumbbell#define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1) 644254885Sdumbbell#define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF 645254885Sdumbbell#define S_000013_SPARE(x) (((x) & 0x3) << 22) 646254885Sdumbbell#define G_000013_SPARE(x) (((x) >> 22) & 0x3) 647254885Sdumbbell#define C_000013_SPARE 0xFF3FFFFF 648254885Sdumbbell#define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24) 649254885Sdumbbell#define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF) 650254885Sdumbbell#define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF 651254885Sdumbbell 652254885Sdumbbell#endif 653