r500_reg.h revision 282199
1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * Copyright 2009 Jerome Glisse. 5254885Sdumbbell * 6254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 7254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 8254885Sdumbbell * to deal in the Software without restriction, including without limitation 9254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 11254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 12254885Sdumbbell * 13254885Sdumbbell * The above copyright notice and this permission notice shall be included in 14254885Sdumbbell * all copies or substantial portions of the Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: Dave Airlie 25254885Sdumbbell * Alex Deucher 26254885Sdumbbell * Jerome Glisse 27254885Sdumbbell */ 28254885Sdumbbell#ifndef __R500_REG_H__ 29254885Sdumbbell#define __R500_REG_H__ 30254885Sdumbbell 31254885Sdumbbell#include <sys/cdefs.h> 32254885Sdumbbell__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/r500_reg.h 282199 2015-04-28 19:35:05Z dumbbell $"); 33254885Sdumbbell 34254885Sdumbbell/* pipe config regs */ 35254885Sdumbbell#define R300_GA_POLY_MODE 0x4288 36254885Sdumbbell# define R300_FRONT_PTYPE_POINT (0 << 4) 37254885Sdumbbell# define R300_FRONT_PTYPE_LINE (1 << 4) 38254885Sdumbbell# define R300_FRONT_PTYPE_TRIANGE (2 << 4) 39254885Sdumbbell# define R300_BACK_PTYPE_POINT (0 << 7) 40254885Sdumbbell# define R300_BACK_PTYPE_LINE (1 << 7) 41254885Sdumbbell# define R300_BACK_PTYPE_TRIANGE (2 << 7) 42254885Sdumbbell#define R300_GA_ROUND_MODE 0x428c 43254885Sdumbbell# define R300_GEOMETRY_ROUND_TRUNC (0 << 0) 44254885Sdumbbell# define R300_GEOMETRY_ROUND_NEAREST (1 << 0) 45254885Sdumbbell# define R300_COLOR_ROUND_TRUNC (0 << 2) 46254885Sdumbbell# define R300_COLOR_ROUND_NEAREST (1 << 2) 47254885Sdumbbell#define R300_GB_MSPOS0 0x4010 48254885Sdumbbell# define R300_MS_X0_SHIFT 0 49254885Sdumbbell# define R300_MS_Y0_SHIFT 4 50254885Sdumbbell# define R300_MS_X1_SHIFT 8 51254885Sdumbbell# define R300_MS_Y1_SHIFT 12 52254885Sdumbbell# define R300_MS_X2_SHIFT 16 53254885Sdumbbell# define R300_MS_Y2_SHIFT 20 54254885Sdumbbell# define R300_MSBD0_Y_SHIFT 24 55254885Sdumbbell# define R300_MSBD0_X_SHIFT 28 56254885Sdumbbell#define R300_GB_MSPOS1 0x4014 57254885Sdumbbell# define R300_MS_X3_SHIFT 0 58254885Sdumbbell# define R300_MS_Y3_SHIFT 4 59254885Sdumbbell# define R300_MS_X4_SHIFT 8 60254885Sdumbbell# define R300_MS_Y4_SHIFT 12 61254885Sdumbbell# define R300_MS_X5_SHIFT 16 62254885Sdumbbell# define R300_MS_Y5_SHIFT 20 63254885Sdumbbell# define R300_MSBD1_SHIFT 24 64254885Sdumbbell 65254885Sdumbbell#define R300_GA_ENHANCE 0x4274 66254885Sdumbbell# define R300_GA_DEADLOCK_CNTL (1 << 0) 67254885Sdumbbell# define R300_GA_FASTSYNC_CNTL (1 << 1) 68254885Sdumbbell#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 69254885Sdumbbell# define R300_RB3D_DC_FLUSH (2 << 0) 70254885Sdumbbell# define R300_RB3D_DC_FREE (2 << 2) 71254885Sdumbbell# define R300_RB3D_DC_FINISH (1 << 4) 72254885Sdumbbell#define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 73254885Sdumbbell# define R300_ZC_FLUSH (1 << 0) 74254885Sdumbbell# define R300_ZC_FREE (1 << 1) 75254885Sdumbbell# define R300_ZC_FLUSH_ALL 0x3 76254885Sdumbbell#define R400_GB_PIPE_SELECT 0x402c 77254885Sdumbbell#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 78254885Sdumbbell#define R500_SU_REG_DEST 0x42c8 79254885Sdumbbell#define R300_GB_TILE_CONFIG 0x4018 80254885Sdumbbell# define R300_ENABLE_TILING (1 << 0) 81254885Sdumbbell# define R300_PIPE_COUNT_RV350 (0 << 1) 82254885Sdumbbell# define R300_PIPE_COUNT_R300 (3 << 1) 83254885Sdumbbell# define R300_PIPE_COUNT_R420_3P (6 << 1) 84254885Sdumbbell# define R300_PIPE_COUNT_R420 (7 << 1) 85254885Sdumbbell# define R300_TILE_SIZE_8 (0 << 4) 86254885Sdumbbell# define R300_TILE_SIZE_16 (1 << 4) 87254885Sdumbbell# define R300_TILE_SIZE_32 (2 << 4) 88254885Sdumbbell# define R300_SUBPIXEL_1_12 (0 << 16) 89254885Sdumbbell# define R300_SUBPIXEL_1_16 (1 << 16) 90254885Sdumbbell#define R300_DST_PIPE_CONFIG 0x170c 91261455Seadler# define R300_PIPE_AUTO_CONFIG (1U << 31) 92254885Sdumbbell#define R300_RB2D_DSTCACHE_MODE 0x3428 93254885Sdumbbell# define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 94254885Sdumbbell# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 95254885Sdumbbell 96254885Sdumbbell#define RADEON_CP_STAT 0x7C0 97254885Sdumbbell#define RADEON_RBBM_CMDFIFO_ADDR 0xE70 98254885Sdumbbell#define RADEON_RBBM_CMDFIFO_DATA 0xE74 99254885Sdumbbell#define RADEON_ISYNC_CNTL 0x1724 100254885Sdumbbell# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 101254885Sdumbbell# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 102254885Sdumbbell# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 103254885Sdumbbell# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 104254885Sdumbbell# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 105254885Sdumbbell# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 106254885Sdumbbell 107254885Sdumbbell#define RS480_NB_MC_INDEX 0x168 108254885Sdumbbell# define RS480_NB_MC_IND_WR_EN (1 << 8) 109254885Sdumbbell#define RS480_NB_MC_DATA 0x16c 110254885Sdumbbell 111254885Sdumbbell/* 112254885Sdumbbell * RS690 113254885Sdumbbell */ 114254885Sdumbbell#define RS690_MCCFG_FB_LOCATION 0x100 115254885Sdumbbell#define RS690_MC_FB_START_MASK 0x0000FFFF 116254885Sdumbbell#define RS690_MC_FB_START_SHIFT 0 117254885Sdumbbell#define RS690_MC_FB_TOP_MASK 0xFFFF0000 118254885Sdumbbell#define RS690_MC_FB_TOP_SHIFT 16 119254885Sdumbbell#define RS690_MCCFG_AGP_LOCATION 0x101 120254885Sdumbbell#define RS690_MC_AGP_START_MASK 0x0000FFFF 121254885Sdumbbell#define RS690_MC_AGP_START_SHIFT 0 122254885Sdumbbell#define RS690_MC_AGP_TOP_MASK 0xFFFF0000 123254885Sdumbbell#define RS690_MC_AGP_TOP_SHIFT 16 124254885Sdumbbell#define RS690_MCCFG_AGP_BASE 0x102 125254885Sdumbbell#define RS690_MCCFG_AGP_BASE_2 0x103 126254885Sdumbbell#define RS690_MC_INIT_MISC_LAT_TIMER 0x104 127254885Sdumbbell#define RS690_HDP_FB_LOCATION 0x0134 128254885Sdumbbell#define RS690_MC_INDEX 0x78 129254885Sdumbbell# define RS690_MC_INDEX_MASK 0x1ff 130254885Sdumbbell# define RS690_MC_INDEX_WR_EN (1 << 9) 131254885Sdumbbell# define RS690_MC_INDEX_WR_ACK 0x7f 132254885Sdumbbell#define RS690_MC_DATA 0x7c 133254885Sdumbbell#define RS690_MC_STATUS 0x90 134254885Sdumbbell#define RS690_MC_STATUS_IDLE (1 << 0) 135254885Sdumbbell#define RS480_AGP_BASE_2 0x0164 136254885Sdumbbell#define RS480_MC_MISC_CNTL 0x18 137254885Sdumbbell# define RS480_DISABLE_GTW (1 << 1) 138254885Sdumbbell# define RS480_GART_INDEX_REG_EN (1 << 12) 139254885Sdumbbell# define RS690_BLOCK_GFX_D3_EN (1 << 14) 140254885Sdumbbell#define RS480_GART_FEATURE_ID 0x2b 141254885Sdumbbell# define RS480_HANG_EN (1 << 11) 142254885Sdumbbell# define RS480_TLB_ENABLE (1 << 18) 143254885Sdumbbell# define RS480_P2P_ENABLE (1 << 19) 144254885Sdumbbell# define RS480_GTW_LAC_EN (1 << 25) 145254885Sdumbbell# define RS480_2LEVEL_GART (0 << 30) 146254885Sdumbbell# define RS480_1LEVEL_GART (1 << 30) 147261455Seadler# define RS480_PDC_EN (1U << 31) 148254885Sdumbbell#define RS480_GART_BASE 0x2c 149254885Sdumbbell#define RS480_GART_CACHE_CNTRL 0x2e 150254885Sdumbbell# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 151254885Sdumbbell#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 152254885Sdumbbell# define RS480_GART_EN (1 << 0) 153254885Sdumbbell# define RS480_VA_SIZE_32MB (0 << 1) 154254885Sdumbbell# define RS480_VA_SIZE_64MB (1 << 1) 155254885Sdumbbell# define RS480_VA_SIZE_128MB (2 << 1) 156254885Sdumbbell# define RS480_VA_SIZE_256MB (3 << 1) 157254885Sdumbbell# define RS480_VA_SIZE_512MB (4 << 1) 158254885Sdumbbell# define RS480_VA_SIZE_1GB (5 << 1) 159254885Sdumbbell# define RS480_VA_SIZE_2GB (6 << 1) 160254885Sdumbbell#define RS480_AGP_MODE_CNTL 0x39 161254885Sdumbbell# define RS480_POST_GART_Q_SIZE (1 << 18) 162254885Sdumbbell# define RS480_NONGART_SNOOP (1 << 19) 163254885Sdumbbell# define RS480_AGP_RD_BUF_SIZE (1 << 20) 164254885Sdumbbell# define RS480_REQ_TYPE_SNOOP_SHIFT 22 165254885Sdumbbell# define RS480_REQ_TYPE_SNOOP_MASK 0x3 166254885Sdumbbell# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 167254885Sdumbbell 168254885Sdumbbell#define RS690_AIC_CTRL_SCRATCH 0x3A 169254885Sdumbbell# define RS690_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1) 170254885Sdumbbell 171254885Sdumbbell/* 172254885Sdumbbell * RS600 173254885Sdumbbell */ 174254885Sdumbbell#define RS600_MC_STATUS 0x0 175254885Sdumbbell#define RS600_MC_STATUS_IDLE (1 << 0) 176254885Sdumbbell#define RS600_MC_INDEX 0x70 177254885Sdumbbell# define RS600_MC_ADDR_MASK 0xffff 178254885Sdumbbell# define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 179254885Sdumbbell# define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 180254885Sdumbbell# define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 181254885Sdumbbell# define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 182254885Sdumbbell# define RS600_MC_IND_AIC_RBS (1 << 20) 183254885Sdumbbell# define RS600_MC_IND_CITF_ARB0 (1 << 21) 184254885Sdumbbell# define RS600_MC_IND_CITF_ARB1 (1 << 22) 185254885Sdumbbell# define RS600_MC_IND_WR_EN (1 << 23) 186254885Sdumbbell#define RS600_MC_DATA 0x74 187254885Sdumbbell#define RS600_MC_STATUS 0x0 188254885Sdumbbell# define RS600_MC_IDLE (1 << 1) 189254885Sdumbbell#define RS600_MC_FB_LOCATION 0x4 190254885Sdumbbell#define RS600_MC_FB_START_MASK 0x0000FFFF 191254885Sdumbbell#define RS600_MC_FB_START_SHIFT 0 192254885Sdumbbell#define RS600_MC_FB_TOP_MASK 0xFFFF0000 193254885Sdumbbell#define RS600_MC_FB_TOP_SHIFT 16 194254885Sdumbbell#define RS600_MC_AGP_LOCATION 0x5 195254885Sdumbbell#define RS600_MC_AGP_START_MASK 0x0000FFFF 196254885Sdumbbell#define RS600_MC_AGP_START_SHIFT 0 197254885Sdumbbell#define RS600_MC_AGP_TOP_MASK 0xFFFF0000 198254885Sdumbbell#define RS600_MC_AGP_TOP_SHIFT 16 199254885Sdumbbell#define RS600_MC_AGP_BASE 0x6 200254885Sdumbbell#define RS600_MC_AGP_BASE_2 0x7 201254885Sdumbbell#define RS600_MC_CNTL1 0x9 202254885Sdumbbell# define RS600_ENABLE_PAGE_TABLES (1 << 26) 203254885Sdumbbell#define RS600_MC_PT0_CNTL 0x100 204254885Sdumbbell# define RS600_ENABLE_PT (1 << 0) 205254885Sdumbbell# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 206254885Sdumbbell# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 207254885Sdumbbell# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 208254885Sdumbbell# define RS600_INVALIDATE_L2_CACHE (1 << 29) 209254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_CNTL 0x102 210254885Sdumbbell# define RS600_ENABLE_PAGE_TABLE (1 << 0) 211254885Sdumbbell# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 212254885Sdumbbell#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 213254885Sdumbbell#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 214254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 215254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 216254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 217254885Sdumbbell#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 218254885Sdumbbell#define RS600_MC_PT0_CLIENT0_CNTL 0x16c 219254885Sdumbbell# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 220254885Sdumbbell# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 221254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 222254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 223254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 224254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 225254885Sdumbbell# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 226254885Sdumbbell# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 227254885Sdumbbell# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 228254885Sdumbbell# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 229254885Sdumbbell# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 230254885Sdumbbell# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 231254885Sdumbbell# define RS600_INVALIDATE_L1_TLB (1 << 20) 232254885Sdumbbell/* rs600/rs690/rs740 */ 233254885Sdumbbell# define RS600_BUS_MASTER_DIS (1 << 14) 234254885Sdumbbell# define RS600_MSI_REARM (1 << 20) 235254885Sdumbbell/* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 236254885Sdumbbell 237254885Sdumbbell 238254885Sdumbbell 239254885Sdumbbell#define RV515_MC_FB_LOCATION 0x01 240254885Sdumbbell#define RV515_MC_FB_START_MASK 0x0000FFFF 241254885Sdumbbell#define RV515_MC_FB_START_SHIFT 0 242254885Sdumbbell#define RV515_MC_FB_TOP_MASK 0xFFFF0000 243254885Sdumbbell#define RV515_MC_FB_TOP_SHIFT 16 244254885Sdumbbell#define RV515_MC_AGP_LOCATION 0x02 245254885Sdumbbell#define RV515_MC_AGP_START_MASK 0x0000FFFF 246254885Sdumbbell#define RV515_MC_AGP_START_SHIFT 0 247254885Sdumbbell#define RV515_MC_AGP_TOP_MASK 0xFFFF0000 248254885Sdumbbell#define RV515_MC_AGP_TOP_SHIFT 16 249254885Sdumbbell#define RV515_MC_AGP_BASE 0x03 250254885Sdumbbell#define RV515_MC_AGP_BASE_2 0x04 251254885Sdumbbell 252254885Sdumbbell#define R520_MC_FB_LOCATION 0x04 253254885Sdumbbell#define R520_MC_FB_START_MASK 0x0000FFFF 254254885Sdumbbell#define R520_MC_FB_START_SHIFT 0 255254885Sdumbbell#define R520_MC_FB_TOP_MASK 0xFFFF0000 256254885Sdumbbell#define R520_MC_FB_TOP_SHIFT 16 257254885Sdumbbell#define R520_MC_AGP_LOCATION 0x05 258254885Sdumbbell#define R520_MC_AGP_START_MASK 0x0000FFFF 259254885Sdumbbell#define R520_MC_AGP_START_SHIFT 0 260254885Sdumbbell#define R520_MC_AGP_TOP_MASK 0xFFFF0000 261254885Sdumbbell#define R520_MC_AGP_TOP_SHIFT 16 262254885Sdumbbell#define R520_MC_AGP_BASE 0x06 263254885Sdumbbell#define R520_MC_AGP_BASE_2 0x07 264254885Sdumbbell 265254885Sdumbbell 266254885Sdumbbell#define AVIVO_MC_INDEX 0x0070 267254885Sdumbbell#define R520_MC_STATUS 0x00 268254885Sdumbbell#define R520_MC_STATUS_IDLE (1<<1) 269254885Sdumbbell#define RV515_MC_STATUS 0x08 270254885Sdumbbell#define RV515_MC_STATUS_IDLE (1<<4) 271254885Sdumbbell#define RV515_MC_INIT_MISC_LAT_TIMER 0x09 272254885Sdumbbell#define AVIVO_MC_DATA 0x0074 273254885Sdumbbell 274254885Sdumbbell#define R520_MC_IND_INDEX 0x70 275254885Sdumbbell#define R520_MC_IND_WR_EN (1 << 24) 276254885Sdumbbell#define R520_MC_IND_DATA 0x74 277254885Sdumbbell 278254885Sdumbbell#define RV515_MC_CNTL 0x5 279254885Sdumbbell# define RV515_MEM_NUM_CHANNELS_MASK 0x3 280254885Sdumbbell#define R520_MC_CNTL0 0x8 281254885Sdumbbell# define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) 282254885Sdumbbell# define R520_MEM_NUM_CHANNELS_SHIFT 24 283254885Sdumbbell# define R520_MC_CHANNEL_SIZE (1 << 23) 284254885Sdumbbell 285254885Sdumbbell#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ 286254885Sdumbbell# define AVIVO_CP_FORCEON (1 << 0) 287254885Sdumbbell#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ 288254885Sdumbbell# define AVIVO_E2_FORCEON (1 << 0) 289254885Sdumbbell#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ 290254885Sdumbbell# define AVIVO_IDCT_FORCEON (1 << 0) 291254885Sdumbbell 292254885Sdumbbell#define AVIVO_HDP_FB_LOCATION 0x134 293254885Sdumbbell 294254885Sdumbbell#define AVIVO_VGA_RENDER_CONTROL 0x0300 295254885Sdumbbell# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) 296254885Sdumbbell#define AVIVO_D1VGA_CONTROL 0x0330 297254885Sdumbbell# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) 298254885Sdumbbell# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) 299254885Sdumbbell# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) 300254885Sdumbbell# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) 301254885Sdumbbell# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) 302254885Sdumbbell# define AVIVO_DVGA_CONTROL_ROTATE (1<<24) 303254885Sdumbbell#define AVIVO_D2VGA_CONTROL 0x0338 304254885Sdumbbell 305254885Sdumbbell#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 306254885Sdumbbell#define AVIVO_EXT1_PPLL_REF_DIV 0x404 307254885Sdumbbell#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 308254885Sdumbbell#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c 309254885Sdumbbell 310254885Sdumbbell#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 311254885Sdumbbell#define AVIVO_EXT2_PPLL_REF_DIV 0x414 312254885Sdumbbell#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 313254885Sdumbbell#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c 314254885Sdumbbell 315254885Sdumbbell#define AVIVO_EXT1_PPLL_FB_DIV 0x430 316254885Sdumbbell#define AVIVO_EXT2_PPLL_FB_DIV 0x434 317254885Sdumbbell 318254885Sdumbbell#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 319254885Sdumbbell#define AVIVO_EXT1_PPLL_POST_DIV 0x43c 320254885Sdumbbell 321254885Sdumbbell#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 322254885Sdumbbell#define AVIVO_EXT2_PPLL_POST_DIV 0x444 323254885Sdumbbell 324254885Sdumbbell#define AVIVO_EXT1_PPLL_CNTL 0x448 325254885Sdumbbell#define AVIVO_EXT2_PPLL_CNTL 0x44c 326254885Sdumbbell 327254885Sdumbbell#define AVIVO_P1PLL_CNTL 0x450 328254885Sdumbbell#define AVIVO_P2PLL_CNTL 0x454 329254885Sdumbbell#define AVIVO_P1PLL_INT_SS_CNTL 0x458 330254885Sdumbbell#define AVIVO_P2PLL_INT_SS_CNTL 0x45c 331254885Sdumbbell#define AVIVO_P1PLL_TMDSA_CNTL 0x460 332254885Sdumbbell#define AVIVO_P2PLL_LVTMA_CNTL 0x464 333254885Sdumbbell 334254885Sdumbbell#define AVIVO_PCLK_CRTC1_CNTL 0x480 335254885Sdumbbell#define AVIVO_PCLK_CRTC2_CNTL 0x484 336254885Sdumbbell 337254885Sdumbbell#define AVIVO_D1CRTC_H_TOTAL 0x6000 338254885Sdumbbell#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 339254885Sdumbbell#define AVIVO_D1CRTC_H_SYNC_A 0x6008 340254885Sdumbbell#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c 341254885Sdumbbell#define AVIVO_D1CRTC_H_SYNC_B 0x6010 342254885Sdumbbell#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 343254885Sdumbbell 344254885Sdumbbell#define AVIVO_D1CRTC_V_TOTAL 0x6020 345254885Sdumbbell#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 346254885Sdumbbell#define AVIVO_D1CRTC_V_SYNC_A 0x6028 347254885Sdumbbell#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c 348254885Sdumbbell#define AVIVO_D1CRTC_V_SYNC_B 0x6030 349254885Sdumbbell#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 350254885Sdumbbell 351254885Sdumbbell#define AVIVO_D1CRTC_CONTROL 0x6080 352254885Sdumbbell# define AVIVO_CRTC_EN (1 << 0) 353254885Sdumbbell# define AVIVO_CRTC_DISP_READ_REQUEST_DISABLE (1 << 24) 354254885Sdumbbell#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 355254885Sdumbbell#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 356254885Sdumbbell#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c 357254885Sdumbbell#define AVIVO_D1CRTC_STATUS 0x609c 358254885Sdumbbell# define AVIVO_D1CRTC_V_BLANK (1 << 0) 359254885Sdumbbell#define AVIVO_D1CRTC_STATUS_POSITION 0x60a0 360254885Sdumbbell#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4 361254885Sdumbbell#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 362254885Sdumbbell 363282199Sdumbbell#define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0 364254885Sdumbbell#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 365282199Sdumbbell#define AVIVO_D1CRTC_UPDATE_LOCK 0x60e8 366254885Sdumbbell 367254885Sdumbbell/* master controls */ 368254885Sdumbbell#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 369254885Sdumbbell#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc 370254885Sdumbbell 371254885Sdumbbell#define AVIVO_D1GRPH_ENABLE 0x6100 372254885Sdumbbell#define AVIVO_D1GRPH_CONTROL 0x6104 373254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0) 374254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0) 375254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0) 376254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0) 377254885Sdumbbell 378254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8) 379254885Sdumbbell 380254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8) 381254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8) 382254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8) 383254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8) 384254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8) 385254885Sdumbbell 386254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8) 387254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8) 388254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8) 389254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8) 390254885Sdumbbell 391254885Sdumbbell 392254885Sdumbbell# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8) 393254885Sdumbbell 394254885Sdumbbell# define AVIVO_D1GRPH_SWAP_RB (1 << 16) 395254885Sdumbbell# define AVIVO_D1GRPH_TILED (1 << 20) 396254885Sdumbbell# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21) 397254885Sdumbbell 398254885Sdumbbell# define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL (0 << 20) 399254885Sdumbbell# define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED (1 << 20) 400254885Sdumbbell# define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1 (2 << 20) 401254885Sdumbbell# define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1 (4 << 20) 402254885Sdumbbell 403254885Sdumbbell/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2 404254885Sdumbbell * block and vice versa. This applies to GRPH, CUR, etc. 405254885Sdumbbell */ 406254885Sdumbbell#define AVIVO_D1GRPH_LUT_SEL 0x6108 407254885Sdumbbell#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 408254885Sdumbbell#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914 409254885Sdumbbell#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114 410254885Sdumbbell#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 411254885Sdumbbell#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c 412254885Sdumbbell#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c 413254885Sdumbbell#define AVIVO_D1GRPH_PITCH 0x6120 414254885Sdumbbell#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 415254885Sdumbbell#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 416254885Sdumbbell#define AVIVO_D1GRPH_X_START 0x612c 417254885Sdumbbell#define AVIVO_D1GRPH_Y_START 0x6130 418254885Sdumbbell#define AVIVO_D1GRPH_X_END 0x6134 419254885Sdumbbell#define AVIVO_D1GRPH_Y_END 0x6138 420254885Sdumbbell#define AVIVO_D1GRPH_UPDATE 0x6144 421254885Sdumbbell# define AVIVO_D1GRPH_SURFACE_UPDATE_PENDING (1 << 2) 422254885Sdumbbell# define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16) 423254885Sdumbbell#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 424254885Sdumbbell# define AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0) 425254885Sdumbbell 426254885Sdumbbell#define AVIVO_D1CUR_CONTROL 0x6400 427254885Sdumbbell# define AVIVO_D1CURSOR_EN (1 << 0) 428254885Sdumbbell# define AVIVO_D1CURSOR_MODE_SHIFT 8 429254885Sdumbbell# define AVIVO_D1CURSOR_MODE_MASK (3 << 8) 430254885Sdumbbell# define AVIVO_D1CURSOR_MODE_24BPP 2 431254885Sdumbbell#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 432254885Sdumbbell#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c 433254885Sdumbbell#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c 434254885Sdumbbell#define AVIVO_D1CUR_SIZE 0x6410 435254885Sdumbbell#define AVIVO_D1CUR_POSITION 0x6414 436254885Sdumbbell#define AVIVO_D1CUR_HOT_SPOT 0x6418 437254885Sdumbbell#define AVIVO_D1CUR_UPDATE 0x6424 438254885Sdumbbell# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) 439254885Sdumbbell 440254885Sdumbbell#define AVIVO_DC_LUT_RW_SELECT 0x6480 441254885Sdumbbell#define AVIVO_DC_LUT_RW_MODE 0x6484 442254885Sdumbbell#define AVIVO_DC_LUT_RW_INDEX 0x6488 443254885Sdumbbell#define AVIVO_DC_LUT_SEQ_COLOR 0x648c 444254885Sdumbbell#define AVIVO_DC_LUT_PWL_DATA 0x6490 445254885Sdumbbell#define AVIVO_DC_LUT_30_COLOR 0x6494 446254885Sdumbbell#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 447254885Sdumbbell#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c 448254885Sdumbbell#define AVIVO_DC_LUT_AUTOFILL 0x64a0 449254885Sdumbbell 450254885Sdumbbell#define AVIVO_DC_LUTA_CONTROL 0x64c0 451254885Sdumbbell#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 452254885Sdumbbell#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 453254885Sdumbbell#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc 454254885Sdumbbell#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 455254885Sdumbbell#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 456254885Sdumbbell#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 457254885Sdumbbell 458254885Sdumbbell#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 459254885Sdumbbell# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 460254885Sdumbbell# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 461254885Sdumbbell# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 462254885Sdumbbell# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 463254885Sdumbbell# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 464254885Sdumbbell# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 465254885Sdumbbell# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) 466254885Sdumbbell# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 467254885Sdumbbell# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff 468254885Sdumbbell 469254885Sdumbbell#define AVIVO_D1MODE_DATA_FORMAT 0x6528 470254885Sdumbbell# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) 471254885Sdumbbell#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C 472254885Sdumbbell#define AVIVO_D1MODE_VBLANK_STATUS 0x6534 473254885Sdumbbell# define AVIVO_VBLANK_ACK (1 << 4) 474254885Sdumbbell#define AVIVO_D1MODE_VLINE_START_END 0x6538 475254885Sdumbbell#define AVIVO_D1MODE_VLINE_STATUS 0x653c 476254885Sdumbbell# define AVIVO_D1MODE_VLINE_STAT (1 << 12) 477254885Sdumbbell#define AVIVO_DxMODE_INT_MASK 0x6540 478254885Sdumbbell# define AVIVO_D1MODE_INT_MASK (1 << 0) 479254885Sdumbbell# define AVIVO_D2MODE_INT_MASK (1 << 8) 480254885Sdumbbell#define AVIVO_D1MODE_VIEWPORT_START 0x6580 481254885Sdumbbell#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 482254885Sdumbbell#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 483254885Sdumbbell#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c 484254885Sdumbbell 485254885Sdumbbell#define AVIVO_D1SCL_SCALER_ENABLE 0x6590 486254885Sdumbbell#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 487254885Sdumbbell#define AVIVO_D1SCL_UPDATE 0x65cc 488254885Sdumbbell# define AVIVO_D1SCL_UPDATE_LOCK (1 << 16) 489254885Sdumbbell 490254885Sdumbbell/* second crtc */ 491254885Sdumbbell#define AVIVO_D2CRTC_H_TOTAL 0x6800 492254885Sdumbbell#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 493254885Sdumbbell#define AVIVO_D2CRTC_H_SYNC_A 0x6808 494254885Sdumbbell#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c 495254885Sdumbbell#define AVIVO_D2CRTC_H_SYNC_B 0x6810 496254885Sdumbbell#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 497254885Sdumbbell 498254885Sdumbbell#define AVIVO_D2CRTC_V_TOTAL 0x6820 499254885Sdumbbell#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 500254885Sdumbbell#define AVIVO_D2CRTC_V_SYNC_A 0x6828 501254885Sdumbbell#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c 502254885Sdumbbell#define AVIVO_D2CRTC_V_SYNC_B 0x6830 503254885Sdumbbell#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 504254885Sdumbbell 505254885Sdumbbell#define AVIVO_D2CRTC_CONTROL 0x6880 506254885Sdumbbell#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 507254885Sdumbbell#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 508254885Sdumbbell#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c 509254885Sdumbbell#define AVIVO_D2CRTC_STATUS_POSITION 0x68a0 510254885Sdumbbell#define AVIVO_D2CRTC_FRAME_COUNT 0x68a4 511254885Sdumbbell#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 512254885Sdumbbell 513254885Sdumbbell#define AVIVO_D2GRPH_ENABLE 0x6900 514254885Sdumbbell#define AVIVO_D2GRPH_CONTROL 0x6904 515254885Sdumbbell#define AVIVO_D2GRPH_LUT_SEL 0x6908 516254885Sdumbbell#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 517254885Sdumbbell#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 518254885Sdumbbell#define AVIVO_D2GRPH_PITCH 0x6920 519254885Sdumbbell#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 520254885Sdumbbell#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 521254885Sdumbbell#define AVIVO_D2GRPH_X_START 0x692c 522254885Sdumbbell#define AVIVO_D2GRPH_Y_START 0x6930 523254885Sdumbbell#define AVIVO_D2GRPH_X_END 0x6934 524254885Sdumbbell#define AVIVO_D2GRPH_Y_END 0x6938 525254885Sdumbbell#define AVIVO_D2GRPH_UPDATE 0x6944 526254885Sdumbbell#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 527254885Sdumbbell 528254885Sdumbbell#define AVIVO_D2CUR_CONTROL 0x6c00 529254885Sdumbbell#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 530254885Sdumbbell#define AVIVO_D2CUR_SIZE 0x6c10 531254885Sdumbbell#define AVIVO_D2CUR_POSITION 0x6c14 532254885Sdumbbell 533254885Sdumbbell#define AVIVO_D2MODE_VBLANK_STATUS 0x6d34 534254885Sdumbbell#define AVIVO_D2MODE_VLINE_START_END 0x6d38 535254885Sdumbbell#define AVIVO_D2MODE_VLINE_STATUS 0x6d3c 536254885Sdumbbell#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 537254885Sdumbbell#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 538254885Sdumbbell#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 539254885Sdumbbell#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c 540254885Sdumbbell 541254885Sdumbbell#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 542254885Sdumbbell#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 543254885Sdumbbell 544254885Sdumbbell#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 545254885Sdumbbell 546254885Sdumbbell#define AVIVO_DACA_ENABLE 0x7800 547254885Sdumbbell# define AVIVO_DAC_ENABLE (1 << 0) 548254885Sdumbbell#define AVIVO_DACA_SOURCE_SELECT 0x7804 549254885Sdumbbell# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) 550254885Sdumbbell# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) 551254885Sdumbbell# define AVIVO_DAC_SOURCE_TV (2 << 0) 552254885Sdumbbell 553254885Sdumbbell#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c 554254885Sdumbbell# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) 555254885Sdumbbell# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) 556254885Sdumbbell# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) 557254885Sdumbbell# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) 558254885Sdumbbell# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) 559254885Sdumbbell# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) 560254885Sdumbbell#define AVIVO_DACA_POWERDOWN 0x7850 561254885Sdumbbell# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) 562254885Sdumbbell# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) 563254885Sdumbbell# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) 564254885Sdumbbell# define AVIVO_DACA_POWERDOWN_RED (1 << 24) 565254885Sdumbbell 566254885Sdumbbell#define AVIVO_DACB_ENABLE 0x7a00 567254885Sdumbbell#define AVIVO_DACB_SOURCE_SELECT 0x7a04 568254885Sdumbbell#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c 569254885Sdumbbell# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) 570254885Sdumbbell# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) 571254885Sdumbbell# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) 572254885Sdumbbell# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) 573254885Sdumbbell# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) 574254885Sdumbbell# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) 575254885Sdumbbell#define AVIVO_DACB_POWERDOWN 0x7a50 576254885Sdumbbell# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) 577254885Sdumbbell# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) 578254885Sdumbbell# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) 579254885Sdumbbell# define AVIVO_DACB_POWERDOWN_RED 580254885Sdumbbell 581254885Sdumbbell#define AVIVO_TMDSA_CNTL 0x7880 582254885Sdumbbell# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) 583254885Sdumbbell# define AVIVO_TMDSA_CNTL_HDMI_EN (1 << 2) 584254885Sdumbbell# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) 585254885Sdumbbell# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) 586254885Sdumbbell# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) 587254885Sdumbbell# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) 588254885Sdumbbell# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) 589254885Sdumbbell# define AVIVO_TMDSA_CNTL_SWAP (1 << 28) 590254885Sdumbbell#define AVIVO_TMDSA_SOURCE_SELECT 0x7884 591254885Sdumbbell/* 78a8 appears to be some kind of (reasonably tolerant) clock? 592254885Sdumbbell * 78d0 definitely hits the transmitter, definitely clock. */ 593254885Sdumbbell/* MYSTERY1 This appears to control dithering? */ 594254885Sdumbbell#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 595254885Sdumbbell# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) 596254885Sdumbbell# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) 597254885Sdumbbell# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) 598254885Sdumbbell# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) 599254885Sdumbbell# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) 600254885Sdumbbell# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) 601254885Sdumbbell# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) 602254885Sdumbbell# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) 603254885Sdumbbell#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 604254885Sdumbbell# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) 605254885Sdumbbell# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) 606254885Sdumbbell# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) 607254885Sdumbbell# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) 608254885Sdumbbell#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 609254885Sdumbbell# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) 610254885Sdumbbell# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) 611254885Sdumbbell#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 612254885Sdumbbell#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 613254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) 614254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) 615254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) 616254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) 617254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) 618254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) 619254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) 620254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) 621254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) 622254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) 623254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) 624254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) 625254885Sdumbbell 626254885Sdumbbell#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 627254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) 628254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) 629254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) 630254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) 631254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) 632254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) 633254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) 634254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) 635254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) 636254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) 637254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) 638254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) 639254885Sdumbbell# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) 640261455Seadler# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31) 641254885Sdumbbell 642254885Sdumbbell#define AVIVO_LVTMA_CNTL 0x7a80 643254885Sdumbbell# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) 644254885Sdumbbell# define AVIVO_LVTMA_CNTL_HDMI_EN (1 << 2) 645254885Sdumbbell# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) 646254885Sdumbbell# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) 647254885Sdumbbell# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) 648254885Sdumbbell# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) 649254885Sdumbbell# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) 650254885Sdumbbell# define AVIVO_LVTMA_CNTL_SWAP (1 << 28) 651254885Sdumbbell#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 652254885Sdumbbell#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 653254885Sdumbbell#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 654254885Sdumbbell# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) 655254885Sdumbbell# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) 656254885Sdumbbell# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) 657254885Sdumbbell# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) 658254885Sdumbbell# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) 659254885Sdumbbell# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) 660254885Sdumbbell# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) 661254885Sdumbbell# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) 662254885Sdumbbell 663254885Sdumbbell 664254885Sdumbbell 665254885Sdumbbell#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 666254885Sdumbbell# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) 667254885Sdumbbell# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) 668254885Sdumbbell# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) 669254885Sdumbbell# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) 670254885Sdumbbell 671254885Sdumbbell#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 672254885Sdumbbell# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) 673254885Sdumbbell# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) 674254885Sdumbbell#define R500_LVTMA_CLOCK_ENABLE 0x7b00 675254885Sdumbbell#define R600_LVTMA_CLOCK_ENABLE 0x7b04 676254885Sdumbbell 677254885Sdumbbell#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 678254885Sdumbbell#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 679254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) 680254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) 681254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) 682254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) 683254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) 684254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) 685254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) 686254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) 687254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) 688254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) 689254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) 690254885Sdumbbell 691254885Sdumbbell#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 692254885Sdumbbell#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 693254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) 694254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) 695254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) 696254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) 697254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) 698254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) 699254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) 700254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) 701254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) 702254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) 703254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) 704254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) 705254885Sdumbbell# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) 706261455Seadler# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1U << 31) 707254885Sdumbbell 708254885Sdumbbell#define R500_LVTMA_PWRSEQ_CNTL 0x7af0 709254885Sdumbbell#define R600_LVTMA_PWRSEQ_CNTL 0x7af4 710254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) 711254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) 712254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) 713254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) 714254885Sdumbbell# define AVIVO_LVTMA_SYNCEN (1 << 8) 715254885Sdumbbell# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) 716254885Sdumbbell# define AVIVO_LVTMA_SYNCEN_POL (1 << 10) 717254885Sdumbbell# define AVIVO_LVTMA_DIGON (1 << 16) 718254885Sdumbbell# define AVIVO_LVTMA_DIGON_OVRD (1 << 17) 719254885Sdumbbell# define AVIVO_LVTMA_DIGON_POL (1 << 18) 720254885Sdumbbell# define AVIVO_LVTMA_BLON (1 << 24) 721254885Sdumbbell# define AVIVO_LVTMA_BLON_OVRD (1 << 25) 722254885Sdumbbell# define AVIVO_LVTMA_BLON_POL (1 << 26) 723254885Sdumbbell 724254885Sdumbbell#define R500_LVTMA_PWRSEQ_STATE 0x7af4 725254885Sdumbbell#define R600_LVTMA_PWRSEQ_STATE 0x7af8 726254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) 727254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) 728254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) 729254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) 730254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) 731254885Sdumbbell# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) 732254885Sdumbbell 733254885Sdumbbell#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 734254885Sdumbbell# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) 735254885Sdumbbell# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 736254885Sdumbbell# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 737254885Sdumbbell 738254885Sdumbbell#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 739254885Sdumbbell 740254885Sdumbbell#define AVIVO_DC_GPIO_HPD_A 0x7e94 741254885Sdumbbell#define AVIVO_DC_GPIO_HPD_Y 0x7e9c 742254885Sdumbbell 743254885Sdumbbell#define AVIVO_DC_I2C_STATUS1 0x7d30 744254885Sdumbbell# define AVIVO_DC_I2C_DONE (1 << 0) 745254885Sdumbbell# define AVIVO_DC_I2C_NACK (1 << 1) 746254885Sdumbbell# define AVIVO_DC_I2C_HALT (1 << 2) 747254885Sdumbbell# define AVIVO_DC_I2C_GO (1 << 3) 748254885Sdumbbell#define AVIVO_DC_I2C_RESET 0x7d34 749254885Sdumbbell# define AVIVO_DC_I2C_SOFT_RESET (1 << 0) 750254885Sdumbbell# define AVIVO_DC_I2C_ABORT (1 << 8) 751254885Sdumbbell#define AVIVO_DC_I2C_CONTROL1 0x7d38 752254885Sdumbbell# define AVIVO_DC_I2C_START (1 << 0) 753254885Sdumbbell# define AVIVO_DC_I2C_STOP (1 << 1) 754254885Sdumbbell# define AVIVO_DC_I2C_RECEIVE (1 << 2) 755254885Sdumbbell# define AVIVO_DC_I2C_EN (1 << 8) 756254885Sdumbbell# define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16) 757254885Sdumbbell# define AVIVO_SEL_DDC1 0 758254885Sdumbbell# define AVIVO_SEL_DDC2 1 759254885Sdumbbell# define AVIVO_SEL_DDC3 2 760254885Sdumbbell#define AVIVO_DC_I2C_CONTROL2 0x7d3c 761254885Sdumbbell# define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0) 762254885Sdumbbell# define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8) 763254885Sdumbbell#define AVIVO_DC_I2C_CONTROL3 0x7d40 764254885Sdumbbell# define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0) 765254885Sdumbbell# define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1) 766254885Sdumbbell# define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7) 767254885Sdumbbell# define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8) 768254885Sdumbbell# define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16) 769254885Sdumbbell# define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24) 770254885Sdumbbell#define AVIVO_DC_I2C_DATA 0x7d44 771254885Sdumbbell#define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48 772254885Sdumbbell# define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0) 773254885Sdumbbell# define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8) 774254885Sdumbbell# define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16) 775254885Sdumbbell#define AVIVO_DC_I2C_ARBITRATION 0x7d50 776254885Sdumbbell# define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0) 777254885Sdumbbell# define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1) 778254885Sdumbbell# define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8) 779254885Sdumbbell# define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9) 780254885Sdumbbell# define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16) 781254885Sdumbbell# define AVIVO_DC_I2C_HW_USING_I2C (1 << 17) 782254885Sdumbbell 783254885Sdumbbell#define AVIVO_DC_GPIO_DDC1_MASK 0x7e40 784254885Sdumbbell#define AVIVO_DC_GPIO_DDC1_A 0x7e44 785254885Sdumbbell#define AVIVO_DC_GPIO_DDC1_EN 0x7e48 786254885Sdumbbell#define AVIVO_DC_GPIO_DDC1_Y 0x7e4c 787254885Sdumbbell 788254885Sdumbbell#define AVIVO_DC_GPIO_DDC2_MASK 0x7e50 789254885Sdumbbell#define AVIVO_DC_GPIO_DDC2_A 0x7e54 790254885Sdumbbell#define AVIVO_DC_GPIO_DDC2_EN 0x7e58 791254885Sdumbbell#define AVIVO_DC_GPIO_DDC2_Y 0x7e5c 792254885Sdumbbell 793254885Sdumbbell#define AVIVO_DC_GPIO_DDC3_MASK 0x7e60 794254885Sdumbbell#define AVIVO_DC_GPIO_DDC3_A 0x7e64 795254885Sdumbbell#define AVIVO_DC_GPIO_DDC3_EN 0x7e68 796254885Sdumbbell#define AVIVO_DC_GPIO_DDC3_Y 0x7e6c 797254885Sdumbbell 798254885Sdumbbell#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc 799254885Sdumbbell# define AVIVO_D1_VBLANK_INTERRUPT (1 << 4) 800254885Sdumbbell# define AVIVO_D2_VBLANK_INTERRUPT (1 << 5) 801254885Sdumbbell 802254885Sdumbbell#endif 803