nid.h revision 282199
1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2010 Advanced Micro Devices, Inc. 3254885Sdumbbell * 4254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 5254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 6254885Sdumbbell * to deal in the Software without restriction, including without limitation 7254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 9254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 10254885Sdumbbell * 11254885Sdumbbell * The above copyright notice and this permission notice shall be included in 12254885Sdumbbell * all copies or substantial portions of the Software. 13254885Sdumbbell * 14254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17254885Sdumbbell * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20254885Sdumbbell * OTHER DEALINGS IN THE SOFTWARE. 21254885Sdumbbell * 22254885Sdumbbell * Authors: Alex Deucher 23254885Sdumbbell */ 24254885Sdumbbell#ifndef NI_H 25254885Sdumbbell#define NI_H 26254885Sdumbbell 27254885Sdumbbell#include <sys/cdefs.h> 28254885Sdumbbell__FBSDID("$FreeBSD: stable/10/sys/dev/drm2/radeon/nid.h 282199 2015-04-28 19:35:05Z dumbbell $"); 29254885Sdumbbell 30254885Sdumbbell#define CAYMAN_MAX_SH_GPRS 256 31254885Sdumbbell#define CAYMAN_MAX_TEMP_GPRS 16 32254885Sdumbbell#define CAYMAN_MAX_SH_THREADS 256 33254885Sdumbbell#define CAYMAN_MAX_SH_STACK_ENTRIES 4096 34254885Sdumbbell#define CAYMAN_MAX_FRC_EOV_CNT 16384 35254885Sdumbbell#define CAYMAN_MAX_BACKENDS 8 36254885Sdumbbell#define CAYMAN_MAX_BACKENDS_MASK 0xFF 37254885Sdumbbell#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 38254885Sdumbbell#define CAYMAN_MAX_SIMDS 16 39254885Sdumbbell#define CAYMAN_MAX_SIMDS_MASK 0xFFFF 40254885Sdumbbell#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 41254885Sdumbbell#define CAYMAN_MAX_PIPES 8 42254885Sdumbbell#define CAYMAN_MAX_PIPES_MASK 0xFF 43254885Sdumbbell#define CAYMAN_MAX_LDS_NUM 0xFFFF 44254885Sdumbbell#define CAYMAN_MAX_TCC 16 45254885Sdumbbell#define CAYMAN_MAX_TCC_MASK 0xFF 46254885Sdumbbell 47254885Sdumbbell#define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 48254885Sdumbbell#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 49254885Sdumbbell 50254885Sdumbbell#define DMIF_ADDR_CONFIG 0xBD4 51282199Sdumbbell 52282199Sdumbbell/* DCE6 only */ 53282199Sdumbbell#define DMIF_ADDR_CALC 0xC00 54282199Sdumbbell 55254885Sdumbbell#define SRBM_GFX_CNTL 0x0E44 56254885Sdumbbell#define RINGID(x) (((x) & 0x3) << 0) 57254885Sdumbbell#define VMID(x) (((x) & 0x7) << 0) 58254885Sdumbbell#define SRBM_STATUS 0x0E50 59254885Sdumbbell 60254885Sdumbbell#define SRBM_SOFT_RESET 0x0E60 61254885Sdumbbell#define SOFT_RESET_BIF (1 << 1) 62254885Sdumbbell#define SOFT_RESET_CG (1 << 2) 63254885Sdumbbell#define SOFT_RESET_DC (1 << 5) 64254885Sdumbbell#define SOFT_RESET_DMA1 (1 << 6) 65254885Sdumbbell#define SOFT_RESET_GRBM (1 << 8) 66254885Sdumbbell#define SOFT_RESET_HDP (1 << 9) 67254885Sdumbbell#define SOFT_RESET_IH (1 << 10) 68254885Sdumbbell#define SOFT_RESET_MC (1 << 11) 69254885Sdumbbell#define SOFT_RESET_RLC (1 << 13) 70254885Sdumbbell#define SOFT_RESET_ROM (1 << 14) 71254885Sdumbbell#define SOFT_RESET_SEM (1 << 15) 72254885Sdumbbell#define SOFT_RESET_VMC (1 << 17) 73254885Sdumbbell#define SOFT_RESET_DMA (1 << 20) 74254885Sdumbbell#define SOFT_RESET_TST (1 << 21) 75254885Sdumbbell#define SOFT_RESET_REGBB (1 << 22) 76254885Sdumbbell#define SOFT_RESET_ORB (1 << 23) 77254885Sdumbbell 78254885Sdumbbell#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 79254885Sdumbbell#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 80254885Sdumbbell#define RESPONSE_TYPE_MASK 0x000000F0 81254885Sdumbbell#define RESPONSE_TYPE_SHIFT 4 82254885Sdumbbell#define VM_L2_CNTL 0x1400 83254885Sdumbbell#define ENABLE_L2_CACHE (1 << 0) 84254885Sdumbbell#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 85254885Sdumbbell#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 86254885Sdumbbell#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 87254885Sdumbbell#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 88254885Sdumbbell#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 89254885Sdumbbell/* CONTEXT1_IDENTITY_ACCESS_MODE 90254885Sdumbbell * 0 physical = logical 91254885Sdumbbell * 1 logical via context1 page table 92254885Sdumbbell * 2 inside identity aperture use translation, outside physical = logical 93254885Sdumbbell * 3 inside identity aperture physical = logical, outside use translation 94254885Sdumbbell */ 95254885Sdumbbell#define VM_L2_CNTL2 0x1404 96254885Sdumbbell#define INVALIDATE_ALL_L1_TLBS (1 << 0) 97254885Sdumbbell#define INVALIDATE_L2_CACHE (1 << 1) 98254885Sdumbbell#define VM_L2_CNTL3 0x1408 99254885Sdumbbell#define BANK_SELECT(x) ((x) << 0) 100254885Sdumbbell#define CACHE_UPDATE_MODE(x) ((x) << 6) 101254885Sdumbbell#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 102254885Sdumbbell#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 103254885Sdumbbell#define VM_L2_STATUS 0x140C 104254885Sdumbbell#define L2_BUSY (1 << 0) 105254885Sdumbbell#define VM_CONTEXT0_CNTL 0x1410 106254885Sdumbbell#define ENABLE_CONTEXT (1 << 0) 107254885Sdumbbell#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 108254885Sdumbbell#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 109254885Sdumbbell#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 110254885Sdumbbell#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 111254885Sdumbbell#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 112254885Sdumbbell#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 113254885Sdumbbell#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 114254885Sdumbbell#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 115254885Sdumbbell#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 116254885Sdumbbell#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 117254885Sdumbbell#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 118254885Sdumbbell#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 119254885Sdumbbell#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 120254885Sdumbbell#define VM_CONTEXT1_CNTL 0x1414 121254885Sdumbbell#define VM_CONTEXT0_CNTL2 0x1430 122254885Sdumbbell#define VM_CONTEXT1_CNTL2 0x1434 123254885Sdumbbell#define VM_INVALIDATE_REQUEST 0x1478 124254885Sdumbbell#define VM_INVALIDATE_RESPONSE 0x147c 125254885Sdumbbell#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 126254885Sdumbbell#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 127254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 128254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 129254885Sdumbbell#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 130254885Sdumbbell 131254885Sdumbbell#define MC_SHARED_CHMAP 0x2004 132254885Sdumbbell#define NOOFCHAN_SHIFT 12 133254885Sdumbbell#define NOOFCHAN_MASK 0x00003000 134254885Sdumbbell#define MC_SHARED_CHREMAP 0x2008 135254885Sdumbbell 136254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 137254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 138254885Sdumbbell#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 139254885Sdumbbell#define MC_VM_MX_L1_TLB_CNTL 0x2064 140254885Sdumbbell#define ENABLE_L1_TLB (1 << 0) 141254885Sdumbbell#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 142254885Sdumbbell#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 143254885Sdumbbell#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 144254885Sdumbbell#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 145254885Sdumbbell#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 146254885Sdumbbell#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 147254885Sdumbbell#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 148254885Sdumbbell#define FUS_MC_VM_FB_OFFSET 0x2068 149254885Sdumbbell 150254885Sdumbbell#define MC_SHARED_BLACKOUT_CNTL 0x20ac 151254885Sdumbbell#define MC_ARB_RAMCFG 0x2760 152254885Sdumbbell#define NOOFBANK_SHIFT 0 153254885Sdumbbell#define NOOFBANK_MASK 0x00000003 154254885Sdumbbell#define NOOFRANK_SHIFT 2 155254885Sdumbbell#define NOOFRANK_MASK 0x00000004 156254885Sdumbbell#define NOOFROWS_SHIFT 3 157254885Sdumbbell#define NOOFROWS_MASK 0x00000038 158254885Sdumbbell#define NOOFCOLS_SHIFT 6 159254885Sdumbbell#define NOOFCOLS_MASK 0x000000C0 160254885Sdumbbell#define CHANSIZE_SHIFT 8 161254885Sdumbbell#define CHANSIZE_MASK 0x00000100 162254885Sdumbbell#define BURSTLENGTH_SHIFT 9 163254885Sdumbbell#define BURSTLENGTH_MASK 0x00000200 164254885Sdumbbell#define CHANSIZE_OVERRIDE (1 << 11) 165254885Sdumbbell#define MC_SEQ_SUP_CNTL 0x28c8 166254885Sdumbbell#define RUN_MASK (1 << 0) 167254885Sdumbbell#define MC_SEQ_SUP_PGM 0x28cc 168254885Sdumbbell#define MC_IO_PAD_CNTL_D0 0x29d0 169254885Sdumbbell#define MEM_FALL_OUT_CMD (1 << 8) 170254885Sdumbbell#define MC_SEQ_MISC0 0x2a00 171254885Sdumbbell#define MC_SEQ_MISC0_GDDR5_SHIFT 28 172254885Sdumbbell#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 173254885Sdumbbell#define MC_SEQ_MISC0_GDDR5_VALUE 5 174254885Sdumbbell#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 175254885Sdumbbell#define MC_SEQ_IO_DEBUG_DATA 0x2a48 176254885Sdumbbell 177254885Sdumbbell#define HDP_HOST_PATH_CNTL 0x2C00 178254885Sdumbbell#define HDP_NONSURFACE_BASE 0x2C04 179254885Sdumbbell#define HDP_NONSURFACE_INFO 0x2C08 180254885Sdumbbell#define HDP_NONSURFACE_SIZE 0x2C0C 181254885Sdumbbell#define HDP_ADDR_CONFIG 0x2F48 182254885Sdumbbell#define HDP_MISC_CNTL 0x2F4C 183254885Sdumbbell#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 184254885Sdumbbell 185254885Sdumbbell#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 186254885Sdumbbell#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 187254885Sdumbbell#define CGTS_SYS_TCC_DISABLE 0x3F90 188254885Sdumbbell#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 189254885Sdumbbell 190254885Sdumbbell#define RLC_GFX_INDEX 0x3FC4 191254885Sdumbbell 192254885Sdumbbell#define CONFIG_MEMSIZE 0x5428 193254885Sdumbbell 194254885Sdumbbell#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 195254885Sdumbbell#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 196254885Sdumbbell 197254885Sdumbbell#define GRBM_CNTL 0x8000 198254885Sdumbbell#define GRBM_READ_TIMEOUT(x) ((x) << 0) 199254885Sdumbbell#define GRBM_STATUS 0x8010 200254885Sdumbbell#define CMDFIFO_AVAIL_MASK 0x0000000F 201254885Sdumbbell#define RING2_RQ_PENDING (1 << 4) 202254885Sdumbbell#define SRBM_RQ_PENDING (1 << 5) 203254885Sdumbbell#define RING1_RQ_PENDING (1 << 6) 204254885Sdumbbell#define CF_RQ_PENDING (1 << 7) 205254885Sdumbbell#define PF_RQ_PENDING (1 << 8) 206254885Sdumbbell#define GDS_DMA_RQ_PENDING (1 << 9) 207254885Sdumbbell#define GRBM_EE_BUSY (1 << 10) 208254885Sdumbbell#define SX_CLEAN (1 << 11) 209254885Sdumbbell#define DB_CLEAN (1 << 12) 210254885Sdumbbell#define CB_CLEAN (1 << 13) 211254885Sdumbbell#define TA_BUSY (1 << 14) 212254885Sdumbbell#define GDS_BUSY (1 << 15) 213254885Sdumbbell#define VGT_BUSY_NO_DMA (1 << 16) 214254885Sdumbbell#define VGT_BUSY (1 << 17) 215254885Sdumbbell#define IA_BUSY_NO_DMA (1 << 18) 216254885Sdumbbell#define IA_BUSY (1 << 19) 217254885Sdumbbell#define SX_BUSY (1 << 20) 218254885Sdumbbell#define SH_BUSY (1 << 21) 219254885Sdumbbell#define SPI_BUSY (1 << 22) 220254885Sdumbbell#define SC_BUSY (1 << 24) 221254885Sdumbbell#define PA_BUSY (1 << 25) 222254885Sdumbbell#define DB_BUSY (1 << 26) 223254885Sdumbbell#define CP_COHERENCY_BUSY (1 << 28) 224254885Sdumbbell#define CP_BUSY (1 << 29) 225254885Sdumbbell#define CB_BUSY (1 << 30) 226261455Seadler#define GUI_ACTIVE (1U << 31) 227254885Sdumbbell#define GRBM_STATUS_SE0 0x8014 228254885Sdumbbell#define GRBM_STATUS_SE1 0x8018 229254885Sdumbbell#define SE_SX_CLEAN (1 << 0) 230254885Sdumbbell#define SE_DB_CLEAN (1 << 1) 231254885Sdumbbell#define SE_CB_CLEAN (1 << 2) 232254885Sdumbbell#define SE_VGT_BUSY (1 << 23) 233254885Sdumbbell#define SE_PA_BUSY (1 << 24) 234254885Sdumbbell#define SE_TA_BUSY (1 << 25) 235254885Sdumbbell#define SE_SX_BUSY (1 << 26) 236254885Sdumbbell#define SE_SPI_BUSY (1 << 27) 237254885Sdumbbell#define SE_SH_BUSY (1 << 28) 238254885Sdumbbell#define SE_SC_BUSY (1 << 29) 239254885Sdumbbell#define SE_DB_BUSY (1 << 30) 240261455Seadler#define SE_CB_BUSY (1U << 31) 241254885Sdumbbell#define GRBM_SOFT_RESET 0x8020 242254885Sdumbbell#define SOFT_RESET_CP (1 << 0) 243254885Sdumbbell#define SOFT_RESET_CB (1 << 1) 244254885Sdumbbell#define SOFT_RESET_DB (1 << 3) 245254885Sdumbbell#define SOFT_RESET_GDS (1 << 4) 246254885Sdumbbell#define SOFT_RESET_PA (1 << 5) 247254885Sdumbbell#define SOFT_RESET_SC (1 << 6) 248254885Sdumbbell#define SOFT_RESET_SPI (1 << 8) 249254885Sdumbbell#define SOFT_RESET_SH (1 << 9) 250254885Sdumbbell#define SOFT_RESET_SX (1 << 10) 251254885Sdumbbell#define SOFT_RESET_TC (1 << 11) 252254885Sdumbbell#define SOFT_RESET_TA (1 << 12) 253254885Sdumbbell#define SOFT_RESET_VGT (1 << 14) 254254885Sdumbbell#define SOFT_RESET_IA (1 << 15) 255254885Sdumbbell 256254885Sdumbbell#define GRBM_GFX_INDEX 0x802C 257254885Sdumbbell#define INSTANCE_INDEX(x) ((x) << 0) 258254885Sdumbbell#define SE_INDEX(x) ((x) << 16) 259254885Sdumbbell#define INSTANCE_BROADCAST_WRITES (1 << 30) 260261455Seadler#define SE_BROADCAST_WRITES (1U << 31) 261254885Sdumbbell 262254885Sdumbbell#define SCRATCH_REG0 0x8500 263254885Sdumbbell#define SCRATCH_REG1 0x8504 264254885Sdumbbell#define SCRATCH_REG2 0x8508 265254885Sdumbbell#define SCRATCH_REG3 0x850C 266254885Sdumbbell#define SCRATCH_REG4 0x8510 267254885Sdumbbell#define SCRATCH_REG5 0x8514 268254885Sdumbbell#define SCRATCH_REG6 0x8518 269254885Sdumbbell#define SCRATCH_REG7 0x851C 270254885Sdumbbell#define SCRATCH_UMSK 0x8540 271254885Sdumbbell#define SCRATCH_ADDR 0x8544 272254885Sdumbbell#define CP_SEM_WAIT_TIMER 0x85BC 273254885Sdumbbell#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 274254885Sdumbbell#define CP_COHER_CNTL2 0x85E8 275254885Sdumbbell#define CP_STALLED_STAT1 0x8674 276254885Sdumbbell#define CP_STALLED_STAT2 0x8678 277254885Sdumbbell#define CP_BUSY_STAT 0x867C 278254885Sdumbbell#define CP_STAT 0x8680 279254885Sdumbbell#define CP_ME_CNTL 0x86D8 280254885Sdumbbell#define CP_ME_HALT (1 << 28) 281254885Sdumbbell#define CP_PFP_HALT (1 << 26) 282254885Sdumbbell#define CP_RB2_RPTR 0x86f8 283254885Sdumbbell#define CP_RB1_RPTR 0x86fc 284254885Sdumbbell#define CP_RB0_RPTR 0x8700 285254885Sdumbbell#define CP_RB_WPTR_DELAY 0x8704 286254885Sdumbbell#define CP_MEQ_THRESHOLDS 0x8764 287254885Sdumbbell#define MEQ1_START(x) ((x) << 0) 288254885Sdumbbell#define MEQ2_START(x) ((x) << 8) 289254885Sdumbbell#define CP_PERFMON_CNTL 0x87FC 290254885Sdumbbell 291254885Sdumbbell#define VGT_CACHE_INVALIDATION 0x88C4 292254885Sdumbbell#define CACHE_INVALIDATION(x) ((x) << 0) 293254885Sdumbbell#define VC_ONLY 0 294254885Sdumbbell#define TC_ONLY 1 295254885Sdumbbell#define VC_AND_TC 2 296254885Sdumbbell#define AUTO_INVLD_EN(x) ((x) << 6) 297254885Sdumbbell#define NO_AUTO 0 298254885Sdumbbell#define ES_AUTO 1 299254885Sdumbbell#define GS_AUTO 2 300254885Sdumbbell#define ES_AND_GS_AUTO 3 301254885Sdumbbell#define VGT_GS_VERTEX_REUSE 0x88D4 302254885Sdumbbell 303254885Sdumbbell#define CC_GC_SHADER_PIPE_CONFIG 0x8950 304254885Sdumbbell#define GC_USER_SHADER_PIPE_CONFIG 0x8954 305254885Sdumbbell#define INACTIVE_QD_PIPES(x) ((x) << 8) 306254885Sdumbbell#define INACTIVE_QD_PIPES_MASK 0x0000FF00 307254885Sdumbbell#define INACTIVE_QD_PIPES_SHIFT 8 308254885Sdumbbell#define INACTIVE_SIMDS(x) ((x) << 16) 309254885Sdumbbell#define INACTIVE_SIMDS_MASK 0xFFFF0000 310254885Sdumbbell#define INACTIVE_SIMDS_SHIFT 16 311254885Sdumbbell 312254885Sdumbbell#define VGT_PRIMITIVE_TYPE 0x8958 313254885Sdumbbell#define VGT_NUM_INSTANCES 0x8974 314254885Sdumbbell#define VGT_TF_RING_SIZE 0x8988 315254885Sdumbbell#define VGT_OFFCHIP_LDS_BASE 0x89b4 316254885Sdumbbell 317254885Sdumbbell#define PA_SC_LINE_STIPPLE_STATE 0x8B10 318254885Sdumbbell#define PA_CL_ENHANCE 0x8A14 319254885Sdumbbell#define CLIP_VTX_REORDER_ENA (1 << 0) 320254885Sdumbbell#define NUM_CLIP_SEQ(x) ((x) << 1) 321254885Sdumbbell#define PA_SC_FIFO_SIZE 0x8BCC 322254885Sdumbbell#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 323254885Sdumbbell#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 324254885Sdumbbell#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 325254885Sdumbbell#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 326254885Sdumbbell#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 327254885Sdumbbell#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 328254885Sdumbbell 329254885Sdumbbell#define SQ_CONFIG 0x8C00 330254885Sdumbbell#define VC_ENABLE (1 << 0) 331254885Sdumbbell#define EXPORT_SRC_C (1 << 1) 332254885Sdumbbell#define GFX_PRIO(x) ((x) << 2) 333254885Sdumbbell#define CS1_PRIO(x) ((x) << 4) 334254885Sdumbbell#define CS2_PRIO(x) ((x) << 6) 335254885Sdumbbell#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 336254885Sdumbbell#define NUM_PS_GPRS(x) ((x) << 0) 337254885Sdumbbell#define NUM_VS_GPRS(x) ((x) << 16) 338254885Sdumbbell#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 339254885Sdumbbell#define SQ_ESGS_RING_SIZE 0x8c44 340254885Sdumbbell#define SQ_GSVS_RING_SIZE 0x8c4c 341254885Sdumbbell#define SQ_ESTMP_RING_BASE 0x8c50 342254885Sdumbbell#define SQ_ESTMP_RING_SIZE 0x8c54 343254885Sdumbbell#define SQ_GSTMP_RING_BASE 0x8c58 344254885Sdumbbell#define SQ_GSTMP_RING_SIZE 0x8c5c 345254885Sdumbbell#define SQ_VSTMP_RING_BASE 0x8c60 346254885Sdumbbell#define SQ_VSTMP_RING_SIZE 0x8c64 347254885Sdumbbell#define SQ_PSTMP_RING_BASE 0x8c68 348254885Sdumbbell#define SQ_PSTMP_RING_SIZE 0x8c6c 349254885Sdumbbell#define SQ_MS_FIFO_SIZES 0x8CF0 350254885Sdumbbell#define CACHE_FIFO_SIZE(x) ((x) << 0) 351254885Sdumbbell#define FETCH_FIFO_HIWATER(x) ((x) << 8) 352254885Sdumbbell#define DONE_FIFO_HIWATER(x) ((x) << 16) 353254885Sdumbbell#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 354254885Sdumbbell#define SQ_LSTMP_RING_BASE 0x8e10 355254885Sdumbbell#define SQ_LSTMP_RING_SIZE 0x8e14 356254885Sdumbbell#define SQ_HSTMP_RING_BASE 0x8e18 357254885Sdumbbell#define SQ_HSTMP_RING_SIZE 0x8e1c 358254885Sdumbbell#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 359254885Sdumbbell#define DYN_GPR_ENABLE (1 << 8) 360254885Sdumbbell#define SQ_CONST_MEM_BASE 0x8df8 361254885Sdumbbell 362254885Sdumbbell#define SX_EXPORT_BUFFER_SIZES 0x900C 363254885Sdumbbell#define COLOR_BUFFER_SIZE(x) ((x) << 0) 364254885Sdumbbell#define POSITION_BUFFER_SIZE(x) ((x) << 8) 365254885Sdumbbell#define SMX_BUFFER_SIZE(x) ((x) << 16) 366254885Sdumbbell#define SX_DEBUG_1 0x9058 367254885Sdumbbell#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 368254885Sdumbbell 369254885Sdumbbell#define SPI_CONFIG_CNTL 0x9100 370254885Sdumbbell#define GPR_WRITE_PRIORITY(x) ((x) << 0) 371254885Sdumbbell#define SPI_CONFIG_CNTL_1 0x913C 372254885Sdumbbell#define VTX_DONE_DELAY(x) ((x) << 0) 373254885Sdumbbell#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 374254885Sdumbbell#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 375254885Sdumbbell 376254885Sdumbbell#define CGTS_TCC_DISABLE 0x9148 377254885Sdumbbell#define CGTS_USER_TCC_DISABLE 0x914C 378254885Sdumbbell#define TCC_DISABLE_MASK 0xFFFF0000 379254885Sdumbbell#define TCC_DISABLE_SHIFT 16 380254885Sdumbbell#define CGTS_SM_CTRL_REG 0x9150 381254885Sdumbbell#define OVERRIDE (1 << 21) 382254885Sdumbbell 383254885Sdumbbell#define TA_CNTL_AUX 0x9508 384254885Sdumbbell#define DISABLE_CUBE_WRAP (1 << 0) 385254885Sdumbbell#define DISABLE_CUBE_ANISO (1 << 1) 386254885Sdumbbell 387254885Sdumbbell#define TCP_CHAN_STEER_LO 0x960c 388254885Sdumbbell#define TCP_CHAN_STEER_HI 0x9610 389254885Sdumbbell 390254885Sdumbbell#define CC_RB_BACKEND_DISABLE 0x98F4 391254885Sdumbbell#define BACKEND_DISABLE(x) ((x) << 16) 392254885Sdumbbell#define GB_ADDR_CONFIG 0x98F8 393254885Sdumbbell#define NUM_PIPES(x) ((x) << 0) 394254885Sdumbbell#define NUM_PIPES_MASK 0x00000007 395254885Sdumbbell#define NUM_PIPES_SHIFT 0 396254885Sdumbbell#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 397254885Sdumbbell#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 398254885Sdumbbell#define PIPE_INTERLEAVE_SIZE_SHIFT 4 399254885Sdumbbell#define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 400254885Sdumbbell#define NUM_SHADER_ENGINES(x) ((x) << 12) 401254885Sdumbbell#define NUM_SHADER_ENGINES_MASK 0x00003000 402254885Sdumbbell#define NUM_SHADER_ENGINES_SHIFT 12 403254885Sdumbbell#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 404254885Sdumbbell#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 405254885Sdumbbell#define SHADER_ENGINE_TILE_SIZE_SHIFT 16 406254885Sdumbbell#define NUM_GPUS(x) ((x) << 20) 407254885Sdumbbell#define NUM_GPUS_MASK 0x00700000 408254885Sdumbbell#define NUM_GPUS_SHIFT 20 409254885Sdumbbell#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 410254885Sdumbbell#define MULTI_GPU_TILE_SIZE_MASK 0x03000000 411254885Sdumbbell#define MULTI_GPU_TILE_SIZE_SHIFT 24 412254885Sdumbbell#define ROW_SIZE(x) ((x) << 28) 413254885Sdumbbell#define ROW_SIZE_MASK 0x30000000 414254885Sdumbbell#define ROW_SIZE_SHIFT 28 415254885Sdumbbell#define NUM_LOWER_PIPES(x) ((x) << 30) 416254885Sdumbbell#define NUM_LOWER_PIPES_MASK 0x40000000 417254885Sdumbbell#define NUM_LOWER_PIPES_SHIFT 30 418254885Sdumbbell#define GB_BACKEND_MAP 0x98FC 419254885Sdumbbell 420254885Sdumbbell#define CB_PERF_CTR0_SEL_0 0x9A20 421254885Sdumbbell#define CB_PERF_CTR0_SEL_1 0x9A24 422254885Sdumbbell#define CB_PERF_CTR1_SEL_0 0x9A28 423254885Sdumbbell#define CB_PERF_CTR1_SEL_1 0x9A2C 424254885Sdumbbell#define CB_PERF_CTR2_SEL_0 0x9A30 425254885Sdumbbell#define CB_PERF_CTR2_SEL_1 0x9A34 426254885Sdumbbell#define CB_PERF_CTR3_SEL_0 0x9A38 427254885Sdumbbell#define CB_PERF_CTR3_SEL_1 0x9A3C 428254885Sdumbbell 429254885Sdumbbell#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 430254885Sdumbbell#define BACKEND_DISABLE_MASK 0x00FF0000 431254885Sdumbbell#define BACKEND_DISABLE_SHIFT 16 432254885Sdumbbell 433254885Sdumbbell#define SMX_DC_CTL0 0xA020 434254885Sdumbbell#define USE_HASH_FUNCTION (1 << 0) 435254885Sdumbbell#define NUMBER_OF_SETS(x) ((x) << 1) 436254885Sdumbbell#define FLUSH_ALL_ON_EVENT (1 << 10) 437254885Sdumbbell#define STALL_ON_EVENT (1 << 11) 438254885Sdumbbell#define SMX_EVENT_CTL 0xA02C 439254885Sdumbbell#define ES_FLUSH_CTL(x) ((x) << 0) 440254885Sdumbbell#define GS_FLUSH_CTL(x) ((x) << 3) 441254885Sdumbbell#define ACK_FLUSH_CTL(x) ((x) << 6) 442254885Sdumbbell#define SYNC_FLUSH_CTL (1 << 8) 443254885Sdumbbell 444254885Sdumbbell#define CP_RB0_BASE 0xC100 445254885Sdumbbell#define CP_RB0_CNTL 0xC104 446254885Sdumbbell#define RB_BUFSZ(x) ((x) << 0) 447254885Sdumbbell#define RB_BLKSZ(x) ((x) << 8) 448254885Sdumbbell#define RB_NO_UPDATE (1 << 27) 449261455Seadler#define RB_RPTR_WR_ENA (1U << 31) 450254885Sdumbbell#define BUF_SWAP_32BIT (2 << 16) 451254885Sdumbbell#define CP_RB0_RPTR_ADDR 0xC10C 452254885Sdumbbell#define CP_RB0_RPTR_ADDR_HI 0xC110 453254885Sdumbbell#define CP_RB0_WPTR 0xC114 454254885Sdumbbell 455254885Sdumbbell#define CP_INT_CNTL 0xC124 456254885Sdumbbell# define CNTX_BUSY_INT_ENABLE (1 << 19) 457254885Sdumbbell# define CNTX_EMPTY_INT_ENABLE (1 << 20) 458254885Sdumbbell# define TIME_STAMP_INT_ENABLE (1 << 26) 459254885Sdumbbell 460254885Sdumbbell#define CP_RB1_BASE 0xC180 461254885Sdumbbell#define CP_RB1_CNTL 0xC184 462254885Sdumbbell#define CP_RB1_RPTR_ADDR 0xC188 463254885Sdumbbell#define CP_RB1_RPTR_ADDR_HI 0xC18C 464254885Sdumbbell#define CP_RB1_WPTR 0xC190 465254885Sdumbbell#define CP_RB2_BASE 0xC194 466254885Sdumbbell#define CP_RB2_CNTL 0xC198 467254885Sdumbbell#define CP_RB2_RPTR_ADDR 0xC19C 468254885Sdumbbell#define CP_RB2_RPTR_ADDR_HI 0xC1A0 469254885Sdumbbell#define CP_RB2_WPTR 0xC1A4 470254885Sdumbbell#define CP_PFP_UCODE_ADDR 0xC150 471254885Sdumbbell#define CP_PFP_UCODE_DATA 0xC154 472254885Sdumbbell#define CP_ME_RAM_RADDR 0xC158 473254885Sdumbbell#define CP_ME_RAM_WADDR 0xC15C 474254885Sdumbbell#define CP_ME_RAM_DATA 0xC160 475254885Sdumbbell#define CP_DEBUG 0xC1FC 476254885Sdumbbell 477254885Sdumbbell#define VGT_EVENT_INITIATOR 0x28a90 478254885Sdumbbell# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 479254885Sdumbbell# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 480254885Sdumbbell 481254885Sdumbbell/* 482254885Sdumbbell * PM4 483254885Sdumbbell */ 484254885Sdumbbell#define PACKET_TYPE0 0 485254885Sdumbbell#define PACKET_TYPE1 1 486254885Sdumbbell#define PACKET_TYPE2 2 487254885Sdumbbell#define PACKET_TYPE3 3 488254885Sdumbbell 489254885Sdumbbell#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 490254885Sdumbbell#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 491254885Sdumbbell#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 492254885Sdumbbell#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 493254885Sdumbbell#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 494254885Sdumbbell (((reg) >> 2) & 0xFFFF) | \ 495254885Sdumbbell ((n) & 0x3FFF) << 16) 496254885Sdumbbell#define CP_PACKET2 0x80000000 497254885Sdumbbell#define PACKET2_PAD_SHIFT 0 498254885Sdumbbell#define PACKET2_PAD_MASK (0x3fffffff << 0) 499254885Sdumbbell 500254885Sdumbbell#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 501254885Sdumbbell 502254885Sdumbbell#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 503254885Sdumbbell (((op) & 0xFF) << 8) | \ 504254885Sdumbbell ((n) & 0x3FFF) << 16) 505254885Sdumbbell 506254885Sdumbbell/* Packet 3 types */ 507254885Sdumbbell#define PACKET3_NOP 0x10 508254885Sdumbbell#define PACKET3_SET_BASE 0x11 509254885Sdumbbell#define PACKET3_CLEAR_STATE 0x12 510254885Sdumbbell#define PACKET3_INDEX_BUFFER_SIZE 0x13 511254885Sdumbbell#define PACKET3_DEALLOC_STATE 0x14 512254885Sdumbbell#define PACKET3_DISPATCH_DIRECT 0x15 513254885Sdumbbell#define PACKET3_DISPATCH_INDIRECT 0x16 514254885Sdumbbell#define PACKET3_INDIRECT_BUFFER_END 0x17 515254885Sdumbbell#define PACKET3_MODE_CONTROL 0x18 516254885Sdumbbell#define PACKET3_SET_PREDICATION 0x20 517254885Sdumbbell#define PACKET3_REG_RMW 0x21 518254885Sdumbbell#define PACKET3_COND_EXEC 0x22 519254885Sdumbbell#define PACKET3_PRED_EXEC 0x23 520254885Sdumbbell#define PACKET3_DRAW_INDIRECT 0x24 521254885Sdumbbell#define PACKET3_DRAW_INDEX_INDIRECT 0x25 522254885Sdumbbell#define PACKET3_INDEX_BASE 0x26 523254885Sdumbbell#define PACKET3_DRAW_INDEX_2 0x27 524254885Sdumbbell#define PACKET3_CONTEXT_CONTROL 0x28 525254885Sdumbbell#define PACKET3_DRAW_INDEX_OFFSET 0x29 526254885Sdumbbell#define PACKET3_INDEX_TYPE 0x2A 527254885Sdumbbell#define PACKET3_DRAW_INDEX 0x2B 528254885Sdumbbell#define PACKET3_DRAW_INDEX_AUTO 0x2D 529254885Sdumbbell#define PACKET3_DRAW_INDEX_IMMD 0x2E 530254885Sdumbbell#define PACKET3_NUM_INSTANCES 0x2F 531254885Sdumbbell#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 532254885Sdumbbell#define PACKET3_INDIRECT_BUFFER 0x32 533254885Sdumbbell#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 534254885Sdumbbell#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 535254885Sdumbbell#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 536254885Sdumbbell#define PACKET3_WRITE_DATA 0x37 537254885Sdumbbell#define PACKET3_MEM_SEMAPHORE 0x39 538254885Sdumbbell#define PACKET3_MPEG_INDEX 0x3A 539254885Sdumbbell#define PACKET3_WAIT_REG_MEM 0x3C 540254885Sdumbbell#define PACKET3_MEM_WRITE 0x3D 541254885Sdumbbell#define PACKET3_PFP_SYNC_ME 0x42 542254885Sdumbbell#define PACKET3_SURFACE_SYNC 0x43 543254885Sdumbbell# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 544254885Sdumbbell# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 545254885Sdumbbell# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 546254885Sdumbbell# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 547254885Sdumbbell# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 548254885Sdumbbell# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 549254885Sdumbbell# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 550254885Sdumbbell# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 551254885Sdumbbell# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 552254885Sdumbbell# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 553254885Sdumbbell# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 554254885Sdumbbell# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 555254885Sdumbbell# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 556254885Sdumbbell# define PACKET3_FULL_CACHE_ENA (1 << 20) 557254885Sdumbbell# define PACKET3_TC_ACTION_ENA (1 << 23) 558254885Sdumbbell# define PACKET3_CB_ACTION_ENA (1 << 25) 559254885Sdumbbell# define PACKET3_DB_ACTION_ENA (1 << 26) 560254885Sdumbbell# define PACKET3_SH_ACTION_ENA (1 << 27) 561254885Sdumbbell# define PACKET3_SX_ACTION_ENA (1 << 28) 562254885Sdumbbell#define PACKET3_ME_INITIALIZE 0x44 563254885Sdumbbell#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 564254885Sdumbbell#define PACKET3_COND_WRITE 0x45 565254885Sdumbbell#define PACKET3_EVENT_WRITE 0x46 566254885Sdumbbell#define EVENT_TYPE(x) ((x) << 0) 567254885Sdumbbell#define EVENT_INDEX(x) ((x) << 8) 568254885Sdumbbell /* 0 - any non-TS event 569254885Sdumbbell * 1 - ZPASS_DONE 570254885Sdumbbell * 2 - SAMPLE_PIPELINESTAT 571254885Sdumbbell * 3 - SAMPLE_STREAMOUTSTAT* 572254885Sdumbbell * 4 - *S_PARTIAL_FLUSH 573254885Sdumbbell * 5 - TS events 574254885Sdumbbell */ 575254885Sdumbbell#define PACKET3_EVENT_WRITE_EOP 0x47 576254885Sdumbbell#define DATA_SEL(x) ((x) << 29) 577254885Sdumbbell /* 0 - discard 578254885Sdumbbell * 1 - send low 32bit data 579254885Sdumbbell * 2 - send 64bit data 580254885Sdumbbell * 3 - send 64bit counter value 581254885Sdumbbell */ 582254885Sdumbbell#define INT_SEL(x) ((x) << 24) 583254885Sdumbbell /* 0 - none 584254885Sdumbbell * 1 - interrupt only (DATA_SEL = 0) 585254885Sdumbbell * 2 - interrupt when data write is confirmed 586254885Sdumbbell */ 587254885Sdumbbell#define PACKET3_EVENT_WRITE_EOS 0x48 588254885Sdumbbell#define PACKET3_PREAMBLE_CNTL 0x4A 589254885Sdumbbell# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 590254885Sdumbbell# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 591254885Sdumbbell#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 592254885Sdumbbell#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 593254885Sdumbbell#define PACKET3_ALU_PS_CONST_UPDATE 0x4E 594254885Sdumbbell#define PACKET3_ALU_VS_CONST_UPDATE 0x4F 595254885Sdumbbell#define PACKET3_ONE_REG_WRITE 0x57 596254885Sdumbbell#define PACKET3_SET_CONFIG_REG 0x68 597254885Sdumbbell#define PACKET3_SET_CONFIG_REG_START 0x00008000 598254885Sdumbbell#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 599254885Sdumbbell#define PACKET3_SET_CONTEXT_REG 0x69 600254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_START 0x00028000 601254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_END 0x00029000 602254885Sdumbbell#define PACKET3_SET_ALU_CONST 0x6A 603254885Sdumbbell/* alu const buffers only; no reg file */ 604254885Sdumbbell#define PACKET3_SET_BOOL_CONST 0x6B 605254885Sdumbbell#define PACKET3_SET_BOOL_CONST_START 0x0003a500 606254885Sdumbbell#define PACKET3_SET_BOOL_CONST_END 0x0003a518 607254885Sdumbbell#define PACKET3_SET_LOOP_CONST 0x6C 608254885Sdumbbell#define PACKET3_SET_LOOP_CONST_START 0x0003a200 609254885Sdumbbell#define PACKET3_SET_LOOP_CONST_END 0x0003a500 610254885Sdumbbell#define PACKET3_SET_RESOURCE 0x6D 611254885Sdumbbell#define PACKET3_SET_RESOURCE_START 0x00030000 612254885Sdumbbell#define PACKET3_SET_RESOURCE_END 0x00038000 613254885Sdumbbell#define PACKET3_SET_SAMPLER 0x6E 614254885Sdumbbell#define PACKET3_SET_SAMPLER_START 0x0003c000 615254885Sdumbbell#define PACKET3_SET_SAMPLER_END 0x0003c600 616254885Sdumbbell#define PACKET3_SET_CTL_CONST 0x6F 617254885Sdumbbell#define PACKET3_SET_CTL_CONST_START 0x0003cff0 618254885Sdumbbell#define PACKET3_SET_CTL_CONST_END 0x0003ff0c 619254885Sdumbbell#define PACKET3_SET_RESOURCE_OFFSET 0x70 620254885Sdumbbell#define PACKET3_SET_ALU_CONST_VS 0x71 621254885Sdumbbell#define PACKET3_SET_ALU_CONST_DI 0x72 622254885Sdumbbell#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 623254885Sdumbbell#define PACKET3_SET_RESOURCE_INDIRECT 0x74 624254885Sdumbbell#define PACKET3_SET_APPEND_CNT 0x75 625254885Sdumbbell#define PACKET3_ME_WRITE 0x7A 626254885Sdumbbell 627254885Sdumbbell/* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 628254885Sdumbbell#define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 629254885Sdumbbell#define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 630254885Sdumbbell 631254885Sdumbbell#define DMA_RB_CNTL 0xd000 632254885Sdumbbell# define DMA_RB_ENABLE (1 << 0) 633254885Sdumbbell# define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 634254885Sdumbbell# define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 635254885Sdumbbell# define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 636254885Sdumbbell# define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 637254885Sdumbbell# define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 638254885Sdumbbell#define DMA_RB_BASE 0xd004 639254885Sdumbbell#define DMA_RB_RPTR 0xd008 640254885Sdumbbell#define DMA_RB_WPTR 0xd00c 641254885Sdumbbell 642254885Sdumbbell#define DMA_RB_RPTR_ADDR_HI 0xd01c 643254885Sdumbbell#define DMA_RB_RPTR_ADDR_LO 0xd020 644254885Sdumbbell 645254885Sdumbbell#define DMA_IB_CNTL 0xd024 646254885Sdumbbell# define DMA_IB_ENABLE (1 << 0) 647254885Sdumbbell# define DMA_IB_SWAP_ENABLE (1 << 4) 648261455Seadler# define CMD_VMID_FORCE (1U << 31) 649254885Sdumbbell#define DMA_IB_RPTR 0xd028 650254885Sdumbbell#define DMA_CNTL 0xd02c 651254885Sdumbbell# define TRAP_ENABLE (1 << 0) 652254885Sdumbbell# define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 653254885Sdumbbell# define SEM_WAIT_INT_ENABLE (1 << 2) 654254885Sdumbbell# define DATA_SWAP_ENABLE (1 << 3) 655254885Sdumbbell# define FENCE_SWAP_ENABLE (1 << 4) 656254885Sdumbbell# define CTXEMPTY_INT_ENABLE (1 << 28) 657254885Sdumbbell#define DMA_STATUS_REG 0xd034 658254885Sdumbbell# define DMA_IDLE (1 << 0) 659254885Sdumbbell#define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 660254885Sdumbbell#define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 661254885Sdumbbell#define DMA_TILING_CONFIG 0xd0b8 662254885Sdumbbell#define DMA_MODE 0xd0bc 663254885Sdumbbell 664254885Sdumbbell#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 665254885Sdumbbell (((t) & 0x1) << 23) | \ 666254885Sdumbbell (((s) & 0x1) << 22) | \ 667254885Sdumbbell (((n) & 0xFFFFF) << 0)) 668254885Sdumbbell 669254885Sdumbbell#define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 670254885Sdumbbell (((vmid) & 0xF) << 20) | \ 671254885Sdumbbell (((n) & 0xFFFFF) << 0)) 672254885Sdumbbell 673254885Sdumbbell/* async DMA Packet types */ 674254885Sdumbbell#define DMA_PACKET_WRITE 0x2 675254885Sdumbbell#define DMA_PACKET_COPY 0x3 676254885Sdumbbell#define DMA_PACKET_INDIRECT_BUFFER 0x4 677254885Sdumbbell#define DMA_PACKET_SEMAPHORE 0x5 678254885Sdumbbell#define DMA_PACKET_FENCE 0x6 679254885Sdumbbell#define DMA_PACKET_TRAP 0x7 680254885Sdumbbell#define DMA_PACKET_SRBM_WRITE 0x9 681254885Sdumbbell#define DMA_PACKET_CONSTANT_FILL 0xd 682254885Sdumbbell#define DMA_PACKET_NOP 0xf 683254885Sdumbbell 684254885Sdumbbell#endif 685