radeon_irq.c revision 189130 
1/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
2/*-
3 * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 *    Keith Whitwell <keith@tungstengraphics.com>
30 *    Michel D���zer <michel@daenzer.net>
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_irq.c 189130 2009-02-28 02:37:55Z rnoland $");
35
36#include "dev/drm/drmP.h"
37#include "dev/drm/drm.h"
38#include "dev/drm/radeon_drm.h"
39#include "dev/drm/radeon_drv.h"
40
41void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
42{
43	drm_radeon_private_t *dev_priv = dev->dev_private;
44
45	if (state)
46		dev_priv->irq_enable_reg |= mask;
47	else
48		dev_priv->irq_enable_reg &= ~mask;
49
50	if (dev->irq_enabled)
51		RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
52}
53
54static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
55{
56	drm_radeon_private_t *dev_priv = dev->dev_private;
57
58	if (state)
59		dev_priv->r500_disp_irq_reg |= mask;
60	else
61		dev_priv->r500_disp_irq_reg &= ~mask;
62
63	if (dev->irq_enabled)
64		RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
65}
66
67int radeon_enable_vblank(struct drm_device *dev, int crtc)
68{
69	drm_radeon_private_t *dev_priv = dev->dev_private;
70
71	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
72		switch (crtc) {
73		case 0:
74			r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
75			break;
76		case 1:
77			r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
78			break;
79		default:
80			DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
81				  crtc);
82			return EINVAL;
83		}
84	} else {
85		switch (crtc) {
86		case 0:
87			radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
88			break;
89		case 1:
90			radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
91			break;
92		default:
93			DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
94				  crtc);
95			return EINVAL;
96		}
97	}
98
99	return 0;
100}
101
102void radeon_disable_vblank(struct drm_device *dev, int crtc)
103{
104	drm_radeon_private_t *dev_priv = dev->dev_private;
105
106	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
107		switch (crtc) {
108		case 0:
109			r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
110			break;
111		case 1:
112			r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
113			break;
114		default:
115			DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
116				  crtc);
117			break;
118		}
119	} else {
120		switch (crtc) {
121		case 0:
122			radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
123			break;
124		case 1:
125			radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
126			break;
127		default:
128			DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
129				  crtc);
130			break;
131		}
132	}
133}
134
135static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
136{
137	u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
138	u32 irq_mask = RADEON_SW_INT_TEST;
139
140	*r500_disp_int = 0;
141	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
142		/* vbl interrupts in a different place */
143
144		if (irqs & R500_DISPLAY_INT_STATUS) {
145			/* if a display interrupt */
146			u32 disp_irq;
147
148			disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
149
150			*r500_disp_int = disp_irq;
151			if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
152				RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
153			}
154			if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
155				RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
156			}
157		}
158		irq_mask |= R500_DISPLAY_INT_STATUS;
159	} else
160		irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
161
162	irqs &=	irq_mask;
163
164	if (irqs)
165		RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
166
167	return irqs;
168}
169
170/* Interrupts - Used for device synchronization and flushing in the
171 * following circumstances:
172 *
173 * - Exclusive FB access with hw idle:
174 *    - Wait for GUI Idle (?) interrupt, then do normal flush.
175 *
176 * - Frame throttling, NV_fence:
177 *    - Drop marker irq's into command stream ahead of time.
178 *    - Wait on irq's with lock *not held*
179 *    - Check each for termination condition
180 *
181 * - Internally in cp_getbuffer, etc:
182 *    - as above, but wait with lock held???
183 *
184 * NOTE: These functions are misleadingly named -- the irq's aren't
185 * tied to dma at all, this is just a hangover from dri prehistory.
186 */
187
188irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
189{
190	struct drm_device *dev = (struct drm_device *) arg;
191	drm_radeon_private_t *dev_priv =
192	    (drm_radeon_private_t *) dev->dev_private;
193	u32 stat;
194	u32 r500_disp_int;
195	u32 tmp;
196
197	/* Only consider the bits we're interested in - others could be used
198	 * outside the DRM
199	 */
200	stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
201	if (!stat)
202		return IRQ_NONE;
203
204	stat &= dev_priv->irq_enable_reg;
205
206	/* SW interrupt */
207	if (stat & RADEON_SW_INT_TEST)
208		DRM_WAKEUP(&dev_priv->swi_queue);
209
210	/* VBLANK interrupt */
211	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
212		if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
213			drm_handle_vblank(dev, 0);
214		if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
215			drm_handle_vblank(dev, 1);
216	} else {
217		if (stat & RADEON_CRTC_VBLANK_STAT)
218			drm_handle_vblank(dev, 0);
219		if (stat & RADEON_CRTC2_VBLANK_STAT)
220			drm_handle_vblank(dev, 1);
221	}
222	if (dev->msi_enabled) {
223		switch(dev_priv->flags & RADEON_FAMILY_MASK) {
224			case CHIP_RS400:
225			case CHIP_RS480:
226				tmp = RADEON_READ(RADEON_AIC_CNTL) &
227				    ~RS400_MSI_REARM;
228				RADEON_WRITE(RADEON_AIC_CNTL, tmp);
229				RADEON_WRITE(RADEON_AIC_CNTL,
230				    tmp | RS400_MSI_REARM);
231				break;
232			case CHIP_RS690:
233			case CHIP_RS740:
234				tmp = RADEON_READ(RADEON_BUS_CNTL) &
235				    ~RS600_MSI_REARM;
236				RADEON_WRITE(RADEON_BUS_CNTL, tmp);
237				RADEON_WRITE(RADEON_BUS_CNTL, tmp |
238				    RS600_MSI_REARM);
239				break;
240			 default:
241				tmp = RADEON_READ(RADEON_MSI_REARM_EN) &
242				    ~RV370_MSI_REARM_EN;
243				RADEON_WRITE(RADEON_MSI_REARM_EN, tmp);
244				RADEON_WRITE(RADEON_MSI_REARM_EN,
245				    tmp | RV370_MSI_REARM_EN);
246				break;
247		}
248	}
249	return IRQ_HANDLED;
250}
251
252static int radeon_emit_irq(struct drm_device * dev)
253{
254	drm_radeon_private_t *dev_priv = dev->dev_private;
255	unsigned int ret;
256	RING_LOCALS;
257
258	atomic_inc(&dev_priv->swi_emitted);
259	ret = atomic_read(&dev_priv->swi_emitted);
260
261	BEGIN_RING(4);
262	OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
263	OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
264	ADVANCE_RING();
265	COMMIT_RING();
266
267	return ret;
268}
269
270static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
271{
272	drm_radeon_private_t *dev_priv =
273	    (drm_radeon_private_t *) dev->dev_private;
274	int ret = 0;
275
276	if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
277		return 0;
278
279	dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
280
281	DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
282		    RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
283
284	return ret;
285}
286
287u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
288{
289	drm_radeon_private_t *dev_priv = dev->dev_private;
290
291	if (!dev_priv) {
292		DRM_ERROR("called with no initialization\n");
293		return -EINVAL;
294	}
295
296	if (crtc < 0 || crtc > 1) {
297		DRM_ERROR("Invalid crtc %d\n", crtc);
298		return -EINVAL;
299	}
300
301	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
302		if (crtc == 0)
303			return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
304		else
305			return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
306	} else {
307		if (crtc == 0)
308			return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
309		else
310			return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
311	}
312}
313
314/* Needs the lock as it touches the ring.
315 */
316int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
317{
318	drm_radeon_private_t *dev_priv = dev->dev_private;
319	drm_radeon_irq_emit_t *emit = data;
320	int result;
321
322	LOCK_TEST_WITH_RETURN(dev, file_priv);
323
324	if (!dev_priv) {
325		DRM_ERROR("called with no initialization\n");
326		return -EINVAL;
327	}
328
329	result = radeon_emit_irq(dev);
330
331	if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
332		DRM_ERROR("copy_to_user\n");
333		return -EFAULT;
334	}
335
336	return 0;
337}
338
339/* Doesn't need the hardware lock.
340 */
341int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
342{
343	drm_radeon_private_t *dev_priv = dev->dev_private;
344	drm_radeon_irq_wait_t *irqwait = data;
345
346	if (!dev_priv) {
347		DRM_ERROR("called with no initialization\n");
348		return -EINVAL;
349	}
350
351	return radeon_wait_irq(dev, irqwait->irq_seq);
352}
353
354/* drm_dma.h hooks
355*/
356void radeon_driver_irq_preinstall(struct drm_device * dev)
357{
358	drm_radeon_private_t *dev_priv =
359	    (drm_radeon_private_t *) dev->dev_private;
360	u32 dummy;
361
362	/* Disable *all* interrupts */
363	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
364		RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
365	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
366
367	/* Clear bits if they're already high */
368	radeon_acknowledge_irqs(dev_priv, &dummy);
369}
370
371int radeon_driver_irq_postinstall(struct drm_device * dev)
372{
373	drm_radeon_private_t *dev_priv =
374	    (drm_radeon_private_t *) dev->dev_private;
375
376	atomic_set(&dev_priv->swi_emitted, 0);
377	DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
378
379	dev->max_vblank_count = 0x001fffff;
380
381	radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
382
383	return 0;
384}
385
386void radeon_driver_irq_uninstall(struct drm_device * dev)
387{
388	drm_radeon_private_t *dev_priv =
389	    (drm_radeon_private_t *) dev->dev_private;
390	if (!dev_priv)
391		return;
392
393	dev_priv->irq_enabled = 0;
394
395	if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
396		RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
397	/* Disable *all* interrupts */
398	RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
399}
400
401
402int radeon_vblank_crtc_get(struct drm_device *dev)
403{
404	drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
405
406	return dev_priv->vblank_crtc;
407}
408
409int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
410{
411	drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
412	if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
413		DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
414		return -EINVAL;
415	}
416	dev_priv->vblank_crtc = (unsigned int)value;
417	return 0;
418}
419