i915_drv.h revision 189130
1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/drm/i915_drv.h 189130 2009-02-28 02:37:55Z rnoland $"); 32 33#ifndef _I915_DRV_H_ 34#define _I915_DRV_H_ 35 36#include "dev/drm/i915_reg.h" 37 38/* General customization: 39 */ 40 41#define DRIVER_AUTHOR "Tungsten Graphics, Inc." 42 43#define DRIVER_NAME "i915" 44#define DRIVER_DESC "Intel Graphics" 45#define DRIVER_DATE "20080730" 46 47enum pipe { 48 PIPE_A = 0, 49 PIPE_B, 50}; 51 52#define I915_NUM_PIPE 2 53 54/* Interface history: 55 * 56 * 1.1: Original. 57 * 1.2: Add Power Management 58 * 1.3: Add vblank support 59 * 1.4: Fix cmdbuffer path, add heap destroy 60 * 1.5: Add vblank pipe configuration 61 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 62 * - Support vertical blank on secondary display pipe 63 */ 64#define DRIVER_MAJOR 1 65#define DRIVER_MINOR 6 66#define DRIVER_PATCHLEVEL 0 67 68#define WATCH_COHERENCY 0 69#define WATCH_BUF 0 70#define WATCH_EXEC 0 71#define WATCH_LRU 0 72#define WATCH_RELOC 0 73#define WATCH_INACTIVE 0 74#define WATCH_PWRITE 0 75 76typedef struct _drm_i915_ring_buffer { 77 int tail_mask; 78 unsigned long Size; 79 u8 *virtual_start; 80 int head; 81 int tail; 82 int space; 83 drm_local_map_t map; 84 struct drm_gem_object *ring_obj; 85} drm_i915_ring_buffer_t; 86 87struct mem_block { 88 struct mem_block *next; 89 struct mem_block *prev; 90 int start; 91 int size; 92 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 93}; 94 95struct opregion_header; 96struct opregion_acpi; 97struct opregion_swsci; 98struct opregion_asle; 99 100struct intel_opregion { 101 struct opregion_header *header; 102 struct opregion_acpi *acpi; 103 struct opregion_swsci *swsci; 104 struct opregion_asle *asle; 105 int enabled; 106}; 107 108typedef struct drm_i915_private { 109 struct drm_device *dev; 110 111 drm_local_map_t *sarea; 112 drm_local_map_t *mmio_map; 113 114 drm_i915_sarea_t *sarea_priv; 115 drm_i915_ring_buffer_t ring; 116 117 drm_dma_handle_t *status_page_dmah; 118 void *hw_status_page; 119 dma_addr_t dma_status_page; 120 uint32_t counter; 121 unsigned int status_gfx_addr; 122 drm_local_map_t hws_map; 123 struct drm_gem_object *hws_obj; 124 125 unsigned int cpp; 126 int back_offset; 127 int front_offset; 128 int current_page; 129 int page_flipping; 130 131 wait_queue_head_t irq_queue; 132 atomic_t irq_received; 133 /** Protects user_irq_refcount and irq_mask_reg */ 134 DRM_SPINTYPE user_irq_lock; 135 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ 136 int user_irq_refcount; 137 /** Cached value of IER to avoid reads in updating the bitfield */ 138 u32 irq_mask_reg; 139 u32 pipestat[2]; 140 141 int tex_lru_log_granularity; 142 int allow_batchbuffer; 143 struct mem_block *agp_heap; 144 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 145 int vblank_pipe; 146 147 struct intel_opregion opregion; 148 149 /* Register state */ 150 u8 saveLBB; 151 u32 saveDSPACNTR; 152 u32 saveDSPBCNTR; 153 u32 saveDSPARB; 154 u32 savePIPEACONF; 155 u32 savePIPEBCONF; 156 u32 savePIPEASRC; 157 u32 savePIPEBSRC; 158 u32 saveFPA0; 159 u32 saveFPA1; 160 u32 saveDPLL_A; 161 u32 saveDPLL_A_MD; 162 u32 saveHTOTAL_A; 163 u32 saveHBLANK_A; 164 u32 saveHSYNC_A; 165 u32 saveVTOTAL_A; 166 u32 saveVBLANK_A; 167 u32 saveVSYNC_A; 168 u32 saveBCLRPAT_A; 169 u32 savePIPEASTAT; 170 u32 saveDSPASTRIDE; 171 u32 saveDSPASIZE; 172 u32 saveDSPAPOS; 173 u32 saveDSPAADDR; 174 u32 saveDSPASURF; 175 u32 saveDSPATILEOFF; 176 u32 savePFIT_PGM_RATIOS; 177 u32 saveBLC_PWM_CTL; 178 u32 saveBLC_PWM_CTL2; 179 u32 saveFPB0; 180 u32 saveFPB1; 181 u32 saveDPLL_B; 182 u32 saveDPLL_B_MD; 183 u32 saveHTOTAL_B; 184 u32 saveHBLANK_B; 185 u32 saveHSYNC_B; 186 u32 saveVTOTAL_B; 187 u32 saveVBLANK_B; 188 u32 saveVSYNC_B; 189 u32 saveBCLRPAT_B; 190 u32 savePIPEBSTAT; 191 u32 saveDSPBSTRIDE; 192 u32 saveDSPBSIZE; 193 u32 saveDSPBPOS; 194 u32 saveDSPBADDR; 195 u32 saveDSPBSURF; 196 u32 saveDSPBTILEOFF; 197 u32 saveVGA0; 198 u32 saveVGA1; 199 u32 saveVGA_PD; 200 u32 saveVGACNTRL; 201 u32 saveADPA; 202 u32 saveLVDS; 203 u32 savePP_ON_DELAYS; 204 u32 savePP_OFF_DELAYS; 205 u32 saveDVOA; 206 u32 saveDVOB; 207 u32 saveDVOC; 208 u32 savePP_ON; 209 u32 savePP_OFF; 210 u32 savePP_CONTROL; 211 u32 savePP_DIVISOR; 212 u32 savePFIT_CONTROL; 213 u32 save_palette_a[256]; 214 u32 save_palette_b[256]; 215 u32 saveFBC_CFB_BASE; 216 u32 saveFBC_LL_BASE; 217 u32 saveFBC_CONTROL; 218 u32 saveFBC_CONTROL2; 219 u32 saveIER; 220 u32 saveIIR; 221 u32 saveIMR; 222 u32 saveCACHE_MODE_0; 223 u32 saveD_STATE; 224 u32 saveCG_2D_DIS; 225 u32 saveMI_ARB_STATE; 226 u32 saveSWF0[16]; 227 u32 saveSWF1[16]; 228 u32 saveSWF2[3]; 229 u8 saveMSR; 230 u8 saveSR[8]; 231 u8 saveGR[25]; 232 u8 saveAR_INDEX; 233 u8 saveAR[21]; 234 u8 saveDACMASK; 235 u8 saveDACDATA[256*3]; /* 256 3-byte colors */ 236 u8 saveCR[37]; 237 struct { 238#ifdef __linux__ 239 struct drm_mm gtt_space; 240#endif 241 /** 242 * List of objects currently involved in rendering from the 243 * ringbuffer. 244 * 245 * A reference is held on the buffer while on this list. 246 */ 247 struct list_head active_list; 248 249 /** 250 * List of objects which are not in the ringbuffer but which 251 * still have a write_domain which needs to be flushed before 252 * unbinding. 253 * 254 * A reference is held on the buffer while on this list. 255 */ 256 struct list_head flushing_list; 257 258 /** 259 * LRU list of objects which are not in the ringbuffer and 260 * are ready to unbind, but are still in the GTT. 261 * 262 * A reference is not held on the buffer while on this list, 263 * as merely being GTT-bound shouldn't prevent its being 264 * freed, and we'll pull it off the list in the free path. 265 */ 266 struct list_head inactive_list; 267 268 /** 269 * List of breadcrumbs associated with GPU requests currently 270 * outstanding. 271 */ 272 struct list_head request_list; 273#ifdef __linux__ 274 /** 275 * We leave the user IRQ off as much as possible, 276 * but this means that requests will finish and never 277 * be retired once the system goes idle. Set a timer to 278 * fire periodically while the ring is running. When it 279 * fires, go retire requests. 280 */ 281 struct delayed_work retire_work; 282#endif 283 uint32_t next_gem_seqno; 284 285 /** 286 * Waiting sequence number, if any 287 */ 288 uint32_t waiting_gem_seqno; 289 290 /** 291 * Last seq seen at irq time 292 */ 293 uint32_t irq_gem_seqno; 294 295 /** 296 * Flag if the X Server, and thus DRM, is not currently in 297 * control of the device. 298 * 299 * This is set between LeaveVT and EnterVT. It needs to be 300 * replaced with a semaphore. It also needs to be 301 * transitioned away from for kernel modesetting. 302 */ 303 int suspended; 304 305 /** 306 * Flag if the hardware appears to be wedged. 307 * 308 * This is set when attempts to idle the device timeout. 309 * It prevents command submission from occuring and makes 310 * every pending request fail 311 */ 312 int wedged; 313 314 /** Bit 6 swizzling required for X tiling */ 315 uint32_t bit_6_swizzle_x; 316 /** Bit 6 swizzling required for Y tiling */ 317 uint32_t bit_6_swizzle_y; 318 } mm; 319} drm_i915_private_t; 320 321enum intel_chip_family { 322 CHIP_I8XX = 0x01, 323 CHIP_I9XX = 0x02, 324 CHIP_I915 = 0x04, 325 CHIP_I965 = 0x08, 326}; 327 328/** driver private structure attached to each drm_gem_object */ 329struct drm_i915_gem_object { 330 struct drm_gem_object *obj; 331 332 /** Current space allocated to this object in the GTT, if any. */ 333 struct drm_mm_node *gtt_space; 334 335 /** This object's place on the active/flushing/inactive lists */ 336 struct list_head list; 337 338 /** 339 * This is set if the object is on the active or flushing lists 340 * (has pending rendering), and is not set if it's on inactive (ready 341 * to be unbound). 342 */ 343 int active; 344 345 /** 346 * This is set if the object has been written to since last bound 347 * to the GTT 348 */ 349 int dirty; 350 351 /** AGP memory structure for our GTT binding. */ 352 DRM_AGP_MEM *agp_mem; 353 354 struct page **page_list; 355 356 /** 357 * Current offset of the object in GTT space. 358 * 359 * This is the same as gtt_space->start 360 */ 361 uint32_t gtt_offset; 362 363 /** Boolean whether this object has a valid gtt offset. */ 364 int gtt_bound; 365 366 /** How many users have pinned this object in GTT space */ 367 int pin_count; 368 369 /** Breadcrumb of last rendering to the buffer. */ 370 uint32_t last_rendering_seqno; 371 372 /** Current tiling mode for the object. */ 373 uint32_t tiling_mode; 374 375 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ 376 uint32_t agp_type; 377 378 /** 379 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when 380 * GEM_DOMAIN_CPU is not in the object's read domain. 381 */ 382 uint8_t *page_cpu_valid; 383}; 384 385/** 386 * Request queue structure. 387 * 388 * The request queue allows us to note sequence numbers that have been emitted 389 * and may be associated with active buffers to be retired. 390 * 391 * By keeping this list, we can avoid having to do questionable 392 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 393 * an emission time with seqnos for tracking how far ahead of the GPU we are. 394 */ 395struct drm_i915_gem_request { 396 /** GEM sequence number associated with this request. */ 397 uint32_t seqno; 398 399 /** Time at which this request was emitted, in jiffies. */ 400 unsigned long emitted_jiffies; 401 402 /** Cache domains that were flushed at the start of the request. */ 403 uint32_t flush_domains; 404 405 struct list_head list; 406}; 407 408struct drm_i915_file_private { 409 struct { 410 uint32_t last_gem_seqno; 411 uint32_t last_gem_throttle_seqno; 412 } mm; 413}; 414 415extern struct drm_ioctl_desc i915_ioctls[]; 416extern int i915_max_ioctl; 417 418 /* i915_dma.c */ 419extern void i915_kernel_lost_context(struct drm_device * dev); 420extern int i915_driver_load(struct drm_device *, unsigned long flags); 421extern int i915_driver_unload(struct drm_device *); 422extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 423extern void i915_driver_lastclose(struct drm_device * dev); 424extern void i915_driver_preclose(struct drm_device *dev, 425 struct drm_file *file_priv); 426extern void i915_driver_postclose(struct drm_device *dev, 427 struct drm_file *file_priv); 428extern int i915_driver_device_is_agp(struct drm_device * dev); 429extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 430 unsigned long arg); 431extern int i915_emit_box(struct drm_device *dev, 432 struct drm_clip_rect __user *boxes, 433 int i, int DR1, int DR4); 434 435/* i915_irq.c */ 436extern int i915_irq_emit(struct drm_device *dev, void *data, 437 struct drm_file *file_priv); 438extern int i915_irq_wait(struct drm_device *dev, void *data, 439 struct drm_file *file_priv); 440void i915_user_irq_get(struct drm_device *dev); 441void i915_user_irq_put(struct drm_device *dev); 442 443extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 444extern void i915_driver_irq_preinstall(struct drm_device * dev); 445extern int i915_driver_irq_postinstall(struct drm_device *dev); 446extern void i915_driver_irq_uninstall(struct drm_device * dev); 447extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 448 struct drm_file *file_priv); 449extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 450 struct drm_file *file_priv); 451extern int i915_enable_vblank(struct drm_device *dev, int crtc); 452extern void i915_disable_vblank(struct drm_device *dev, int crtc); 453extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 454extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); 455extern int i915_vblank_swap(struct drm_device *dev, void *data, 456 struct drm_file *file_priv); 457 458void 459i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 460 461void 462i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 463 464 465/* i915_mem.c */ 466extern int i915_mem_alloc(struct drm_device *dev, void *data, 467 struct drm_file *file_priv); 468extern int i915_mem_free(struct drm_device *dev, void *data, 469 struct drm_file *file_priv); 470extern int i915_mem_init_heap(struct drm_device *dev, void *data, 471 struct drm_file *file_priv); 472extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, 473 struct drm_file *file_priv); 474extern void i915_mem_takedown(struct mem_block **heap); 475extern void i915_mem_release(struct drm_device * dev, 476 struct drm_file *file_priv, struct mem_block *heap); 477#ifdef I915_HAVE_GEM 478/* i915_gem.c */ 479int i915_gem_init_ioctl(struct drm_device *dev, void *data, 480 struct drm_file *file_priv); 481int i915_gem_create_ioctl(struct drm_device *dev, void *data, 482 struct drm_file *file_priv); 483int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 484 struct drm_file *file_priv); 485int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 486 struct drm_file *file_priv); 487int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 488 struct drm_file *file_priv); 489int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 490 struct drm_file *file_priv); 491int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 492 struct drm_file *file_priv); 493int i915_gem_execbuffer(struct drm_device *dev, void *data, 494 struct drm_file *file_priv); 495int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 496 struct drm_file *file_priv); 497int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 498 struct drm_file *file_priv); 499int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 500 struct drm_file *file_priv); 501int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 502 struct drm_file *file_priv); 503int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 504 struct drm_file *file_priv); 505int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 506 struct drm_file *file_priv); 507int i915_gem_set_tiling(struct drm_device *dev, void *data, 508 struct drm_file *file_priv); 509int i915_gem_get_tiling(struct drm_device *dev, void *data, 510 struct drm_file *file_priv); 511void i915_gem_load(struct drm_device *dev); 512int i915_gem_proc_init(struct drm_minor *minor); 513void i915_gem_proc_cleanup(struct drm_minor *minor); 514int i915_gem_init_object(struct drm_gem_object *obj); 515void i915_gem_free_object(struct drm_gem_object *obj); 516int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); 517void i915_gem_object_unpin(struct drm_gem_object *obj); 518void i915_gem_lastclose(struct drm_device *dev); 519uint32_t i915_get_gem_seqno(struct drm_device *dev); 520void i915_gem_retire_requests(struct drm_device *dev); 521void i915_gem_retire_work_handler(struct work_struct *work); 522void i915_gem_clflush_object(struct drm_gem_object *obj); 523 524/* i915_gem_tiling.c */ 525void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 526 527/* i915_gem_debug.c */ 528void i915_gem_dump_object(struct drm_gem_object *obj, int len, 529 const char *where, uint32_t mark); 530#if WATCH_INACTIVE 531void i915_verify_inactive(struct drm_device *dev, char *file, int line); 532#else 533#define i915_verify_inactive(dev, file, line) 534#endif 535void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); 536void i915_gem_dump_object(struct drm_gem_object *obj, int len, 537 const char *where, uint32_t mark); 538void i915_dump_lru(struct drm_device *dev, const char *where); 539#endif /* I915_HAVE_GEM */ 540 541/* i915_suspend.c */ 542extern int i915_save_state(struct drm_device *dev); 543extern int i915_restore_state(struct drm_device *dev); 544 545/* i915_opregion.c */ 546extern int intel_opregion_init(struct drm_device *dev); 547extern void intel_opregion_free(struct drm_device *dev); 548extern void opregion_asle_intr(struct drm_device *dev); 549extern void opregion_enable_asle(struct drm_device *dev); 550 551/** 552 * Lock test for when it's just for synchronization of ring access. 553 * 554 * In that case, we don't need to do it when GEM is initialized as nobody else 555 * has access to the ring. 556 */ 557#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ 558 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ 559 LOCK_TEST_WITH_RETURN(dev, file_priv); \ 560} while (0) 561 562#if defined(__FreeBSD__) 563typedef boolean_t bool; 564#endif 565 566#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 567#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 568#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 569#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 570#define I915_READ8(reg) DRM_READ8(dev_priv->mmio_map, (reg)) 571#define I915_WRITE8(reg,val) DRM_WRITE8(dev_priv->mmio_map, (reg), (val)) 572 573#define I915_VERBOSE 0 574 575#define RING_LOCALS unsigned int outring, ringmask, outcount; \ 576 volatile char *virt; 577 578#define BEGIN_LP_RING(n) do { \ 579 if (I915_VERBOSE) \ 580 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 581 if (dev_priv->ring.space < (n)*4) \ 582 i915_wait_ring(dev, (n)*4, __func__); \ 583 outcount = 0; \ 584 outring = dev_priv->ring.tail; \ 585 ringmask = dev_priv->ring.tail_mask; \ 586 virt = dev_priv->ring.virtual_start; \ 587} while (0) 588 589#define OUT_RING(n) do { \ 590 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 591 *(volatile unsigned int *)(virt + outring) = (n); \ 592 outcount++; \ 593 outring += 4; \ 594 outring &= ringmask; \ 595} while (0) 596 597#define ADVANCE_LP_RING() do { \ 598 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 599 dev_priv->ring.tail = outring; \ 600 dev_priv->ring.space -= outcount * 4; \ 601 I915_WRITE(PRB0_TAIL, outring); \ 602} while(0) 603 604/** 605 * Reads a dword out of the status page, which is written to from the command 606 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 607 * MI_STORE_DATA_IMM. 608 * 609 * The following dwords have a reserved meaning: 610 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 611 * 0x04: ring 0 head pointer 612 * 0x05: ring 1 head pointer (915-class) 613 * 0x06: ring 2 head pointer (915-class) 614 * 0x10-0x1b: Context status DWords (GM45) 615 * 0x1f: Last written status offset. (GM45) 616 * 617 * The area from dword 0x20 to 0x3ff is available for driver usage. 618 */ 619#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 620#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 621#define I915_GEM_HWS_INDEX 0x20 622#define I915_BREADCRUMB_INDEX 0x21 623 624extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 625 626#define IS_I830(dev) ((dev)->pci_device == 0x3577) 627#define IS_845G(dev) ((dev)->pci_device == 0x2562) 628#define IS_I85X(dev) ((dev)->pci_device == 0x3582) 629#define IS_I855(dev) ((dev)->pci_device == 0x3582) 630#define IS_I865G(dev) ((dev)->pci_device == 0x2572) 631 632#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) 633#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 634#define IS_I945G(dev) ((dev)->pci_device == 0x2772) 635#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ 636 (dev)->pci_device == 0x27AE) 637#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 638 (dev)->pci_device == 0x2982 || \ 639 (dev)->pci_device == 0x2992 || \ 640 (dev)->pci_device == 0x29A2 || \ 641 (dev)->pci_device == 0x2A02 || \ 642 (dev)->pci_device == 0x2A12 || \ 643 (dev)->pci_device == 0x2A42 || \ 644 (dev)->pci_device == 0x2E02 || \ 645 (dev)->pci_device == 0x2E12 || \ 646 (dev)->pci_device == 0x2E22) 647 648#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 649 650#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 651 652#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 653 (dev)->pci_device == 0x2E12 || \ 654 (dev)->pci_device == 0x2E22) 655 656#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 657 (dev)->pci_device == 0x29B2 || \ 658 (dev)->pci_device == 0x29D2) 659 660#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 661 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 662 663#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 664 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) 665 666#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 667 668#define PRIMARY_RINGBUFFER_SIZE (128*1024) 669 670#endif 671