if_dcreg.h revision 66681
167754Smsmith/* 267754Smsmith * Copyright (c) 1997, 1998, 1999 367754Smsmith * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 467754Smsmith * 567754Smsmith * Redistribution and use in source and binary forms, with or without 667754Smsmith * modification, are permitted provided that the following conditions 7217365Sjkim * are met: 8306536Sjkim * 1. Redistributions of source code must retain the above copyright 970243Smsmith * notice, this list of conditions and the following disclaimer. 1067754Smsmith * 2. Redistributions in binary form must reproduce the above copyright 11217365Sjkim * notice, this list of conditions and the following disclaimer in the 12217365Sjkim * documentation and/or other materials provided with the distribution. 13217365Sjkim * 3. All advertising materials mentioning features or use of this software 14217365Sjkim * must display the following acknowledgement: 15217365Sjkim * This product includes software developed by Bill Paul. 16217365Sjkim * 4. Neither the name of the author nor the names of any co-contributors 17217365Sjkim * may be used to endorse or promote products derived from this software 18217365Sjkim * without specific prior written permission. 19217365Sjkim * 20217365Sjkim * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21217365Sjkim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22217365Sjkim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23217365Sjkim * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24217365Sjkim * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2567754Smsmith * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26217365Sjkim * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27217365Sjkim * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28217365Sjkim * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2967754Smsmith * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30217365Sjkim * THE POSSIBILITY OF SUCH DAMAGE. 31217365Sjkim * 32217365Sjkim * $FreeBSD: head/sys/dev/dc/if_dcreg.h 66681 2000-10-05 17:36:14Z wpaul $ 33217365Sjkim */ 34217365Sjkim 35217365Sjkim/* 36217365Sjkim * 21143 and clone common register definitions. 37217365Sjkim */ 38217365Sjkim 39217365Sjkim#define DC_BUSCTL 0x00 /* bus control */ 40217365Sjkim#define DC_TXSTART 0x08 /* tx start demand */ 41217365Sjkim#define DC_RXSTART 0x10 /* rx start demand */ 42217365Sjkim#define DC_RXADDR 0x18 /* rx descriptor list start addr */ 4367754Smsmith#define DC_TXADDR 0x20 /* tx descriptor list start addr */ 4467754Smsmith#define DC_ISR 0x28 /* interrupt status register */ 4567754Smsmith#define DC_NETCFG 0x30 /* network config register */ 4667754Smsmith#define DC_IMR 0x38 /* interrupt mask */ 47151937Sjkim#define DC_FRAMESDISCARDED 0x40 /* # of discarded frames */ 4867754Smsmith#define DC_SIO 0x48 /* MII and ROM/EEPROM access */ 49193341Sjkim#define DC_ROM 0x50 /* ROM programming address */ 50151937Sjkim#define DC_TIMER 0x58 /* general timer */ 51151937Sjkim#define DC_10BTSTAT 0x60 /* SIA status */ 5267754Smsmith#define DC_SIARESET 0x68 /* SIA connectivity */ 53151937Sjkim#define DC_10BTCTRL 0x70 /* SIA transmit and receive */ 54167802Sjkim#define DC_WATCHDOG 0x78 /* SIA and general purpose port */ 55167802Sjkim 56167802Sjkim/* 57167802Sjkim * There are two general 'types' of MX chips that we need to be 58167802Sjkim * concerned with. One is the original 98713, which has its internal 5967754Smsmith * NWAY support controlled via the MDIO bits in the serial I/O 60167802Sjkim * register. The other is everything else (from the 98713A on up), 61151937Sjkim * which has its internal NWAY controlled via CSR13, CSR14 and CSR15, 62151937Sjkim * just like the 21143. This type setting also governs which of the 6367754Smsmith * 'magic' numbers we write to CSR16. The PNIC II falls into the 64151937Sjkim * 98713A/98715/98715A/98725 category. 65151937Sjkim */ 66151937Sjkim#define DC_TYPE_98713 0x1 67151937Sjkim#define DC_TYPE_98713A 0x2 68151937Sjkim#define DC_TYPE_987x5 0x3 69151937Sjkim 70151937Sjkim/* Other type of supported chips. */ 71151937Sjkim#define DC_TYPE_21143 0x4 /* Intel 21143 */ 72151937Sjkim#define DC_TYPE_ASIX 0x5 /* ASIX AX88140A/AX88141 */ 7367754Smsmith#define DC_TYPE_AL981 0x6 /* ADMtek AL981 Comet */ 74151937Sjkim#define DC_TYPE_AN985 0x7 /* ADMtek AN985 Centaur */ 7567754Smsmith#define DC_TYPE_DM9102 0x8 /* Davicom DM9102 */ 76151937Sjkim#define DC_TYPE_PNICII 0x9 /* 82c115 PNIC II */ 7767754Smsmith#define DC_TYPE_PNIC 0xA /* 82c168/82c169 PNIC I */ 78228110Sjkim 79228110Sjkim#define DC_IS_MACRONIX(x) \ 80228110Sjkim (x->dc_type == DC_TYPE_98713 || \ 81228110Sjkim x->dc_type == DC_TYPE_98713A || \ 82228110Sjkim x->dc_type == DC_TYPE_987x5) 83228110Sjkim 84228110Sjkim#define DC_IS_ADMTEK(x) \ 85228110Sjkim (x->dc_type == DC_TYPE_AL981 || \ 86228110Sjkim x->dc_type == DC_TYPE_AN985) 87228110Sjkim 88228110Sjkim#define DC_IS_INTEL(x) (x->dc_type == DC_TYPE_21143) 89228110Sjkim#define DC_IS_ASIX(x) (x->dc_type == DC_TYPE_ASIX) 90228110Sjkim#define DC_IS_COMET(x) (x->dc_type == DC_TYPE_AL981) 91228110Sjkim#define DC_IS_CENTAUR(x) (x->dc_type == DC_TYPE_AN985) 92228110Sjkim#define DC_IS_DAVICOM(x) (x->dc_type == DC_TYPE_DM9102) 93228110Sjkim#define DC_IS_PNICII(x) (x->dc_type == DC_TYPE_PNICII) 94228110Sjkim#define DC_IS_PNIC(x) (x->dc_type == DC_TYPE_PNIC) 95228110Sjkim 96228110Sjkim/* MII/symbol mode port types */ 97228110Sjkim#define DC_PMODE_MII 0x1 98228110Sjkim#define DC_PMODE_SYM 0x2 99228110Sjkim#define DC_PMODE_SIA 0x3 100228110Sjkim 101228110Sjkim/* 102228110Sjkim * Bus control bits. 103228110Sjkim */ 104228110Sjkim#define DC_BUSCTL_RESET 0x00000001 105228110Sjkim#define DC_BUSCTL_ARBITRATION 0x00000002 106228110Sjkim#define DC_BUSCTL_SKIPLEN 0x0000007C 107228110Sjkim#define DC_BUSCTL_BUF_BIGENDIAN 0x00000080 108228110Sjkim#define DC_BUSCTL_BURSTLEN 0x00003F00 109228110Sjkim#define DC_BUSCTL_CACHEALIGN 0x0000C000 110228110Sjkim#define DC_BUSCTL_TXPOLL 0x000E0000 111228110Sjkim#define DC_BUSCTL_DBO 0x00100000 11267754Smsmith#define DC_BUSCTL_MRME 0x00200000 113228110Sjkim#define DC_BUSCTL_MRLE 0x00800000 114228110Sjkim#define DC_BUSCTL_MWIE 0x01000000 115151937Sjkim#define DC_BUSCTL_ONNOW_ENB 0x04000000 116114237Snjl 117151937Sjkim#define DC_SKIPLEN_1LONG 0x00000004 118151937Sjkim#define DC_SKIPLEN_2LONG 0x00000008 11967754Smsmith#define DC_SKIPLEN_3LONG 0x00000010 120151937Sjkim#define DC_SKIPLEN_4LONG 0x00000020 12167754Smsmith#define DC_SKIPLEN_5LONG 0x00000040 122151937Sjkim 123151937Sjkim#define DC_CACHEALIGN_NONE 0x00000000 12467754Smsmith#define DC_CACHEALIGN_8LONG 0x00004000 12567754Smsmith#define DC_CACHEALIGN_16LONG 0x00008000 126228110Sjkim#define DC_CACHEALIGN_32LONG 0x0000C000 127228110Sjkim 128228110Sjkim#define DC_BURSTLEN_USECA 0x00000000 129151937Sjkim#define DC_BURSTLEN_1LONG 0x00000100 130151937Sjkim#define DC_BURSTLEN_2LONG 0x00000200 131151937Sjkim#define DC_BURSTLEN_4LONG 0x00000400 132151937Sjkim#define DC_BURSTLEN_8LONG 0x00000800 133306536Sjkim#define DC_BURSTLEN_16LONG 0x00001000 134167802Sjkim#define DC_BURSTLEN_32LONG 0x00002000 13599679Siwasaki 136151937Sjkim#define DC_TXPOLL_OFF 0x00000000 137102550Siwasaki#define DC_TXPOLL_1 0x00020000 138151937Sjkim#define DC_TXPOLL_2 0x00040000 13999679Siwasaki#define DC_TXPOLL_3 0x00060000 140228110Sjkim#define DC_TXPOLL_4 0x00080000 141228110Sjkim#define DC_TXPOLL_5 0x000A0000 142228110Sjkim#define DC_TXPOLL_6 0x000C0000 143228110Sjkim#define DC_TXPOLL_7 0x000E0000 144228110Sjkim 145228110Sjkim/* 146228110Sjkim * Interrupt status bits. 147228110Sjkim */ 148228110Sjkim#define DC_ISR_TX_OK 0x00000001 149228110Sjkim#define DC_ISR_TX_IDLE 0x00000002 150228110Sjkim#define DC_ISR_TX_NOBUF 0x00000004 151228110Sjkim#define DC_ISR_TX_JABBERTIMEO 0x00000008 152228110Sjkim#define DC_ISR_LINKGOOD 0x00000010 153228110Sjkim#define DC_ISR_TX_UNDERRUN 0x00000020 154228110Sjkim#define DC_ISR_RX_OK 0x00000040 155228110Sjkim#define DC_ISR_RX_NOBUF 0x00000080 156228110Sjkim#define DC_ISR_RX_READ 0x00000100 157228110Sjkim#define DC_ISR_RX_WATDOGTIMEO 0x00000200 158228110Sjkim#define DC_ISR_TX_EARLY 0x00000400 15999679Siwasaki#define DC_ISR_TIMER_EXPIRED 0x00000800 160228110Sjkim#define DC_ISR_LINKFAIL 0x00001000 161228110Sjkim#define DC_ISR_BUS_ERR 0x00002000 162151937Sjkim#define DC_ISR_RX_EARLY 0x00004000 16399679Siwasaki#define DC_ISR_ABNORMAL 0x00008000 164151937Sjkim#define DC_ISR_NORMAL 0x00010000 16599679Siwasaki#define DC_ISR_RX_STATE 0x000E0000 16699679Siwasaki#define DC_ISR_TX_STATE 0x00700000 167151937Sjkim#define DC_ISR_BUSERRTYPE 0x03800000 16899679Siwasaki#define DC_ISR_100MBPSLINK 0x08000000 169151937Sjkim#define DC_ISR_MAGICKPACK 0x10000000 170228110Sjkim 171151937Sjkim#define DC_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 17299679Siwasaki#define DC_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 173151937Sjkim#define DC_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 17467754Smsmith#define DC_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 175167802Sjkim#define DC_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 176228110Sjkim#define DC_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 177167802Sjkim#define DC_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 17867754Smsmith#define DC_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 179228110Sjkim 18067754Smsmith#define DC_TXSTATE_RESET 0x00000000 /* 000 - reset */ 181167802Sjkim#define DC_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 182167802Sjkim#define DC_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 183167802Sjkim#define DC_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 184167802Sjkim#define DC_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 185167802Sjkim#define DC_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 186167802Sjkim#define DC_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 187167802Sjkim#define DC_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 188167802Sjkim 189167802Sjkim/* 190151937Sjkim * Network config bits. 191151937Sjkim */ 192151937Sjkim#define DC_NETCFG_RX_HASHPERF 0x00000001 19367754Smsmith#define DC_NETCFG_RX_ON 0x00000002 194151937Sjkim#define DC_NETCFG_RX_HASHONLY 0x00000004 195151937Sjkim#define DC_NETCFG_RX_BADFRAMES 0x00000008 196151937Sjkim#define DC_NETCFG_RX_INVFILT 0x00000010 19767754Smsmith#define DC_NETCFG_BACKOFFCNT 0x00000020 19867754Smsmith#define DC_NETCFG_RX_PROMISC 0x00000040 199151937Sjkim#define DC_NETCFG_RX_ALLMULTI 0x00000080 200281075Sdim#define DC_NETCFG_FULLDUPLEX 0x00000200 201151937Sjkim#define DC_NETCFG_LOOPBACK 0x00000C00 20267754Smsmith#define DC_NETCFG_FORCECOLL 0x00001000 20367754Smsmith#define DC_NETCFG_TX_ON 0x00002000 204151937Sjkim#define DC_NETCFG_TX_THRESH 0x0000C000 20567754Smsmith#define DC_NETCFG_TX_BACKOFF 0x00020000 206151937Sjkim#define DC_NETCFG_PORTSEL 0x00040000 /* 0 == 10, 1 == 100 */ 20767754Smsmith#define DC_NETCFG_HEARTBEAT 0x00080000 20867754Smsmith#define DC_NETCFG_STORENFWD 0x00200000 209151937Sjkim#define DC_NETCFG_SPEEDSEL 0x00400000 /* 1 == 10, 0 == 100 */ 210151937Sjkim#define DC_NETCFG_PCS 0x00800000 211151937Sjkim#define DC_NETCFG_SCRAMBLER 0x01000000 21267754Smsmith#define DC_NETCFG_NO_RXCRC 0x02000000 213151937Sjkim#define DC_NETCFG_RX_ALL 0x40000000 214167802Sjkim#define DC_NETCFG_CAPEFFECT 0x80000000 215151937Sjkim 21667754Smsmith#define DC_OPMODE_NORM 0x00000000 21767754Smsmith#define DC_OPMODE_INTLOOP 0x00000400 218151937Sjkim#define DC_OPMODE_EXTLOOP 0x00000800 219167802Sjkim 220151937Sjkim#define DC_TXTHRESH_72BYTES 0x00000000 22167754Smsmith#define DC_TXTHRESH_96BYTES 0x00004000 22267754Smsmith#define DC_TXTHRESH_128BYTES 0x00008000 223151937Sjkim#define DC_TXTHRESH_160BYTES 0x0000C000 224167802Sjkim 225151937Sjkim 22667754Smsmith/* 22767754Smsmith * Interrupt mask bits. 228151937Sjkim */ 229151937Sjkim#define DC_IMR_TX_OK 0x00000001 230306536Sjkim#define DC_IMR_TX_IDLE 0x00000002 231151937Sjkim#define DC_IMR_TX_NOBUF 0x00000004 23267754Smsmith#define DC_IMR_TX_JABBERTIMEO 0x00000008 23367754Smsmith#define DC_IMR_LINKGOOD 0x00000010 234151937Sjkim#define DC_IMR_TX_UNDERRUN 0x00000020 235167802Sjkim#define DC_IMR_RX_OK 0x00000040 236151937Sjkim#define DC_IMR_RX_NOBUF 0x00000080 23767754Smsmith#define DC_IMR_RX_READ 0x00000100 238228110Sjkim#define DC_IMR_RX_WATDOGTIMEO 0x00000200 239228110Sjkim#define DC_IMR_TX_EARLY 0x00000400 240228110Sjkim#define DC_IMR_TIMER_EXPIRED 0x00000800 241228110Sjkim#define DC_IMR_LINKFAIL 0x00001000 24267754Smsmith#define DC_IMR_BUS_ERR 0x00002000 243151937Sjkim#define DC_IMR_RX_EARLY 0x00004000 244151937Sjkim#define DC_IMR_ABNORMAL 0x00008000 245151937Sjkim#define DC_IMR_NORMAL 0x00010000 24667754Smsmith#define DC_IMR_100MBPSLINK 0x08000000 247151937Sjkim#define DC_IMR_MAGICKPACK 0x10000000 248151937Sjkim 249151937Sjkim#define DC_INTRS \ 250151937Sjkim (DC_IMR_RX_OK|DC_IMR_TX_OK|DC_IMR_RX_NOBUF|DC_IMR_RX_WATDOGTIMEO|\ 25167754Smsmith DC_IMR_TX_NOBUF|DC_IMR_TX_UNDERRUN|DC_IMR_BUS_ERR| \ 25267754Smsmith DC_IMR_ABNORMAL|DC_IMR_NORMAL/*|DC_IMR_TX_EARLY*/) 253151937Sjkim/* 254281075Sdim * Serial I/O (EEPROM/ROM) bits. 255281075Sdim */ 256151937Sjkim#define DC_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 25767754Smsmith#define DC_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 25867754Smsmith#define DC_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 259151937Sjkim#define DC_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 260151937Sjkim#define DC_SIO_ROMDATA4 0x00000010 261151937Sjkim#define DC_SIO_ROMDATA5 0x00000020 26267754Smsmith#define DC_SIO_ROMDATA6 0x00000040 26367754Smsmith#define DC_SIO_ROMDATA7 0x00000080 264151937Sjkim#define DC_SIO_EESEL 0x00000800 265167802Sjkim#define DC_SIO_ROMSEL 0x00001000 266167802Sjkim#define DC_SIO_ROMCTL_WRITE 0x00002000 267167802Sjkim#define DC_SIO_ROMCTL_READ 0x00004000 268167802Sjkim#define DC_SIO_MII_CLK 0x00010000 /* MDIO clock */ 269245582Sjkim#define DC_SIO_MII_DATAOUT 0x00020000 /* MDIO data out */ 27067754Smsmith#define DC_SIO_MII_DIR 0x00040000 /* MDIO dir */ 27167754Smsmith#define DC_SIO_MII_DATAIN 0x00080000 /* MDIO data in */ 272151937Sjkim 273151937Sjkim#define DC_EECMD_WRITE 0x140 274151937Sjkim#define DC_EECMD_READ 0x180 275151937Sjkim#define DC_EECMD_ERASE 0x1c0 27667754Smsmith 27767754Smsmith#define DC_EE_NODEADDR_OFFSET 0x70 278151937Sjkim#define DC_EE_NODEADDR 10 279151937Sjkim 280151937Sjkim/* 281151937Sjkim * General purpose timer register 282151937Sjkim */ 283151937Sjkim#define DC_TIMER_VALUE 0x0000FFFF 284151937Sjkim#define DC_TIMER_CONTINUOUS 0x00010000 28567754Smsmith 286151937Sjkim/* 287151937Sjkim * 10baseT status register 288151937Sjkim */ 289151937Sjkim#define DC_TSTAT_MIIACT 0x00000001 /* MII port activity */ 29077424Smsmith#define DC_TSTAT_LS100 0x00000002 /* link status of 100baseTX */ 29177424Smsmith#define DC_TSTAT_LS10 0x00000004 /* link status of 10baseT */ 292151937Sjkim#define DC_TSTAT_AUTOPOLARITY 0x00000008 293151937Sjkim#define DC_TSTAT_AUIACT 0x00000100 /* AUI activity */ 294151937Sjkim#define DC_TSTAT_10BTACT 0x00000200 /* 10baseT activity */ 29577424Smsmith#define DC_TSTAT_NSN 0x00000400 /* non-stable FLPs detected */ 296151937Sjkim#define DC_TSTAT_REMFAULT 0x00000800 297151937Sjkim#define DC_TSTAT_ANEGSTAT 0x00007000 298151937Sjkim#define DC_TSTAT_LP_CAN_NWAY 0x00008000 /* link partner supports NWAY */ 299151937Sjkim#define DC_TSTAT_LPCODEWORD 0xFFFF0000 /* link partner's code word */ 30067754Smsmith 30167754Smsmith#define DC_ASTAT_DISABLE 0x00000000 302151937Sjkim#define DC_ASTAT_TXDISABLE 0x00001000 303151937Sjkim#define DC_ASTAT_ABDETECT 0x00002000 304151937Sjkim#define DC_ASTAT_ACKDETECT 0x00003000 305151937Sjkim#define DC_ASTAT_CMPACKDETECT 0x00004000 30667754Smsmith#define DC_ASTAT_AUTONEGCMP 0x00005000 30767754Smsmith#define DC_ASTAT_LINKCHECK 0x00006000 308151937Sjkim 309151937Sjkim/* 310151937Sjkim * PHY reset register 311151937Sjkim */ 312151937Sjkim#define DC_SIA_RESET 0x00000001 313151937Sjkim#define DC_SIA_AUI 0x00000008 /* AUI or 10baseT */ 314151937Sjkim 315151937Sjkim/* 316151937Sjkim * 10baseT control register 31767754Smsmith */ 318151937Sjkim#define DC_TCTL_ENCODER_ENB 0x00000001 319151937Sjkim#define DC_TCTL_LOOPBACK 0x00000002 320151937Sjkim#define DC_TCTL_DRIVER_ENB 0x00000004 321151937Sjkim#define DC_TCTL_LNKPULSE_ENB 0x00000008 32267754Smsmith#define DC_TCTL_HALFDUPLEX 0x00000040 323151937Sjkim#define DC_TCTL_AUTONEGENBL 0x00000080 324151937Sjkim#define DC_TCTL_RX_SQUELCH 0x00000100 325151937Sjkim#define DC_TCTL_COLL_SQUELCH 0x00000200 326151937Sjkim#define DC_TCTL_COLL_DETECT 0x00000400 32767754Smsmith#define DC_TCTL_SQE_ENB 0x00000800 328151937Sjkim#define DC_TCTL_LINKTEST 0x00001000 329151937Sjkim#define DC_TCTL_AUTOPOLARITY 0x00002000 330151937Sjkim#define DC_TCTL_SET_POL_PLUS 0x00004000 331151937Sjkim#define DC_TCTL_AUTOSENSE 0x00008000 /* 10bt/AUI autosense */ 332151937Sjkim#define DC_TCTL_100BTXHALF 0x00010000 333151937Sjkim#define DC_TCTL_100BTXFULL 0x00020000 334151937Sjkim#define DC_TCTL_100BT4 0x00040000 33567754Smsmith 336151937Sjkim/* 337151937Sjkim * Watchdog timer register 338151937Sjkim */ 339151937Sjkim#define DC_WDOG_JABBERDIS 0x00000001 340151937Sjkim#define DC_WDOG_HOSTUNJAB 0x00000002 34167754Smsmith#define DC_WDOG_JABBERCLK 0x00000004 342151937Sjkim#define DC_WDOG_RXWDOGDIS 0x00000010 343151937Sjkim#define DC_WDOG_RXWDOGCLK 0x00000020 344151937Sjkim#define DC_WDOG_MUSTBEZERO 0x00000100 345151937Sjkim#define DC_WDOG_AUIBNC 0x00100000 346151937Sjkim#define DC_WDOG_ACTIVITY 0x00200000 34767754Smsmith#define DC_WDOG_RX_MATCH 0x00400000 348151937Sjkim#define DC_WDOG_LINK 0x00800000 349151937Sjkim#define DC_WDOG_CTLWREN 0x08000000 350151937Sjkim 351151937Sjkim/* 35267754Smsmith * Size of a setup frame. 35367754Smsmith */ 354151937Sjkim#define DC_SFRAME_LEN 192 355281687Sjkim 356151937Sjkim/* 357281687Sjkim * 21x4x TX/RX list structure. 358151937Sjkim */ 359151937Sjkim 360151937Sjkimstruct dc_desc { 36167754Smsmith u_int32_t dc_status; 362151937Sjkim u_int32_t dc_ctl; 363151937Sjkim u_int32_t dc_ptr1; 364151937Sjkim u_int32_t dc_ptr2; 365281687Sjkim}; 36667754Smsmith 36767754Smsmith#define dc_data dc_ptr1 368151937Sjkim#define dc_next dc_ptr2 369151937Sjkim 370151937Sjkim#define DC_RXSTAT_FIFOOFLOW 0x00000001 371151937Sjkim#define DC_RXSTAT_CRCERR 0x00000002 372151937Sjkim#define DC_RXSTAT_DRIBBLE 0x00000004 373151937Sjkim#define DC_RXSTAT_WATCHDOG 0x00000010 374151937Sjkim#define DC_RXSTAT_FRAMETYPE 0x00000020 /* 0 == IEEE 802.3 */ 375151937Sjkim#define DC_RXSTAT_COLLSEEN 0x00000040 376151937Sjkim#define DC_RXSTAT_GIANT 0x00000080 377151937Sjkim#define DC_RXSTAT_LASTFRAG 0x00000100 378151937Sjkim#define DC_RXSTAT_FIRSTFRAG 0x00000200 379151937Sjkim#define DC_RXSTAT_MULTICAST 0x00000400 380151937Sjkim#define DC_RXSTAT_RUNT 0x00000800 381151937Sjkim#define DC_RXSTAT_RXTYPE 0x00003000 382151937Sjkim#define DC_RXSTAT_RXERR 0x00008000 383151937Sjkim#define DC_RXSTAT_RXLEN 0x3FFF0000 384151937Sjkim#define DC_RXSTAT_OWN 0x80000000 385228110Sjkim 386228110Sjkim#define DC_RXBYTES(x) ((x & DC_RXSTAT_RXLEN) >> 16) 387228110Sjkim#define DC_RXSTAT (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG|DC_RXSTAT_OWN) 388228110Sjkim 389228110Sjkim#define DC_RXCTL_BUFLEN1 0x00000FFF 39067754Smsmith#define DC_RXCTL_BUFLEN2 0x00FFF000 391151937Sjkim#define DC_RXCTL_RLINK 0x01000000 39267754Smsmith#define DC_RXCTL_RLAST 0x02000000 393151937Sjkim 394151937Sjkim#define DC_TXSTAT_DEFER 0x00000001 395151937Sjkim#define DC_TXSTAT_UNDERRUN 0x00000002 396151937Sjkim#define DC_TXSTAT_LINKFAIL 0x00000003 397151937Sjkim#define DC_TXSTAT_COLLCNT 0x00000078 398151937Sjkim#define DC_TXSTAT_SQE 0x00000080 399151937Sjkim#define DC_TXSTAT_EXCESSCOLL 0x00000100 400151937Sjkim#define DC_TXSTAT_LATECOLL 0x00000200 401151937Sjkim#define DC_TXSTAT_NOCARRIER 0x00000400 402151937Sjkim#define DC_TXSTAT_CARRLOST 0x00000800 403151937Sjkim#define DC_TXSTAT_JABTIMEO 0x00004000 404151937Sjkim#define DC_TXSTAT_ERRSUM 0x00008000 405151937Sjkim#define DC_TXSTAT_OWN 0x80000000 406151937Sjkim 407151937Sjkim#define DC_TXCTL_BUFLEN1 0x000007FF 408228110Sjkim#define DC_TXCTL_BUFLEN2 0x003FF800 409151937Sjkim#define DC_TXCTL_FILTTYPE0 0x00400000 410151937Sjkim#define DC_TXCTL_PAD 0x00800000 411245582Sjkim#define DC_TXCTL_TLINK 0x01000000 412151937Sjkim#define DC_TXCTL_TLAST 0x02000000 413151937Sjkim#define DC_TXCTL_NOCRC 0x04000000 414245582Sjkim#define DC_TXCTL_SETUP 0x08000000 415151937Sjkim#define DC_TXCTL_FILTTYPE1 0x10000000 416151937Sjkim#define DC_TXCTL_FIRSTFRAG 0x20000000 417151937Sjkim#define DC_TXCTL_LASTFRAG 0x40000000 418151937Sjkim#define DC_TXCTL_FINT 0x80000000 419245582Sjkim 420151937Sjkim#define DC_FILTER_PERFECT 0x00000000 421151937Sjkim#define DC_FILTER_HASHPERF 0x00400000 422151937Sjkim#define DC_FILTER_INVERSE 0x10000000 423151937Sjkim#define DC_FILTER_HASHONLY 0x10400000 424151937Sjkim 425245582Sjkim#define DC_MAXFRAGS 16 426151937Sjkim#define DC_RX_LIST_CNT 64 427151937Sjkim#define DC_TX_LIST_CNT 256 428151937Sjkim#define DC_MIN_FRAMELEN 60 429151937Sjkim#define DC_RXLEN 1536 430151937Sjkim 431151937Sjkim#define DC_INC(x, y) (x) = (x + 1) % y 432151937Sjkim 433228110Sjkimstruct dc_list_data { 434228110Sjkim struct dc_desc dc_rx_list[DC_RX_LIST_CNT]; 435228110Sjkim struct dc_desc dc_tx_list[DC_TX_LIST_CNT]; 436228110Sjkim}; 437228110Sjkim 438228110Sjkimstruct dc_chain_data { 439245582Sjkim struct mbuf *dc_rx_chain[DC_RX_LIST_CNT]; 440151937Sjkim struct mbuf *dc_tx_chain[DC_TX_LIST_CNT]; 441151937Sjkim u_int32_t dc_sbuf[DC_SFRAME_LEN/sizeof(u_int32_t)]; 44267754Smsmith u_int8_t dc_pad[DC_MIN_FRAMELEN]; 443 int dc_tx_prod; 444 int dc_tx_cons; 445 int dc_tx_cnt; 446 int dc_rx_prod; 447}; 448 449struct dc_mediainfo { 450 int dc_media; 451 u_int8_t *dc_gp_ptr; 452 u_int8_t dc_gp_len; 453 u_int8_t *dc_reset_ptr; 454 u_int8_t dc_reset_len; 455 struct dc_mediainfo *dc_next; 456}; 457 458 459struct dc_type { 460 u_int16_t dc_vid; 461 u_int16_t dc_did; 462 char *dc_name; 463}; 464 465struct dc_mii_frame { 466 u_int8_t mii_stdelim; 467 u_int8_t mii_opcode; 468 u_int8_t mii_phyaddr; 469 u_int8_t mii_regaddr; 470 u_int8_t mii_turnaround; 471 u_int16_t mii_data; 472}; 473 474/* 475 * MII constants 476 */ 477#define DC_MII_STARTDELIM 0x01 478#define DC_MII_READOP 0x02 479#define DC_MII_WRITEOP 0x01 480#define DC_MII_TURNAROUND 0x02 481 482 483/* 484 * Registers specific to clone devices. 485 * This mainly relates to RX filter programming: not all 21x4x clones 486 * use the standard DEC filter programming mechanism. 487 */ 488 489/* 490 * ADMtek specific registers and constants for the AL981 and AN985. 491 * The AN985 doesn't use the magic PHY registers. 492 */ 493#define DC_AL_PAR0 0xA4 /* station address */ 494#define DC_AL_PAR1 0xA8 /* station address */ 495#define DC_AL_MAR0 0xAC /* multicast hash filter */ 496#define DC_AL_MAR1 0xB0 /* multicast hash filter */ 497#define DC_AL_BMCR 0xB4 /* built in PHY control */ 498#define DC_AL_BMSR 0xB8 /* built in PHY status */ 499#define DC_AL_VENID 0xBC /* built in PHY ID0 */ 500#define DC_AL_DEVID 0xC0 /* built in PHY ID1 */ 501#define DC_AL_ANAR 0xC4 /* built in PHY autoneg advert */ 502#define DC_AL_LPAR 0xC8 /* bnilt in PHY link part. ability */ 503#define DC_AL_ANER 0xCC /* built in PHY autoneg expansion */ 504 505#define DC_ADMTEK_PHYADDR 0x1 506#define DC_AL_EE_NODEADDR 4 507/* End of ADMtek specific registers */ 508 509/* 510 * ASIX specific registers. 511 */ 512#define DC_AX_FILTIDX 0x68 /* RX filter index */ 513#define DC_AX_FILTDATA 0x70 /* RX filter data */ 514 515/* 516 * Special ASIX-specific bits in the ASIX NETCFG register (CSR6). 517 */ 518#define DC_AX_NETCFG_RX_BROAD 0x00000100 519 520/* 521 * RX Filter Index Register values 522 */ 523#define DC_AX_FILTIDX_PAR0 0x00000000 524#define DC_AX_FILTIDX_PAR1 0x00000001 525#define DC_AX_FILTIDX_MAR0 0x00000002 526#define DC_AX_FILTIDX_MAR1 0x00000003 527/* End of ASIX specific registers */ 528 529/* 530 * Macronix specific registers. The Macronix chips have a special 531 * register for reading the NWAY status, which we don't use, plus 532 * a magic packet register, which we need to tweak a bit per the 533 * Macronix application notes. 534 */ 535#define DC_MX_MAGICPACKET 0x80 536#define DC_MX_NWAYSTAT 0xA0 537 538/* 539 * Magic packet register 540 */ 541#define DC_MX_MPACK_DISABLE 0x00400000 542 543/* 544 * NWAY status register. 545 */ 546#define DC_MX_NWAY_10BTHALF 0x08000000 547#define DC_MX_NWAY_10BTFULL 0x10000000 548#define DC_MX_NWAY_100BTHALF 0x20000000 549#define DC_MX_NWAY_100BTFULL 0x40000000 550#define DC_MX_NWAY_100BT4 0x80000000 551 552/* 553 * These are magic values that must be written into CSR16 554 * (DC_MX_MAGICPACKET) in order to put the chip into proper 555 * operating mode. The magic numbers are documented in the 556 * Macronix 98715 application notes. 557 */ 558#define DC_MX_MAGIC_98713 0x0F370000 559#define DC_MX_MAGIC_98713A 0x0B3C0000 560#define DC_MX_MAGIC_98715 0x0B3C0000 561#define DC_MX_MAGIC_98725 0x0B3C0000 562/* End of Macronix specific registers */ 563 564/* 565 * PNIC 82c168/82c169 specific registers. 566 * The PNIC has its own special NWAY support, which doesn't work, 567 * and shortcut ways of reading the EEPROM and MII bus. 568 */ 569#define DC_PN_GPIO 0x60 /* general purpose pins control */ 570#define DC_PN_PWRUP_CFG 0x90 /* config register, set by EEPROM */ 571#define DC_PN_SIOCTL 0x98 /* serial EEPROM control register */ 572#define DC_PN_MII 0xA0 /* MII access register */ 573#define DC_PN_NWAY 0xB8 /* Internal NWAY register */ 574 575/* Serial I/O EEPROM register */ 576#define DC_PN_SIOCTL_DATA 0x0000003F 577#define DC_PN_SIOCTL_OPCODE 0x00000300 578#define DC_PN_SIOCTL_BUSY 0x80000000 579 580#define DC_PN_EEOPCODE_ERASE 0x00000300 581#define DC_PN_EEOPCODE_READ 0x00000600 582#define DC_PN_EEOPCODE_WRITE 0x00000100 583 584/* 585 * The first two general purpose pins control speed selection and 586 * 100Mbps loopback on the 82c168 chip. The control bits should always 587 * be set (to make the data pins outputs) and the speed selction and 588 * loopback bits set accordingly when changing media. Physically, this 589 * will set the state of a relay mounted on the card. 590 */ 591#define DC_PN_GPIO_DATA0 0x000000001 592#define DC_PN_GPIO_DATA1 0x000000002 593#define DC_PN_GPIO_DATA2 0x000000004 594#define DC_PN_GPIO_DATA3 0x000000008 595#define DC_PN_GPIO_CTL0 0x000000010 596#define DC_PN_GPIO_CTL1 0x000000020 597#define DC_PN_GPIO_CTL2 0x000000040 598#define DC_PN_GPIO_CTL3 0x000000080 599#define DC_PN_GPIO_SPEEDSEL DC_PN_GPIO_DATA0/* 1 == 100Mbps, 0 == 10Mbps */ 600#define DC_PN_GPIO_100TX_LOOP DC_PN_GPIO_DATA1/* 1 == normal, 0 == loop */ 601#define DC_PN_GPIO_BNC_ENB DC_PN_GPIO_DATA2 602#define DC_PN_GPIO_100TX_LNK DC_PN_GPIO_DATA3 603#define DC_PN_GPIO_SETBIT(sc, r) \ 604 DC_SETBIT(sc, DC_PN_GPIO, ((r) | (r << 4))) 605#define DC_PN_GPIO_CLRBIT(sc, r) \ 606 { \ 607 DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \ 608 DC_CLRBIT(sc, DC_PN_GPIO, (r)); \ 609 } 610 611/* shortcut MII access register */ 612#define DC_PN_MII_DATA 0x0000FFFF 613#define DC_PN_MII_RESERVER 0x00020000 614#define DC_PN_MII_REGADDR 0x007C0000 615#define DC_PN_MII_PHYADDR 0x0F800000 616#define DC_PN_MII_OPCODE 0x30000000 617#define DC_PN_MII_BUSY 0x80000000 618 619#define DC_PN_MIIOPCODE_READ 0x60020000 620#define DC_PN_MIIOPCODE_WRITE 0x50020000 621 622/* Internal NWAY bits */ 623#define DC_PN_NWAY_RESET 0x00000001 /* reset */ 624#define DC_PN_NWAY_PDOWN 0x00000002 /* power down */ 625#define DC_PN_NWAY_BYPASS 0x00000004 /* bypass */ 626#define DC_PN_NWAY_AUILOWCUR 0x00000008 /* AUI low current */ 627#define DC_PN_NWAY_TPEXTEND 0x00000010 /* low squelch voltage */ 628#define DC_PN_NWAY_POLARITY 0x00000020 /* 0 == on, 1 == off */ 629#define DC_PN_NWAY_TP 0x00000040 /* 1 == tp, 0 == AUI */ 630#define DC_PN_NWAY_AUIVOLT 0x00000080 /* 1 == full, 0 == half */ 631#define DC_PN_NWAY_DUPLEX 0x00000100 /* LED, 1 == full, 0 == half */ 632#define DC_PN_NWAY_LINKTEST 0x00000200 /* 0 == on, 1 == off */ 633#define DC_PN_NWAY_AUTODETECT 0x00000400 /* 1 == off, 0 == on */ 634#define DC_PN_NWAY_SPEEDSEL 0x00000800 /* LED, 0 = 10, 1 == 100 */ 635#define DC_PN_NWAY_NWAY_ENB 0x00001000 /* 0 == off, 1 == on */ 636#define DC_PN_NWAY_CAP10HDX 0x00002000 637#define DC_PN_NWAY_CAP10FDX 0x00004000 638#define DC_PN_NWAY_CAP100FDX 0x00008000 639#define DC_PN_NWAY_CAP100HDX 0x00010000 640#define DC_PN_NWAY_CAP100T4 0x00020000 641#define DC_PN_NWAY_ANEGRESTART 0x02000000 /* resets when aneg done */ 642#define DC_PN_NWAY_REMFAULT 0x04000000 643#define DC_PN_NWAY_LPAR10HDX 0x08000000 644#define DC_PN_NWAY_LPAR10FDX 0x10000000 645#define DC_PN_NWAY_LPAR100FDX 0x20000000 646#define DC_PN_NWAY_LPAR100HDX 0x40000000 647#define DC_PN_NWAY_LPAR100T4 0x80000000 648 649/* End of PNIC specific registers */ 650 651struct dc_softc { 652 struct arpcom arpcom; /* interface info */ 653 bus_space_handle_t dc_bhandle; /* bus space handle */ 654 bus_space_tag_t dc_btag; /* bus space tag */ 655 void *dc_intrhand; 656 struct resource *dc_irq; 657 struct resource *dc_res; 658 struct dc_type *dc_info; /* adapter info */ 659 device_t dc_miibus; 660 u_int8_t dc_unit; /* interface number */ 661 u_int8_t dc_type; 662 u_int8_t dc_pmode; 663 u_int8_t dc_link; 664 u_int8_t dc_cachesize; 665 int dc_pnic_rx_bug_save; 666 unsigned char *dc_pnic_rx_buf; 667 int dc_if_flags; 668 int dc_if_media; 669 u_int32_t dc_flags; 670 u_int32_t dc_txthresh; 671 u_int8_t dc_srom[1024]; 672 struct dc_mediainfo *dc_mi; 673 struct dc_list_data *dc_ldata; 674 struct dc_chain_data dc_cdata; 675 struct callout_handle dc_stat_ch; 676#ifdef SRM_MEDIA 677 int dc_srm_media; 678#endif 679}; 680 681#define DC_TX_POLL 0x00000001 682#define DC_TX_COALESCE 0x00000002 683#define DC_TX_ADMTEK_WAR 0x00000004 684#define DC_TX_USE_TX_INTR 0x00000008 685#define DC_RX_FILTER_TULIP 0x00000010 686#define DC_TX_INTR_FIRSTFRAG 0x00000020 687#define DC_PNIC_RX_BUG_WAR 0x00000040 688#define DC_TX_FIXED_RING 0x00000080 689#define DC_TX_STORENFWD 0x00000100 690#define DC_REDUCED_MII_POLL 0x00000200 691#define DC_TX_INTR_ALWAYS 0x00000400 692#define DC_21143_NWAY 0x00000800 693#define DC_128BIT_HASH 0x00001000 694#define DC_64BIT_HASH 0x00002000 695#define DC_TULIP_LEDS 0x00004000 696#define DC_TX_ONE 0x00008000 697 698/* 699 * register space access macros 700 */ 701#define CSR_WRITE_4(sc, reg, val) \ 702 bus_space_write_4(sc->dc_btag, sc->dc_bhandle, reg, val) 703 704#define CSR_READ_4(sc, reg) \ 705 bus_space_read_4(sc->dc_btag, sc->dc_bhandle, reg) 706 707#define DC_TIMEOUT 1000 708#define ETHER_ALIGN 2 709 710/* 711 * General constants that are fun to know. 712 */ 713 714/* 715 * DEC PCI vendor ID 716 */ 717#define DC_VENDORID_DEC 0x1011 718 719/* 720 * DEC/Intel 21143 PCI device ID 721 */ 722#define DC_DEVICEID_21143 0x0019 723 724/* 725 * Macronix PCI vendor ID 726 */ 727#define DC_VENDORID_MX 0x10D9 728 729/* 730 * Macronix PMAC device IDs. 731 */ 732#define DC_DEVICEID_98713 0x0512 733#define DC_DEVICEID_987x5 0x0531 734#define DC_DEVICEID_98727 0x0532 735#define DC_DEVICEID_98732 0x0532 736 737/* Macronix PCI revision codes. */ 738#define DC_REVISION_98713 0x00 739#define DC_REVISION_98713A 0x10 740#define DC_REVISION_98715 0x20 741#define DC_REVISION_98715AEC_C 0x25 742#define DC_REVISION_98725 0x30 743 744/* 745 * Compex PCI vendor ID. 746 */ 747#define DC_VENDORID_CP 0x11F6 748 749/* 750 * Compex PMAC PCI device IDs. 751 */ 752#define DC_DEVICEID_98713_CP 0x9881 753 754/* 755 * Lite-On PNIC PCI vendor ID 756 */ 757#define DC_VENDORID_LO 0x11AD 758 759/* 760 * 82c168/82c169 PNIC device IDs. Both chips have the same device 761 * ID but different revisions. Revision 0x10 is the 82c168, and 762 * 0x20 is the 82c169. 763 */ 764#define DC_DEVICEID_82C168 0x0002 765 766#define DC_REVISION_82C168 0x10 767#define DC_REVISION_82C169 0x20 768 769/* 770 * Lite-On PNIC II device ID. Note: this is actually a Macronix 98715A 771 * with wake on lan/magic packet support. 772 */ 773#define DC_DEVICEID_82C115 0xc115 774 775/* 776 * Davicom vendor ID. 777 */ 778#define DC_VENDORID_DAVICOM 0x1282 779 780/* 781 * Davicom device IDs. 782 */ 783#define DC_DEVICEID_DM9100 0x9100 784#define DC_DEVICEID_DM9102 0x9102 785 786/* 787 * The DM9102A has the same PCI device ID as the DM9102, 788 * but a higher revision code. 789 */ 790#define DC_REVISION_DM9102 0x10 791#define DC_REVISION_DM9102A 0x30 792 793/* 794 * ADMtek vendor ID. 795 */ 796#define DC_VENDORID_ADMTEK 0x1317 797 798/* 799 * ADMtek device IDs. 800 */ 801#define DC_DEVICEID_AL981 0x0981 802#define DC_DEVICEID_AN985 0x0985 803 804/* 805 * ASIX vendor ID. 806 */ 807#define DC_VENDORID_ASIX 0x125B 808 809/* 810 * ASIX device IDs. 811 */ 812#define DC_DEVICEID_AX88140A 0x1400 813 814/* 815 * The ASIX AX88140 and ASIX AX88141 have the same vendor and 816 * device IDs but different revision values. 817 */ 818#define DC_REVISION_88140 0x00 819#define DC_REVISION_88141 0x10 820 821/* 822 * Accton vendor ID. 823 */ 824#define DC_VENDORID_ACCTON 0x1113 825 826/* 827 * Accton device IDs. 828 */ 829#define DC_DEVICEID_EN1217 0x1217 830 831/* 832 * PCI low memory base and low I/O base register, and 833 * other PCI registers. 834 */ 835 836#define DC_PCI_CFID 0x00 /* Id */ 837#define DC_PCI_CFCS 0x04 /* Command and status */ 838#define DC_PCI_CFRV 0x08 /* Revision */ 839#define DC_PCI_CFLT 0x0C /* Latency timer */ 840#define DC_PCI_CFBIO 0x10 /* Base I/O address */ 841#define DC_PCI_CFBMA 0x14 /* Base memory address */ 842#define DC_PCI_CCIS 0x28 /* Card info struct */ 843#define DC_PCI_CSID 0x2C /* Subsystem ID */ 844#define DC_PCI_CBER 0x30 /* Expansion ROM base address */ 845#define DC_PCI_CCAP 0x34 /* Caps pointer - PD/TD chip only */ 846#define DC_PCI_CFIT 0x3C /* Interrupt */ 847#define DC_PCI_CFDD 0x40 /* Device and driver area */ 848#define DC_PCI_CWUA0 0x44 /* Wake-Up LAN addr 0 */ 849#define DC_PCI_CWUA1 0x48 /* Wake-Up LAN addr 1 */ 850#define DC_PCI_SOP0 0x4C /* SecureON passwd 0 */ 851#define DC_PCI_SOP1 0x50 /* SecureON passwd 1 */ 852#define DC_PCI_CWUC 0x54 /* Configuration Wake-Up cmd */ 853#define DC_PCI_CCID 0xDC /* Capability ID - PD/TD only */ 854#define DC_PCI_CPMC 0xE0 /* Pwrmgmt ctl & sts - PD/TD only */ 855 856/* PCI ID register */ 857#define DC_CFID_VENDOR 0x0000FFFF 858#define DC_CFID_DEVICE 0xFFFF0000 859 860/* PCI command/status register */ 861#define DC_CFCS_IOSPACE 0x00000001 /* I/O space enable */ 862#define DC_CFCS_MEMSPACE 0x00000002 /* memory space enable */ 863#define DC_CFCS_BUSMASTER 0x00000004 /* bus master enable */ 864#define DC_CFCS_MWI_ENB 0x00000008 /* mem write and inval enable */ 865#define DC_CFCS_PARITYERR_ENB 0x00000020 /* parity error enable */ 866#define DC_CFCS_SYSERR_ENB 0x00000080 /* system error enable */ 867#define DC_CFCS_NEWCAPS 0x00100000 /* new capabilities */ 868#define DC_CFCS_FAST_B2B 0x00800000 /* fast back-to-back capable */ 869#define DC_CFCS_DATAPARITY 0x01000000 /* Parity error report */ 870#define DC_CFCS_DEVSELTIM 0x06000000 /* devsel timing */ 871#define DC_CFCS_TGTABRT 0x10000000 /* received target abort */ 872#define DC_CFCS_MASTERABRT 0x20000000 /* received master abort */ 873#define DC_CFCS_SYSERR 0x40000000 /* asserted system error */ 874#define DC_CFCS_PARITYERR 0x80000000 /* asserted parity error */ 875 876/* PCI revision register */ 877#define DC_CFRV_STEPPING 0x0000000F 878#define DC_CFRV_REVISION 0x000000F0 879#define DC_CFRV_SUBCLASS 0x00FF0000 880#define DC_CFRV_BASECLASS 0xFF000000 881 882#define DC_21143_PB_REV 0x00000030 883#define DC_21143_TB_REV 0x00000030 884#define DC_21143_PC_REV 0x00000030 885#define DC_21143_TC_REV 0x00000030 886#define DC_21143_PD_REV 0x00000041 887#define DC_21143_TD_REV 0x00000041 888 889/* PCI latency timer register */ 890#define DC_CFLT_CACHELINESIZE 0x000000FF 891#define DC_CFLT_LATENCYTIMER 0x0000FF00 892 893/* PCI subsystem ID register */ 894#define DC_CSID_VENDOR 0x0000FFFF 895#define DC_CSID_DEVICE 0xFFFF0000 896 897/* PCI cababilities pointer */ 898#define DC_CCAP_OFFSET 0x000000FF 899 900/* PCI interrupt config register */ 901#define DC_CFIT_INTLINE 0x000000FF 902#define DC_CFIT_INTPIN 0x0000FF00 903#define DC_CFIT_MIN_GNT 0x00FF0000 904#define DC_CFIT_MAX_LAT 0xFF000000 905 906/* PCI capability register */ 907#define DC_CCID_CAPID 0x000000FF 908#define DC_CCID_NEXTPTR 0x0000FF00 909#define DC_CCID_PM_VERS 0x00070000 910#define DC_CCID_PME_CLK 0x00080000 911#define DC_CCID_DVSPEC_INT 0x00200000 912#define DC_CCID_STATE_D1 0x02000000 913#define DC_CCID_STATE_D2 0x04000000 914#define DC_CCID_PME_D0 0x08000000 915#define DC_CCID_PME_D1 0x10000000 916#define DC_CCID_PME_D2 0x20000000 917#define DC_CCID_PME_D3HOT 0x40000000 918#define DC_CCID_PME_D3COLD 0x80000000 919 920/* PCI power management control/status register */ 921#define DC_CPMC_STATE 0x00000003 922#define DC_CPMC_PME_ENB 0x00000100 923#define DC_CPMC_PME_STS 0x00008000 924 925#define DC_PSTATE_D0 0x0 926#define DC_PSTATE_D1 0x1 927#define DC_PSTATE_D2 0x2 928#define DC_PSTATE_D3 0x3 929 930/* Device specific region */ 931/* Configuration and driver area */ 932#define DC_CFDD_DRVUSE 0x0000FFFF 933#define DC_CFDD_SNOOZE_MODE 0x40000000 934#define DC_CFDD_SLEEP_MODE 0x80000000 935 936/* Configuration wake-up command register */ 937#define DC_CWUC_MUST_BE_ZERO 0x00000001 938#define DC_CWUC_SECUREON_ENB 0x00000002 939#define DC_CWUC_FORCE_WUL 0x00000004 940#define DC_CWUC_BNC_ABILITY 0x00000008 941#define DC_CWUC_AUI_ABILITY 0x00000010 942#define DC_CWUC_TP10_ABILITY 0x00000020 943#define DC_CWUC_MII_ABILITY 0x00000040 944#define DC_CWUC_SYM_ABILITY 0x00000080 945#define DC_CWUC_LOCK 0x00000100 946 947/* 948 * SROM nonsense. 949 */ 950 951#define DC_IB_CTLRCNT 0x13 952#define DC_IB_LEAF0_CNUM 0x1A 953#define DC_IB_LEAF0_OFFSET 0x1B 954 955struct dc_info_leaf { 956 u_int16_t dc_conntype; 957 u_int8_t dc_blkcnt; 958 u_int8_t dc_rsvd; 959 u_int16_t dc_infoblk; 960}; 961 962#define DC_CTYPE_10BT 0x0000 963#define DC_CTYPE_10BT_NWAY 0x0100 964#define DC_CTYPE_10BT_FDX 0x0204 965#define DC_CTYPE_10B2 0x0001 966#define DC_CTYPE_10B5 0x0002 967#define DC_CTYPE_100BT 0x0003 968#define DC_CTYPE_100BT_FDX 0x0205 969#define DC_CTYPE_100T4 0x0006 970#define DC_CTYPE_100FX 0x0007 971#define DC_CTYPE_100FX_FDX 0x0208 972#define DC_CTYPE_MII_10BT 0x0009 973#define DC_CTYPE_MII_10BT_FDX 0x020A 974#define DC_CTYPE_MII_100BT 0x000D 975#define DC_CTYPE_MII_100BT_FDX 0x020E 976#define DC_CTYPE_MII_100T4 0x000F 977#define DC_CTYPE_MII_100FX 0x0010 978#define DC_CTYPE_MII_100FX_FDX 0x0211 979#define DC_CTYPE_DYN_PUP_AUTOSENSE 0x0800 980#define DC_CTYPE_PUP_AUTOSENSe 0x8800 981#define DC_CTYPE_NOMEDIA 0xFFFF 982 983#define DC_EBLOCK_SIA 0x0002 984#define DC_EBLOCK_MII 0x0003 985#define DC_EBLOCK_SYM 0x0004 986#define DC_EBLOCK_RESET 0x0005 987#define DC_EBLOCK_PHY_SHUTDOWN 0x0006 988 989struct dc_leaf_hdr { 990 u_int16_t dc_mtype; 991 u_int8_t dc_mcnt; 992 u_int8_t dc_rsvd; 993}; 994 995struct dc_eblock_hdr { 996 u_int8_t dc_len; 997 u_int8_t dc_type; 998}; 999 1000struct dc_eblock_sia { 1001 struct dc_eblock_hdr dc_sia_hdr; 1002 u_int8_t dc_sia_code; 1003 u_int8_t dc_sia_mediaspec[6]; /* CSR13, CSR14, CSR15 */ 1004 u_int8_t dc_sia_gpio_ctl[2]; 1005 u_int8_t dc_sia_gpio_dat[2]; 1006}; 1007 1008#define DC_SIA_CODE_10BT 0x00 1009#define DC_SIA_CODE_10B2 0x01 1010#define DC_SIA_CODE_10B5 0x02 1011#define DC_SIA_CODE_10BT_FDX 0x04 1012#define DC_SIA_CODE_EXT 0x40 1013 1014/* 1015 * Note that the first word in the gpr and reset 1016 * sequences is always a control word. 1017 */ 1018struct dc_eblock_mii { 1019 struct dc_eblock_hdr dc_mii_hdr; 1020 u_int8_t dc_mii_phynum; 1021 u_int8_t dc_gpr_len; 1022/* u_int16_t dc_gpr_dat[n]; */ 1023/* u_int8_t dc_reset_len; */ 1024/* u_int16_t dc_reset_dat[n]; */ 1025/* There are other fields after these, but we don't 1026 * care about them since they can be determined by looking 1027 * at the PHY. 1028 */ 1029}; 1030 1031struct dc_eblock_sym { 1032 struct dc_eblock_hdr dc_sym_hdr; 1033 u_int8_t dc_sym_code; 1034 u_int8_t dc_sym_gpio_ctl[2]; 1035 u_int8_t dc_sym_gpio_dat[2]; 1036 u_int8_t dc_sym_cmd[2]; 1037}; 1038 1039#define DC_SYM_CODE_100BT 0x03 1040#define DC_SYM_CODE_100BT_FDX 0x05 1041#define DC_SYM_CODE_100T4 0x06 1042#define DC_SYM_CODE_100FX 0x07 1043#define DC_SYM_CODE_100FX_FDX 0x08 1044 1045struct dc_eblock_reset { 1046 struct dc_eblock_hdr dc_reset_hdr; 1047 u_int8_t dc_reset_len; 1048/* u_int16_t dc_reset_dat[n]; */ 1049}; 1050 1051#ifdef __alpha__ 1052#undef vtophys 1053#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 1054#endif 1055