1139749Simp/*- 2126177Srik * Hitachi HD64570 serial communications adaptor registers. 3126177Srik * 4126177Srik * Copyright (C) 1996 Cronyx Engineering. 5126177Srik * Author: Serge Vakulenko, <vak@cronyx.ru> 6126177Srik * 7126177Srik * This software is distributed with NO WARRANTIES, not even the implied 8126177Srik * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 9126177Srik * 10126177Srik * Authors grant any other persons or organisations permission to use 11126177Srik * or modify this software as long as this message is kept with the software, 12126177Srik * all derivative works or modified versions. 13126177Srik * 14126177Srik * Cronyx Id: hdc64570.h,v 1.1.2.2 2003/11/12 17:31:21 rik Exp $ 15126177Srik * $FreeBSD: releng/10.2/sys/dev/ctau/hdc64570.h 139749 2005-01-06 01:43:34Z imp $ 16126177Srik */ 17126177Srik 18126177Srik/* 19126177Srik * Low power mode control register. 20126177Srik */ 21126177Srik#define HD_LPR 0x00 /* low power register */ 22126177Srik 23126177Srik/* 24126177Srik * Interrupt control registers. 25126177Srik */ 26126177Srik#define HD_IVR 0x1a /* interrupt vector register */ 27126177Srik#define HD_IMVR 0x1c /* interrupt modified vector register */ 28126177Srik#define HD_ITCR 0x18 /* interrupt control register */ 29126177Srik#define HD_ISR0 0x10 /* interrupt status register 0, ro */ 30126177Srik#define HD_ISR1 0x11 /* interrupt status register 1, ro */ 31126177Srik#define HD_ISR2 0x12 /* interrupt status register 2, ro */ 32126177Srik#define HD_IER0 0x14 /* interrupt enable register 0 */ 33126177Srik#define HD_IER1 0x15 /* interrupt enable register 1 */ 34126177Srik#define HD_IER2 0x16 /* interrupt enable register 2 */ 35126177Srik 36126177Srik/* 37126177Srik * Multiprotocol serial communication interface registers. 38126177Srik */ 39126177Srik#define HD_MD0_0 0x2e /* mode register 0 chan 0 */ 40126177Srik#define HD_MD0_1 0x4e /* mode register 0 chan 1 */ 41126177Srik#define HD_MD1_0 0x2f /* mode register 1 chan 0 */ 42126177Srik#define HD_MD1_1 0x4f /* mode register 1 chan 1 */ 43126177Srik#define HD_MD2_0 0x30 /* mode register 2 chan 0 */ 44126177Srik#define HD_MD2_1 0x50 /* mode register 2 chan 1 */ 45126177Srik#define HD_CTL_0 0x31 /* control register chan 0 */ 46126177Srik#define HD_CTL_1 0x51 /* control register chan 1 */ 47126177Srik#define HD_RXS_0 0x36 /* RX clock source register chan 0 */ 48126177Srik#define HD_RXS_1 0x56 /* RX clock source register chan 1 */ 49126177Srik#define HD_TXS_0 0x37 /* TX clock source register chan 0 */ 50126177Srik#define HD_TXS_1 0x57 /* TX clock source register chan 1 */ 51126177Srik#define HD_TMC_0 0x35 /* time constant register chan 0 */ 52126177Srik#define HD_TMC_1 0x55 /* time constant register chan 1 */ 53126177Srik#define HD_CMD_0 0x2c /* command register chan 0, wo */ 54126177Srik#define HD_CMD_1 0x4c /* command register chan 1, wo */ 55126177Srik#define HD_ST0_0 0x22 /* status register 0 chan 0, ro */ 56126177Srik#define HD_ST0_1 0x42 /* status register 0 chan 1, ro */ 57126177Srik#define HD_ST1_0 0x23 /* status register 1 chan 0 */ 58126177Srik#define HD_ST1_1 0x43 /* status register 1 chan 1 */ 59126177Srik#define HD_ST2_0 0x24 /* status register 2 chan 0 */ 60126177Srik#define HD_ST2_1 0x44 /* status register 2 chan 1 */ 61126177Srik#define HD_ST3_0 0x25 /* status register 3 chan 0, ro */ 62126177Srik#define HD_ST3_1 0x45 /* status register 3 chan 1, ro */ 63126177Srik#define HD_FST_0 0x26 /* frame status register chan 0 */ 64126177Srik#define HD_FST_1 0x46 /* frame status register chan 1 */ 65126177Srik#define HD_IE0_0 0x28 /* interrupt enable register 0 chan 0 */ 66126177Srik#define HD_IE0_1 0x48 /* interrupt enable register 0 chan 1 */ 67126177Srik#define HD_IE1_0 0x29 /* interrupt enable register 1 chan 0 */ 68126177Srik#define HD_IE1_1 0x49 /* interrupt enable register 1 chan 1 */ 69126177Srik#define HD_IE2_0 0x2a /* interrupt enable register 2 chan 0 */ 70126177Srik#define HD_IE2_1 0x4a /* interrupt enable register 2 chan 1 */ 71126177Srik#define HD_FIE_0 0x2b /* frame interrupt enable register chan 0 */ 72126177Srik#define HD_FIE_1 0x4b /* frame interrupt enable register chan 1 */ 73126177Srik#define HD_SA0_0 0x32 /* sync/address register 0 chan 0 */ 74126177Srik#define HD_SA0_1 0x52 /* sync/address register 0 chan 1 */ 75126177Srik#define HD_SA1_0 0x33 /* sync/address register 1 chan 0 */ 76126177Srik#define HD_SA1_1 0x53 /* sync/address register 1 chan 1 */ 77126177Srik#define HD_IDL_0 0x34 /* idle pattern register chan 0 */ 78126177Srik#define HD_IDL_1 0x54 /* idle pattern register chan 1 */ 79126177Srik#define HD_TRB_0 0x20 /* TX/RX buffer register chan 0 */ 80126177Srik#define HD_TRB_1 0x40 /* TX/RX buffer register chan 1 */ 81126177Srik#define HD_RRC_0 0x3a /* RX ready control register chan 0 */ 82126177Srik#define HD_RRC_1 0x5a /* RX ready control register chan 1 */ 83126177Srik#define HD_TRC0_0 0x38 /* TX ready control register 0 chan 0 */ 84126177Srik#define HD_TRC0_1 0x58 /* TX ready control register 0 chan 1 */ 85126177Srik#define HD_TRC1_0 0x39 /* TX ready control register 1 chan 0 */ 86126177Srik#define HD_TRC1_1 0x59 /* TX ready control register 1 chan 1 */ 87126177Srik#define HD_CST_0 0x3c /* current status register chan 0 */ 88126177Srik#define HD_CST_1 0x5c /* current status register chan 1 */ 89126177Srik 90126177Srik/* 91126177Srik * DMA controller registers. 92126177Srik */ 93126177Srik#define HD_PCR 0x08 /* DMA priority control register */ 94126177Srik#define HD_DMER 0x09 /* DMA master enable register */ 95126177Srik 96126177Srik#define HD_DAR_0R 0x80 /* destination address chan 0rx */ 97126177Srik#define HD_DAR_0T 0xa0 /* destination address chan 0tx */ 98126177Srik#define HD_DAR_1R 0xc0 /* destination address chan 1rx */ 99126177Srik#define HD_DAR_1T 0xe0 /* destination address chan 1tx */ 100126177Srik#define HD_DARB_0R 0x82 /* destination address B chan 0rx */ 101126177Srik#define HD_DARB_0T 0xa2 /* destination address B chan 0tx */ 102126177Srik#define HD_DARB_1R 0xc2 /* destination address B chan 1rx */ 103126177Srik#define HD_DARB_1T 0xe2 /* destination address B chan 1tx */ 104126177Srik#define HD_SAR_0R 0x84 /* source address chan 0rx */ 105126177Srik#define HD_SAR_0T 0xa4 /* source address chan 0tx */ 106126177Srik#define HD_SAR_1R 0xc4 /* source address chan 1rx */ 107126177Srik#define HD_SAR_1T 0xe4 /* source address chan 1tx */ 108126177Srik#define HD_SARB_0R 0x86 /* source address B chan 0rx */ 109126177Srik#define HD_SARB_0T 0xa6 /* source address B chan 0tx */ 110126177Srik#define HD_SARB_1R 0xc6 /* source address B chan 1rx */ 111126177Srik#define HD_SARB_1T 0xe6 /* source address B chan 1tx */ 112126177Srik#define HD_CDA_0R 0x88 /* current descriptor address chan 0rx */ 113126177Srik#define HD_CDA_0T 0xa8 /* current descriptor address chan 0tx */ 114126177Srik#define HD_CDA_1R 0xc8 /* current descriptor address chan 1rx */ 115126177Srik#define HD_CDA_1T 0xe8 /* current descriptor address chan 1tx */ 116126177Srik#define HD_EDA_0R 0x8a /* error descriptor address chan 0rx */ 117126177Srik#define HD_EDA_0T 0xaa /* error descriptor address chan 0tx */ 118126177Srik#define HD_EDA_1R 0xca /* error descriptor address chan 1rx */ 119126177Srik#define HD_EDA_1T 0xea /* error descriptor address chan 1tx */ 120126177Srik#define HD_BFL_0R 0x8c /* receive buffer length chan 0rx */ 121126177Srik#define HD_BFL_1R 0xcc /* receive buffer length chan 1rx */ 122126177Srik#define HD_BCR_0R 0x8e /* byte count register chan 0rx */ 123126177Srik#define HD_BCR_0T 0xae /* byte count register chan 0tx */ 124126177Srik#define HD_BCR_1R 0xce /* byte count register chan 1rx */ 125126177Srik#define HD_BCR_1T 0xee /* byte count register chan 1tx */ 126126177Srik#define HD_DSR_0R 0x90 /* DMA status register chan 0rx */ 127126177Srik#define HD_DSR_0T 0xb0 /* DMA status register chan 0tx */ 128126177Srik#define HD_DSR_1R 0xd0 /* DMA status register chan 1rx */ 129126177Srik#define HD_DSR_1T 0xf0 /* DMA status register chan 1tx */ 130126177Srik#define HD_DMR_0R 0x91 /* DMA mode register chan 0rx */ 131126177Srik#define HD_DMR_0T 0xb1 /* DMA mode register chan 0tx */ 132126177Srik#define HD_DMR_1R 0xd1 /* DMA mode register chan 1rx */ 133126177Srik#define HD_DMR_1T 0xf1 /* DMA mode register chan 1tx */ 134126177Srik#define HD_FCT_0R 0x93 /* end-of-frame intr counter chan 0rx, ro */ 135126177Srik#define HD_FCT_0T 0xb3 /* end-of-frame intr counter chan 0tx, ro */ 136126177Srik#define HD_FCT_1R 0xd3 /* end-of-frame intr counter chan 1rx, ro */ 137126177Srik#define HD_FCT_1T 0xf3 /* end-of-frame intr counter chan 1tx, ro */ 138126177Srik#define HD_DIR_0R 0x94 /* DMA interrupt enable register chan 0rx */ 139126177Srik#define HD_DIR_0T 0xb4 /* DMA interrupt enable register chan 0tx */ 140126177Srik#define HD_DIR_1R 0xd4 /* DMA interrupt enable register chan 1rx */ 141126177Srik#define HD_DIR_1T 0xf4 /* DMA interrupt enable register chan 1tx */ 142126177Srik#define HD_DCR_0R 0x95 /* DMA command register chan 0rx, wo */ 143126177Srik#define HD_DCR_0T 0xb5 /* DMA command register chan 0tx, wo */ 144126177Srik#define HD_DCR_1R 0xd5 /* DMA command register chan 1rx, wo */ 145126177Srik#define HD_DCR_1T 0xf5 /* DMA command register chan 1tx, wo */ 146126177Srik 147126177Srik/* 148126177Srik * Timer registers. 149126177Srik */ 150126177Srik#define HD_TCNT_0R 0x60 /* timer up counter chan 0rx */ 151126177Srik#define HD_TCNT_0T 0x68 /* timer up counter chan 0tx */ 152126177Srik#define HD_TCNT_1R 0x70 /* timer up counter chan 1rx */ 153126177Srik#define HD_TCNT_1T 0x78 /* timer up counter chan 1tx */ 154126177Srik#define HD_TCONR_0R 0x62 /* timer constant register chan 0rx, wo */ 155126177Srik#define HD_TCONR_0T 0x6a /* timer constant register chan 0tx, wo */ 156126177Srik#define HD_TCONR_1R 0x72 /* timer constant register chan 1rx, wo */ 157126177Srik#define HD_TCONR_1T 0x7a /* timer constant register chan 1tx, wo */ 158126177Srik#define HD_TCSR_0R 0x64 /* timer control/status register chan 0rx */ 159126177Srik#define HD_TCSR_0T 0x6c /* timer control/status register chan 0tx */ 160126177Srik#define HD_TCSR_1R 0x74 /* timer control/status register chan 1rx */ 161126177Srik#define HD_TCSR_1T 0x7c /* timer control/status register chan 1tx */ 162126177Srik#define HD_TEPR_0R 0x65 /* timer expand prescale register chan 0rx */ 163126177Srik#define HD_TEPR_0T 0x6d /* timer expand prescale register chan 0tx */ 164126177Srik#define HD_TEPR_1R 0x75 /* timer expand prescale register chan 1rx */ 165126177Srik#define HD_TEPR_1T 0x7d /* timer expand prescale register chan 1tx */ 166126177Srik 167126177Srik/* 168126177Srik * Wait controller registers. 169126177Srik */ 170126177Srik#define HD_PABR0 0x02 /* physical address boundary register 0 */ 171126177Srik#define HD_PABR1 0x03 /* physical address boundary register 1 */ 172126177Srik#define HD_WCRL 0x04 /* wait control register L */ 173126177Srik#define HD_WCRM 0x05 /* wait control register M */ 174126177Srik#define HD_WCRH 0x06 /* wait control register H */ 175126177Srik 176126177Srik/* 177126177Srik * Interrupt modified vector register (IMVR) bits. 178126177Srik */ 179126177Srik#define IMVR_CHAN1 040 /* channel 1 vector bit */ 180126177Srik#define IMVR_VECT_MASK 037 /* interrupt reason mask */ 181126177Srik 182126177Srik#define IMVR_RX_RDY 004 /* receive buffer ready */ 183126177Srik#define IMVR_RX_INT 010 /* receive status */ 184126177Srik#define IMVR_RX_DMERR 024 /* receive DMA error */ 185126177Srik#define IMVR_RX_DMOK 026 /* receive DMA normal end */ 186126177Srik#define IMVR_RX_TIMER 034 /* timer 0/2 count match */ 187126177Srik 188126177Srik#define IMVR_TX_RDY 006 /* transmit buffer ready */ 189126177Srik#define IMVR_TX_INT 012 /* transmit status */ 190126177Srik#define IMVR_TX_DMERR 030 /* transmit DMA error */ 191126177Srik#define IMVR_TX_DMOK 032 /* transmit DMA normal end */ 192126177Srik#define IMVR_TX_TIMER 036 /* timer 1/3 count match */ 193126177Srik 194126177Srik/* 195126177Srik * Interrupt control register (ITCR) bits. 196126177Srik */ 197126177Srik#define ITCR_PRIO_DMAC 0x80 /* DMA priority higher than MSCI */ 198126177Srik#define ITCR_CYCLE_VOID 0x00 /* non-acknowledge cycle */ 199126177Srik#define ITCR_CYCLE_SINGLE 0x20 /* single acknowledge cycle */ 200126177Srik#define ITCR_CYCLE_DOUBLE 0x40 /* double acknowledge cycle */ 201126177Srik#define ITCR_VECT_MOD 0x10 /* interrupt modified vector flag */ 202126177Srik 203126177Srik/* 204126177Srik * Interrupt status register 0 (ISR0) bits. 205126177Srik */ 206126177Srik#define ISR0_RX_RDY_0 0x01 /* channel 0 receiver ready */ 207126177Srik#define ISR0_TX_RDY_0 0x02 /* channel 0 transmitter ready */ 208126177Srik#define ISR0_RX_INT_0 0x04 /* channel 0 receiver status */ 209126177Srik#define ISR0_TX_INT_0 0x08 /* channel 0 transmitter status */ 210126177Srik#define ISR0_RX_RDY_1 0x10 /* channel 1 receiver ready */ 211126177Srik#define ISR0_TX_RDY_1 0x20 /* channel 1 transmitter ready */ 212126177Srik#define ISR0_RX_INT_1 0x40 /* channel 1 receiver status */ 213126177Srik#define ISR0_TX_INT_1 0x80 /* channel 1 transmitter status */ 214126177Srik 215126177Srik/* 216126177Srik * Interrupt status register 1 (ISR1) bits. 217126177Srik */ 218126177Srik#define ISR1_RX_DMERR_0 0x01 /* channel 0 receive DMA error */ 219126177Srik#define ISR1_RX_DMOK_0 0x02 /* channel 0 receive DMA finished */ 220126177Srik#define ISR1_TX_DMERR_0 0x04 /* channel 0 transmit DMA error */ 221126177Srik#define ISR1_TX_DMOK_0 0x08 /* channel 0 transmit DMA finished */ 222126177Srik#define ISR1_RX_DMERR_1 0x10 /* channel 1 receive DMA error */ 223126177Srik#define ISR1_RX_DMOK_1 0x20 /* channel 1 receive DMA finished */ 224126177Srik#define ISR1_TX_DMERR_1 0x40 /* channel 1 transmit DMA error */ 225126177Srik#define ISR1_TX_DMOK_1 0x80 /* channel 1 transmit DMA finished */ 226126177Srik 227126177Srik/* 228126177Srik * Interrupt status register 2 (ISR2) bits. 229126177Srik */ 230126177Srik#define ISR2_RX_TIMER_0 0x10 /* channel 0 receive timer */ 231126177Srik#define ISR2_TX_TIMER_0 0x20 /* channel 0 transmit timer */ 232126177Srik#define ISR2_RX_TIMER_1 0x40 /* channel 1 receive timer */ 233126177Srik#define ISR2_TX_TIMER_1 0x80 /* channel 1 transmit timer */ 234126177Srik 235126177Srik/* 236126177Srik * Interrupt enable register 0 (IER0) bits. 237126177Srik */ 238126177Srik#define IER0_RX_RDYE_0 0x01 /* channel 0 receiver ready enable */ 239126177Srik#define IER0_TX_RDYE_0 0x02 /* channel 0 transmitter ready enable */ 240126177Srik#define IER0_RX_INTE_0 0x04 /* channel 0 receiver status enable */ 241126177Srik#define IER0_TX_INTE_0 0x08 /* channel 0 transmitter status enable */ 242126177Srik#define IER0_RX_RDYE_1 0x10 /* channel 1 receiver ready enable */ 243126177Srik#define IER0_TX_RDYE_1 0x20 /* channel 1 transmitter ready enable */ 244126177Srik#define IER0_RX_INTE_1 0x40 /* channel 1 receiver status enable */ 245126177Srik#define IER0_TX_INTE_1 0x80 /* channel 1 transmitter status enable */ 246126177Srik#define IER0_MASK_0 0x0f /* channel 0 bits */ 247126177Srik#define IER0_MASK_1 0xf0 /* channel 1 bits */ 248126177Srik 249126177Srik/* 250126177Srik * Interrupt enable register 1 (IER1) bits. 251126177Srik */ 252126177Srik#define IER1_RX_DMERE_0 0x01 /* channel 0 receive DMA error enable */ 253126177Srik#define IER1_RX_DME_0 0x02 /* channel 0 receive DMA finished enable */ 254126177Srik#define IER1_TX_DMERE_0 0x04 /* channel 0 transmit DMA error enable */ 255126177Srik#define IER1_TX_DME_0 0x08 /* channel 0 transmit DMA finished enable */ 256126177Srik#define IER1_RX_DMERE_1 0x10 /* channel 1 receive DMA error enable */ 257126177Srik#define IER1_RX_DME_1 0x20 /* channel 1 receive DMA finished enable */ 258126177Srik#define IER1_TX_DMERE_1 0x40 /* channel 1 transmit DMA error enable */ 259126177Srik#define IER1_TX_DME_1 0x80 /* channel 1 transmit DMA finished enable */ 260126177Srik#define IER1_MASK_0 0x0f /* channel 0 bits */ 261126177Srik#define IER1_MASK_1 0xf0 /* channel 1 bits */ 262126177Srik 263126177Srik/* 264126177Srik * Interrupt enable register 2 (IER2) bits. 265126177Srik */ 266126177Srik#define IER2_RX_TME_0 0x10 /* channel 0 receive timer enable */ 267126177Srik#define IER2_TX_TME_0 0x20 /* channel 0 transmit timer enable */ 268126177Srik#define IER2_RX_TME_1 0x40 /* channel 1 receive timer enable */ 269126177Srik#define IER2_TX_TME_1 0x80 /* channel 1 transmit timer enable */ 270126177Srik#define IER2_MASK_0 0x30 /* channel 0 bits */ 271126177Srik#define IER2_MASK_1 0xc0 /* channel 1 bits */ 272126177Srik 273126177Srik/* 274126177Srik * Control register (CTL) bits. 275126177Srik */ 276126177Srik#define CTL_RTS_INV 0x01 /* RTS control bit (inverted) */ 277126177Srik#define CTL_SYNCLD 0x04 /* load SYN characters */ 278126177Srik#define CTL_BRK 0x08 /* async: send break */ 279126177Srik#define CTL_IDLE_MARK 0 /* HDLC: when idle, transmit mark */ 280126177Srik#define CTL_IDLE_PTRN 0x10 /* HDLC: when idle, transmit an idle pattern */ 281126177Srik#define CTL_UDRN_ABORT 0 /* HDLC: on underrun - abort */ 282126177Srik#define CTL_UDRN_FCS 0x20 /* HDLC: on underrun - send FCS/flag */ 283126177Srik 284126177Srik/* 285126177Srik * Command register (CMD) values. 286126177Srik */ 287126177Srik#define CMD_TX_RESET 001 /* reset: disable, clear buffer/status/BRK */ 288126177Srik#define CMD_TX_ENABLE 002 /* transmitter enable */ 289126177Srik#define CMD_TX_DISABLE 003 /* transmitter disable */ 290126177Srik#define CMD_TX_CRC_INIT 004 /* initialize CRC calculator */ 291126177Srik#define CMD_TX_EOM_CHAR 006 /* set end-of-message char */ 292126177Srik#define CMD_TX_ABORT 007 /* abort transmission (HDLC mode) */ 293126177Srik#define CMD_TX_MPON 010 /* transmit char with MP bit on (async) */ 294126177Srik#define CMD_TX_CLEAR 011 /* clear the transmit buffer */ 295126177Srik 296126177Srik#define CMD_RX_RESET 021 /* reset: disable, clear buffer/status */ 297126177Srik#define CMD_RX_ENABLE 022 /* receiver enable */ 298126177Srik#define CMD_RX_DISABLE 023 /* receiver disable */ 299126177Srik#define CMD_RX_CRC_INIT 024 /* initialize CRC calculator */ 300126177Srik#define CMD_RX_REJECT 025 /* reject current message (sync mode) */ 301126177Srik#define CMD_RX_SRCH_MP 026 /* skip all until the char witn MP bit on */ 302126177Srik 303126177Srik#define CMD_NOOP 000 /* continue current operation */ 304126177Srik#define CMD_CHAN_RESET 041 /* init registers, disable/clear RX/TX */ 305126177Srik#define CMD_SEARCH_MODE 061 /* set the ADPLL to search mode */ 306126177Srik 307126177Srik/* 308126177Srik * Status register 0 (ST0) bits. 309126177Srik */ 310126177Srik#define ST0_RX_RDY 0x01 /* receiver ready */ 311126177Srik#define ST0_TX_RDY 0x02 /* transmitter ready */ 312126177Srik#define ST0_RX_INT 0x40 /* receiver status interrupt */ 313126177Srik#define ST0_TX_INT 0x80 /* transmitter status interrupt */ 314126177Srik 315126177Srik/* 316126177Srik * Status register 1 (ST1) bits. 317126177Srik */ 318126177Srik#define ST1_CDCD 0x04 /* carrier changed */ 319126177Srik#define ST1_CCTS 0x08 /* CTS changed */ 320126177Srik#define ST1_IDL 0x40 /* transmitter idle, ro */ 321126177Srik 322126177Srik#define ST1_ASYNC_BRKE 0x01 /* break end detected */ 323126177Srik#define ST1_ASYNC_BRKD 0x02 /* break start detected */ 324126177Srik#define ST1_ASYNC_BITS "\20\1brke\2brkd\3cdcd\4ccts\7idl" 325126177Srik 326126177Srik#define ST1_HDLC_IDLD 0x01 /* idle sequence start detected */ 327126177Srik#define ST1_HDLC_ABTD 0x02 /* abort sequence start detected */ 328126177Srik#define ST1_HDLC_FLGD 0x10 /* flag detected */ 329126177Srik#define ST1_HDLC_UDRN 0x80 /* underrun detected */ 330126177Srik#define ST1_HDLC_BITS "\20\1idld\2abtd\3cdcd\4ccts\5flgd\7idl\10udrn" 331126177Srik 332126177Srik/* 333126177Srik * Status register 2 (ST2) bits. 334126177Srik */ 335126177Srik#define ST2_OVRN 0x08 /* overrun error detected */ 336126177Srik 337126177Srik#define ST2_ASYNC_FRME 0x10 /* framing error detected */ 338126177Srik#define ST2_ASYNC_PE 0x20 /* parity error detected */ 339126177Srik#define ST2_ASYNC_PMP 0x40 /* parity/MP bit = 1 */ 340126177Srik#define ST2_ASYNC_BITS "\20\4ovrn\5frme\6pe\7pmp" 341126177Srik 342126177Srik#define ST2_HDLC_CRCE 0x04 /* CRC error detected */ 343126177Srik#define ST2_HDLC_RBIT 0x10 /* residual bit frame detected */ 344126177Srik#define ST2_HDLC_ABT 0x20 /* frame with abort end detected */ 345126177Srik#define ST2_HDLC_SHRT 0x40 /* short frame detected */ 346126177Srik#define ST2_HDLC_EOM 0x80 /* receive frame end detected */ 347126177Srik#define ST2_HDLC_BITS "\20\3crce\4ovrn\5rbit\6abt\7shrt\10eom" 348126177Srik 349126177Srik/* 350126177Srik * Status register 3 (ST3) bits. 351126177Srik */ 352126177Srik#define ST3_RX_ENABLED 0x01 /* receiver is enabled */ 353126177Srik#define ST3_TX_ENABLED 0x02 /* transmitter is enabled */ 354126177Srik#define ST3_DCD_INV 0x04 /* DCD input line inverted */ 355126177Srik#define ST3_CTS_INV 0x08 /* CTS input line inverted */ 356126177Srik#define ST3_ASYNC_BITS "\20\1rx\2tx\3nodcd\4nocts" 357126177Srik 358126177Srik#define ST3_HDLC_SEARCH 0x10 /* ADPLL search mode */ 359126177Srik#define ST3_HDLC_TX 0x20 /* channel is transmitting data */ 360126177Srik#define ST3_HDLC_BITS "\20\1rx\2tx\3nodcd\4nocts\5search\6txact" 361126177Srik 362126177Srik/* 363126177Srik * Frame status register (FST) bits, HDLC mode only. 364126177Srik */ 365126177Srik#define FST_CRCE 0x04 /* CRC error detected */ 366126177Srik#define FST_OVRN 0x08 /* overrun error detected */ 367126177Srik#define FST_RBIT 0x10 /* residual bit frame detected */ 368126177Srik#define FST_ABT 0x20 /* frame with abort end detected */ 369126177Srik#define FST_SHRT 0x40 /* short frame detected */ 370126177Srik#define FST_EOM 0x80 /* frame end flag */ 371126177Srik 372126177Srik#define FST_EOT 0x01 /* end of transfer, transmit only */ 373126177Srik 374126177Srik/* 375126177Srik * Interrupt enable register 0 (IE0) bits. 376126177Srik */ 377126177Srik#define IE0_RX_RDYE 0x01 /* receiver ready interrupt enable */ 378126177Srik#define IE0_TX_RDYE 0x02 /* transmitter ready interrupt enable */ 379126177Srik#define IE0_RX_INTE 0x40 /* receiver status interrupt enable */ 380126177Srik#define IE0_TX_INTE 0x80 /* transmitter status interrupt enable */ 381126177Srik 382126177Srik/* 383126177Srik * Interrupt enable register 1 (IE1) bits. 384126177Srik */ 385126177Srik#define IE1_CDCDE 0x04 /* carrier changed */ 386126177Srik#define IE1_CCTSE 0x08 /* CTS changed */ 387126177Srik#define IE1_IDLE 0x40 /* transmitter idle, ro */ 388126177Srik 389126177Srik#define IE1_ASYNC_BRKEE 0x01 /* break end detected */ 390126177Srik#define IE1_ASYNC_BRKDE 0x02 /* break start detected */ 391126177Srik 392126177Srik#define IE1_HDLC_IDLDE 0x01 /* idle sequence start detected */ 393126177Srik#define IE1_HDLC_ABTDE 0x02 /* abort sequence start detected */ 394126177Srik#define IE1_HDLC_FLGDE 0x10 /* flag detected */ 395126177Srik#define IE1_HDLC_UDRNE 0x80 /* underrun detected */ 396126177Srik 397126177Srik/* 398126177Srik * Interrupt enable register 2 (IE2) bits. 399126177Srik */ 400126177Srik#define IE2_OVRNE 0x08 /* overrun error detected */ 401126177Srik 402126177Srik#define IE2_ASYNC_FRMEE 0x10 /* framing error detected */ 403126177Srik#define IE2_ASYNC_PEE 0x20 /* parity error detected */ 404126177Srik#define IE2_ASYNC_PMPE 0x40 /* parity/MP bit = 1 */ 405126177Srik 406126177Srik#define IE2_HDLC_CRCEE 0x04 /* CRC error detected */ 407126177Srik#define IE2_HDLC_RBITE 0x10 /* residual bit frame detected */ 408126177Srik#define IE2_HDLC_ABTE 0x20 /* frame with abort end detected */ 409126177Srik#define IE2_HDLC_SHRTE 0x40 /* short frame detected */ 410126177Srik#define IE2_HDLC_EOME 0x80 /* receive frame end detected */ 411126177Srik 412126177Srik/* 413126177Srik * Frame interrupt enable register (FIE) bits, HDLC mode only. 414126177Srik */ 415126177Srik#define FIE_EOMFE 0x80 /* receive frame end detected */ 416126177Srik 417126177Srik/* 418126177Srik * Current status register (CST0,CST1) bits. 419126177Srik * For other bits, see ST2. 420126177Srik */ 421126177Srik#define CST0_CDE 0x0001 /* data present on top of FIFO */ 422126177Srik#define CST1_CDE 0x0100 /* data present on second stage of FIFO */ 423126177Srik 424126177Srik/* 425126177Srik * Receive/transmit clock source register (RXS/TXS) bits. 426126177Srik */ 427126177Srik#define CLK_MASK 0x70 /* RXC/TXC clock input mask */ 428126177Srik#define CLK_LINE 0x00 /* RXC/TXC line input */ 429126177Srik#define CLK_INT 0x40 /* internal baud rate generator */ 430126177Srik 431126177Srik#define CLK_RXS_LINE_NS 0x20 /* RXC line with noise suppression */ 432126177Srik#define CLK_RXS_DPLL_INT 0x60 /* ADPLL based on internal BRG */ 433126177Srik#define CLK_RXS_DPLL_LINE 0x70 /* ADPLL based on RXC line */ 434126177Srik 435126177Srik#define CLK_TXS_RECV 0x60 /* receive clock */ 436126177Srik 437126177Srik/* 438126177Srik * DMA status register (DSR) bits. 439126177Srik */ 440126177Srik#define DSR_DMA_DISABLE 0x00 /* disable DMA channel */ 441126177Srik#define DSR_DMA_ENABLE 0x02 /* enable DMA channel */ 442126177Srik#define DSR_DMA_CONTINUE 0x01 /* do not enable/disable DMA channel */ 443126177Srik#define DSR_CHAIN_COF 0x10 /* counter overflow */ 444126177Srik#define DSR_CHAIN_BOF 0x20 /* buffer overflow/underflow */ 445126177Srik#define DSR_CHAIN_EOM 0x40 /* frame transfer completed */ 446126177Srik#define DSR_EOT 0x80 /* transfer completed */ 447126177Srik#define DSR_BITS "\20\1cont\2enab\5cof\6bof\7eom\10eot" 448126177Srik 449126177Srik/* 450126177Srik * DMA mode register (DMR) bits. 451126177Srik */ 452126177Srik#define DMR_CHAIN_CNTE 0x02 /* enable frame interrupt counter (FCT) */ 453126177Srik#define DMR_CHAIN_NF 0x04 /* multi-frame block chain */ 454126177Srik#define DMR_TMOD 0x10 /* chained-block transfer mode */ 455126177Srik 456126177Srik/* 457126177Srik * DMA interrupt enable register (DIR) bits. 458126177Srik */ 459126177Srik#define DIR_CHAIN_COFE 0x10 /* counter overflow */ 460126177Srik#define DIR_CHAIN_BOFE 0x20 /* buffer overflow/underflow */ 461126177Srik#define DIR_CHAIN_EOME 0x40 /* frame transfer completed */ 462126177Srik#define DIR_EOTE 0x80 /* transfer completed */ 463126177Srik 464126177Srik/* 465126177Srik * DMA command register (DCR) values. 466126177Srik */ 467126177Srik#define DCR_ABORT 1 /* software abort: initialize DMA channel */ 468126177Srik#define DCR_CLEAR 2 /* clear FCT and EOM bit of DSR */ 469126177Srik 470126177Srik/* 471126177Srik * DMA master enable register (DME) bits. 472126177Srik */ 473126177Srik#define DME_ENABLE 0x80 /* enable DMA master operation */ 474126177Srik 475126177Srik/* 476126177Srik * Timer control/status register (TCSR) bits. 477126177Srik */ 478126177Srik#define TCSR_ENABLE 0x10 /* timer starts incrementing */ 479126177Srik#define TCSR_INTR 0x40 /* timer interrupt enable */ 480126177Srik#define TCSR_MATCH 0x80 /* TCNT and TCONR are equal */ 481126177Srik 482126177Srik/* 483126177Srik * Timer expand prescale register (TEPR) values. 484126177Srik */ 485126177Srik#define TEPR_1 0 /* sysclk/8 */ 486126177Srik#define TEPR_2 1 /* sysclk/8/2 */ 487126177Srik#define TEPR_4 2 /* sysclk/8/4 */ 488126177Srik#define TEPR_8 3 /* sysclk/8/8 */ 489126177Srik#define TEPR_16 4 /* sysclk/8/16 */ 490126177Srik#define TEPR_32 5 /* sysclk/8/32 */ 491126177Srik#define TEPR_64 6 /* sysclk/8/64 */ 492126177Srik#define TEPR_128 7 /* sysclk/8/128 */ 493