ds2153.h revision 139749
1139749Simp/*- 2126177Srik * Dallas DS2153, DS21x54 single-chip E1 tranceiver registers. 3126177Srik * 4126177Srik * Copyright (C) 1996 Cronyx Engineering. 5126177Srik * Author: Serge Vakulenko, <vak@cronyx.ru> 6126177Srik * 7126177Srik * This software is distributed with NO WARRANTIES, not even the implied 8126177Srik * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 9126177Srik * 10126177Srik * Authors grant any other persons or organisations permission to use 11126177Srik * or modify this software as long as this message is kept with the software, 12126177Srik * all derivative works or modified versions. 13126177Srik * 14126177Srik * Cronyx Id: ds2153.h,v 1.2.4.1 2003/11/12 17:22:33 rik Exp $ 15126177Srik * $FreeBSD: head/sys/dev/ctau/ds2153.h 139749 2005-01-06 01:43:34Z imp $ 16126177Srik */ 17126177Srik 18126177Srik/* 19126177Srik * Control and test registers 20126177Srik */ 21126177Srik#define DS_RCR1 0x10 /* rw - receive control 1 */ 22126177Srik#define DS_RCR2 0x11 /* rw - receive control 2 */ 23126177Srik#define DS_TCR1 0x12 /* rw - transmit control 1 */ 24126177Srik#define DS_TCR2 0x13 /* rw - transmit control 2 */ 25126177Srik#define DS_CCR1 0x14 /* rw - common control 1 */ 26126177Srik#define DS_CCR2 0x1a /* rw - common control 2 */ 27126177Srik#define DS_CCR3 0x1b /* rw - common control 3 */ 28126177Srik#define DS_LICR 0x18 /* rw - line interface control */ 29126177Srik#define DS_IMR1 0x16 /* rw - interrupt mask 1 */ 30126177Srik#define DS_IMR2 0x17 /* rw - interrupt mask 2 */ 31126177Srik#define DS_TEST1 0x15 /* rw - test 1 */ 32126177Srik#define DS_TEST2 0x19 /* rw - test 2 */ 33126177Srik 34126177Srik/* 35126177Srik * Status and information registers 36126177Srik */ 37126177Srik#define DS_RIR 0x08 /* r - receive information */ 38126177Srik#define DS_SSR 0x1e /* r - synchronizer status */ 39126177Srik#define DS_SR1 0x06 /* r - status 1 */ 40126177Srik#define DS_SR2 0x07 /* r - status 2 */ 41126177Srik 42126177Srik/* 43126177Srik * Error count registers 44126177Srik */ 45126177Srik#define DS_VCR1 0x00 /* r - BPV or code violation count 1 */ 46126177Srik#define DS_VCR2 0x01 /* r - BPV or code violation count 2 */ 47126177Srik#define DS_CRCCR1 0x02 /* r - CRC4 error count 1 */ 48126177Srik#define DS_CRCCR2 0x03 /* r - CRC4 error count 2 */ 49126177Srik#define DS_EBCR1 0x04 /* r - E-bit count 1 */ 50126177Srik#define DS_EBCR2 0x05 /* r - E-bit count 2 */ 51126177Srik#define DS_FASCR1 0x02 /* r - FAS error count 1 */ 52126177Srik#define DS_FASCR2 0x04 /* r - FAS error count 2 */ 53126177Srik 54126177Srik/* 55126177Srik * Signaling registers 56126177Srik */ 57126177Srik#define DS_RS 0x30 /* r - receive signaling 1..16 */ 58126177Srik#define DS_TS 0x40 /* rw - transmit signaling 1..16 */ 59126177Srik 60126177Srik/* 61126177Srik * Transmit idle registers 62126177Srik */ 63126177Srik#define DS_TIR 0x26 /* rw - transmit idle 1..4 */ 64126177Srik#define DS_TIDR 0x2a /* rw - transmit idle definition */ 65126177Srik 66126177Srik/* 67126177Srik * Clock blocking registers 68126177Srik */ 69126177Srik#define DS_RCBR 0x2b /* rw - receive channel blocking 1..4 */ 70126177Srik#define DS_TCBR 0x22 /* rw - transmit channel blocking 1..4 */ 71126177Srik 72126177Srik/* 73126177Srik * Slot 0 registers 74126177Srik */ 75126177Srik#define DS_RAF 0x2f /* r - receive align frame */ 76126177Srik#define DS_RNAF 0x1f /* r - receive non-align frame */ 77126177Srik#define DS_TAF 0x20 /* rw - transmit align frame */ 78126177Srik#define DS_TNAF 0x21 /* rw - transmit non-align frame */ 79126177Srik 80126177Srik/*---------------------------------------------- 81126177Srik * Receive control register 1 82126177Srik */ 83126177Srik#define RCR1_RSO 0x00 /* RSYNC outputs frame boundaries */ 84126177Srik#define RCR1_RSI 0x20 /* RSYNC is input (elastic store) */ 85126177Srik#define RCR1_RSO_CAS 0x40 /* RSYNC outputs CAS multiframe boundaries */ 86126177Srik#define RCR1_RSO_CRC4 0xc0 /* RSYNC outputs CRC4 multiframe boundaries */ 87126177Srik 88126177Srik#define RCR1_FRC 0x04 /* frame resync criteria */ 89126177Srik#define RCR1_SYNCD 0x02 /* auto resync disable */ 90126177Srik#define RCR1_RESYNC 0x01 /* force resync */ 91126177Srik 92126177Srik/* 93126177Srik * Receive control register 2 94126177Srik */ 95126177Srik#define RCR2_SA_8 0x80 /* output Sa8 bit at RLINK pin */ 96126177Srik#define RCR2_SA_7 0x40 /* output Sa7 bit at RLINK pin */ 97126177Srik#define RCR2_SA_6 0x20 /* output Sa6 bit at RLINK pin */ 98126177Srik#define RCR2_SA_5 0x10 /* output Sa5 bit at RLINK pin */ 99126177Srik#define RCR2_SA_4 0x08 /* output Sa4 bit at RLINK pin */ 100126177Srik#define RCR2_RSCLKM 0x04 /* receive side SYSCLK mode 2048 */ 101126177Srik#define RCR2_RESE 0x02 /* receive side elastic store enable */ 102126177Srik 103126177Srik/* 104126177Srik * Transmit control register 1 105126177Srik */ 106126177Srik#define TCR1_TFPT 0x40 /* source timeslot 0 from TSER pin */ 107126177Srik#define TCR1_T16S 0x20 /* source timeslot 16 from TS1..TS16 regs */ 108126177Srik#define TCR1_TUA1 0x10 /* transmit unframed all ones */ 109126177Srik#define TCR1_TSIS 0x08 /* source Si bits from TAF/TNAF registers */ 110126177Srik#define TCR1_TSA1 0x04 /* transmit timeslot 16 all ones */ 111126177Srik 112126177Srik#define TCR1_TSI 0x00 /* TSYNC is input */ 113126177Srik#define TCR1_TSO 0x01 /* TSYNC outputs frame boundaries */ 114126177Srik#define TCR1_TSO_MF 0x03 /* TSYNC outputs CAS/CRC4 m/f boundaries */ 115126177Srik 116126177Srik/* 117126177Srik * Transmit control register 2 118126177Srik */ 119126177Srik#define TCR2_SA_8 0x80 /* source Sa8 bit from TLINK pin */ 120126177Srik#define TCR2_SA_7 0x40 /* source Sa7 bit from TLINK pin */ 121126177Srik#define TCR2_SA_6 0x20 /* source Sa6 bit from TLINK pin */ 122126177Srik#define TCR2_SA_5 0x10 /* source Sa5 bit from TLINK pin */ 123126177Srik#define TCR2_SA_4 0x08 /* source Sa4 bit from TLINK pin */ 124126177Srik#define TCR2_AEBE 0x02 /* automatic E-bit enable */ 125126177Srik#define TCR2_P16F 0x01 /* pin 16 is Loss of Transmit Clock */ 126126177Srik 127126177Srik/* 128126177Srik * Common control register 1 129126177Srik */ 130126177Srik#define CCR1_FLOOP 0x80 /* enable framer loopback */ 131126177Srik#define CCR1_THDB3 0x40 /* enable transmit HDB3 */ 132126177Srik#define CCR1_TG802 0x20 /* enable transmit G.802 */ 133126177Srik#define CCR1_TCRC4 0x10 /* enable transmit CRC4 */ 134126177Srik#define CCR1_CCS 0x08 /* common channel signaling mode */ 135126177Srik#define CCR1_RHDB3 0x04 /* enable receive HDB3 */ 136126177Srik#define CCR1_RG802 0x02 /* enable receive G.802 */ 137126177Srik#define CCR1_RCRC4 0x01 /* enable receive CRC4 */ 138126177Srik 139126177Srik/* 140126177Srik * Common control register 2 141126177Srik */ 142126177Srik#define CCR2_EC625 0x80 /* update error counters every 62.5 ms */ 143126177Srik#define CCR2_CNTCV 0x40 /* count code violations */ 144126177Srik#define CCR2_AUTOAIS 0x20 /* automatic AIS generation */ 145126177Srik#define CCR2_AUTORA 0x10 /* automatic remote alarm generation */ 146126177Srik#define CCR2_LOFA1 0x08 /* force RSER to 1 under loss of frame align */ 147126177Srik#define CCR2_TRCLK 0x04 /* switch transmitter to RCLK if TCLK stops */ 148126177Srik#define CCR2_RLOOP 0x02 /* enable remote loopback */ 149126177Srik#define CCR2_LLOOP 0x01 /* enable local loopback */ 150126177Srik 151126177Srik/* 152126177Srik * Common control register 3 153126177Srik */ 154126177Srik#define CCR3_TESE 0x80 /* enable transmit elastic store */ 155126177Srik#define CCR3_TCBFS 0x40 /* TCBRs define signaling bits to insert */ 156126177Srik#define CCR3_TIRSER 0x20 /* TIRs define data channels from RSER pin */ 157126177Srik#define CCR3_ESRESET 0x10 /* elastic store reset */ 158126177Srik#define CCR3_LIRESET 0x08 /* line interface reset */ 159126177Srik#define CCR3_THSE 0x04 /* insert signaling from TSIG into TSER */ 160126177Srik#define CCR3_TSCLKM 0x02 /* transmit backplane clock 2048 */ 161126177Srik 162126177Srik/* 163126177Srik * Line interface control register 164126177Srik */ 165126177Srik#define LICR_DB21 0x80 /* return loss 21 dB */ 166126177Srik 167126177Srik#define LICR_LB75 0x00 /* 75 Ohm normal */ 168126177Srik#define LICR_LB120 0x20 /* 120 Ohm normal */ 169126177Srik#define LICR_LB75P 0x40 /* 75 Ohm protected */ 170126177Srik#define LICR_LB120P 0x60 /* 120 Ohm protected */ 171126177Srik 172126177Srik#define LICR_HIGAIN 0x10 /* receive gain 30 dB */ 173126177Srik#define LICR_JA_TX 0x08 /* transmit side jitter attenuator select */ 174126177Srik#define LICR_JA_LOW 0x04 /* low jitter attenuator depth (32 bits) */ 175126177Srik#define LICR_JA_DISABLE 0x02 /* disable jitter attenuator */ 176126177Srik#define LICR_POWERDOWN 0x01 /* transmit power down */ 177126177Srik 178126177Srik/*---------------------------------------------- 179126177Srik * Receive information register 180126177Srik */ 181126177Srik#define RIR_TES_FULL 0x80 /* transmit elastic store full */ 182126177Srik#define RIR_TES_EMPTY 0x40 /* transmit elastic store empty */ 183126177Srik#define RIR_JALT 0x20 /* jitter attenuation limit trip */ 184126177Srik#define RIR_ES_FULL 0x10 /* elastic store full */ 185126177Srik#define RIR_ES_EMPTY 0x08 /* elastic store empty */ 186126177Srik#define RIR_RESYNC_CRC 0x04 /* CRC4 resync (915/1000 errors) */ 187126177Srik#define RIR_RESYNC 0x02 /* frame resync (three consec errors) */ 188126177Srik#define RIR_RESYNC_CAS 0x01 /* CAS resync (two consec errors) */ 189126177Srik 190126177Srik/* 191126177Srik * Synchronizer status register 192126177Srik */ 193126177Srik#define SSR_CSC(v) (((v) >> 2) & 0x3c | ((v) >> 3) & 1) 194126177Srik /* CRC4 sync counter (6 bits, bit 1 n/a) */ 195126177Srik#define SSR_SYNC 0x04 /* frame alignment sync active */ 196126177Srik#define SSR_SYNC_CAS 0x02 /* CAS multiframe sync active */ 197126177Srik#define SSR_SYNC_CRC4 0x01 /* CRC4 multiframe sync active */ 198126177Srik 199126177Srik/* 200126177Srik * Status register 1 201126177Srik */ 202126177Srik#define SR1_RSA1 0x80 /* receive signaling all ones */ 203126177Srik#define SR1_RDMA 0x40 /* receive distant multiframe alarm */ 204126177Srik#define SR1_RSA0 0x20 /* receive signaling all zeros */ 205126177Srik#define SR1_RSLIP 0x10 /* receive elastic store slip event */ 206126177Srik#define SR1_RUA1 0x08 /* receive unframed all ones */ 207126177Srik#define SR1_RRA 0x04 /* receive remote alarm */ 208126177Srik#define SR1_RCL 0x02 /* receive carrier loss */ 209126177Srik#define SR1_RLOS 0x01 /* receive loss of sync */ 210126177Srik 211126177Srik/* 212126177Srik * Status register 2 213126177Srik */ 214126177Srik#define SR2_RMF 0x80 /* receive CAS multiframe (every 2 ms) */ 215126177Srik#define SR2_RAF 0x40 /* receive align frame (every 250 us) */ 216126177Srik#define SR2_TMF 0x20 /* transmit multiframe (every 2 ms) */ 217126177Srik#define SR2_SEC 0x10 /* one second timer (or 62.5 ms) */ 218126177Srik#define SR2_TAF 0x08 /* transmit align frame (every 250 us) */ 219126177Srik#define SR2_LOTC 0x04 /* loss of transmit clock */ 220126177Srik#define SR2_RCMF 0x02 /* receive CRC4 multiframe (every 2 ms) */ 221126177Srik#define SR2_TSLIP 0x01 /* transmit elastic store slip event */ 222126177Srik 223126177Srik/* 224126177Srik * Error count registers 225126177Srik */ 226126177Srik#define VCR(h,l) (((short) (h) << 8) | (l)) /* 16-bit code violation */ 227126177Srik#define CRCCR(h,l) (((short) (h) << 8 & 0x300) | (l)) /* 10-bit CRC4 error count */ 228126177Srik#define EBCR(h,l) (((short) (h) << 8 & 0x300) | (l)) /* 10-bit E-bit count */ 229126177Srik#define FASCR(h,l) (((short) (h) << 4 & 0xfc0) | (l) >> 2) /* 12-bit FAS error count */ 230126177Srik 231126177Srik#define FASCRH(h) ((h) << 4) /* 12-bit FAS error count */ 232126177Srik#define FASCRL(l) ((l) >> 2) /* 12-bit FAS error count */ 233126177Srik 234126177Srik/* 235126177Srik * DS21x54 additional registers 236126177Srik */ 237126177Srik#define DS_IDR 0x0f /* r - device id */ 238126177Srik#define DS_TSACR 0x1c /* rw - transmit Sa bit control */ 239126177Srik#define DS_CCR6 0x1d /* rw - common control 6 */ 240126177Srik 241126177Srik#define DS_TSIAF 0x50 /* rw - transmit Si bits align frame */ 242126177Srik#define DS_TSINAF 0x51 /* rw - transmit Si bits non-align frame */ 243126177Srik#define DS_TRA 0x52 /* rw - transmit remote alarm bits */ 244126177Srik#define DS_TSA4 0x53 /* rw - transmit Sa4 bits */ 245126177Srik#define DS_TSA5 0x54 /* rw - transmit Sa5 bits */ 246126177Srik#define DS_TSA6 0x55 /* rw - transmit Sa6 bits */ 247126177Srik#define DS_TSA7 0x56 /* rw - transmit Sa7 bits */ 248126177Srik#define DS_TSA8 0x57 /* rw - transmit Sa8 bits */ 249126177Srik#define DS_RSIAF 0x58 /* r - receive Si bits align frame */ 250126177Srik#define DS_RSINAF 0x59 /* r - receive Si bits non-align frame */ 251126177Srik#define DS_RRA 0x5a /* r - receive remote alarm bits */ 252126177Srik#define DS_RSA4 0x5b /* r - receive Sa4 bits */ 253126177Srik#define DS_RSA5 0x5c /* r - receive Sa5 bits */ 254126177Srik#define DS_RSA6 0x5d /* r - receive Sa6 bits */ 255126177Srik#define DS_RSA7 0x5e /* r - receive Sa7 bits */ 256126177Srik#define DS_RSA8 0x5f /* r - receive Sa8 bits */ 257126177Srik 258126177Srik#define DS_TCC1 0xa0 /* rw - transmit channel control 1 */ 259126177Srik#define DS_TCC2 0xa1 /* rw - transmit channel control 2 */ 260126177Srik#define DS_TCC3 0xa2 /* rw - transmit channel control 3 */ 261126177Srik#define DS_TCC4 0xa3 /* rw - transmit channel control 4 */ 262126177Srik#define DS_RCC1 0xa4 /* rw - receive channel control 1 */ 263126177Srik#define DS_RCC2 0xa5 /* rw - receive channel control 2 */ 264126177Srik#define DS_RCC3 0xa6 /* rw - receive channel control 3 */ 265126177Srik#define DS_RCC4 0xa7 /* rw - receive channel control 4 */ 266126177Srik 267126177Srik#define DS_CCR4 0xa8 /* rw - common control 4 */ 268126177Srik#define DS_TDS0M 0xa9 /* r - transmit ds0 monitor */ 269126177Srik#define DS_CCR5 0xaa /* rw - common control 5 */ 270126177Srik#define DS_RDS0M 0xab /* r - receive ds0 monitor */ 271126177Srik#define DS_TEST3 0xac /* rw - test 3, set to 00h */ 272126177Srik 273126177Srik#define DS_HCR 0xb0 /* rw - hdlc control */ 274126177Srik#define DS_HSR 0xb1 /* rw - hdlc status */ 275126177Srik#define DS_HIMR 0xb2 /* rw - hdlc interrupt mask */ 276126177Srik#define DS_RHIR 0xb3 /* rw - receive hdlc information */ 277126177Srik#define DS_RHFR 0xb4 /* rw - receive hdlc fifo */ 278126177Srik#define DS_IBO 0xb5 /* rw - interleave bus operation */ 279126177Srik#define DS_THIR 0xb6 /* rw - transmit hdlc information */ 280126177Srik#define DS_THFR 0xb7 /* rw - transmit hdlc fifo */ 281126177Srik#define DS_RDC1 0xb8 /* rw - receive hdlc ds0 control 1 */ 282126177Srik#define DS_RDC2 0xb9 /* rw - receive hdlc ds0 control 2 */ 283126177Srik#define DS_TDC1 0xba /* rw - transmit hdlc ds0 control 1 */ 284126177Srik#define DS_TDC2 0xbb /* rw - transmit hdlc ds0 control 2 */ 285126177Srik 286126177Srik#define CCR4_RLB 0x80 /* enable remote loopback */ 287126177Srik#define CCR4_LLB 0x40 /* enable local loopback */ 288126177Srik#define CCR5_LIRST 0x80 /* line interface reset */ 289126177Srik#define CCR6_RESR 0x02 /* receive elastic store reset */ 290126177Srik#define CCR6_TESR 0x01 /* transmit elastic store reset */ 291