cfi_reg.h revision 184251
1184251Smarcel/*-
2184251Smarcel * Copyright (c) 2007, Juniper Networks, Inc.
3184251Smarcel * All rights reserved.
4184251Smarcel *
5184251Smarcel * Redistribution and use in source and binary forms, with or without
6184251Smarcel * modification, are permitted provided that the following conditions
7184251Smarcel * are met:
8184251Smarcel * 1. Redistributions of source code must retain the above copyright
9184251Smarcel *    notice, this list of conditions and the following disclaimer.
10184251Smarcel * 2. Redistributions in binary form must reproduce the above copyright
11184251Smarcel *    notice, this list of conditions and the following disclaimer in the
12184251Smarcel *    documentation and/or other materials provided with the distribution.
13184251Smarcel * 3. Neither the name of the author nor the names of any co-contributors
14184251Smarcel *    may be used to endorse or promote products derived from this software
15184251Smarcel *    without specific prior written permission.
16184251Smarcel *
17184251Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18184251Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19184251Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20184251Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21184251Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22184251Smarcel * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23184251Smarcel * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24184251Smarcel * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25184251Smarcel * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26184251Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27184251Smarcel * SUCH DAMAGE.
28184251Smarcel *
29184251Smarcel * $FreeBSD: head/sys/dev/cfi/cfi_reg.h 184251 2008-10-25 06:18:12Z marcel $
30184251Smarcel */
31184251Smarcel
32184251Smarcel#ifndef _DEV_CFI_REG_H_
33184251Smarcel#define	_DEV_CFI_REG_H_
34184251Smarcel
35184251Smarcelstruct cfi_qry {
36184251Smarcel	u_char		reserved[16];
37184251Smarcel	u_char		ident[3];	/* "QRY" */
38184251Smarcel	u_char		pri_vend[2];
39184251Smarcel	u_char		pri_vend_eqt[2];
40184251Smarcel	u_char		alt_vend[2];
41184251Smarcel	u_char		alt_vend_eqt[2];
42184251Smarcel	/* System Interface Information. */
43184251Smarcel	u_char		min_vcc;
44184251Smarcel	u_char		max_vcc;
45184251Smarcel	u_char		min_vpp;
46184251Smarcel	u_char		max_vpp;
47184251Smarcel	u_char		tto_byte_write;		/* 2**n milliseconds. */
48184251Smarcel	u_char		tto_buf_write;		/* 2**n milliseconds. */
49184251Smarcel	u_char		tto_block_erase;	/* 2**n milliseconds. */
50184251Smarcel	u_char		tto_chip_erase;		/* 2**n milliseconds. */
51184251Smarcel	u_char		mto_byte_write;		/* 2**n times typical t/o. */
52184251Smarcel	u_char		mto_buf_write;		/* 2**n times typical t/o. */
53184251Smarcel	u_char		mto_block_erase;	/* 2**n times typical t/o. */
54184251Smarcel	u_char		mto_chip_erase;		/* 2**n times typical t/o. */
55184251Smarcel	/* Device Geometry Definition. */
56184251Smarcel	u_char		size;			/* 2**n bytes. */
57184251Smarcel	u_char		iface[2];
58184251Smarcel	u_char		max_buf_write_size[2];	/* 2**n. */
59184251Smarcel	u_char		nregions;		/* Number of erase regions. */
60184251Smarcel	u_char		region[4];		/* Single entry. */
61184251Smarcel	/* Additional entries follow. */
62184251Smarcel	/* Primary Vendor-specific Extended Query table follows. */
63184251Smarcel	/* Alternate Vendor-specific Extended Query table follows. */
64184251Smarcel};
65184251Smarcel
66184251Smarcel#define	CFI_QRY_CMD_ADDR	0x55
67184251Smarcel#define	CFI_QRY_CMD_DATA	0x98
68184251Smarcel
69184251Smarcel#define	CFI_QRY_IDENT		offsetof(struct cfi_qry, ident)
70184251Smarcel#define	CFI_QRY_VEND		offsetof(struct cfi_qry, pri_vend)
71184251Smarcel
72184251Smarcel#define	CFI_QRY_TTO_WRITE	offsetof(struct cfi_qry, tto_byte_write)
73184251Smarcel#define	CFI_QRY_TTO_ERASE	offsetof(struct cfi_qry, tto_block_erase)
74184251Smarcel#define	CFI_QRY_MTO_WRITE	offsetof(struct cfi_qry, mto_byte_write)
75184251Smarcel#define	CFI_QRY_MTO_ERASE	offsetof(struct cfi_qry, mto_block_erase)
76184251Smarcel
77184251Smarcel#define	CFI_QRY_SIZE		offsetof(struct cfi_qry, size)
78184251Smarcel#define	CFI_QRY_IFACE		offsetof(struct cfi_qry, iface)
79184251Smarcel#define	CFI_QRY_NREGIONS	offsetof(struct cfi_qry, nregions)
80184251Smarcel#define	CFI_QRY_REGION0		offsetof(struct cfi_qry, region)
81184251Smarcel#define	CFI_QRY_REGION(x)	(CFI_QRY_REGION0 + (x) * 4)
82184251Smarcel
83184251Smarcel#define	CFI_VEND_NONE		0x0000
84184251Smarcel#define	CFI_VEND_INTEL_ECS	0x0001
85184251Smarcel#define	CFI_VEND_AMD_SCS	0x0002
86184251Smarcel#define	CFI_VEND_INTEL_SCS	0x0003
87184251Smarcel#define	CFI_VEND_AMD_ECS	0x0004
88184251Smarcel#define	CFI_VEND_MITSUBISHI_SCS	0x0100
89184251Smarcel#define	CFI_VEND_MITSUBISHI_ECS	0x0101
90184251Smarcel
91184251Smarcel#define	CFI_IFACE_X8		0x0000
92184251Smarcel#define	CFI_IFACE_X16		0x0001
93184251Smarcel#define	CFI_IFACE_X8X16		0x0002
94184251Smarcel#define	CFI_IFACE_X32		0x0003
95184251Smarcel#define	CFI_IFACE_X16X32	0x0005
96184251Smarcel
97184251Smarcel/* Standard Command Set (aka Basic Command Set) */
98184251Smarcel#define	CFI_BCS_BLOCK_ERASE	0x20
99184251Smarcel#define	CFI_BCS_PROGRAM		0x40
100184251Smarcel#define	CFI_BCS_CLEAR_STATUS	0x50
101184251Smarcel#define	CFI_BCS_READ_STATUS	0x70
102184251Smarcel#define	CFI_BCS_ERASE_SUSPEND	0xb0
103184251Smarcel#define	CFI_BCS_ERASE_RESUME	0xd0	/* Equals CONFIRM */
104184251Smarcel#define	CFI_BCS_CONFIRM		0xd0
105184251Smarcel#define	CFI_BCS_READ_ARRAY	0xff
106184251Smarcel
107184251Smarcel/* AMD commands. */
108184251Smarcel#define	CFI_AMD_BLOCK_ERASE	0x30
109184251Smarcel#define	CFI_AMD_UNLOCK_ACK	0x55
110184251Smarcel#define	CFI_AMD_ERASE_SECTOR	0x80
111184251Smarcel#define	CFI_AMD_PROGRAM		0xa0
112184251Smarcel#define	CFI_AMD_UNLOCK		0xaa
113184251Smarcel
114184251Smarcel#define	AMD_ADDR_START		0xaaa
115184251Smarcel#define	AMD_ADDR_ACK		0x555
116184251Smarcel
117184251Smarcel#endif /* _DEV_CFI_REG_H_ */
118