1184251Smarcel/*- 2184251Smarcel * Copyright (c) 2007, Juniper Networks, Inc. 3255207Sbrooks * Copyright (c) 2012-2013, SRI International 4184251Smarcel * All rights reserved. 5184251Smarcel * 6255207Sbrooks * Portions of this software were developed by SRI International and the 7255207Sbrooks * University of Cambridge Computer Laboratory under DARPA/AFRL contract 8255207Sbrooks * (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research 9255207Sbrooks * programme. 10255207Sbrooks * 11184251Smarcel * Redistribution and use in source and binary forms, with or without 12184251Smarcel * modification, are permitted provided that the following conditions 13184251Smarcel * are met: 14184251Smarcel * 1. Redistributions of source code must retain the above copyright 15184251Smarcel * notice, this list of conditions and the following disclaimer. 16184251Smarcel * 2. Redistributions in binary form must reproduce the above copyright 17184251Smarcel * notice, this list of conditions and the following disclaimer in the 18184251Smarcel * documentation and/or other materials provided with the distribution. 19184251Smarcel * 3. Neither the name of the author nor the names of any co-contributors 20184251Smarcel * may be used to endorse or promote products derived from this software 21184251Smarcel * without specific prior written permission. 22184251Smarcel * 23184251Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24184251Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25184251Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26184251Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27184251Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 28184251Smarcel * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29184251Smarcel * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30184251Smarcel * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31184251Smarcel * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32184251Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33184251Smarcel * SUCH DAMAGE. 34184251Smarcel * 35184251Smarcel * $FreeBSD: releng/10.2/sys/dev/cfi/cfi_reg.h 255207 2013-09-04 17:19:21Z brooks $ 36184251Smarcel */ 37184251Smarcel 38184251Smarcel#ifndef _DEV_CFI_REG_H_ 39184251Smarcel#define _DEV_CFI_REG_H_ 40184251Smarcel 41184251Smarcelstruct cfi_qry { 42184251Smarcel u_char reserved[16]; 43184251Smarcel u_char ident[3]; /* "QRY" */ 44184251Smarcel u_char pri_vend[2]; 45184251Smarcel u_char pri_vend_eqt[2]; 46184251Smarcel u_char alt_vend[2]; 47184251Smarcel u_char alt_vend_eqt[2]; 48184251Smarcel /* System Interface Information. */ 49184251Smarcel u_char min_vcc; 50184251Smarcel u_char max_vcc; 51184251Smarcel u_char min_vpp; 52184251Smarcel u_char max_vpp; 53255207Sbrooks u_char tto_byte_write; /* 2**n microseconds. */ 54255207Sbrooks u_char tto_buf_write; /* 2**n microseconds. */ 55184251Smarcel u_char tto_block_erase; /* 2**n milliseconds. */ 56184251Smarcel u_char tto_chip_erase; /* 2**n milliseconds. */ 57184251Smarcel u_char mto_byte_write; /* 2**n times typical t/o. */ 58184251Smarcel u_char mto_buf_write; /* 2**n times typical t/o. */ 59184251Smarcel u_char mto_block_erase; /* 2**n times typical t/o. */ 60184251Smarcel u_char mto_chip_erase; /* 2**n times typical t/o. */ 61184251Smarcel /* Device Geometry Definition. */ 62184251Smarcel u_char size; /* 2**n bytes. */ 63184251Smarcel u_char iface[2]; 64184251Smarcel u_char max_buf_write_size[2]; /* 2**n. */ 65184251Smarcel u_char nregions; /* Number of erase regions. */ 66184251Smarcel u_char region[4]; /* Single entry. */ 67184251Smarcel /* Additional entries follow. */ 68184251Smarcel /* Primary Vendor-specific Extended Query table follows. */ 69184251Smarcel /* Alternate Vendor-specific Extended Query table follows. */ 70184251Smarcel}; 71184251Smarcel 72184251Smarcel#define CFI_QRY_CMD_ADDR 0x55 73184251Smarcel#define CFI_QRY_CMD_DATA 0x98 74184251Smarcel 75184251Smarcel#define CFI_QRY_IDENT offsetof(struct cfi_qry, ident) 76184251Smarcel#define CFI_QRY_VEND offsetof(struct cfi_qry, pri_vend) 77184251Smarcel 78184251Smarcel#define CFI_QRY_TTO_WRITE offsetof(struct cfi_qry, tto_byte_write) 79255207Sbrooks#define CFI_QRY_TTO_BUFWRITE offsetof(struct cfi_qry, tto_buf_write) 80184251Smarcel#define CFI_QRY_TTO_ERASE offsetof(struct cfi_qry, tto_block_erase) 81184251Smarcel#define CFI_QRY_MTO_WRITE offsetof(struct cfi_qry, mto_byte_write) 82255207Sbrooks#define CFI_QRY_MTO_BUFWRITE offsetof(struct cfi_qry, mto_buf_write) 83184251Smarcel#define CFI_QRY_MTO_ERASE offsetof(struct cfi_qry, mto_block_erase) 84184251Smarcel 85184251Smarcel#define CFI_QRY_SIZE offsetof(struct cfi_qry, size) 86184251Smarcel#define CFI_QRY_IFACE offsetof(struct cfi_qry, iface) 87255207Sbrooks#define CFI_QRY_MAXBUF offsetof(struct cfi_qry, max_buf_write_size) 88184251Smarcel#define CFI_QRY_NREGIONS offsetof(struct cfi_qry, nregions) 89184251Smarcel#define CFI_QRY_REGION0 offsetof(struct cfi_qry, region) 90184251Smarcel#define CFI_QRY_REGION(x) (CFI_QRY_REGION0 + (x) * 4) 91184251Smarcel 92184251Smarcel#define CFI_VEND_NONE 0x0000 93184251Smarcel#define CFI_VEND_INTEL_ECS 0x0001 94184251Smarcel#define CFI_VEND_AMD_SCS 0x0002 95184251Smarcel#define CFI_VEND_INTEL_SCS 0x0003 96184251Smarcel#define CFI_VEND_AMD_ECS 0x0004 97184251Smarcel#define CFI_VEND_MITSUBISHI_SCS 0x0100 98184251Smarcel#define CFI_VEND_MITSUBISHI_ECS 0x0101 99184251Smarcel 100184251Smarcel#define CFI_IFACE_X8 0x0000 101184251Smarcel#define CFI_IFACE_X16 0x0001 102184251Smarcel#define CFI_IFACE_X8X16 0x0002 103184251Smarcel#define CFI_IFACE_X32 0x0003 104184251Smarcel#define CFI_IFACE_X16X32 0x0005 105184251Smarcel 106184251Smarcel/* Standard Command Set (aka Basic Command Set) */ 107184251Smarcel#define CFI_BCS_BLOCK_ERASE 0x20 108184251Smarcel#define CFI_BCS_PROGRAM 0x40 109184251Smarcel#define CFI_BCS_CLEAR_STATUS 0x50 110184251Smarcel#define CFI_BCS_READ_STATUS 0x70 111184251Smarcel#define CFI_BCS_ERASE_SUSPEND 0xb0 112184251Smarcel#define CFI_BCS_ERASE_RESUME 0xd0 /* Equals CONFIRM */ 113184251Smarcel#define CFI_BCS_CONFIRM 0xd0 114255207Sbrooks#define CFI_BCS_BUF_PROG_SETUP 0xe8 115184251Smarcel#define CFI_BCS_READ_ARRAY 0xff 116184251Smarcel 117188156Ssam/* Intel commands. */ 118251118Sbrooks#define CFI_INTEL_LB 0x01 /* Lock Block */ 119251118Sbrooks#define CFI_INTEL_LBS 0x60 /* Lock Block Setup */ 120188156Ssam#define CFI_INTEL_READ_ID 0x90 /* Read Identifier */ 121188156Ssam#define CFI_INTEL_PP_SETUP 0xc0 /* Protection Program Setup */ 122251118Sbrooks#define CFI_INTEL_UB 0xd0 /* Unlock Block */ 123188156Ssam 124188156Ssam/* NB: these are addresses for 16-bit accesses */ 125188156Ssam#define CFI_INTEL_PLR 0x80 /* Protection Lock Register */ 126188156Ssam#define CFI_INTEL_PR(n) (0x81+(n)) /* Protection Register */ 127188156Ssam 128188156Ssam/* Status register definitions */ 129188156Ssam#define CFI_INTEL_STATUS_WSMS 0x0080 /* Write Machine Status */ 130188156Ssam#define CFI_INTEL_STATUS_ESS 0x0040 /* Erase Suspend Status */ 131188156Ssam#define CFI_INTEL_STATUS_ECLBS 0x0020 /* Erase and Clear Lock-Bit Status */ 132188156Ssam#define CFI_INTEL_STATUS_PSLBS 0x0010 /* Program and Set Lock-Bit Status */ 133188156Ssam#define CFI_INTEL_STATUS_VPENS 0x0008 /* Programming Voltage Status */ 134188156Ssam#define CFI_INTEL_STATUS_PSS 0x0004 /* Program Suspend Status */ 135188156Ssam#define CFI_INTEL_STATUS_DPS 0x0002 /* Device Protect Status */ 136188156Ssam#define CFI_INTEL_STATUS_RSVD 0x0001 /* reserved */ 137188156Ssam 138188156Ssam/* eXtended Status register definitions */ 139188156Ssam#define CFI_INTEL_XSTATUS_WBS 0x8000 /* Write Buffer Status */ 140188156Ssam#define CFI_INTEL_XSTATUS_RSVD 0x7f00 /* reserved */ 141188156Ssam 142184251Smarcel/* AMD commands. */ 143184251Smarcel#define CFI_AMD_BLOCK_ERASE 0x30 144184251Smarcel#define CFI_AMD_UNLOCK_ACK 0x55 145184251Smarcel#define CFI_AMD_ERASE_SECTOR 0x80 146184251Smarcel#define CFI_AMD_PROGRAM 0xa0 147184251Smarcel#define CFI_AMD_UNLOCK 0xaa 148184251Smarcel 149184251Smarcel#define AMD_ADDR_START 0xaaa 150184251Smarcel#define AMD_ADDR_ACK 0x555 151184251Smarcel 152184251Smarcel#endif /* _DEV_CFI_REG_H_ */ 153