ecore_reg.h revision 258203
1/*- 2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: stable/10/sys/dev/bxe/ecore_reg.h 258203 2013-11-16 00:31:32Z edavis $"); 36 37#ifndef ECORE_REG_H 38#define ECORE_REG_H 39 40 41#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR \ 42 (0x1<<0) 43#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS \ 44 (0x1<<2) 45#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU \ 46 (0x1<<5) 47#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT \ 48 (0x1<<3) 49#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR \ 50 (0x1<<4) 51#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND \ 52 (0x1<<1) 53#define ATC_REG_ATC_INIT_DONE \ 54 0x1100bcUL 55#define ATC_REG_ATC_INT_STS_CLR \ 56 0x1101c0UL 57#define ATC_REG_ATC_PRTY_MASK \ 58 0x1101d8UL 59#define ATC_REG_ATC_PRTY_STS_CLR \ 60 0x1101d0UL 61#define BRB1_REG_BRB1_INT_MASK \ 62 0x60128UL 63#define BRB1_REG_BRB1_PRTY_MASK \ 64 0x60138UL 65#define BRB1_REG_BRB1_PRTY_STS_CLR \ 66 0x60130UL 67#define BRB1_REG_MAC_GUARANTIED_0 \ 68 0x601e8UL 69#define BRB1_REG_MAC_GUARANTIED_1 \ 70 0x60240UL 71#define BRB1_REG_NUM_OF_FULL_BLOCKS \ 72 0x60090UL 73#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 \ 74 0x60078UL 75#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 \ 76 0x60068UL 77#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 \ 78 0x60094UL 79#define CCM_REG_CCM_INT_MASK \ 80 0xd01e4UL 81#define CCM_REG_CCM_PRTY_MASK \ 82 0xd01f4UL 83#define CCM_REG_CCM_PRTY_STS_CLR \ 84 0xd01ecUL 85#define CDU_REG_CDU_GLOBAL_PARAMS \ 86 0x101020UL 87#define CDU_REG_CDU_INT_MASK \ 88 0x10103cUL 89#define CDU_REG_CDU_PRTY_MASK \ 90 0x10104cUL 91#define CDU_REG_CDU_PRTY_STS_CLR \ 92 0x101044UL 93#define CFC_REG_AC_INIT_DONE \ 94 0x104078UL 95#define CFC_REG_CAM_INIT_DONE \ 96 0x10407cUL 97#define CFC_REG_CFC_INT_MASK \ 98 0x104108UL 99#define CFC_REG_CFC_INT_STS_CLR \ 100 0x104100UL 101#define CFC_REG_CFC_PRTY_MASK \ 102 0x104118UL 103#define CFC_REG_CFC_PRTY_STS_CLR \ 104 0x104110UL 105#define CFC_REG_DEBUG0 \ 106 0x104050UL 107#define CFC_REG_INIT_REG \ 108 0x10404cUL 109#define CFC_REG_LL_INIT_DONE \ 110 0x104074UL 111#define CFC_REG_NUM_LCIDS_INSIDE_PF \ 112 0x104120UL 113#define CFC_REG_STRONG_ENABLE_PF \ 114 0x104128UL 115#define CFC_REG_WEAK_ENABLE_PF \ 116 0x104124UL 117#define CSDM_REG_CSDM_INT_MASK_0 \ 118 0xc229cUL 119#define CSDM_REG_CSDM_INT_MASK_1 \ 120 0xc22acUL 121#define CSDM_REG_CSDM_PRTY_MASK \ 122 0xc22bcUL 123#define CSDM_REG_CSDM_PRTY_STS_CLR \ 124 0xc22b4UL 125#define CSEM_REG_CSEM_INT_MASK_0 \ 126 0x200110UL 127#define CSEM_REG_CSEM_INT_MASK_1 \ 128 0x200120UL 129#define CSEM_REG_CSEM_PRTY_MASK_0 \ 130 0x200130UL 131#define CSEM_REG_CSEM_PRTY_MASK_1 \ 132 0x200140UL 133#define CSEM_REG_CSEM_PRTY_STS_CLR_0 \ 134 0x200128UL 135#define CSEM_REG_CSEM_PRTY_STS_CLR_1 \ 136 0x200138UL 137#define CSEM_REG_FAST_MEMORY \ 138 0x220000UL 139#define CSEM_REG_INT_TABLE \ 140 0x200400UL 141#define CSEM_REG_PASSIVE_BUFFER \ 142 0x202000UL 143#define CSEM_REG_PRAM \ 144 0x240000UL 145#define CSEM_REG_VFPF_ERR_NUM \ 146 0x200380UL 147#define DBG_REG_DBG_PRTY_MASK \ 148 0xc0a8UL 149#define DBG_REG_DBG_PRTY_STS_CLR \ 150 0xc0a0UL 151#define DMAE_REG_BACKWARD_COMP_EN \ 152 0x10207cUL 153#define DMAE_REG_CMD_MEM \ 154 0x102400UL 155#define DMAE_REG_DMAE_INT_MASK \ 156 0x102054UL 157#define DMAE_REG_DMAE_PRTY_MASK \ 158 0x102064UL 159#define DMAE_REG_DMAE_PRTY_STS_CLR \ 160 0x10205cUL 161#define DMAE_REG_GO_C0 \ 162 0x102080UL 163#define DMAE_REG_GO_C1 \ 164 0x102084UL 165#define DMAE_REG_GO_C10 \ 166 0x102088UL 167#define DMAE_REG_GO_C11 \ 168 0x10208cUL 169#define DMAE_REG_GO_C12 \ 170 0x102090UL 171#define DMAE_REG_GO_C13 \ 172 0x102094UL 173#define DMAE_REG_GO_C14 \ 174 0x102098UL 175#define DMAE_REG_GO_C15 \ 176 0x10209cUL 177#define DMAE_REG_GO_C2 \ 178 0x1020a0UL 179#define DMAE_REG_GO_C3 \ 180 0x1020a4UL 181#define DMAE_REG_GO_C4 \ 182 0x1020a8UL 183#define DMAE_REG_GO_C5 \ 184 0x1020acUL 185#define DMAE_REG_GO_C6 \ 186 0x1020b0UL 187#define DMAE_REG_GO_C7 \ 188 0x1020b4UL 189#define DMAE_REG_GO_C8 \ 190 0x1020b8UL 191#define DMAE_REG_GO_C9 \ 192 0x1020bcUL 193#define DORQ_REG_DORQ_INT_MASK \ 194 0x170180UL 195#define DORQ_REG_DORQ_INT_STS_CLR \ 196 0x170178UL 197#define DORQ_REG_DORQ_PRTY_MASK \ 198 0x170190UL 199#define DORQ_REG_DORQ_PRTY_STS_CLR \ 200 0x170188UL 201#define DORQ_REG_DPM_CID_OFST \ 202 0x170030UL 203#define DORQ_REG_MAX_RVFID_SIZE \ 204 0x1701ecUL 205#define DORQ_REG_NORM_CID_OFST \ 206 0x17002cUL 207#define DORQ_REG_PF_USAGE_CNT \ 208 0x1701d0UL 209#define DORQ_REG_VF_NORM_CID_BASE \ 210 0x1701a0UL 211#define DORQ_REG_VF_NORM_CID_OFST \ 212 0x1701f4UL 213#define DORQ_REG_VF_NORM_CID_WND_SIZE \ 214 0x1701a4UL 215#define DORQ_REG_VF_NORM_MAX_CID_COUNT \ 216 0x1701e4UL 217#define DORQ_REG_VF_NORM_VF_BASE \ 218 0x1701a8UL 219#define DORQ_REG_VF_TYPE_MASK_0 \ 220 0x170218UL 221#define DORQ_REG_VF_TYPE_MAX_MCID_0 \ 222 0x1702d8UL 223#define DORQ_REG_VF_TYPE_MIN_MCID_0 \ 224 0x170298UL 225#define DORQ_REG_VF_TYPE_VALUE_0 \ 226 0x170258UL 227#define DORQ_REG_VF_USAGE_CT_LIMIT \ 228 0x170340UL 229#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 \ 230 (0x1<<4) 231#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 \ 232 (0x1<<0) 233#define HC_CONFIG_0_REG_INT_LINE_EN_0 \ 234 (0x1<<3) 235#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 \ 236 (0x1<<7) 237#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 \ 238 (0x1<<2) 239#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 \ 240 (0x1<<1) 241#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 \ 242 (0x1<<0) 243#define HC_REG_ATTN_MSG0_ADDR_L \ 244 0x108018UL 245#define HC_REG_ATTN_MSG1_ADDR_L \ 246 0x108020UL 247#define HC_REG_COMMAND_REG \ 248 0x108180UL 249#define HC_REG_CONFIG_0 \ 250 0x108000UL 251#define HC_REG_CONFIG_1 \ 252 0x108004UL 253#define HC_REG_HC_PRTY_MASK \ 254 0x1080a0UL 255#define HC_REG_HC_PRTY_STS_CLR \ 256 0x108098UL 257#define HC_REG_INT_MASK \ 258 0x108108UL 259#define HC_REG_LEADING_EDGE_0 \ 260 0x108040UL 261#define HC_REG_MAIN_MEMORY \ 262 0x108800UL 263#define HC_REG_MAIN_MEMORY_SIZE \ 264 152 265#define HC_REG_TRAILING_EDGE_0 \ 266 0x108044UL 267#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN \ 268 (0x1<<1) 269#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE \ 270 (0x1<<0) 271#define IGU_REG_ATTENTION_ACK_BITS \ 272 0x130108UL 273#define IGU_REG_ATTN_MSG_ADDR_H \ 274 0x13011cUL 275#define IGU_REG_ATTN_MSG_ADDR_L \ 276 0x130120UL 277#define IGU_REG_BLOCK_CONFIGURATION \ 278 0x130000UL 279#define IGU_REG_COMMAND_REG_32LSB_DATA \ 280 0x130124UL 281#define IGU_REG_COMMAND_REG_CTRL \ 282 0x13012cUL 283#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP \ 284 0x130200UL 285#define IGU_REG_IGU_PRTY_MASK \ 286 0x1300a8UL 287#define IGU_REG_IGU_PRTY_STS_CLR \ 288 0x1300a0UL 289#define IGU_REG_LEADING_EDGE_LATCH \ 290 0x130134UL 291#define IGU_REG_MAPPING_MEMORY \ 292 0x131000UL 293#define IGU_REG_MAPPING_MEMORY_SIZE \ 294 136 295#define IGU_REG_PBA_STATUS_LSB \ 296 0x130138UL 297#define IGU_REG_PBA_STATUS_MSB \ 298 0x13013cUL 299#define IGU_REG_PCI_PF_MSIX_EN \ 300 0x130144UL 301#define IGU_REG_PCI_PF_MSIX_FUNC_MASK \ 302 0x130148UL 303#define IGU_REG_PCI_PF_MSI_EN \ 304 0x130140UL 305#define IGU_REG_PENDING_BITS_STATUS \ 306 0x130300UL 307#define IGU_REG_PF_CONFIGURATION \ 308 0x130154UL 309#define IGU_REG_PROD_CONS_MEMORY \ 310 0x132000UL 311#define IGU_REG_RESET_MEMORIES \ 312 0x130158UL 313#define IGU_REG_SB_INT_BEFORE_MASK_LSB \ 314 0x13015cUL 315#define IGU_REG_SB_INT_BEFORE_MASK_MSB \ 316 0x130160UL 317#define IGU_REG_SB_MASK_LSB \ 318 0x130164UL 319#define IGU_REG_SB_MASK_MSB \ 320 0x130168UL 321#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT \ 322 0x130800UL 323#define IGU_REG_TRAILING_EDGE_LATCH \ 324 0x130104UL 325#define MCP_REG_MCPR_ACCESS_LOCK \ 326 0x8009c 327#define MCP_REG_MCPR_GP_INPUTS \ 328 0x800c0 329#define MCP_REG_MCPR_GP_OENABLE \ 330 0x800c8 331#define MCP_REG_MCPR_GP_OUTPUTS \ 332 0x800c4 333#define MCP_REG_MCPR_IMC_COMMAND \ 334 0x85900 335#define MCP_REG_MCPR_IMC_DATAREG0 \ 336 0x85920 337#define MCP_REG_MCPR_IMC_SLAVE_CONTROL \ 338 0x85904 339#define MCP_REG_MCPR_NVM_ACCESS_ENABLE \ 340 0x86424 341#define MCP_REG_MCPR_NVM_ADDR \ 342 0x8640c 343#define MCP_REG_MCPR_NVM_CFG4 \ 344 0x8642c 345#define MCP_REG_MCPR_NVM_COMMAND \ 346 0x86400 347#define MCP_REG_MCPR_NVM_READ \ 348 0x86410 349#define MCP_REG_MCPR_NVM_SW_ARB \ 350 0x86420 351#define MCP_REG_MCPR_NVM_WRITE \ 352 0x86408 353#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK \ 354 (0x1<<1) 355#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK \ 356 (0x1<<0) 357#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 \ 358 0xa42cUL 359#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 \ 360 0xa438UL 361#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 \ 362 0xa444UL 363#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 \ 364 0xa450UL 365#define MISC_REG_AEU_AFTER_INVERT_4_MCP \ 366 0xa458UL 367#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 \ 368 0xa700UL 369#define MISC_REG_AEU_CLR_LATCH_SIGNAL \ 370 0xa45cUL 371#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 \ 372 0xa06cUL 373#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 \ 374 0xa07cUL 375#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 \ 376 0xa08cUL 377#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 \ 378 0xa10cUL 379#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 \ 380 0xa11cUL 381#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 \ 382 0xa12cUL 383#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 \ 384 0xa078UL 385#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 \ 386 0xa118UL 387#define MISC_REG_AEU_ENABLE4_NIG_0 \ 388 0xa0f8UL 389#define MISC_REG_AEU_ENABLE4_NIG_1 \ 390 0xa198UL 391#define MISC_REG_AEU_ENABLE4_PXP_0 \ 392 0xa108UL 393#define MISC_REG_AEU_ENABLE4_PXP_1 \ 394 0xa1a8UL 395#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 \ 396 0xa688UL 397#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 \ 398 0xa6b0UL 399#define MISC_REG_AEU_GENERAL_ATTN_1 \ 400 0xa004UL 401#define MISC_REG_AEU_GENERAL_ATTN_10 \ 402 0xa028UL 403#define MISC_REG_AEU_GENERAL_ATTN_11 \ 404 0xa02cUL 405#define MISC_REG_AEU_GENERAL_ATTN_12 \ 406 0xa030UL 407#define MISC_REG_AEU_GENERAL_ATTN_2 \ 408 0xa008UL 409#define MISC_REG_AEU_GENERAL_ATTN_3 \ 410 0xa00cUL 411#define MISC_REG_AEU_GENERAL_ATTN_4 \ 412 0xa010UL 413#define MISC_REG_AEU_GENERAL_ATTN_5 \ 414 0xa014UL 415#define MISC_REG_AEU_GENERAL_ATTN_6 \ 416 0xa018UL 417#define MISC_REG_AEU_GENERAL_ATTN_7 \ 418 0xa01cUL 419#define MISC_REG_AEU_GENERAL_ATTN_8 \ 420 0xa020UL 421#define MISC_REG_AEU_GENERAL_ATTN_9 \ 422 0xa024UL 423#define MISC_REG_AEU_GENERAL_MASK \ 424 0xa61cUL 425#define MISC_REG_AEU_MASK_ATTN_FUNC_0 \ 426 0xa060UL 427#define MISC_REG_AEU_MASK_ATTN_FUNC_1 \ 428 0xa064UL 429#define MISC_REG_BOND_ID \ 430 0xa400UL 431#define MISC_REG_CHIP_NUM \ 432 0xa408UL 433#define MISC_REG_CHIP_REV \ 434 0xa40cUL 435#define MISC_REG_CHIP_TYPE \ 436 0xac60UL 437#define MISC_REG_CHIP_TYPE_57811_MASK \ 438 (1<<1) 439#define MISC_REG_CPMU_LP_DR_ENABLE \ 440 0xa858UL 441#define MISC_REG_CPMU_LP_FW_ENABLE_P0 \ 442 0xa84cUL 443#define MISC_REG_CPMU_LP_IDLE_THR_P0 \ 444 0xa8a0UL 445#define MISC_REG_CPMU_LP_MASK_ENT_P0 \ 446 0xa880UL 447#define MISC_REG_CPMU_LP_MASK_EXT_P0 \ 448 0xa888UL 449#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 \ 450 0xa8b8UL 451#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 \ 452 0xa8bcUL 453#define MISC_REG_DRIVER_CONTROL_1 \ 454 0xa510UL 455#define MISC_REG_DRIVER_CONTROL_7 \ 456 0xa3c8UL 457#define MISC_REG_FOUR_PORT_PATH_SWAP \ 458 0xa75cUL 459#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR \ 460 0xa738UL 461#define MISC_REG_FOUR_PORT_PORT_SWAP \ 462 0xa754UL 463#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR \ 464 0xa734UL 465#define MISC_REG_GENERIC_CR_0 \ 466 0xa460UL 467#define MISC_REG_GENERIC_CR_1 \ 468 0xa464UL 469#define MISC_REG_GENERIC_POR_1 \ 470 0xa474UL 471#define MISC_REG_GEN_PURP_HWG \ 472 0xa9a0UL 473#define MISC_REG_GPIO \ 474 0xa490UL 475#define MISC_REG_GPIO_EVENT_EN \ 476 0xa2bcUL 477#define MISC_REG_GPIO_INT \ 478 0xa494UL 479#define MISC_REG_GRC_RSV_ATTN \ 480 0xa3c0UL 481#define MISC_REG_GRC_TIMEOUT_ATTN \ 482 0xa3c4UL 483#define MISC_REG_LCPLL_E40_PWRDWN \ 484 0xaa74UL 485#define MISC_REG_LCPLL_E40_RESETB_ANA \ 486 0xaa78UL 487#define MISC_REG_LCPLL_E40_RESETB_DIG \ 488 0xaa7cUL 489#define MISC_REG_MISC_INT_MASK \ 490 0xa388UL 491#define MISC_REG_MISC_PRTY_MASK \ 492 0xa398UL 493#define MISC_REG_MISC_PRTY_STS_CLR \ 494 0xa390UL 495#define MISC_REG_PORT4MODE_EN \ 496 0xa750UL 497#define MISC_REG_PORT4MODE_EN_OVWR \ 498 0xa720UL 499#define MISC_REG_RESET_REG_1 \ 500 0xa580UL 501#define MISC_REG_RESET_REG_2 \ 502 0xa590UL 503#define MISC_REG_SHARED_MEM_ADDR \ 504 0xa2b4UL 505#define MISC_REG_SPIO \ 506 0xa4fcUL 507#define MISC_REG_SPIO_EVENT_EN \ 508 0xa2b8UL 509#define MISC_REG_SPIO_INT \ 510 0xa500UL 511#define MISC_REG_TWO_PORT_PATH_SWAP \ 512 0xa758UL 513#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR \ 514 0xa72cUL 515#define MISC_REG_UNPREPARED \ 516 0xa424UL 517#define MISC_REG_WC0_CTRL_PHY_ADDR \ 518 0xa9ccUL 519#define MISC_REG_WC0_RESET \ 520 0xac30UL 521#define MISC_REG_XMAC_CORE_PORT_MODE \ 522 0xa964UL 523#define MISC_REG_XMAC_PHY_PORT_MODE \ 524 0xa960UL 525#define MSTAT_REG_RX_STAT_GR64_LO \ 526 0x200UL 527#define MSTAT_REG_TX_STAT_GTXPOK_LO \ 528 0UL 529#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN \ 530 (0x1<<0) 531#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN \ 532 (0x1<<0) 533#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT \ 534 (0x1<<0) 535#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS \ 536 (0x1<<9) 537#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G \ 538 (0x1<<15) 539#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS \ 540 (0xf<<18) 541#define NIG_REG_BMAC0_IN_EN \ 542 0x100acUL 543#define NIG_REG_BMAC0_OUT_EN \ 544 0x100e0UL 545#define NIG_REG_BMAC0_PAUSE_OUT_EN \ 546 0x10110UL 547#define NIG_REG_BMAC0_REGS_OUT_EN \ 548 0x100e8UL 549#define NIG_REG_BRB0_PAUSE_IN_EN \ 550 0x100c4UL 551#define NIG_REG_BRB1_PAUSE_IN_EN \ 552 0x100c8UL 553#define NIG_REG_DEBUG_PACKET_LB \ 554 0x10800UL 555#define NIG_REG_EGRESS_DRAIN0_MODE \ 556 0x10060UL 557#define NIG_REG_EGRESS_EMAC0_OUT_EN \ 558 0x10120UL 559#define NIG_REG_EGRESS_EMAC0_PORT \ 560 0x10058UL 561#define NIG_REG_EMAC0_IN_EN \ 562 0x100a4UL 563#define NIG_REG_EMAC0_PAUSE_OUT_EN \ 564 0x10118UL 565#define NIG_REG_EMAC0_STATUS_MISC_MI_INT \ 566 0x10494UL 567#define NIG_REG_INGRESS_BMAC0_MEM \ 568 0x10c00UL 569#define NIG_REG_INGRESS_BMAC1_MEM \ 570 0x11000UL 571#define NIG_REG_INGRESS_EOP_LB_EMPTY \ 572 0x104e0UL 573#define NIG_REG_INGRESS_EOP_LB_FIFO \ 574 0x104e4UL 575#define NIG_REG_LATCH_BC_0 \ 576 0x16210UL 577#define NIG_REG_LATCH_STATUS_0 \ 578 0x18000UL 579#define NIG_REG_LED_10G_P0 \ 580 0x10320UL 581#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 \ 582 0x10318UL 583#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 \ 584 0x10310UL 585#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 \ 586 0x10308UL 587#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 \ 588 0x102f8UL 589#define NIG_REG_LED_CONTROL_TRAFFIC_P0 \ 590 0x10300UL 591#define NIG_REG_LED_MODE_P0 \ 592 0x102f0UL 593#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 \ 594 0x16070UL 595#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 \ 596 0x16074UL 597#define NIG_REG_LLFC_ENABLE_0 \ 598 0x16208UL 599#define NIG_REG_LLFC_ENABLE_1 \ 600 0x1620cUL 601#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 \ 602 0x16058UL 603#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 \ 604 0x1605cUL 605#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 \ 606 0x16060UL 607#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 \ 608 0x16064UL 609#define NIG_REG_LLFC_OUT_EN_0 \ 610 0x160c8UL 611#define NIG_REG_LLFC_OUT_EN_1 \ 612 0x160ccUL 613#define NIG_REG_LLH0_BRB1_DRV_MASK \ 614 0x10244UL 615#define NIG_REG_LLH0_BRB1_DRV_MASK_MF \ 616 0x16048UL 617#define NIG_REG_LLH0_BRB1_NOT_MCP \ 618 0x1025cUL 619#define NIG_REG_LLH0_CLS_TYPE \ 620 0x16080UL 621#define NIG_REG_LLH0_FUNC_EN \ 622 0x160fcUL 623#define NIG_REG_LLH0_FUNC_MEM \ 624 0x16180UL 625#define NIG_REG_LLH0_FUNC_MEM_ENABLE \ 626 0x16140UL 627#define NIG_REG_LLH0_FUNC_VLAN_ID \ 628 0x16100UL 629#define NIG_REG_LLH0_XCM_MASK \ 630 0x10130UL 631#define NIG_REG_LLH1_BRB1_NOT_MCP \ 632 0x102dcUL 633#define NIG_REG_LLH1_CLS_TYPE \ 634 0x16084UL 635#define NIG_REG_LLH1_FUNC_MEM \ 636 0x161c0UL 637#define NIG_REG_LLH1_FUNC_MEM_ENABLE \ 638 0x16160UL 639#define NIG_REG_LLH1_FUNC_MEM_SIZE \ 640 16 641#define NIG_REG_LLH1_MF_MODE \ 642 0x18614UL 643#define NIG_REG_LLH1_XCM_MASK \ 644 0x10134UL 645#define NIG_REG_LLH_E1HOV_MODE \ 646 0x160d8UL 647#define NIG_REG_LLH_MF_MODE \ 648 0x16024UL 649#define NIG_REG_MASK_INTERRUPT_PORT0 \ 650 0x10330UL 651#define NIG_REG_MASK_INTERRUPT_PORT1 \ 652 0x10334UL 653#define NIG_REG_NIG_EMAC0_EN \ 654 0x1003cUL 655#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC \ 656 0x10044UL 657#define NIG_REG_NIG_INT_STS_CLR_0 \ 658 0x103b4UL 659#define NIG_REG_NIG_PRTY_MASK \ 660 0x103dcUL 661#define NIG_REG_NIG_PRTY_MASK_0 \ 662 0x183c8UL 663#define NIG_REG_NIG_PRTY_MASK_1 \ 664 0x183d8UL 665#define NIG_REG_NIG_PRTY_STS_CLR \ 666 0x103d4UL 667#define NIG_REG_NIG_PRTY_STS_CLR_0 \ 668 0x183c0UL 669#define NIG_REG_NIG_PRTY_STS_CLR_1 \ 670 0x183d0UL 671#define NIG_REG_P0_HDRS_AFTER_BASIC \ 672 0x18038UL 673#define NIG_REG_P0_HWPFC_ENABLE \ 674 0x18078UL 675#define NIG_REG_P0_LLH_FUNC_MEM2 \ 676 0x18480UL 677#define NIG_REG_P0_MAC_IN_EN \ 678 0x185acUL 679#define NIG_REG_P0_MAC_OUT_EN \ 680 0x185b0UL 681#define NIG_REG_P0_MAC_PAUSE_OUT_EN \ 682 0x185b4UL 683#define NIG_REG_P0_PKT_PRIORITY_TO_COS \ 684 0x18054UL 685#define NIG_REG_P0_RX_COS0_PRIORITY_MASK \ 686 0x18058UL 687#define NIG_REG_P0_RX_COS1_PRIORITY_MASK \ 688 0x1805cUL 689#define NIG_REG_P0_RX_COS2_PRIORITY_MASK \ 690 0x186b0UL 691#define NIG_REG_P0_RX_COS3_PRIORITY_MASK \ 692 0x186b4UL 693#define NIG_REG_P0_RX_COS4_PRIORITY_MASK \ 694 0x186b8UL 695#define NIG_REG_P0_RX_COS5_PRIORITY_MASK \ 696 0x186bcUL 697#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP \ 698 0x180f0UL 699#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB \ 700 0x18688UL 701#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB \ 702 0x1868cUL 703#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT \ 704 0x180e8UL 705#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ \ 706 0x180ecUL 707#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 \ 708 0x1810cUL 709#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 \ 710 0x18110UL 711#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 \ 712 0x18114UL 713#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 \ 714 0x18118UL 715#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 \ 716 0x1811cUL 717#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 \ 718 0x186a0UL 719#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 \ 720 0x186a4UL 721#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 \ 722 0x186a8UL 723#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 \ 724 0x186acUL 725#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 \ 726 0x180f8UL 727#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 \ 728 0x180fcUL 729#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 \ 730 0x18100UL 731#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 \ 732 0x18104UL 733#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 \ 734 0x18108UL 735#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 \ 736 0x18690UL 737#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 \ 738 0x18694UL 739#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 \ 740 0x18698UL 741#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 \ 742 0x1869cUL 743#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS \ 744 0x180f4UL 745#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT \ 746 0x180e4UL 747#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB \ 748 0x18680UL 749#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB \ 750 0x18684UL 751#define NIG_REG_P1_HDRS_AFTER_BASIC \ 752 0x1818cUL 753#define NIG_REG_P1_HWPFC_ENABLE \ 754 0x181d0UL 755#define NIG_REG_P1_LLH_FUNC_MEM2 \ 756 0x184c0UL 757#define NIG_REG_P1_MAC_IN_EN \ 758 0x185c0UL 759#define NIG_REG_P1_MAC_OUT_EN \ 760 0x185c4UL 761#define NIG_REG_P1_MAC_PAUSE_OUT_EN \ 762 0x185c8UL 763#define NIG_REG_P1_PKT_PRIORITY_TO_COS \ 764 0x181a8UL 765#define NIG_REG_P1_RX_COS0_PRIORITY_MASK \ 766 0x181acUL 767#define NIG_REG_P1_RX_COS1_PRIORITY_MASK \ 768 0x181b0UL 769#define NIG_REG_P1_RX_COS2_PRIORITY_MASK \ 770 0x186f8UL 771#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB \ 772 0x186e8UL 773#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB \ 774 0x186ecUL 775#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT \ 776 0x18234UL 777#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ \ 778 0x18238UL 779#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 \ 780 0x18258UL 781#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 \ 782 0x1825cUL 783#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 \ 784 0x18260UL 785#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 \ 786 0x18264UL 787#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 \ 788 0x18268UL 789#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 \ 790 0x186f4UL 791#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 \ 792 0x18244UL 793#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 \ 794 0x18248UL 795#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 \ 796 0x1824cUL 797#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 \ 798 0x18250UL 799#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 \ 800 0x18254UL 801#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 \ 802 0x186f0UL 803#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS \ 804 0x18240UL 805#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB \ 806 0x186e0UL 807#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB \ 808 0x186e4UL 809#define NIG_REG_PAUSE_ENABLE_0 \ 810 0x160c0UL 811#define NIG_REG_PAUSE_ENABLE_1 \ 812 0x160c4UL 813#define NIG_REG_PORT_SWAP \ 814 0x10394UL 815#define NIG_REG_PPP_ENABLE_0 \ 816 0x160b0UL 817#define NIG_REG_PPP_ENABLE_1 \ 818 0x160b4UL 819#define NIG_REG_PRS_REQ_IN_EN \ 820 0x100b8UL 821#define NIG_REG_SERDES0_CTRL_MD_DEVAD \ 822 0x10370UL 823#define NIG_REG_SERDES0_CTRL_MD_ST \ 824 0x1036cUL 825#define NIG_REG_SERDES0_CTRL_PHY_ADDR \ 826 0x10374UL 827#define NIG_REG_SERDES0_STATUS_LINK_STATUS \ 828 0x10578UL 829#define NIG_REG_STAT0_BRB_DISCARD \ 830 0x105f0UL 831#define NIG_REG_STAT0_BRB_TRUNCATE \ 832 0x105f8UL 833#define NIG_REG_STAT0_EGRESS_MAC_PKT0 \ 834 0x10750UL 835#define NIG_REG_STAT0_EGRESS_MAC_PKT1 \ 836 0x10760UL 837#define NIG_REG_STAT1_BRB_DISCARD \ 838 0x10628UL 839#define NIG_REG_STAT1_EGRESS_MAC_PKT0 \ 840 0x107a0UL 841#define NIG_REG_STAT1_EGRESS_MAC_PKT1 \ 842 0x107b0UL 843#define NIG_REG_STAT2_BRB_OCTET \ 844 0x107e0UL 845#define NIG_REG_STATUS_INTERRUPT_PORT0 \ 846 0x10328UL 847#define NIG_REG_STRAP_OVERRIDE \ 848 0x10398UL 849#define NIG_REG_XCM0_OUT_EN \ 850 0x100f0UL 851#define NIG_REG_XCM1_OUT_EN \ 852 0x100f4UL 853#define NIG_REG_XGXS0_CTRL_MD_DEVAD \ 854 0x1033cUL 855#define NIG_REG_XGXS0_CTRL_MD_ST \ 856 0x10338UL 857#define NIG_REG_XGXS0_CTRL_PHY_ADDR \ 858 0x10340UL 859#define NIG_REG_XGXS0_STATUS_LINK10G \ 860 0x10680UL 861#define NIG_REG_XGXS0_STATUS_LINK_STATUS \ 862 0x10684UL 863#define NIG_REG_XGXS_LANE_SEL_P0 \ 864 0x102e8UL 865#define NIG_REG_XGXS_SERDES0_MODE_SEL \ 866 0x102e0UL 867#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT \ 868 (0x1<<0) 869#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS \ 870 (0x1<<9) 871#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G \ 872 (0x1<<15) 873#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS \ 874 (0xf<<18) 875#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE \ 876 18 877#define PBF_REG_COS0_UPPER_BOUND \ 878 0x15c05cUL 879#define PBF_REG_COS0_UPPER_BOUND_P0 \ 880 0x15c2ccUL 881#define PBF_REG_COS0_UPPER_BOUND_P1 \ 882 0x15c2e4UL 883#define PBF_REG_COS0_WEIGHT \ 884 0x15c054UL 885#define PBF_REG_COS0_WEIGHT_P0 \ 886 0x15c2a8UL 887#define PBF_REG_COS0_WEIGHT_P1 \ 888 0x15c2c0UL 889#define PBF_REG_COS1_UPPER_BOUND \ 890 0x15c060UL 891#define PBF_REG_COS1_WEIGHT \ 892 0x15c058UL 893#define PBF_REG_COS1_WEIGHT_P0 \ 894 0x15c2acUL 895#define PBF_REG_COS1_WEIGHT_P1 \ 896 0x15c2c4UL 897#define PBF_REG_COS2_WEIGHT_P0 \ 898 0x15c2b0UL 899#define PBF_REG_COS2_WEIGHT_P1 \ 900 0x15c2c8UL 901#define PBF_REG_COS3_WEIGHT_P0 \ 902 0x15c2b4UL 903#define PBF_REG_COS4_WEIGHT_P0 \ 904 0x15c2b8UL 905#define PBF_REG_COS5_WEIGHT_P0 \ 906 0x15c2bcUL 907#define PBF_REG_CREDIT_LB_Q \ 908 0x140338UL 909#define PBF_REG_CREDIT_Q0 \ 910 0x14033cUL 911#define PBF_REG_CREDIT_Q1 \ 912 0x140340UL 913#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 \ 914 0x14005cUL 915#define PBF_REG_DISABLE_PF \ 916 0x1402e8UL 917#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 \ 918 0x15c288UL 919#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 \ 920 0x15c28cUL 921#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 \ 922 0x15c278UL 923#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 \ 924 0x15c27cUL 925#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 \ 926 0x15c280UL 927#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 \ 928 0x15c284UL 929#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 \ 930 0x15c2a0UL 931#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 \ 932 0x15c2a4UL 933#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 \ 934 0x15c270UL 935#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 \ 936 0x15c274UL 937#define PBF_REG_ETS_ENABLED \ 938 0x15c050UL 939#define PBF_REG_HDRS_AFTER_BASIC \ 940 0x15c0a8UL 941#define PBF_REG_HDRS_AFTER_TAG_0 \ 942 0x15c0b8UL 943#define PBF_REG_HIGH_PRIORITY_COS_NUM \ 944 0x15c04cUL 945#define PBF_REG_INIT_CRD_LB_Q \ 946 0x15c248UL 947#define PBF_REG_INIT_CRD_Q0 \ 948 0x15c230UL 949#define PBF_REG_INIT_CRD_Q1 \ 950 0x15c234UL 951#define PBF_REG_INIT_P0 \ 952 0x140004UL 953#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q \ 954 0x140354UL 955#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 \ 956 0x140358UL 957#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 \ 958 0x14035cUL 959#define PBF_REG_MUST_HAVE_HDRS \ 960 0x15c0c4UL 961#define PBF_REG_NUM_STRICT_ARB_SLOTS \ 962 0x15c064UL 963#define PBF_REG_P0_ARB_THRSH \ 964 0x1400e4UL 965#define PBF_REG_P0_CREDIT \ 966 0x140200UL 967#define PBF_REG_P0_INIT_CRD \ 968 0x1400d0UL 969#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT \ 970 0x140308UL 971#define PBF_REG_P0_PAUSE_ENABLE \ 972 0x140014UL 973#define PBF_REG_P0_TQ_LINES_FREED_CNT \ 974 0x1402f0UL 975#define PBF_REG_P0_TQ_OCCUPANCY \ 976 0x1402fcUL 977#define PBF_REG_P1_CREDIT \ 978 0x140208UL 979#define PBF_REG_P1_INIT_CRD \ 980 0x1400d4UL 981#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT \ 982 0x14030cUL 983#define PBF_REG_P1_TQ_LINES_FREED_CNT \ 984 0x1402f4UL 985#define PBF_REG_P1_TQ_OCCUPANCY \ 986 0x140300UL 987#define PBF_REG_P4_CREDIT \ 988 0x140210UL 989#define PBF_REG_P4_INIT_CRD \ 990 0x1400e0UL 991#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT \ 992 0x140310UL 993#define PBF_REG_P4_TQ_LINES_FREED_CNT \ 994 0x1402f8UL 995#define PBF_REG_P4_TQ_OCCUPANCY \ 996 0x140304UL 997#define PBF_REG_PBF_INT_MASK \ 998 0x1401d4UL 999#define PBF_REG_PBF_PRTY_MASK \ 1000 0x1401e4UL 1001#define PBF_REG_PBF_PRTY_STS_CLR \ 1002 0x1401dcUL 1003#define PBF_REG_TAG_ETHERTYPE_0 \ 1004 0x15c090UL 1005#define PBF_REG_TAG_LEN_0 \ 1006 0x15c09cUL 1007#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q \ 1008 0x14038cUL 1009#define PBF_REG_TQ_LINES_FREED_CNT_Q0 \ 1010 0x140390UL 1011#define PBF_REG_TQ_LINES_FREED_CNT_Q1 \ 1012 0x140394UL 1013#define PBF_REG_TQ_OCCUPANCY_LB_Q \ 1014 0x1403a8UL 1015#define PBF_REG_TQ_OCCUPANCY_Q0 \ 1016 0x1403acUL 1017#define PBF_REG_TQ_OCCUPANCY_Q1 \ 1018 0x1403b0UL 1019#define PB_REG_PB_INT_MASK \ 1020 0x28UL 1021#define PB_REG_PB_PRTY_MASK \ 1022 0x38UL 1023#define PB_REG_PB_PRTY_STS_CLR \ 1024 0x30UL 1025#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR \ 1026 (0x1<<0) 1027#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW \ 1028 (0x1<<8) 1029#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR \ 1030 (0x1<<1) 1031#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN \ 1032 (0x1<<6) 1033#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN \ 1034 (0x1<<7) 1035#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN \ 1036 (0x1<<4) 1037#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN \ 1038 (0x1<<3) 1039#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN \ 1040 (0x1<<5) 1041#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN \ 1042 (0x1<<2) 1043#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR \ 1044 0x9418UL 1045#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 1046 0x942cUL 1047#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 1048 0x9430UL 1049#define PGLUE_B_REG_PGLUE_B_INT_STS \ 1050 0x9298UL 1051#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR \ 1052 0x929cUL 1053#define PGLUE_B_REG_PGLUE_B_PRTY_MASK \ 1054 0x92b4UL 1055#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR \ 1056 0x92acUL 1057#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR \ 1058 0x9458UL 1059#define PGLUE_B_REG_TAGS_63_32 \ 1060 0x9244UL 1061#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR \ 1062 0x9470UL 1063#define PRS_REG_A_PRSU_20 \ 1064 0x40134UL 1065#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT \ 1066 0x4011cUL 1067#define PRS_REG_E1HOV_MODE \ 1068 0x401c8UL 1069#define PRS_REG_HDRS_AFTER_BASIC \ 1070 0x40238UL 1071#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 \ 1072 0x40270UL 1073#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 \ 1074 0x40290UL 1075#define PRS_REG_HDRS_AFTER_TAG_0 \ 1076 0x40248UL 1077#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 \ 1078 0x40280UL 1079#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 \ 1080 0x402a0UL 1081#define PRS_REG_MUST_HAVE_HDRS \ 1082 0x40254UL 1083#define PRS_REG_MUST_HAVE_HDRS_PORT_0 \ 1084 0x4028cUL 1085#define PRS_REG_MUST_HAVE_HDRS_PORT_1 \ 1086 0x402acUL 1087#define PRS_REG_NIC_MODE \ 1088 0x40138UL 1089#define PRS_REG_NUM_OF_PACKETS \ 1090 0x40124UL 1091#define PRS_REG_PRS_PRTY_MASK \ 1092 0x401a4UL 1093#define PRS_REG_PRS_PRTY_STS_CLR \ 1094 0x4019cUL 1095#define PRS_REG_TAG_ETHERTYPE_0 \ 1096 0x401d4UL 1097#define PRS_REG_TAG_LEN_0 \ 1098 0x4022cUL 1099#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT \ 1100 (0x1<<19) 1101#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF \ 1102 (0x1<<20) 1103#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN \ 1104 (0x1<<22) 1105#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED \ 1106 (0x1<<23) 1107#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED \ 1108 (0x1<<24) 1109#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR \ 1110 (0x1<<7) 1111#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR \ 1112 (0x1<<7) 1113#define PXP2_REG_PGL_ADDR_88_F0 \ 1114 0x120534UL 1115#define PXP2_REG_PGL_ADDR_88_F1 \ 1116 0x120544UL 1117#define PXP2_REG_PGL_ADDR_8C_F0 \ 1118 0x120538UL 1119#define PXP2_REG_PGL_ADDR_8C_F1 \ 1120 0x120548UL 1121#define PXP2_REG_PGL_ADDR_90_F0 \ 1122 0x12053cUL 1123#define PXP2_REG_PGL_ADDR_90_F1 \ 1124 0x12054cUL 1125#define PXP2_REG_PGL_ADDR_94_F0 \ 1126 0x120540UL 1127#define PXP2_REG_PGL_ADDR_94_F1 \ 1128 0x120550UL 1129#define PXP2_REG_PGL_EXP_ROM2 \ 1130 0x120808UL 1131#define PXP2_REG_PGL_PRETEND_FUNC_F0 \ 1132 0x120674UL 1133#define PXP2_REG_PGL_PRETEND_FUNC_F1 \ 1134 0x120678UL 1135#define PXP2_REG_PGL_TAGS_LIMIT \ 1136 0x1205a8UL 1137#define PXP2_REG_PSWRQ_BW_ADD1 \ 1138 0x1201c0UL 1139#define PXP2_REG_PSWRQ_BW_ADD10 \ 1140 0x1201e4UL 1141#define PXP2_REG_PSWRQ_BW_ADD11 \ 1142 0x1201e8UL 1143#define PXP2_REG_PSWRQ_BW_ADD2 \ 1144 0x1201c4UL 1145#define PXP2_REG_PSWRQ_BW_ADD28 \ 1146 0x120228UL 1147#define PXP2_REG_PSWRQ_BW_ADD3 \ 1148 0x1201c8UL 1149#define PXP2_REG_PSWRQ_BW_ADD6 \ 1150 0x1201d4UL 1151#define PXP2_REG_PSWRQ_BW_ADD7 \ 1152 0x1201d8UL 1153#define PXP2_REG_PSWRQ_BW_ADD8 \ 1154 0x1201dcUL 1155#define PXP2_REG_PSWRQ_BW_ADD9 \ 1156 0x1201e0UL 1157#define PXP2_REG_PSWRQ_BW_L1 \ 1158 0x1202b0UL 1159#define PXP2_REG_PSWRQ_BW_L10 \ 1160 0x1202d4UL 1161#define PXP2_REG_PSWRQ_BW_L11 \ 1162 0x1202d8UL 1163#define PXP2_REG_PSWRQ_BW_L2 \ 1164 0x1202b4UL 1165#define PXP2_REG_PSWRQ_BW_L28 \ 1166 0x120318UL 1167#define PXP2_REG_PSWRQ_BW_L3 \ 1168 0x1202b8UL 1169#define PXP2_REG_PSWRQ_BW_L6 \ 1170 0x1202c4UL 1171#define PXP2_REG_PSWRQ_BW_L7 \ 1172 0x1202c8UL 1173#define PXP2_REG_PSWRQ_BW_L8 \ 1174 0x1202ccUL 1175#define PXP2_REG_PSWRQ_BW_L9 \ 1176 0x1202d0UL 1177#define PXP2_REG_PSWRQ_BW_RD \ 1178 0x120324UL 1179#define PXP2_REG_PSWRQ_BW_UB1 \ 1180 0x120238UL 1181#define PXP2_REG_PSWRQ_BW_UB10 \ 1182 0x12025cUL 1183#define PXP2_REG_PSWRQ_BW_UB11 \ 1184 0x120260UL 1185#define PXP2_REG_PSWRQ_BW_UB2 \ 1186 0x12023cUL 1187#define PXP2_REG_PSWRQ_BW_UB28 \ 1188 0x1202a0UL 1189#define PXP2_REG_PSWRQ_BW_UB3 \ 1190 0x120240UL 1191#define PXP2_REG_PSWRQ_BW_UB6 \ 1192 0x12024cUL 1193#define PXP2_REG_PSWRQ_BW_UB7 \ 1194 0x120250UL 1195#define PXP2_REG_PSWRQ_BW_UB8 \ 1196 0x120254UL 1197#define PXP2_REG_PSWRQ_BW_UB9 \ 1198 0x120258UL 1199#define PXP2_REG_PSWRQ_BW_WR \ 1200 0x120328UL 1201#define PXP2_REG_PSWRQ_CDU0_L2P \ 1202 0x120000UL 1203#define PXP2_REG_PSWRQ_QM0_L2P \ 1204 0x120038UL 1205#define PXP2_REG_PSWRQ_SRC0_L2P \ 1206 0x120054UL 1207#define PXP2_REG_PSWRQ_TM0_L2P \ 1208 0x12001cUL 1209#define PXP2_REG_PXP2_INT_MASK_0 \ 1210 0x120578UL 1211#define PXP2_REG_PXP2_INT_MASK_1 \ 1212 0x120614UL 1213#define PXP2_REG_PXP2_INT_STS_0 \ 1214 0x12056cUL 1215#define PXP2_REG_PXP2_INT_STS_1 \ 1216 0x120608UL 1217#define PXP2_REG_PXP2_INT_STS_CLR_0 \ 1218 0x120570UL 1219#define PXP2_REG_PXP2_PRTY_MASK_0 \ 1220 0x120588UL 1221#define PXP2_REG_PXP2_PRTY_MASK_1 \ 1222 0x120598UL 1223#define PXP2_REG_PXP2_PRTY_STS_CLR_0 \ 1224 0x120580UL 1225#define PXP2_REG_PXP2_PRTY_STS_CLR_1 \ 1226 0x120590UL 1227#define PXP2_REG_RD_BLK_CNT \ 1228 0x120418UL 1229#define PXP2_REG_RD_CDURD_SWAP_MODE \ 1230 0x120404UL 1231#define PXP2_REG_RD_DISABLE_INPUTS \ 1232 0x120374UL 1233#define PXP2_REG_RD_INIT_DONE \ 1234 0x120370UL 1235#define PXP2_REG_RD_PBF_SWAP_MODE \ 1236 0x1203f4UL 1237#define PXP2_REG_RD_PORT_IS_IDLE_0 \ 1238 0x12041cUL 1239#define PXP2_REG_RD_PORT_IS_IDLE_1 \ 1240 0x120420UL 1241#define PXP2_REG_RD_QM_SWAP_MODE \ 1242 0x1203f8UL 1243#define PXP2_REG_RD_SRC_SWAP_MODE \ 1244 0x120400UL 1245#define PXP2_REG_RD_SR_CNT \ 1246 0x120414UL 1247#define PXP2_REG_RD_START_INIT \ 1248 0x12036cUL 1249#define PXP2_REG_RD_TM_SWAP_MODE \ 1250 0x1203fcUL 1251#define PXP2_REG_RQ_BW_RD_ADD0 \ 1252 0x1201bcUL 1253#define PXP2_REG_RQ_BW_RD_ADD12 \ 1254 0x1201ecUL 1255#define PXP2_REG_RQ_BW_RD_ADD13 \ 1256 0x1201f0UL 1257#define PXP2_REG_RQ_BW_RD_ADD14 \ 1258 0x1201f4UL 1259#define PXP2_REG_RQ_BW_RD_ADD15 \ 1260 0x1201f8UL 1261#define PXP2_REG_RQ_BW_RD_ADD16 \ 1262 0x1201fcUL 1263#define PXP2_REG_RQ_BW_RD_ADD17 \ 1264 0x120200UL 1265#define PXP2_REG_RQ_BW_RD_ADD18 \ 1266 0x120204UL 1267#define PXP2_REG_RQ_BW_RD_ADD19 \ 1268 0x120208UL 1269#define PXP2_REG_RQ_BW_RD_ADD20 \ 1270 0x12020cUL 1271#define PXP2_REG_RQ_BW_RD_ADD22 \ 1272 0x120210UL 1273#define PXP2_REG_RQ_BW_RD_ADD23 \ 1274 0x120214UL 1275#define PXP2_REG_RQ_BW_RD_ADD24 \ 1276 0x120218UL 1277#define PXP2_REG_RQ_BW_RD_ADD25 \ 1278 0x12021cUL 1279#define PXP2_REG_RQ_BW_RD_ADD26 \ 1280 0x120220UL 1281#define PXP2_REG_RQ_BW_RD_ADD27 \ 1282 0x120224UL 1283#define PXP2_REG_RQ_BW_RD_ADD4 \ 1284 0x1201ccUL 1285#define PXP2_REG_RQ_BW_RD_ADD5 \ 1286 0x1201d0UL 1287#define PXP2_REG_RQ_BW_RD_L0 \ 1288 0x1202acUL 1289#define PXP2_REG_RQ_BW_RD_L12 \ 1290 0x1202dcUL 1291#define PXP2_REG_RQ_BW_RD_L13 \ 1292 0x1202e0UL 1293#define PXP2_REG_RQ_BW_RD_L14 \ 1294 0x1202e4UL 1295#define PXP2_REG_RQ_BW_RD_L15 \ 1296 0x1202e8UL 1297#define PXP2_REG_RQ_BW_RD_L16 \ 1298 0x1202ecUL 1299#define PXP2_REG_RQ_BW_RD_L17 \ 1300 0x1202f0UL 1301#define PXP2_REG_RQ_BW_RD_L18 \ 1302 0x1202f4UL 1303#define PXP2_REG_RQ_BW_RD_L19 \ 1304 0x1202f8UL 1305#define PXP2_REG_RQ_BW_RD_L20 \ 1306 0x1202fcUL 1307#define PXP2_REG_RQ_BW_RD_L22 \ 1308 0x120300UL 1309#define PXP2_REG_RQ_BW_RD_L23 \ 1310 0x120304UL 1311#define PXP2_REG_RQ_BW_RD_L24 \ 1312 0x120308UL 1313#define PXP2_REG_RQ_BW_RD_L25 \ 1314 0x12030cUL 1315#define PXP2_REG_RQ_BW_RD_L26 \ 1316 0x120310UL 1317#define PXP2_REG_RQ_BW_RD_L27 \ 1318 0x120314UL 1319#define PXP2_REG_RQ_BW_RD_L4 \ 1320 0x1202bcUL 1321#define PXP2_REG_RQ_BW_RD_L5 \ 1322 0x1202c0UL 1323#define PXP2_REG_RQ_BW_RD_UBOUND0 \ 1324 0x120234UL 1325#define PXP2_REG_RQ_BW_RD_UBOUND12 \ 1326 0x120264UL 1327#define PXP2_REG_RQ_BW_RD_UBOUND13 \ 1328 0x120268UL 1329#define PXP2_REG_RQ_BW_RD_UBOUND14 \ 1330 0x12026cUL 1331#define PXP2_REG_RQ_BW_RD_UBOUND15 \ 1332 0x120270UL 1333#define PXP2_REG_RQ_BW_RD_UBOUND16 \ 1334 0x120274UL 1335#define PXP2_REG_RQ_BW_RD_UBOUND17 \ 1336 0x120278UL 1337#define PXP2_REG_RQ_BW_RD_UBOUND18 \ 1338 0x12027cUL 1339#define PXP2_REG_RQ_BW_RD_UBOUND19 \ 1340 0x120280UL 1341#define PXP2_REG_RQ_BW_RD_UBOUND20 \ 1342 0x120284UL 1343#define PXP2_REG_RQ_BW_RD_UBOUND22 \ 1344 0x120288UL 1345#define PXP2_REG_RQ_BW_RD_UBOUND23 \ 1346 0x12028cUL 1347#define PXP2_REG_RQ_BW_RD_UBOUND24 \ 1348 0x120290UL 1349#define PXP2_REG_RQ_BW_RD_UBOUND25 \ 1350 0x120294UL 1351#define PXP2_REG_RQ_BW_RD_UBOUND26 \ 1352 0x120298UL 1353#define PXP2_REG_RQ_BW_RD_UBOUND27 \ 1354 0x12029cUL 1355#define PXP2_REG_RQ_BW_RD_UBOUND4 \ 1356 0x120244UL 1357#define PXP2_REG_RQ_BW_RD_UBOUND5 \ 1358 0x120248UL 1359#define PXP2_REG_RQ_BW_WR_ADD29 \ 1360 0x12022cUL 1361#define PXP2_REG_RQ_BW_WR_ADD30 \ 1362 0x120230UL 1363#define PXP2_REG_RQ_BW_WR_L29 \ 1364 0x12031cUL 1365#define PXP2_REG_RQ_BW_WR_L30 \ 1366 0x120320UL 1367#define PXP2_REG_RQ_BW_WR_UBOUND29 \ 1368 0x1202a4UL 1369#define PXP2_REG_RQ_BW_WR_UBOUND30 \ 1370 0x1202a8UL 1371#define PXP2_REG_RQ_CDU_ENDIAN_M \ 1372 0x1201a0UL 1373#define PXP2_REG_RQ_CDU_FIRST_ILT \ 1374 0x12061cUL 1375#define PXP2_REG_RQ_CDU_LAST_ILT \ 1376 0x120620UL 1377#define PXP2_REG_RQ_CDU_P_SIZE \ 1378 0x120018UL 1379#define PXP2_REG_RQ_CFG_DONE \ 1380 0x1201b4UL 1381#define PXP2_REG_RQ_DBG_ENDIAN_M \ 1382 0x1201a4UL 1383#define PXP2_REG_RQ_DISABLE_INPUTS \ 1384 0x120330UL 1385#define PXP2_REG_RQ_DRAM_ALIGN \ 1386 0x1205b0UL 1387#define PXP2_REG_RQ_DRAM_ALIGN_RD \ 1388 0x12092cUL 1389#define PXP2_REG_RQ_DRAM_ALIGN_SEL \ 1390 0x120930UL 1391#define PXP2_REG_RQ_HC_ENDIAN_M \ 1392 0x1201a8UL 1393#define PXP2_REG_RQ_ONCHIP_AT \ 1394 0x122000UL 1395#define PXP2_REG_RQ_ONCHIP_AT_B0 \ 1396 0x128000UL 1397#define PXP2_REG_RQ_PDR_LIMIT \ 1398 0x12033cUL 1399#define PXP2_REG_RQ_QM_ENDIAN_M \ 1400 0x120194UL 1401#define PXP2_REG_RQ_QM_FIRST_ILT \ 1402 0x120634UL 1403#define PXP2_REG_RQ_QM_LAST_ILT \ 1404 0x120638UL 1405#define PXP2_REG_RQ_QM_P_SIZE \ 1406 0x120050UL 1407#define PXP2_REG_RQ_RBC_DONE \ 1408 0x1201b0UL 1409#define PXP2_REG_RQ_RD_MBS0 \ 1410 0x120160UL 1411#define PXP2_REG_RQ_RD_MBS1 \ 1412 0x120168UL 1413#define PXP2_REG_RQ_SRC_ENDIAN_M \ 1414 0x12019cUL 1415#define PXP2_REG_RQ_SRC_FIRST_ILT \ 1416 0x12063cUL 1417#define PXP2_REG_RQ_SRC_LAST_ILT \ 1418 0x120640UL 1419#define PXP2_REG_RQ_SRC_P_SIZE \ 1420 0x12006cUL 1421#define PXP2_REG_RQ_TM_ENDIAN_M \ 1422 0x120198UL 1423#define PXP2_REG_RQ_TM_FIRST_ILT \ 1424 0x120644UL 1425#define PXP2_REG_RQ_TM_LAST_ILT \ 1426 0x120648UL 1427#define PXP2_REG_RQ_TM_P_SIZE \ 1428 0x120034UL 1429#define PXP2_REG_RQ_WR_MBS0 \ 1430 0x12015cUL 1431#define PXP2_REG_RQ_WR_MBS1 \ 1432 0x120164UL 1433#define PXP2_REG_WR_CDU_MPS \ 1434 0x1205f0UL 1435#define PXP2_REG_WR_CSDM_MPS \ 1436 0x1205d0UL 1437#define PXP2_REG_WR_DBG_MPS \ 1438 0x1205e8UL 1439#define PXP2_REG_WR_DMAE_MPS \ 1440 0x1205ecUL 1441#define PXP2_REG_WR_HC_MPS \ 1442 0x1205c8UL 1443#define PXP2_REG_WR_QM_MPS \ 1444 0x1205dcUL 1445#define PXP2_REG_WR_SRC_MPS \ 1446 0x1205e4UL 1447#define PXP2_REG_WR_TM_MPS \ 1448 0x1205e0UL 1449#define PXP2_REG_WR_TSDM_MPS \ 1450 0x1205d4UL 1451#define PXP2_REG_WR_USDMDP_TH \ 1452 0x120348UL 1453#define PXP2_REG_WR_USDM_MPS \ 1454 0x1205ccUL 1455#define PXP2_REG_WR_XSDM_MPS \ 1456 0x1205d8UL 1457#define PXP_REG_HST_DISCARD_DOORBELLS \ 1458 0x1030a4UL 1459#define PXP_REG_HST_DISCARD_INTERNAL_WRITES \ 1460 0x1030a8UL 1461#define PXP_REG_PXP_INT_MASK_0 \ 1462 0x103074UL 1463#define PXP_REG_PXP_INT_MASK_1 \ 1464 0x103084UL 1465#define PXP_REG_PXP_INT_STS_CLR_0 \ 1466 0x10306cUL 1467#define PXP_REG_PXP_INT_STS_CLR_1 \ 1468 0x10307cUL 1469#define PXP_REG_PXP_PRTY_MASK \ 1470 0x103094UL 1471#define PXP_REG_PXP_PRTY_STS_CLR \ 1472 0x10308cUL 1473#define QM_REG_BASEADDR \ 1474 0x168900UL 1475#define QM_REG_BASEADDR_EXT_A \ 1476 0x16e100UL 1477#define QM_REG_BYTECRDCMDQ_0 \ 1478 0x16e6e8UL 1479#define QM_REG_CONNNUM_0 \ 1480 0x168020UL 1481#define QM_REG_PF_EN \ 1482 0x16e70cUL 1483#define QM_REG_PF_USG_CNT_0 \ 1484 0x16e040UL 1485#define QM_REG_PTRTBL \ 1486 0x168a00UL 1487#define QM_REG_PTRTBL_EXT_A \ 1488 0x16e200UL 1489#define QM_REG_QM_INT_MASK \ 1490 0x168444UL 1491#define QM_REG_QM_PRTY_MASK \ 1492 0x168454UL 1493#define QM_REG_QM_PRTY_STS_CLR \ 1494 0x16844cUL 1495#define QM_REG_QVOQIDX_0 \ 1496 0x1680f4UL 1497#define QM_REG_SOFT_RESET \ 1498 0x168428UL 1499#define QM_REG_VOQQMASK_0_LSB \ 1500 0x168240UL 1501#define SEM_FAST_REG_PARITY_RST \ 1502 0x18840UL 1503#define SRC_REG_COUNTFREE0 \ 1504 0x40500UL 1505#define SRC_REG_FIRSTFREE0 \ 1506 0x40510UL 1507#define SRC_REG_KEYSEARCH_0 \ 1508 0x40458UL 1509#define SRC_REG_KEYSEARCH_1 \ 1510 0x4045cUL 1511#define SRC_REG_KEYSEARCH_2 \ 1512 0x40460UL 1513#define SRC_REG_KEYSEARCH_3 \ 1514 0x40464UL 1515#define SRC_REG_KEYSEARCH_4 \ 1516 0x40468UL 1517#define SRC_REG_KEYSEARCH_5 \ 1518 0x4046cUL 1519#define SRC_REG_KEYSEARCH_6 \ 1520 0x40470UL 1521#define SRC_REG_KEYSEARCH_7 \ 1522 0x40474UL 1523#define SRC_REG_KEYSEARCH_8 \ 1524 0x40478UL 1525#define SRC_REG_KEYSEARCH_9 \ 1526 0x4047cUL 1527#define SRC_REG_LASTFREE0 \ 1528 0x40530UL 1529#define SRC_REG_NUMBER_HASH_BITS0 \ 1530 0x40400UL 1531#define SRC_REG_SOFT_RST \ 1532 0x4049cUL 1533#define SRC_REG_SRC_PRTY_MASK \ 1534 0x404c8UL 1535#define SRC_REG_SRC_PRTY_STS_CLR \ 1536 0x404c0UL 1537#define TCM_REG_PRS_IFEN \ 1538 0x50020UL 1539#define TCM_REG_TCM_INT_MASK \ 1540 0x501dcUL 1541#define TCM_REG_TCM_PRTY_MASK \ 1542 0x501ecUL 1543#define TCM_REG_TCM_PRTY_STS_CLR \ 1544 0x501e4UL 1545#define TM_REG_EN_LINEAR0_TIMER \ 1546 0x164014UL 1547#define TM_REG_LIN0_MAX_ACTIVE_CID \ 1548 0x164048UL 1549#define TM_REG_LIN0_NUM_SCANS \ 1550 0x1640a0UL 1551#define TM_REG_LIN0_SCAN_ON \ 1552 0x1640d0UL 1553#define TM_REG_LIN0_SCAN_TIME \ 1554 0x16403cUL 1555#define TM_REG_LIN0_VNIC_UC \ 1556 0x164128UL 1557#define TM_REG_TM_INT_MASK \ 1558 0x1640fcUL 1559#define TM_REG_TM_PRTY_MASK \ 1560 0x16410cUL 1561#define TM_REG_TM_PRTY_STS_CLR \ 1562 0x164104UL 1563#define TSDM_REG_ENABLE_IN1 \ 1564 0x42238UL 1565#define TSDM_REG_TSDM_INT_MASK_0 \ 1566 0x4229cUL 1567#define TSDM_REG_TSDM_INT_MASK_1 \ 1568 0x422acUL 1569#define TSDM_REG_TSDM_PRTY_MASK \ 1570 0x422bcUL 1571#define TSDM_REG_TSDM_PRTY_STS_CLR \ 1572 0x422b4UL 1573#define TSEM_REG_FAST_MEMORY \ 1574 0x1a0000UL 1575#define TSEM_REG_INT_TABLE \ 1576 0x180400UL 1577#define TSEM_REG_PASSIVE_BUFFER \ 1578 0x181000UL 1579#define TSEM_REG_PRAM \ 1580 0x1c0000UL 1581#define TSEM_REG_TSEM_INT_MASK_0 \ 1582 0x180100UL 1583#define TSEM_REG_TSEM_INT_MASK_1 \ 1584 0x180110UL 1585#define TSEM_REG_TSEM_PRTY_MASK_0 \ 1586 0x180120UL 1587#define TSEM_REG_TSEM_PRTY_MASK_1 \ 1588 0x180130UL 1589#define TSEM_REG_TSEM_PRTY_STS_CLR_0 \ 1590 0x180118UL 1591#define TSEM_REG_TSEM_PRTY_STS_CLR_1 \ 1592 0x180128UL 1593#define TSEM_REG_VFPF_ERR_NUM \ 1594 0x180380UL 1595#define UCM_REG_UCM_INT_MASK \ 1596 0xe01d4UL 1597#define UCM_REG_UCM_PRTY_MASK \ 1598 0xe01e4UL 1599#define UCM_REG_UCM_PRTY_STS_CLR \ 1600 0xe01dcUL 1601#define UMAC_COMMAND_CONFIG_REG_HD_ENA \ 1602 (0x1<<10) 1603#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE \ 1604 (0x1<<28) 1605#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA \ 1606 (0x1<<15) 1607#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK \ 1608 (0x1<<24) 1609#define UMAC_COMMAND_CONFIG_REG_PAD_EN \ 1610 (0x1<<5) 1611#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE \ 1612 (0x1<<8) 1613#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN \ 1614 (0x1<<4) 1615#define UMAC_COMMAND_CONFIG_REG_RX_ENA \ 1616 (0x1<<1) 1617#define UMAC_COMMAND_CONFIG_REG_SW_RESET \ 1618 (0x1<<13) 1619#define UMAC_COMMAND_CONFIG_REG_TX_ENA \ 1620 (0x1<<0) 1621#define UMAC_REG_COMMAND_CONFIG \ 1622 0x8UL 1623#define UMAC_REG_EEE_WAKE_TIMER \ 1624 0x6cUL 1625#define UMAC_REG_MAC_ADDR0 \ 1626 0xcUL 1627#define UMAC_REG_MAC_ADDR1 \ 1628 0x10UL 1629#define UMAC_REG_MAXFR \ 1630 0x14UL 1631#define UMAC_REG_UMAC_EEE_CTRL \ 1632 0x64UL 1633#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN \ 1634 (0x1<<3) 1635#define USDM_REG_USDM_INT_MASK_0 \ 1636 0xc42a0UL 1637#define USDM_REG_USDM_INT_MASK_1 \ 1638 0xc42b0UL 1639#define USDM_REG_USDM_PRTY_MASK \ 1640 0xc42c0UL 1641#define USDM_REG_USDM_PRTY_STS_CLR \ 1642 0xc42b8UL 1643#define USEM_REG_FAST_MEMORY \ 1644 0x320000UL 1645#define USEM_REG_INT_TABLE \ 1646 0x300400UL 1647#define USEM_REG_PASSIVE_BUFFER \ 1648 0x302000UL 1649#define USEM_REG_PRAM \ 1650 0x340000UL 1651#define USEM_REG_USEM_INT_MASK_0 \ 1652 0x300110UL 1653#define USEM_REG_USEM_INT_MASK_1 \ 1654 0x300120UL 1655#define USEM_REG_USEM_PRTY_MASK_0 \ 1656 0x300130UL 1657#define USEM_REG_USEM_PRTY_MASK_1 \ 1658 0x300140UL 1659#define USEM_REG_USEM_PRTY_STS_CLR_0 \ 1660 0x300128UL 1661#define USEM_REG_USEM_PRTY_STS_CLR_1 \ 1662 0x300138UL 1663#define USEM_REG_VFPF_ERR_NUM \ 1664 0x300380UL 1665#define VFC_MEMORIES_RST_REG_CAM_RST \ 1666 (0x1<<0) 1667#define VFC_MEMORIES_RST_REG_RAM_RST \ 1668 (0x1<<1) 1669#define VFC_REG_MEMORIES_RST \ 1670 0x1943cUL 1671#define XCM_REG_XCM_INT_MASK \ 1672 0x202b4UL 1673#define XCM_REG_XCM_PRTY_MASK \ 1674 0x202c4UL 1675#define XCM_REG_XCM_PRTY_STS_CLR \ 1676 0x202bcUL 1677#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS \ 1678 (0x1<<0) 1679#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS \ 1680 (0x1<<1) 1681#define XMAC_CTRL_REG_LINE_LOCAL_LPBK \ 1682 (0x1<<2) 1683#define XMAC_CTRL_REG_RX_EN \ 1684 (0x1<<1) 1685#define XMAC_CTRL_REG_SOFT_RESET \ 1686 (0x1<<6) 1687#define XMAC_CTRL_REG_TX_EN \ 1688 (0x1<<0) 1689#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB \ 1690 (0x1<<7) 1691#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN \ 1692 (0x1<<18) 1693#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN \ 1694 (0x1<<17) 1695#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON \ 1696 (0x1<<1) 1697#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN \ 1698 (0x1<<0) 1699#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN \ 1700 (0x1<<3) 1701#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN \ 1702 (0x1<<4) 1703#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN \ 1704 (0x1<<5) 1705#define XMAC_REG_CLEAR_RX_LSS_STATUS \ 1706 0x60UL 1707#define XMAC_REG_CTRL \ 1708 0UL 1709#define XMAC_REG_CTRL_SA_HI \ 1710 0x2cUL 1711#define XMAC_REG_CTRL_SA_LO \ 1712 0x28UL 1713#define XMAC_REG_EEE_CTRL \ 1714 0xd8UL 1715#define XMAC_REG_EEE_TIMERS_HI \ 1716 0xe4UL 1717#define XMAC_REG_PAUSE_CTRL \ 1718 0x68UL 1719#define XMAC_REG_PFC_CTRL \ 1720 0x70UL 1721#define XMAC_REG_PFC_CTRL_HI \ 1722 0x74UL 1723#define XMAC_REG_RX_LSS_CTRL \ 1724 0x50UL 1725#define XMAC_REG_RX_LSS_STATUS \ 1726 0x58UL 1727#define XMAC_REG_RX_MAX_SIZE \ 1728 0x40UL 1729#define XMAC_REG_TX_CTRL \ 1730 0x20UL 1731#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE \ 1732 (0x1<<0) 1733#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE \ 1734 (0x1<<1) 1735#define XSDM_REG_OPERATION_GEN \ 1736 0x1664c4UL 1737#define XSDM_REG_XSDM_INT_MASK_0 \ 1738 0x16629cUL 1739#define XSDM_REG_XSDM_INT_MASK_1 \ 1740 0x1662acUL 1741#define XSDM_REG_XSDM_PRTY_MASK \ 1742 0x1662bcUL 1743#define XSDM_REG_XSDM_PRTY_STS_CLR \ 1744 0x1662b4UL 1745#define XSEM_REG_FAST_MEMORY \ 1746 0x2a0000UL 1747#define XSEM_REG_INT_TABLE \ 1748 0x280400UL 1749#define XSEM_REG_PASSIVE_BUFFER \ 1750 0x282000UL 1751#define XSEM_REG_PRAM \ 1752 0x2c0000UL 1753#define XSEM_REG_VFPF_ERR_NUM \ 1754 0x280380UL 1755#define XSEM_REG_XSEM_INT_MASK_0 \ 1756 0x280110UL 1757#define XSEM_REG_XSEM_INT_MASK_1 \ 1758 0x280120UL 1759#define XSEM_REG_XSEM_PRTY_MASK_0 \ 1760 0x280130UL 1761#define XSEM_REG_XSEM_PRTY_MASK_1 \ 1762 0x280140UL 1763#define XSEM_REG_XSEM_PRTY_STS_CLR_0 \ 1764 0x280128UL 1765#define XSEM_REG_XSEM_PRTY_STS_CLR_1 \ 1766 0x280138UL 1767#define MCPR_ACCESS_LOCK_LOCK (1L<<31) 1768#define MCPR_IMC_COMMAND_ENABLE (1L<<31) 1769#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16 1770#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28 1771#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8 1772#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) 1773#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 1774#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1775#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) 1776#define MCPR_NVM_COMMAND_DOIT (1L<<4) 1777#define MCPR_NVM_COMMAND_DONE (1L<<3) 1778#define MCPR_NVM_COMMAND_FIRST (1L<<7) 1779#define MCPR_NVM_COMMAND_LAST (1L<<8) 1780#define MCPR_NVM_COMMAND_WR (1L<<5) 1781#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) 1782#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 1783#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 1784 1785 1786#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) 1787#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 1788#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) 1789#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) 1790#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) 1791#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3) 1792#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) 1793#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) 1794#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) 1795#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) 1796#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) 1797#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) 1798#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 1799#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 1800#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 1801#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3) 1802#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 1803#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3) 1804#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) 1805#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) 1806#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) 1807#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3) 1808#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) 1809#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3) 1810#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3) 1811#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3) 1812#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3) 1813#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3) 1814#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3) 1815#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3) 1816#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3) 1817 1818 1819#define EMAC_LED_1000MB_OVERRIDE (1L<<1) 1820#define EMAC_LED_100MB_OVERRIDE (1L<<2) 1821#define EMAC_LED_10MB_OVERRIDE (1L<<3) 1822#define EMAC_LED_OVERRIDE (1L<<0) 1823#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 1824#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26) 1825#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 1826#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26) 1827#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 1828#define EMAC_MDIO_COMM_DATA (0xffffL<<0) 1829#define EMAC_MDIO_COMM_START_BUSY (1L<<29) 1830#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 1831#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) 1832#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16) 1833#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 1834#define EMAC_MDIO_STATUS_10MB (1L<<1) 1835#define EMAC_MODE_25G_MODE (1L<<5) 1836#define EMAC_MODE_HALF_DUPLEX (1L<<1) 1837#define EMAC_MODE_PORT_GMII (2L<<2) 1838#define EMAC_MODE_PORT_MII (1L<<2) 1839#define EMAC_MODE_PORT_MII_10M (3L<<2) 1840#define EMAC_MODE_RESET (1L<<0) 1841#define EMAC_REG_EMAC_LED 0xc 1842#define EMAC_REG_EMAC_MAC_MATCH 0x10 1843#define EMAC_REG_EMAC_MDIO_COMM 0xac 1844#define EMAC_REG_EMAC_MDIO_MODE 0xb4 1845#define EMAC_REG_EMAC_MDIO_STATUS 0xb0 1846#define EMAC_REG_EMAC_MODE 0x0 1847#define EMAC_REG_EMAC_RX_MODE 0xc8 1848#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c 1849#define EMAC_REG_EMAC_RX_STAT_AC 0x180 1850#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 1851#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 1852#define EMAC_REG_EMAC_TX_MODE 0xbc 1853#define EMAC_REG_EMAC_TX_STAT_AC 0x280 1854#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 1855#define EMAC_REG_RX_PFC_MODE 0x320 1856#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2) 1857#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1) 1858#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0) 1859#define EMAC_REG_RX_PFC_PARAM 0x324 1860#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0 1861#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16 1862#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328 1863#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0) 1864#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330 1865#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0) 1866#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c 1867#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0) 1868#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334 1869#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0) 1870#define EMAC_RX_MODE_FLOW_EN (1L<<2) 1871#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 1872#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 1873#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 1874#define EMAC_RX_MODE_RESET (1L<<0) 1875#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 1876#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 1877#define EMAC_TX_MODE_FLOW_EN (1L<<4) 1878#define EMAC_TX_MODE_RESET (1L<<0) 1879 1880 1881#define MISC_REGISTERS_GPIO_0 0 1882#define MISC_REGISTERS_GPIO_1 1 1883#define MISC_REGISTERS_GPIO_2 2 1884#define MISC_REGISTERS_GPIO_3 3 1885#define MISC_REGISTERS_GPIO_CLR_POS 16 1886#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 1887#define MISC_REGISTERS_GPIO_FLOAT_POS 24 1888#define MISC_REGISTERS_GPIO_HIGH 1 1889#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 1890#define MISC_REGISTERS_GPIO_INT_CLR_POS 24 1891#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 1892#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 1893#define MISC_REGISTERS_GPIO_INT_SET_POS 16 1894#define MISC_REGISTERS_GPIO_LOW 0 1895#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 1896#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 1897#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 1898#define MISC_REGISTERS_GPIO_SET_POS 8 1899#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 1900#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0) 1901#define MISC_REGISTERS_RESET_REG_1_RST_DORQ \ 1902 (0x1<<19) 1903#define MISC_REGISTERS_RESET_REG_1_RST_HC \ 1904 (0x1<<29) 1905#define MISC_REGISTERS_RESET_REG_1_RST_PXP \ 1906 (0x1<<26) 1907#define MISC_REGISTERS_RESET_REG_1_RST_PXPV \ 1908 (0x1<<27) 1909#define MISC_REGISTERS_RESET_REG_1_RST_QM \ 1910 (0x1<<17) 1911#define MISC_REGISTERS_RESET_REG_1_SET 0x584 1912#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 1913#define MISC_REGISTERS_RESET_REG_2_MSTAT0 \ 1914 (0x1<<24) 1915#define MISC_REGISTERS_RESET_REG_2_MSTAT1 \ 1916 (0x1<<25) 1917#define MISC_REGISTERS_RESET_REG_2_PGLC \ 1918 (0x1<<19) 1919#define MISC_REGISTERS_RESET_REG_2_RST_ATC \ 1920 (0x1<<17) 1921#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 1922#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1) 1923#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2) 1924#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE \ 1925 (0x1<<14) 1926#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3) 1927#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE \ 1928 (0x1<<15) 1929#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) 1930#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) 1931#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8) 1932#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7) 1933#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) 1934#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE \ 1935 (0x1<<11) 1936#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO \ 1937 (0x1<<13) 1938#define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR \ 1939 (0x1<<16) 1940#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 1941#define MISC_REGISTERS_RESET_REG_2_SET 0x594 1942#define MISC_REGISTERS_RESET_REG_2_UMAC0 \ 1943 (0x1<<20) 1944#define MISC_REGISTERS_RESET_REG_2_UMAC1 \ 1945 (0x1<<21) 1946#define MISC_REGISTERS_RESET_REG_2_XMAC \ 1947 (0x1<<22) 1948#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT \ 1949 (0x1<<23) 1950#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 1951#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 1952#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 1953#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) 1954#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) 1955#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) 1956#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) 1957#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) 1958#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) 1959#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) 1960#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 1961#define MISC_SPIO_CLR_POS 16 1962#define MISC_SPIO_FLOAT (0xffL<<24) 1963#define MISC_SPIO_FLOAT_POS 24 1964#define MISC_SPIO_INPUT_HI_Z 2 1965#define MISC_SPIO_INT_OLD_SET_POS 16 1966#define MISC_SPIO_OUTPUT_HIGH 1 1967#define MISC_SPIO_OUTPUT_LOW 0 1968#define MISC_SPIO_SET_POS 8 1969#define MISC_SPIO_SPIO4 0x10 1970#define MISC_SPIO_SPIO5 0x20 1971#define HW_LOCK_MAX_RESOURCE_VALUE 31 1972#define HW_LOCK_RESOURCE_DRV_FLAGS 10 1973#define HW_LOCK_RESOURCE_GPIO 1 1974#define HW_LOCK_RESOURCE_NVRAM 12 1975#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 1976#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 1977#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 1978#define HW_LOCK_RESOURCE_RECOVERY_REG 11 1979#define HW_LOCK_RESOURCE_RESET 5 1980#define HW_LOCK_RESOURCE_SPIO 2 1981 1982 1983#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) 1984#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) 1985#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19) 1986#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) 1987#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31) 1988#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30) 1989#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9) 1990#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8) 1991#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7) 1992#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6) 1993#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29) 1994#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28) 1995#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1) 1996#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0) 1997#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18) 1998#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11) 1999#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10) 2000#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13) 2001#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12) 2002#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2) 2003#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12) 2004#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28) 2005#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1UL<<31) 2006#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29) 2007#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30) 2008#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15) 2009#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14) 2010#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14) 2011#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20) 2012#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1UL<<31) 2013#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30) 2014#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0) 2015#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) 2016#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) 2017#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5) 2018#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4) 2019#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3) 2020#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2) 2021#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3) 2022#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2) 2023#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22) 2024#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15) 2025#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27) 2026#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26) 2027#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5) 2028#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4) 2029#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25) 2030#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24) 2031#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29) 2032#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28) 2033#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23) 2034#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22) 2035#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27) 2036#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26) 2037#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21) 2038#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20) 2039#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25) 2040#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24) 2041#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16) 2042#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9) 2043#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8) 2044#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7) 2045#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6) 2046#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11) 2047#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10) 2048#define HW_PRTY_ASSERT_SET_0 \ 2049(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR |\ 2050 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR |\ 2051 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR |\ 2052 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2053 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2054 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2055 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2056#define HW_PRTY_ASSERT_SET_1 \ 2057(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2058 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR |\ 2059 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2060 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR |\ 2061 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2062 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR |\ 2063 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2064 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2065 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2066 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR |\ 2067 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR |\ 2068 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2069 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR |\ 2070 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR |\ 2071 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2072 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2073#define HW_PRTY_ASSERT_SET_2 \ 2074(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR |\ 2075 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR |\ 2076 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2077 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR |\ 2078 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR |\ 2079 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2080 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR |\ 2081 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2082#define HW_PRTY_ASSERT_SET_3 \ 2083(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2084 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2085 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2086 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2087#define HW_PRTY_ASSERT_SET_4 \ 2088(AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |\ 2089 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2090#define HW_INTERRUT_ASSERT_SET_0 \ 2091(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT |\ 2092 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT |\ 2093 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT |\ 2094 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT |\ 2095 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2096#define HW_INTERRUT_ASSERT_SET_1 \ 2097(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT |\ 2098 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT |\ 2099 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT |\ 2100 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT |\ 2101 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT |\ 2102 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT |\ 2103 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT |\ 2104 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT |\ 2105 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT |\ 2106 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT |\ 2107 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2108#define HW_INTERRUT_ASSERT_SET_2 \ 2109(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT |\ 2110 AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT |\ 2111 AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT |\ 2112 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT |\ 2113 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT |\ 2114 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2115 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2116 2117 2118#define RESERVED_GENERAL_ATTENTION_BIT_0 0 2119 2120#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0 2121#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 2122 2123#define RESERVED_GENERAL_ATTENTION_BIT_6 6 2124#define RESERVED_GENERAL_ATTENTION_BIT_7 7 2125#define RESERVED_GENERAL_ATTENTION_BIT_8 8 2126#define RESERVED_GENERAL_ATTENTION_BIT_9 9 2127#define RESERVED_GENERAL_ATTENTION_BIT_10 10 2128#define RESERVED_GENERAL_ATTENTION_BIT_11 11 2129#define RESERVED_GENERAL_ATTENTION_BIT_12 12 2130#define RESERVED_GENERAL_ATTENTION_BIT_13 13 2131#define RESERVED_GENERAL_ATTENTION_BIT_14 14 2132#define RESERVED_GENERAL_ATTENTION_BIT_15 15 2133#define RESERVED_GENERAL_ATTENTION_BIT_16 16 2134#define RESERVED_GENERAL_ATTENTION_BIT_17 17 2135#define RESERVED_GENERAL_ATTENTION_BIT_18 18 2136#define RESERVED_GENERAL_ATTENTION_BIT_19 19 2137#define RESERVED_GENERAL_ATTENTION_BIT_20 20 2138#define RESERVED_GENERAL_ATTENTION_BIT_21 21 2139 2140/* storm asserts attention bits */ 2141#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 2142#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 2143#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 2144#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 2145 2146/* mcp error attention bit */ 2147#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 2148 2149/*E1H NIG status sync attention mapped to group 4-7*/ 2150#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 2151#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 2152#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 2153#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 2154#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 2155#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 2156#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 2157#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 2158 2159 /* Used For Error Recovery: changing this will require more \ 2160 changes in code that assume 2161 * error recovery uses general attn bit20 ! */ 2162#define ERROR_RECOVERY_ATTENTION_BIT \ 2163 RESERVED_GENERAL_ATTENTION_BIT_20 2164#define RESERVED_ATTENTION_BIT \ 2165 RESERVED_GENERAL_ATTENTION_BIT_21 2166 2167#define LATCHED_ATTN_RBCR 23 2168#define LATCHED_ATTN_RBCT 24 2169#define LATCHED_ATTN_RBCN 25 2170#define LATCHED_ATTN_RBCU 26 2171#define LATCHED_ATTN_RBCP 27 2172#define LATCHED_ATTN_TIMEOUT_GRC 28 2173#define LATCHED_ATTN_RSVD_GRC 29 2174#define LATCHED_ATTN_ROM_PARITY_MCP 30 2175#define LATCHED_ATTN_UM_RX_PARITY_MCP 31 2176#define LATCHED_ATTN_UM_TX_PARITY_MCP 32 2177#define LATCHED_ATTN_SCPAD_PARITY_MCP 33 2178 2179#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) 2180#define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32)) 2181 2182 2183/* 2184 * This file defines GRC base address for every block. 2185 * This file is included by chipsim, asm microcode and cpp microcode. 2186 * These values are used in Design.xml on regBase attribute 2187 * Use the base with the generated offsets of specific registers. 2188 */ 2189 2190#define GRCBASE_PXPCS 0x000000 2191#define GRCBASE_PCICONFIG 0x002000 2192#define GRCBASE_PCIREG 0x002400 2193#define GRCBASE_EMAC0 0x008000 2194#define GRCBASE_EMAC1 0x008400 2195#define GRCBASE_DBU 0x008800 2196#define GRCBASE_PGLUE_B 0x009000 2197#define GRCBASE_MISC 0x00A000 2198#define GRCBASE_DBG 0x00C000 2199#define GRCBASE_NIG 0x010000 2200#define GRCBASE_XCM 0x020000 2201#define GRCBASE_PRS 0x040000 2202#define GRCBASE_SRCH 0x040400 2203#define GRCBASE_TSDM 0x042000 2204#define GRCBASE_TCM 0x050000 2205#define GRCBASE_BRB1 0x060000 2206#define GRCBASE_MCP 0x080000 2207#define GRCBASE_UPB 0x0C1000 2208#define GRCBASE_CSDM 0x0C2000 2209#define GRCBASE_USDM 0x0C4000 2210#define GRCBASE_CCM 0x0D0000 2211#define GRCBASE_UCM 0x0E0000 2212#define GRCBASE_CDU 0x101000 2213#define GRCBASE_DMAE 0x102000 2214#define GRCBASE_PXP 0x103000 2215#define GRCBASE_CFC 0x104000 2216#define GRCBASE_HC 0x108000 2217#define GRCBASE_ATC 0x110000 2218#define GRCBASE_PXP2 0x120000 2219#define GRCBASE_IGU 0x130000 2220#define GRCBASE_PBF 0x140000 2221#define GRCBASE_UMAC0 0x160000 2222#define GRCBASE_UMAC1 0x160400 2223#define GRCBASE_XPB 0x161000 2224#define GRCBASE_MSTAT0 0x162000 2225#define GRCBASE_MSTAT1 0x162800 2226#define GRCBASE_XMAC0 0x163000 2227#define GRCBASE_XMAC1 0x163800 2228#define GRCBASE_TIMERS 0x164000 2229#define GRCBASE_XSDM 0x166000 2230#define GRCBASE_QM 0x168000 2231#define GRCBASE_QM_4PORT 0x168000 2232#define GRCBASE_DQ 0x170000 2233#define GRCBASE_TSEM 0x180000 2234#define GRCBASE_CSEM 0x200000 2235#define GRCBASE_XSEM 0x280000 2236#define GRCBASE_XSEM_4PORT 0x280000 2237#define GRCBASE_USEM 0x300000 2238#define GRCBASE_MCP_A 0x380000 2239#define GRCBASE_MISC_AEU GRCBASE_MISC 2240#define GRCBASE_Tstorm GRCBASE_TSEM 2241#define GRCBASE_Cstorm GRCBASE_CSEM 2242#define GRCBASE_Xstorm GRCBASE_XSEM 2243#define GRCBASE_Ustorm GRCBASE_USEM 2244 2245 2246/* offset of configuration space in the pci core register */ 2247#define PCICFG_OFFSET 0x2000 2248#define PCICFG_VENDOR_ID_OFFSET 0x00 2249#define PCICFG_DEVICE_ID_OFFSET 0x02 2250#define PCICFG_COMMAND_OFFSET 0x04 2251#define PCICFG_COMMAND_IO_SPACE (1<<0) 2252#define PCICFG_COMMAND_MEM_SPACE (1<<1) 2253#define PCICFG_COMMAND_BUS_MASTER (1<<2) 2254#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 2255#define PCICFG_COMMAND_MWI_CYCLES (1<<4) 2256#define PCICFG_COMMAND_VGA_SNOOP (1<<5) 2257#define PCICFG_COMMAND_PERR_ENA (1<<6) 2258#define PCICFG_COMMAND_STEPPING (1<<7) 2259#define PCICFG_COMMAND_SERR_ENA (1<<8) 2260#define PCICFG_COMMAND_FAST_B2B (1<<9) 2261#define PCICFG_COMMAND_INT_DISABLE (1<<10) 2262#define PCICFG_COMMAND_RESERVED (0x1f<<11) 2263#define PCICFG_STATUS_OFFSET 0x06 2264#define PCICFG_REVISION_ID_OFFSET 0x08 2265#define PCICFG_REVESION_ID_MASK 0xff 2266#define PCICFG_REVESION_ID_ERROR_VAL 0xff 2267#define PCICFG_CACHE_LINE_SIZE 0x0c 2268#define PCICFG_LATENCY_TIMER 0x0d 2269#define PCICFG_HEADER_TYPE 0x0e 2270#define PCICFG_HEADER_TYPE_NORMAL 0 2271#define PCICFG_HEADER_TYPE_BRIDGE 1 2272#define PCICFG_HEADER_TYPE_CARDBUS 2 2273#define PCICFG_BAR_1_LOW 0x10 2274#define PCICFG_BAR_1_HIGH 0x14 2275#define PCICFG_BAR_2_LOW 0x18 2276#define PCICFG_BAR_2_HIGH 0x1c 2277#define PCICFG_BAR_3_LOW 0x20 2278#define PCICFG_BAR_3_HIGH 0x24 2279#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 2280#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 2281#define PCICFG_INT_LINE 0x3c 2282#define PCICFG_INT_PIN 0x3d 2283#define PCICFG_PM_CAPABILITY 0x48 2284#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 2285#define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 2286#define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 2287#define PCICFG_PM_CAPABILITY_DSI (1<<21) 2288#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 2289#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 2290#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 2291#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 2292#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 2293#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 2294#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 2295#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 2296#define PCICFG_PM_CSR_OFFSET 0x4c 2297#define PCICFG_PM_CSR_STATE (0x3<<0) 2298#define PCICFG_PM_CSR_PME_ENABLE (1<<8) 2299#define PCICFG_PM_CSR_PME_STATUS (1<<15) 2300#define PCICFG_VPD_FLAG_ADDR_OFFSET 0x50 2301#define PCICFG_VPD_DATA_OFFSET 0x54 2302#define PCICFG_MSI_CAP_ID_OFFSET 0x58 2303#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 2304#define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 2305#define PCICFG_MSI_CONTROL_MENA (0x7<<20) 2306#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 2307#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 2308#define PCICFG_MSI_ADDR_LOW_OFFSET 0x5c 2309#define PCICFG_MSI_ADDR_HIGH_OFFSET 0x60 2310#define PCICFG_MSI_DATA_OFFSET 0x64 2311#define PCICFG_GRC_ADDRESS 0x78 2312#define PCICFG_GRC_DATA 0x80 2313#define PCICFG_ME_REGISTER 0x98 2314#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 2315#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 2316#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 2317#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 2318#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 2319 2320#define PCICFG_DEVICE_CONTROL 0xb4 2321#define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21) 2322#define PCICFG_DEVICE_STATUS 0xb6 2323#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 2324#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 2325#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 2326#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 2327#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 2328#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 2329#define PCICFG_LINK_CONTROL 0xbc 2330 2331 2332/* config_2 offset */ 2333#define GRC_CONFIG_2_SIZE_REG 0x408 2334#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 2335#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 2336#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 2337#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 2338#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 2339#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 2340#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 2341#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 2342#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 2343#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 2344#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 2345#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 2346#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 2347#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 2348#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 2349#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 2350#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 2351#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 2352#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 2353#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 2354#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 2355#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 2356#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 2357#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 2358#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 2359#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 2360#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 2361#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 2362#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 2363#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 2364#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 2365#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 2366#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 2367#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 2368#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 2369#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 2370#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 2371#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 2372#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 2373#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 2374 2375/* config_3 offset */ 2376#define GRC_CONFIG_3_SIZE_REG 0x40c 2377#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 2378#define PCI_CONFIG_3_FORCE_PME (1L<<24) 2379#define PCI_CONFIG_3_PME_STATUS (1L<<25) 2380#define PCI_CONFIG_3_PME_ENABLE (1L<<26) 2381#define PCI_CONFIG_3_PM_STATE (0x3L<<27) 2382#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 2383#define PCI_CONFIG_3_PCI_POWER (1L<<31) 2384 2385#define GRC_REG_DEVICE_CONTROL 0x4d8 2386#define PCIE_SRIOV_DISABLE_IN_PROGRESS \ 2387 (1 << 29) /*When VF Enable is cleared(after it was previously set), 2388 this register will read a value of 1, indicating that all the 2389 VFs that belong to this PF should be flushed. 2390 Software should clear this bit within 1 second of VF Enable 2391 being set by writing a 1 to it, so that VFs are visible to the system again. 2392 WC */ 2393#define PCIE_FLR_IN_PROGRESS \ 2394 (1 << 27) /*When FLR is initiated, this register will read a \ 2395 value of 1 indicating that the 2396 Function is in FLR state. Func can be brought out of FLR state either by 2397 writing 1 to this register (at least 50 ms after FLR was initiated), 2398 or it can also be cleared automatically after 55 ms if auto_clear bit 2399 in private reg space is set. This bit also exists in VF register space 2400 WC */ 2401 2402#define GRC_BAR2_CONFIG 0x4e0 2403#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 2404#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 2405#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 2406#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 2407#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 2408#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 2409#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 2410#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 2411#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 2412#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 2413#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 2414#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 2415#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 2416#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 2417#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 2418#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 2419#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 2420#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 2421 2422#define GRC_BAR3_CONFIG 0x4f4 2423#define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0) 2424#define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0) 2425#define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0) 2426#define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0) 2427#define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0) 2428#define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0) 2429#define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0) 2430#define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0) 2431#define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0) 2432#define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0) 2433#define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0) 2434#define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0) 2435#define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0) 2436#define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0) 2437#define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0) 2438#define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0) 2439#define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0) 2440#define PCI_CONFIG_2_BAR3_64ENA (1L<<4) 2441 2442#define PCI_PM_DATA_A 0x410 2443#define PCI_PM_DATA_B 0x414 2444#define PCI_ID_VAL1 0x434 2445#define PCI_ID_VAL2 0x438 2446#define PCI_ID_VAL3 0x43c 2447#define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24) 2448 2449 2450#define GRC_CONFIG_REG_VF_BAR_REG_1 0x608 2451#define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf 2452 2453#define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C 2454#define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK \ 2455 0x3F /*This field resides in VF only and does not exist in PF. 2456 This register controls the read value of the MSIX_CONTROL[10:0] register 2457 in the VF configuration space. A value of "00000000011" indicates 2458 a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ 2459 define in version.v */ 2460 2461#define GRC_CONFIG_REG_PF_INIT_VF 0x624 2462#define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK \ 2463 0xf /*First VF_NUM for PF is encoded in this register. 2464 The number of VFs assigned to a PF is assumed to be a multiple of 8. 2465 Software should program these bits based on Total Number of VFs \ 2466 programmed for each PF. 2467 Since registers from 0x000-0x7ff are spilt across functions, each PF will have 2468 the same location for the same 4 bits*/ 2469 2470#define PXPCS_TL_CONTROL_5 0x814 2471#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 2472#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 2473#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 2474#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 2475#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 2476#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 2477#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 2478#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 2479#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 2480#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 2481#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 2482#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 2483#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 2484#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 2485#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 2486#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 2487#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 2488#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 2489#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 2490#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 2491#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 2492#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 2493#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 2494#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 2495#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 2496#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 2497#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 2498#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 2499#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 2500#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 2501 2502 2503#define PXPCS_TL_FUNC345_STAT 0x854 2504#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 2505#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 \ 2506 (1 << 28) /* Unsupported Request Error Status in function4, if \ 2507 set, generate pcie_err_attn output when this error is seen. WC */ 2508#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 \ 2509 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \ 2510 generate pcie_err_attn output when this error is seen.. WC */ 2511#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 \ 2512 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \ 2513 generate pcie_err_attn output when this error is seen.. WC */ 2514#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 \ 2515 (1 << 25) /* Receiver Overflow Status Status in function 4, if \ 2516 set, generate pcie_err_attn output when this error is seen.. WC \ 2517 */ 2518#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 \ 2519 (1 << 24) /* Unexpected Completion Status Status in function 4, \ 2520 if set, generate pcie_err_attn output when this error is seen. WC \ 2521 */ 2522#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 \ 2523 (1 << 23) /* Receive UR Statusin function 4. If set, generate \ 2524 pcie_err_attn output when this error is seen. WC */ 2525#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 \ 2526 (1 << 22) /* Completer Timeout Status Status in function 4, if \ 2527 set, generate pcie_err_attn output when this error is seen. WC */ 2528#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 \ 2529 (1 << 21) /* Flow Control Protocol Error Status Status in \ 2530 function 4, if set, generate pcie_err_attn output when this error \ 2531 is seen. WC */ 2532#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 \ 2533 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \ 2534 generate pcie_err_attn output when this error is seen.. WC */ 2535#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 2536#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 \ 2537 (1 << 18) /* Unsupported Request Error Status in function3, if \ 2538 set, generate pcie_err_attn output when this error is seen. WC */ 2539#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 \ 2540 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \ 2541 generate pcie_err_attn output when this error is seen.. WC */ 2542#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 \ 2543 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \ 2544 generate pcie_err_attn output when this error is seen.. WC */ 2545#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 \ 2546 (1 << 15) /* Receiver Overflow Status Status in function 3, if \ 2547 set, generate pcie_err_attn output when this error is seen.. WC \ 2548 */ 2549#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 \ 2550 (1 << 14) /* Unexpected Completion Status Status in function 3, \ 2551 if set, generate pcie_err_attn output when this error is seen. WC \ 2552 */ 2553#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 \ 2554 (1 << 13) /* Receive UR Statusin function 3. If set, generate \ 2555 pcie_err_attn output when this error is seen. WC */ 2556#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 \ 2557 (1 << 12) /* Completer Timeout Status Status in function 3, if \ 2558 set, generate pcie_err_attn output when this error is seen. WC */ 2559#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 \ 2560 (1 << 11) /* Flow Control Protocol Error Status Status in \ 2561 function 3, if set, generate pcie_err_attn output when this error \ 2562 is seen. WC */ 2563#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 \ 2564 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \ 2565 generate pcie_err_attn output when this error is seen.. WC */ 2566#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 2567#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 \ 2568 (1 << 8) /* Unsupported Request Error Status for Function 2, if \ 2569 set, generate pcie_err_attn output when this error is seen. WC */ 2570#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 \ 2571 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \ 2572 generate pcie_err_attn output when this error is seen.. WC */ 2573#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 \ 2574 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \ 2575 generate pcie_err_attn output when this error is seen.. WC */ 2576#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 \ 2577 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \ 2578 set, generate pcie_err_attn output when this error is seen.. WC \ 2579 */ 2580#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 \ 2581 (1 << 4) /* Unexpected Completion Status Status for Function 2, \ 2582 if set, generate pcie_err_attn output when this error is seen. WC \ 2583 */ 2584#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 \ 2585 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \ 2586 pcie_err_attn output when this error is seen. WC */ 2587#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 \ 2588 (1 << 2) /* Completer Timeout Status Status for Function 2, if \ 2589 set, generate pcie_err_attn output when this error is seen. WC */ 2590#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 \ 2591 (1 << 1) /* Flow Control Protocol Error Status Status for \ 2592 Function 2, if set, generate pcie_err_attn output when this error \ 2593 is seen. WC */ 2594#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 \ 2595 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \ 2596 generate pcie_err_attn output when this error is seen.. WC */ 2597 2598 2599#define PXPCS_TL_FUNC678_STAT 0x85C 2600#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 2601#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 \ 2602 (1 << 28) /* Unsupported Request Error Status in function7, if \ 2603 set, generate pcie_err_attn output when this error is seen. WC */ 2604#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 \ 2605 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \ 2606 generate pcie_err_attn output when this error is seen.. WC */ 2607#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 \ 2608 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \ 2609 generate pcie_err_attn output when this error is seen.. WC */ 2610#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 \ 2611 (1 << 25) /* Receiver Overflow Status Status in function 7, if \ 2612 set, generate pcie_err_attn output when this error is seen.. WC \ 2613 */ 2614#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 \ 2615 (1 << 24) /* Unexpected Completion Status Status in function 7, \ 2616 if set, generate pcie_err_attn output when this error is seen. WC \ 2617 */ 2618#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 \ 2619 (1 << 23) /* Receive UR Statusin function 7. If set, generate \ 2620 pcie_err_attn output when this error is seen. WC */ 2621#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 \ 2622 (1 << 22) /* Completer Timeout Status Status in function 7, if \ 2623 set, generate pcie_err_attn output when this error is seen. WC */ 2624#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 \ 2625 (1 << 21) /* Flow Control Protocol Error Status Status in \ 2626 function 7, if set, generate pcie_err_attn output when this error \ 2627 is seen. WC */ 2628#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 \ 2629 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \ 2630 generate pcie_err_attn output when this error is seen.. WC */ 2631#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 2632#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 \ 2633 (1 << 18) /* Unsupported Request Error Status in function6, if \ 2634 set, generate pcie_err_attn output when this error is seen. WC */ 2635#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 \ 2636 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \ 2637 generate pcie_err_attn output when this error is seen.. WC */ 2638#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 \ 2639 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \ 2640 generate pcie_err_attn output when this error is seen.. WC */ 2641#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 \ 2642 (1 << 15) /* Receiver Overflow Status Status in function 6, if \ 2643 set, generate pcie_err_attn output when this error is seen.. WC \ 2644 */ 2645#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 \ 2646 (1 << 14) /* Unexpected Completion Status Status in function 6, \ 2647 if set, generate pcie_err_attn output when this error is seen. WC \ 2648 */ 2649#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 \ 2650 (1 << 13) /* Receive UR Statusin function 6. If set, generate \ 2651 pcie_err_attn output when this error is seen. WC */ 2652#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 \ 2653 (1 << 12) /* Completer Timeout Status Status in function 6, if \ 2654 set, generate pcie_err_attn output when this error is seen. WC */ 2655#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 \ 2656 (1 << 11) /* Flow Control Protocol Error Status Status in \ 2657 function 6, if set, generate pcie_err_attn output when this error \ 2658 is seen. WC */ 2659#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 \ 2660 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \ 2661 generate pcie_err_attn output when this error is seen.. WC */ 2662#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 2663#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 \ 2664 (1 << 8) /* Unsupported Request Error Status for Function 5, if \ 2665 set, generate pcie_err_attn output when this error is seen. WC */ 2666#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 \ 2667 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \ 2668 generate pcie_err_attn output when this error is seen.. WC */ 2669#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 \ 2670 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \ 2671 generate pcie_err_attn output when this error is seen.. WC */ 2672#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 \ 2673 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \ 2674 set, generate pcie_err_attn output when this error is seen.. WC \ 2675 */ 2676#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 \ 2677 (1 << 4) /* Unexpected Completion Status Status for Function 5, \ 2678 if set, generate pcie_err_attn output when this error is seen. WC \ 2679 */ 2680#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 \ 2681 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \ 2682 pcie_err_attn output when this error is seen. WC */ 2683#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 \ 2684 (1 << 2) /* Completer Timeout Status Status for Function 5, if \ 2685 set, generate pcie_err_attn output when this error is seen. WC */ 2686#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 \ 2687 (1 << 1) /* Flow Control Protocol Error Status Status for \ 2688 Function 5, if set, generate pcie_err_attn output when this error \ 2689 is seen. WC */ 2690#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 \ 2691 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \ 2692 generate pcie_err_attn output when this error is seen.. WC */ 2693 2694 2695#define BAR_USTRORM_INTMEM 0x400000 2696#define BAR_CSTRORM_INTMEM 0x410000 2697#define BAR_XSTRORM_INTMEM 0x420000 2698#define BAR_TSTRORM_INTMEM 0x430000 2699 2700/* for accessing the IGU in case of status block ACK */ 2701#define BAR_IGU_INTMEM 0x440000 2702 2703#define BAR_DOORBELL_OFFSET 0x800000 2704 2705#define BAR_ME_REGISTER 0x450000 2706#define ME_REG_PF_NUM_SHIFT 0 2707#define ME_REG_PF_NUM \ 2708 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */ 2709#define ME_REG_VF_VALID (1<<8) 2710#define ME_REG_VF_NUM_SHIFT 9 2711#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT) 2712#define ME_REG_VF_ERR (0x1<<3) 2713#define ME_REG_ABS_PF_NUM_SHIFT 16 2714#define ME_REG_ABS_PF_NUM \ 2715 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */ 2716 2717 2718#define PXP_VF_ADRR_NUM_QUEUES 136 2719#define PXP_ADDR_QUEUE_SIZE 32 2720#define PXP_ADDR_REG_SIZE 512 2721 2722 2723#define PXP_VF_ADDR_IGU_START 0 2724#define PXP_VF_ADDR_IGU_SIZE (0x3000) 2725#define PXP_VF_ADDR_IGU_END \ 2726 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1) 2727 2728#define PXP_VF_ADDR_USDM_QUEUES_START 0x3000 2729#define PXP_VF_ADDR_USDM_QUEUES_SIZE \ 2730 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 2731#define PXP_VF_ADDR_USDM_QUEUES_END \ 2732 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1) 2733 2734#define PXP_VF_ADDR_CSDM_QUEUES_START 0x4100 2735#define PXP_VF_ADDR_CSDM_QUEUES_SIZE \ 2736 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 2737#define PXP_VF_ADDR_CSDM_QUEUES_END \ 2738 ((PXP_VF_ADDR_CSDM_QUEUES_START) + (PXP_VF_ADDR_CSDM_QUEUES_SIZE) - 1) 2739 2740#define PXP_VF_ADDR_XSDM_QUEUES_START 0x5200 2741#define PXP_VF_ADDR_XSDM_QUEUES_SIZE \ 2742 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 2743#define PXP_VF_ADDR_XSDM_QUEUES_END \ 2744 ((PXP_VF_ADDR_XSDM_QUEUES_START) + (PXP_VF_ADDR_XSDM_QUEUES_SIZE) - 1) 2745 2746#define PXP_VF_ADDR_TSDM_QUEUES_START 0x6300 2747#define PXP_VF_ADDR_TSDM_QUEUES_SIZE \ 2748 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 2749#define PXP_VF_ADDR_TSDM_QUEUES_END \ 2750 ((PXP_VF_ADDR_TSDM_QUEUES_START) + (PXP_VF_ADDR_TSDM_QUEUES_SIZE) - 1) 2751 2752#define PXP_VF_ADDR_USDM_GLOBAL_START 0x7400 2753#define PXP_VF_ADDR_USDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 2754#define PXP_VF_ADDR_USDM_GLOBAL_END \ 2755 ((PXP_VF_ADDR_USDM_GLOBAL_START) + (PXP_VF_ADDR_USDM_GLOBAL_SIZE) - 1) 2756 2757#define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600 2758#define PXP_VF_ADDR_CSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 2759#define PXP_VF_ADDR_CSDM_GLOBAL_END \ 2760 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1) 2761 2762#define PXP_VF_ADDR_XSDM_GLOBAL_START 0x7800 2763#define PXP_VF_ADDR_XSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 2764#define PXP_VF_ADDR_XSDM_GLOBAL_END \ 2765 ((PXP_VF_ADDR_XSDM_GLOBAL_START) + (PXP_VF_ADDR_XSDM_GLOBAL_SIZE) - 1) 2766 2767#define PXP_VF_ADDR_TSDM_GLOBAL_START 0x7a00 2768#define PXP_VF_ADDR_TSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 2769#define PXP_VF_ADDR_TSDM_GLOBAL_END \ 2770 ((PXP_VF_ADDR_TSDM_GLOBAL_START) + (PXP_VF_ADDR_TSDM_GLOBAL_SIZE) - 1) 2771 2772#define PXP_VF_ADDR_DB_START 0x7c00 2773#define PXP_VF_ADDR_DB_SIZE (0x200) 2774#define PXP_VF_ADDR_DB_END \ 2775 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1) 2776 2777#define PXP_VF_ADDR_GRC_START 0x7e00 2778#define PXP_VF_ADDR_GRC_SIZE (0x200) 2779#define PXP_VF_ADDR_GRC_END \ 2780 ((PXP_VF_ADDR_GRC_START) + (PXP_VF_ADDR_GRC_SIZE) - 1) 2781 2782#define PXP_VF_ADDR_DORQ_START (0x0) 2783#define PXP_VF_ADDR_DORQ_SIZE (0xffffffff) 2784#define PXP_VF_ADDR_DORQ_END (0xffffffff) 2785 2786#define PXP_BAR_GRC 0 2787#define PXP_BAR_TSDM 0 2788#define PXP_BAR_USDM 0 2789#define PXP_BAR_XSDM 0 2790#define PXP_BAR_CSDM 0 2791#define PXP_BAR_IGU 0 2792#define PXP_BAR_DQ 1 2793 2794#define PXP_VF_BAR_IGU 0 2795#define PXP_VF_BAR_USDM_QUEUES 0 2796#define PXP_VF_BAR_TSDM_QUEUES 0 2797#define PXP_VF_BAR_XSDM_QUEUES 0 2798#define PXP_VF_BAR_CSDM_QUEUES 0 2799#define PXP_VF_BAR_USDM_GLOBAL 0 2800#define PXP_VF_BAR_TSDM_GLOBAL 0 2801#define PXP_VF_BAR_XSDM_GLOBAL 0 2802#define PXP_VF_BAR_CSDM_GLOBAL 0 2803#define PXP_VF_BAR_DB 0 2804#define PXP_VF_BAR_GRC 0 2805#define PXP_VF_BAR_DORQ 1 2806 2807/* PCI CAPABILITIES*/ 2808 2809#define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/ 2810 2811#define PCIE_DEV_CAPS 0x04 2812 2813#define PCIE_DEV_CTRL 0x08 2814#define PCIE_DEV_CTRL_FLR 0x8000; 2815 2816#define PCIE_DEV_STATUS 0x0A 2817 2818#define PCI_CAP_MSIX 0x11 /*MSI-X capability ID*/ 2819#define PCI_MSIX_CONTROL_SHIFT 16 2820#define PCI_MSIX_TABLE_SIZE_MASK 0x07FF 2821#define PCI_MSIX_TABLE_ENABLE_MASK 0x8000 2822 2823 2824#define MDIO_REG_BANK_CL73_IEEEB0 0x0 2825#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 2826#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 2827#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 2828#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 2829 2830#define MDIO_REG_BANK_CL73_IEEEB1 0x10 2831#define MDIO_CL73_IEEEB1_AN_ADV1 0x00 2832#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 2833#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 2834#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 2835#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 2836#define MDIO_CL73_IEEEB1_AN_ADV2 0x01 2837#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 2838#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 2839#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 2840#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 2841#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 2842#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 2843#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 2844#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 2845#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 2846#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 2847 2848#define MDIO_REG_BANK_RX0 0x80b0 2849#define MDIO_RX0_RX_STATUS 0x10 2850#define MDIO_RX0_RX_STATUS_SIGDET 0x8000 2851#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 2852#define MDIO_RX0_RX_EQ_BOOST 0x1c 2853#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2854#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 2855 2856#define MDIO_REG_BANK_RX1 0x80c0 2857#define MDIO_RX1_RX_EQ_BOOST 0x1c 2858#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2859#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 2860 2861#define MDIO_REG_BANK_RX2 0x80d0 2862#define MDIO_RX2_RX_EQ_BOOST 0x1c 2863#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2864#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 2865 2866#define MDIO_REG_BANK_RX3 0x80e0 2867#define MDIO_RX3_RX_EQ_BOOST 0x1c 2868#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2869#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 2870 2871#define MDIO_REG_BANK_RX_ALL 0x80f0 2872#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 2873#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 2874#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 2875 2876#define MDIO_REG_BANK_TX0 0x8060 2877#define MDIO_TX0_TX_DRIVER 0x17 2878#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 2879#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 2880#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 2881#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 2882#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 2883#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 2884#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 2885#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 2886#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 2887 2888#define MDIO_REG_BANK_TX1 0x8070 2889#define MDIO_TX1_TX_DRIVER 0x17 2890#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 2891#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 2892#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 2893#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 2894#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 2895#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 2896#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 2897#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 2898#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 2899 2900#define MDIO_REG_BANK_TX2 0x8080 2901#define MDIO_TX2_TX_DRIVER 0x17 2902#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 2903#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 2904#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 2905#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 2906#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 2907#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 2908#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 2909#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 2910#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 2911 2912#define MDIO_REG_BANK_TX3 0x8090 2913#define MDIO_TX3_TX_DRIVER 0x17 2914#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 2915#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 2916#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 2917#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 2918#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 2919#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 2920#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 2921#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 2922#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 2923 2924#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 2925#define MDIO_BLOCK0_XGXS_CONTROL 0x10 2926 2927#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 2928#define MDIO_BLOCK1_LANE_CTRL0 0x15 2929#define MDIO_BLOCK1_LANE_CTRL1 0x16 2930#define MDIO_BLOCK1_LANE_CTRL2 0x17 2931#define MDIO_BLOCK1_LANE_PRBS 0x19 2932 2933#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 2934#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 2935#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 2936#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 2937#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 2938#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 2939#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 2940#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 2941#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 2942#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 2943 2944#define MDIO_REG_BANK_GP_STATUS 0x8120 2945#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 2946#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 2947#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 2948#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 2949#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 2950#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 2951#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 2952#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 2953#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 2954#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 2955#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 2956#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 2957#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 2958#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 2959#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 2960#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 2961#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 2962#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 2963#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 2964#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 2965#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 2966#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 2967#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 2968#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 2969#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 2970#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 2971#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 2972#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 2973#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 2974#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 2975 2976 2977#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 2978#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 2979#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 2980#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 2981#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 2982#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 2983#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 2984 2985#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 2986#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 2987#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 2988#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 2989#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 2990#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 2991#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 2992#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 2993#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 2994#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 2995#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 2996#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 2997#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 2998#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 2999#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 3000#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 3001#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 3002#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 3003#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 3004#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 3005#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 3006#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 3007#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 3008#define MDIO_SERDES_DIGITAL_MISC1 0x18 3009#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 3010#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 3011#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 3012#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 3013#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 3014#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 3015#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 3016#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 3017#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 3018#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 3019#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 3020#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 3021#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 3022#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 3023#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 3024#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 3025#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 3026#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 3027 3028#define MDIO_REG_BANK_OVER_1G 0x8320 3029#define MDIO_OVER_1G_DIGCTL_3_4 0x14 3030#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 3031#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 3032#define MDIO_OVER_1G_UP1 0x19 3033#define MDIO_OVER_1G_UP1_2_5G 0x0001 3034#define MDIO_OVER_1G_UP1_5G 0x0002 3035#define MDIO_OVER_1G_UP1_6G 0x0004 3036#define MDIO_OVER_1G_UP1_10G 0x0010 3037#define MDIO_OVER_1G_UP1_10GH 0x0008 3038#define MDIO_OVER_1G_UP1_12G 0x0020 3039#define MDIO_OVER_1G_UP1_12_5G 0x0040 3040#define MDIO_OVER_1G_UP1_13G 0x0080 3041#define MDIO_OVER_1G_UP1_15G 0x0100 3042#define MDIO_OVER_1G_UP1_16G 0x0200 3043#define MDIO_OVER_1G_UP2 0x1A 3044#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 3045#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 3046#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 3047#define MDIO_OVER_1G_UP3 0x1B 3048#define MDIO_OVER_1G_UP3_HIGIG2 0x0001 3049#define MDIO_OVER_1G_LP_UP1 0x1C 3050#define MDIO_OVER_1G_LP_UP2 0x1D 3051#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 3052#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 3053#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 3054#define MDIO_OVER_1G_LP_UP3 0x1E 3055 3056#define MDIO_REG_BANK_REMOTE_PHY 0x8330 3057#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 3058#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 3059#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 3060 3061#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 3062#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 3063#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 3064#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 3065 3066#define MDIO_REG_BANK_CL73_USERB0 0x8370 3067#define MDIO_CL73_USERB0_CL73_UCTRL 0x10 3068#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 3069#define MDIO_CL73_USERB0_CL73_USTAT1 0x11 3070#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 3071#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 3072#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 3073#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 3074#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 3075#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 3076#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 3077#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 3078 3079#define MDIO_REG_BANK_AER_BLOCK 0xFFD0 3080#define MDIO_AER_BLOCK_AER_REG 0x1E 3081 3082#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 3083#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 3084#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 3085#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 3086#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 3087#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 3088#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 3089#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 3090#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 3091#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 3092#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 3093#define MDIO_COMBO_IEEE0_MII_STATUS 0x11 3094#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 3095#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 3096#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 3097#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 3098#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 3099#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 3100#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 3101#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 3102#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 3103#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 3104#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 3105#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 3106#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 3107#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 3108#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 3109#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 3110#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 3111#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 3112#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 3113/*WhenthelinkpartnerisinSGMIImode(bit0=1), then 3114bit15=link, bit12=duplex, bits11:10=speed, bit14=acknowledge. 3115Theotherbitsarereservedandshouldbezero*/ 3116#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 3117 3118 3119#define MDIO_PMA_DEVAD 0x1 3120/*ieee*/ 3121#define MDIO_PMA_REG_CTRL 0x0 3122#define MDIO_PMA_REG_STATUS 0x1 3123#define MDIO_PMA_REG_10G_CTRL2 0x7 3124#define MDIO_PMA_REG_TX_DISABLE 0x0009 3125#define MDIO_PMA_REG_RX_SD 0xa 3126/*bcm*/ 3127#define MDIO_PMA_REG_BCM_CTRL 0x0096 3128#define MDIO_PMA_REG_FEC_CTRL 0x00ab 3129#define MDIO_PMA_LASI_RXCTRL 0x9000 3130#define MDIO_PMA_LASI_TXCTRL 0x9001 3131#define MDIO_PMA_LASI_CTRL 0x9002 3132#define MDIO_PMA_LASI_RXSTAT 0x9003 3133#define MDIO_PMA_LASI_TXSTAT 0x9004 3134#define MDIO_PMA_LASI_STAT 0x9005 3135#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 3136#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 3137#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 3138#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 3139#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 3140#define MDIO_PMA_REG_MISC_CTRL 0xca0a 3141#define MDIO_PMA_REG_GEN_CTRL 0xca10 3142#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 3143#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 3144#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 3145#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 3146#define MDIO_PMA_REG_ROM_VER1 0xca19 3147#define MDIO_PMA_REG_ROM_VER2 0xca1a 3148#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 3149#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 3150#define MDIO_PMA_REG_PLL_CTRL 0xca1e 3151#define MDIO_PMA_REG_MISC_CTRL0 0xca23 3152#define MDIO_PMA_REG_LRM_MODE 0xca3f 3153#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 3154#define MDIO_PMA_REG_MISC_CTRL1 0xca85 3155 3156#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 3157#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c 3158#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 3159#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 3160#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 3161#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c 3162#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 3163#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 3164#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 3165#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff 3166#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 3167#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 3168 3169#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 3170#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 3171#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff 3172#define MDIO_PMA_REG_8727_MISC_CTRL 0x8309 3173#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 3174#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 3175#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 3176#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e 3177#define MDIO_PMA_REG_8727_PCS_GP 0xc842 3178#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 3179 3180#define MDIO_AN_REG_8727_MISC_CTRL 0x8309 3181#define MDIO_PMA_REG_8073_CHIP_REV 0xc801 3182#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 3183#define MDIO_PMA_REG_8073_XAUI_WA 0xc841 3184#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 3185 3186#define MDIO_PMA_REG_7101_RESET 0xc000 3187#define MDIO_PMA_REG_7107_LED_CNTL 0xc007 3188#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 3189#define MDIO_PMA_REG_7101_VER1 0xc026 3190#define MDIO_PMA_REG_7101_VER2 0xc027 3191 3192#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 3193#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c 3194#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f 3195#define MDIO_PMA_REG_8481_LED3_MASK 0xa832 3196#define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 3197#define MDIO_PMA_REG_8481_LED5_MASK 0xa838 3198#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 3199#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b 3200#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 3201#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 3202 3203 3204#define MDIO_WIS_DEVAD 0x2 3205/*bcm*/ 3206#define MDIO_WIS_REG_LASI_CNTL 0x9002 3207#define MDIO_WIS_REG_LASI_STATUS 0x9005 3208 3209#define MDIO_PCS_DEVAD 0x3 3210#define MDIO_PCS_REG_STATUS 0x0020 3211#define MDIO_PCS_REG_LASI_STATUS 0x9005 3212#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 3213#define MDIO_PCS_REG_7101_SPI_MUX 0xD008 3214#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 3215#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 3216#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 3217#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 3218#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 3219#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 3220#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 3221 3222 3223#define MDIO_XS_DEVAD 0x4 3224#define MDIO_XS_REG_STATUS 0x0001 3225#define MDIO_XS_PLL_SEQUENCER 0x8000 3226#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 3227 3228#define MDIO_XS_8706_REG_BANK_RX0 0x80bc 3229#define MDIO_XS_8706_REG_BANK_RX1 0x80cc 3230#define MDIO_XS_8706_REG_BANK_RX2 0x80dc 3231#define MDIO_XS_8706_REG_BANK_RX3 0x80ec 3232#define MDIO_XS_8706_REG_BANK_RXA 0x80fc 3233 3234#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA 3235 3236#define MDIO_AN_DEVAD 0x7 3237/*ieee*/ 3238#define MDIO_AN_REG_CTRL 0x0000 3239#define MDIO_AN_REG_STATUS 0x0001 3240#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 3241#define MDIO_AN_REG_ADV_PAUSE 0x0010 3242#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 3243#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 3244#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 3245#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 3246#define MDIO_AN_REG_ADV 0x0011 3247#define MDIO_AN_REG_ADV2 0x0012 3248#define MDIO_AN_REG_LP_AUTO_NEG 0x0013 3249#define MDIO_AN_REG_LP_AUTO_NEG2 0x0014 3250#define MDIO_AN_REG_MASTER_STATUS 0x0021 3251#define MDIO_AN_REG_EEE_ADV 0x003c 3252#define MDIO_AN_REG_LP_EEE_ADV 0x003d 3253/*bcm*/ 3254#define MDIO_AN_REG_LINK_STATUS 0x8304 3255#define MDIO_AN_REG_CL37_CL73 0x8370 3256#define MDIO_AN_REG_CL37_AN 0xffe0 3257#define MDIO_AN_REG_CL37_FC_LD 0xffe4 3258#define MDIO_AN_REG_CL37_FC_LP 0xffe5 3259#define MDIO_AN_REG_1000T_STATUS 0xffea 3260 3261#define MDIO_AN_REG_8073_2_5G 0x8329 3262#define MDIO_AN_REG_8073_BAM 0x8350 3263 3264#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 3265#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 3266#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 3267#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 3268#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 3269#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 3270#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 3271#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0 3272#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 3273#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 3274#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 3275#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 3276#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 3277 3278/* BCM84823 only */ 3279#define MDIO_CTL_DEVAD 0x1e 3280#define MDIO_CTL_REG_84823_MEDIA 0x401a 3281#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 3282 /* These pins configure the BCM84823 interface to MAC after reset. */ 3283#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 3284#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 3285 /* These pins configure the BCM84823 interface to Line after reset. */ 3286#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 3287#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 3288#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 3289 /* When this pin is active high during reset, 10GBASE-T core is power 3290 * down, When it is active low the 10GBASE-T is power up 3291 */ 3292#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 3293#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 3294#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 3295#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 3296#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 3297#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 3298#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 3299#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b 3300#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f 3301#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 3302#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec 3303#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 3304 3305/* BCM84833 only */ 3306#define MDIO_84833_TOP_CFG_FW_REV 0x400f 3307#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 3308#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 3309#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a 3310#define MDIO_84833_SUPER_ISOLATE 0x8000 3311/* These are mailbox register set used by 84833. */ 3312#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 3313#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 3314#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 3315#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 3316#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 3317#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037 3318#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038 3319#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039 3320#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a 3321#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b 3322#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c 3323#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0 3324#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26 3325#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27 3326#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28 3327#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29 3328#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30 3329#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31 3330 3331/* Mailbox command set used by 84833. */ 3332#define PHY84833_CMD_SET_PAIR_SWAP 0x8001 3333#define PHY84833_CMD_GET_EEE_MODE 0x8008 3334#define PHY84833_CMD_SET_EEE_MODE 0x8009 3335#define PHY84833_CMD_GET_CURRENT_TEMP 0x8031 3336/* Mailbox status set used by 84833. */ 3337#define PHY84833_STATUS_CMD_RECEIVED 0x0001 3338#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 3339#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 3340#define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008 3341#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010 3342#define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020 3343#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 3344#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 3345#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 3346 3347 3348/* Warpcore clause 45 addressing */ 3349#define MDIO_WC_DEVAD 0x3 3350#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 3351#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 3352#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 3353#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 3354#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 3355#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 3356#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 3357#define MDIO_WC_REG_PCS_STATUS2 0x0021 3358#define MDIO_WC_REG_PMD_KR_CONTROL 0x0096 3359#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 3360#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e 3361#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 3362#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 3363#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 3364#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 3365#define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018 3366#define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a 3367#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 3368#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 3369#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 3370#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 3371#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 3372#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 3373#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 3374#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 3375#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 3376#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c 3377#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 3378#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 3379#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 3380#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 3381#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 3382#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 3383#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba 3384#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca 3385#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da 3386#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea 3387#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa 3388#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 3389#define MDIO_WC_REG_XGXS_STATUS3 0x8129 3390#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 3391#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 3392#define MDIO_WC_REG_XGXS_STATUS4 0x813c 3393#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 3394#define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142 3395#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B 3396#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 3397#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 3398#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 3399#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 3400#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 3401#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 3402#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 3403#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 3404#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 3405#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 3406#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 3407#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 3408#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 3409#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 3410#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 3411#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 3412#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 3413#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 3414#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 3415#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 3416#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 3417#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc 3418#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE 3419#define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e 3420#define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7) 3421#define MDIO_WC_REG_DSC_SMC 0x8213 3422#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e 3423#define MDIO_WC_REG_TX_FIR_TAP 0x82e2 3424#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 3425#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f 3426#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 3427#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 3428#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a 3429#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 3430#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 3431#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2 3432#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 3433#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 3434#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 3435#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 3436#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec 3437#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 3438#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 3439#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 3440#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 3441#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 3442#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 3443#define MDIO_WC_REG_DIGITAL3_UP1 0x8329 3444#define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c 3445#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c 3446#define MDIO_WC_REG_DIGITAL4_MISC5 0x833e 3447#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 3448#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 3449#define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d 3450#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e 3451#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 3452#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 3453#define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370 3454#define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371 3455#define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372 3456#define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373 3457#define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374 3458#define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b 3459#define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390 3460#define MDIO_WC_REG_TX66_CONTROL 0x83b0 3461#define MDIO_WC_REG_RX66_CONTROL 0x83c0 3462#define MDIO_WC_REG_RX66_SCW0 0x83c2 3463#define MDIO_WC_REG_RX66_SCW1 0x83c3 3464#define MDIO_WC_REG_RX66_SCW2 0x83c4 3465#define MDIO_WC_REG_RX66_SCW3 0x83c5 3466#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 3467#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 3468#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 3469#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 3470#define MDIO_WC_REG_FX100_CTRL1 0x8400 3471#define MDIO_WC_REG_FX100_CTRL3 0x8402 3472#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436 3473#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437 3474#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438 3475#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439 3476#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a 3477#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b 3478#define MDIO_WC_REG_ETA_CL73_OUI1 0x8453 3479#define MDIO_WC_REG_ETA_CL73_OUI2 0x8454 3480#define MDIO_WC_REG_ETA_CL73_OUI3 0x8455 3481#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456 3482#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457 3483#define MDIO_WC_REG_MICROBLK_CMD 0xffc2 3484#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 3485#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc 3486 3487#define MDIO_WC_REG_AERBLK_AER 0xffde 3488#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 3489#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 3490 3491#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A 3492#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 3493#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 3494 3495#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 3496 3497#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f 3498 3499/* 54618se */ 3500#define MDIO_REG_GPHY_MII_STATUS 0x1 3501#define MDIO_REG_GPHY_PHYID_LSB 0x3 3502#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd 3503#define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000 3504#define MDIO_REG_GPHY_CL45_REG_READ 0xc000 3505#define MDIO_REG_GPHY_CL45_DATA_REG 0xe 3506#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e 3507#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15 3508#define MDIO_REG_GPHY_EXP_ACCESS 0x17 3509#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 3510#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 3511#define MDIO_REG_GPHY_AUX_STATUS 0x19 3512#define MDIO_REG_INTR_STATUS 0x1a 3513#define MDIO_REG_INTR_MASK 0x1b 3514#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) 3515#define MDIO_REG_GPHY_SHADOW 0x1c 3516#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) 3517#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) 3518#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) 3519#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) 3520#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) 3521 3522 3523#define IGU_FUNC_BASE 0x0400 3524 3525#define IGU_ADDR_MSIX 0x0000 3526#define IGU_ADDR_INT_ACK 0x0200 3527#define IGU_ADDR_PROD_UPD 0x0201 3528#define IGU_ADDR_ATTN_BITS_UPD 0x0202 3529#define IGU_ADDR_ATTN_BITS_SET 0x0203 3530#define IGU_ADDR_ATTN_BITS_CLR 0x0204 3531#define IGU_ADDR_COALESCE_NOW 0x0205 3532#define IGU_ADDR_SIMD_MASK 0x0206 3533#define IGU_ADDR_SIMD_NOMASK 0x0207 3534#define IGU_ADDR_MSI_CTL 0x0210 3535#define IGU_ADDR_MSI_ADDR_LO 0x0211 3536#define IGU_ADDR_MSI_ADDR_HI 0x0212 3537#define IGU_ADDR_MSI_DATA 0x0213 3538 3539 3540#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 3541#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 3542#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 3543#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3 3544 3545#define COMMAND_REG_INT_ACK 0x0 3546#define COMMAND_REG_PROD_UPD 0x4 3547#define COMMAND_REG_ATTN_BITS_UPD 0x8 3548#define COMMAND_REG_ATTN_BITS_SET 0xc 3549#define COMMAND_REG_ATTN_BITS_CLR 0x10 3550#define COMMAND_REG_COALESCE_NOW 0x14 3551#define COMMAND_REG_SIMD_MASK 0x18 3552#define COMMAND_REG_SIMD_NOMASK 0x1c 3553 3554 3555#define IGU_MEM_BASE 0x0000 3556 3557#define IGU_MEM_MSIX_BASE 0x0000 3558#define IGU_MEM_MSIX_UPPER 0x007f 3559#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 3560 3561#define IGU_MEM_PBA_MSIX_BASE 0x0200 3562#define IGU_MEM_PBA_MSIX_UPPER 0x0200 3563 3564#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 3565#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 3566 3567#define IGU_CMD_INT_ACK_BASE 0x0400 3568#define IGU_CMD_INT_ACK_UPPER \ 3569 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PATH - 1) 3570#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff 3571 3572#define IGU_CMD_E2_PROD_UPD_BASE 0x0500 3573#define IGU_CMD_E2_PROD_UPD_UPPER \ 3574 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PATH - 1) 3575#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f 3576 3577#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 3578#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 3579#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 3580 3581#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 3582#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 3583#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 3584#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 3585 3586 3587#define IGU_REG_RESERVED_UPPER 0x05ff 3588 3589#define IGU_SEG_IDX_ATTN 2 3590#define IGU_SEG_IDX_DEFAULT 1 3591/* Fields of IGU PF CONFIGRATION REGISTER */ 3592#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 3593#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 3594#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 3595#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 3596#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 3597#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 3598 3599/* Fields of IGU VF CONFIGRATION REGISTER */ 3600#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 3601#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 3602#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */ 3603#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */ 3604#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 3605 3606 3607#define IGU_BC_DSB_NUM_SEGS 5 3608#define IGU_BC_NDSB_NUM_SEGS 2 3609#define IGU_NORM_DSB_NUM_SEGS 2 3610#define IGU_NORM_NDSB_NUM_SEGS 1 3611#define IGU_BC_BASE_DSB_PROD 128 3612#define IGU_NORM_BASE_DSB_PROD 136 3613 3614 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ 3615 [5:2] = 0; [1:0] = PF number) */ 3616#define IGU_FID_ENCODE_IS_PF (0x1<<6) 3617#define IGU_FID_ENCODE_IS_PF_SHIFT 6 3618#define IGU_FID_VF_NUM_MASK (0x3f) 3619#define IGU_FID_PF_NUM_MASK (0x7) 3620 3621#define IGU_REG_MAPPING_MEMORY_VALID (1<<0) 3622#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1) 3623#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1 3624#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7) 3625#define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7 3626 3627 3628#define CDU_REGION_NUMBER_XCM_AG 2 3629#define CDU_REGION_NUMBER_UCM_AG 4 3630 3631 3632/* String-to-compress [31:8] = CID (all 24 bits) 3633 * String-to-compress [7:4] = Region 3634 * String-to-compress [3:0] = Type 3635 */ 3636#define CDU_VALID_DATA(_cid, _region, _type) \ 3637 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) 3638#define CDU_CRC8(_cid, _region, _type) \ 3639 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) 3640#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \ 3641 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) 3642#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \ 3643 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) 3644#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) 3645 3646/****************************************************************************** 3647 * Description: 3648 * Calculates crc 8 on a word value: polynomial 0-1-2-8 3649 * Code was translated from Verilog. 3650 * Return: 3651 *****************************************************************************/ 3652static inline uint8_t calc_crc8(uint32_t data, uint8_t crc) 3653{ 3654 uint8_t D[32]; 3655 uint8_t NewCRC[8]; 3656 uint8_t C[8]; 3657 uint8_t crc_res; 3658 uint8_t i; 3659 3660 /* split the data into 31 bits */ 3661 for (i = 0; i < 32; i++) { 3662 D[i] = (uint8_t)(data & 1); 3663 data = data >> 1; 3664 } 3665 3666 /* split the crc into 8 bits */ 3667 for (i = 0; i < 8; i++) { 3668 C[i] = crc & 1; 3669 crc = crc >> 1; 3670 } 3671 3672 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ 3673 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ 3674 C[6] ^ C[7]; 3675 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ 3676 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ 3677 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[6]; 3678 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ 3679 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ 3680 C[0] ^ C[1] ^ C[4] ^ C[5]; 3681 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ 3682 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ 3683 C[1] ^ C[2] ^ C[5] ^ C[6]; 3684 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ 3685 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ 3686 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; 3687 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ 3688 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ 3689 C[3] ^ C[4] ^ C[7]; 3690 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ 3691 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ C[5]; 3692 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ 3693 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ C[6]; 3694 3695 crc_res = 0; 3696 for (i = 0; i < 8; i++) { 3697 crc_res |= (NewCRC[i] << i); 3698 } 3699 3700 return crc_res; 3701} 3702 3703 3704#endif /* ECORE_REG_H */ 3705 3706