if_bfe.c revision 181953
1/*- 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 181953 2008-08-21 04:21:53Z yongari $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/endian.h> 35#include <sys/kernel.h> 36#include <sys/malloc.h> 37#include <sys/mbuf.h> 38#include <sys/module.h> 39#include <sys/rman.h> 40#include <sys/socket.h> 41#include <sys/sockio.h> 42 43#include <net/bpf.h> 44#include <net/if.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48#include <net/if_types.h> 49#include <net/if_vlan_var.h> 50 51#include <dev/mii/mii.h> 52#include <dev/mii/miivar.h> 53 54#include <dev/pci/pcireg.h> 55#include <dev/pci/pcivar.h> 56 57#include <machine/bus.h> 58 59#include <dev/bfe/if_bfereg.h> 60 61MODULE_DEPEND(bfe, pci, 1, 1, 1); 62MODULE_DEPEND(bfe, ether, 1, 1, 1); 63MODULE_DEPEND(bfe, miibus, 1, 1, 1); 64 65/* "device miibus" required. See GENERIC if you get errors here. */ 66#include "miibus_if.h" 67 68#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 69 70static struct bfe_type bfe_devs[] = { 71 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 72 "Broadcom BCM4401 Fast Ethernet" }, 73 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0, 74 "Broadcom BCM4401-B0 Fast Ethernet" }, 75 { 0, 0, NULL } 76}; 77 78static int bfe_probe (device_t); 79static int bfe_attach (device_t); 80static int bfe_detach (device_t); 81static int bfe_suspend (device_t); 82static int bfe_resume (device_t); 83static void bfe_release_resources (struct bfe_softc *); 84static void bfe_intr (void *); 85static int bfe_encap (struct bfe_softc *, struct mbuf **); 86static void bfe_start (struct ifnet *); 87static void bfe_start_locked (struct ifnet *); 88static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 89static void bfe_init (void *); 90static void bfe_init_locked (void *); 91static void bfe_stop (struct bfe_softc *); 92static void bfe_watchdog (struct bfe_softc *); 93static int bfe_shutdown (device_t); 94static void bfe_tick (void *); 95static void bfe_txeof (struct bfe_softc *); 96static void bfe_rxeof (struct bfe_softc *); 97static void bfe_set_rx_mode (struct bfe_softc *); 98static int bfe_list_rx_init (struct bfe_softc *); 99static void bfe_list_tx_init (struct bfe_softc *); 100static void bfe_discard_buf (struct bfe_softc *, int); 101static int bfe_list_newbuf (struct bfe_softc *, int); 102static void bfe_rx_ring_free (struct bfe_softc *); 103 104static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 105static int bfe_ifmedia_upd (struct ifnet *); 106static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 107static int bfe_miibus_readreg (device_t, int, int); 108static int bfe_miibus_writereg (device_t, int, int, int); 109static void bfe_miibus_statchg (device_t); 110static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 111 u_long, const int); 112static void bfe_get_config (struct bfe_softc *sc); 113static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 114static void bfe_stats_update (struct bfe_softc *); 115static void bfe_clear_stats (struct bfe_softc *); 116static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 117static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 118static int bfe_resetphy (struct bfe_softc *); 119static int bfe_setupphy (struct bfe_softc *); 120static void bfe_chip_reset (struct bfe_softc *); 121static void bfe_chip_halt (struct bfe_softc *); 122static void bfe_core_reset (struct bfe_softc *); 123static void bfe_core_disable (struct bfe_softc *); 124static int bfe_dma_alloc (struct bfe_softc *); 125static void bfe_dma_free (struct bfe_softc *sc); 126static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 127static void bfe_cam_write (struct bfe_softc *, u_char *, int); 128 129static device_method_t bfe_methods[] = { 130 /* Device interface */ 131 DEVMETHOD(device_probe, bfe_probe), 132 DEVMETHOD(device_attach, bfe_attach), 133 DEVMETHOD(device_detach, bfe_detach), 134 DEVMETHOD(device_shutdown, bfe_shutdown), 135 DEVMETHOD(device_suspend, bfe_suspend), 136 DEVMETHOD(device_resume, bfe_resume), 137 138 /* bus interface */ 139 DEVMETHOD(bus_print_child, bus_generic_print_child), 140 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 141 142 /* MII interface */ 143 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 144 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 145 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 146 147 { 0, 0 } 148}; 149 150static driver_t bfe_driver = { 151 "bfe", 152 bfe_methods, 153 sizeof(struct bfe_softc) 154}; 155 156static devclass_t bfe_devclass; 157 158DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 159DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 160 161/* 162 * Probe for a Broadcom 4401 chip. 163 */ 164static int 165bfe_probe(device_t dev) 166{ 167 struct bfe_type *t; 168 169 t = bfe_devs; 170 171 while (t->bfe_name != NULL) { 172 if (pci_get_vendor(dev) == t->bfe_vid && 173 pci_get_device(dev) == t->bfe_did) { 174 device_set_desc(dev, t->bfe_name); 175 return (BUS_PROBE_DEFAULT); 176 } 177 t++; 178 } 179 180 return (ENXIO); 181} 182 183struct bfe_dmamap_arg { 184 bus_addr_t bfe_busaddr; 185}; 186 187static int 188bfe_dma_alloc(struct bfe_softc *sc) 189{ 190 struct bfe_dmamap_arg ctx; 191 struct bfe_rx_data *rd; 192 struct bfe_tx_data *td; 193 int error, i; 194 195 /* 196 * parent tag. Apparently the chip cannot handle any DMA address 197 * greater than 1GB. 198 */ 199 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */ 200 1, 0, /* alignment, boundary */ 201 BFE_DMA_MAXADDR, /* lowaddr */ 202 BUS_SPACE_MAXADDR, /* highaddr */ 203 NULL, NULL, /* filter, filterarg */ 204 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 205 0, /* nsegments */ 206 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 207 0, /* flags */ 208 NULL, NULL, /* lockfunc, lockarg */ 209 &sc->bfe_parent_tag); 210 if (error != 0) { 211 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n"); 212 goto fail; 213 } 214 215 /* Create tag for Tx ring. */ 216 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 217 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */ 218 BUS_SPACE_MAXADDR, /* lowaddr */ 219 BUS_SPACE_MAXADDR, /* highaddr */ 220 NULL, NULL, /* filter, filterarg */ 221 BFE_TX_LIST_SIZE, /* maxsize */ 222 1, /* nsegments */ 223 BFE_TX_LIST_SIZE, /* maxsegsize */ 224 0, /* flags */ 225 NULL, NULL, /* lockfunc, lockarg */ 226 &sc->bfe_tx_tag); 227 if (error != 0) { 228 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n"); 229 goto fail; 230 } 231 232 /* Create tag for Rx ring. */ 233 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 234 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */ 235 BUS_SPACE_MAXADDR, /* lowaddr */ 236 BUS_SPACE_MAXADDR, /* highaddr */ 237 NULL, NULL, /* filter, filterarg */ 238 BFE_RX_LIST_SIZE, /* maxsize */ 239 1, /* nsegments */ 240 BFE_RX_LIST_SIZE, /* maxsegsize */ 241 0, /* flags */ 242 NULL, NULL, /* lockfunc, lockarg */ 243 &sc->bfe_rx_tag); 244 if (error != 0) { 245 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n"); 246 goto fail; 247 } 248 249 /* Create tag for Tx buffers. */ 250 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 251 1, 0, /* alignment, boundary */ 252 BUS_SPACE_MAXADDR, /* lowaddr */ 253 BUS_SPACE_MAXADDR, /* highaddr */ 254 NULL, NULL, /* filter, filterarg */ 255 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */ 256 BFE_MAXTXSEGS, /* nsegments */ 257 MCLBYTES, /* maxsegsize */ 258 0, /* flags */ 259 NULL, NULL, /* lockfunc, lockarg */ 260 &sc->bfe_txmbuf_tag); 261 if (error != 0) { 262 device_printf(sc->bfe_dev, 263 "cannot create Tx buffer DMA tag.\n"); 264 goto fail; 265 } 266 267 /* Create tag for Rx buffers. */ 268 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */ 269 1, 0, /* alignment, boundary */ 270 BUS_SPACE_MAXADDR, /* lowaddr */ 271 BUS_SPACE_MAXADDR, /* highaddr */ 272 NULL, NULL, /* filter, filterarg */ 273 MCLBYTES, /* maxsize */ 274 1, /* nsegments */ 275 MCLBYTES, /* maxsegsize */ 276 0, /* flags */ 277 NULL, NULL, /* lockfunc, lockarg */ 278 &sc->bfe_rxmbuf_tag); 279 if (error != 0) { 280 device_printf(sc->bfe_dev, 281 "cannot create Rx buffer DMA tag.\n"); 282 goto fail; 283 } 284 285 /* Allocate DMA'able memory and load DMA map. */ 286 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 287 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map); 288 if (error != 0) { 289 device_printf(sc->bfe_dev, 290 "cannot allocate DMA'able memory for Tx ring.\n"); 291 goto fail; 292 } 293 ctx.bfe_busaddr = 0; 294 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 295 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx, 296 BUS_DMA_NOWAIT); 297 if (error != 0 || ctx.bfe_busaddr == 0) { 298 device_printf(sc->bfe_dev, 299 "cannot load DMA'able memory for Tx ring.\n"); 300 goto fail; 301 } 302 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 303 304 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 305 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map); 306 if (error != 0) { 307 device_printf(sc->bfe_dev, 308 "cannot allocate DMA'able memory for Rx ring.\n"); 309 goto fail; 310 } 311 ctx.bfe_busaddr = 0; 312 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 313 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx, 314 BUS_DMA_NOWAIT); 315 if (error != 0 || ctx.bfe_busaddr == 0) { 316 device_printf(sc->bfe_dev, 317 "cannot load DMA'able memory for Rx ring.\n"); 318 goto fail; 319 } 320 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr); 321 322 /* Create DMA maps for Tx buffers. */ 323 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 324 td = &sc->bfe_tx_ring[i]; 325 td->bfe_mbuf = NULL; 326 td->bfe_map = NULL; 327 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map); 328 if (error != 0) { 329 device_printf(sc->bfe_dev, 330 "cannot create DMA map for Tx.\n"); 331 goto fail; 332 } 333 } 334 335 /* Create spare DMA map for Rx buffers. */ 336 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap); 337 if (error != 0) { 338 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n"); 339 goto fail; 340 } 341 /* Create DMA maps for Rx buffers. */ 342 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 343 rd = &sc->bfe_rx_ring[i]; 344 rd->bfe_mbuf = NULL; 345 rd->bfe_map = NULL; 346 rd->bfe_ctrl = 0; 347 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map); 348 if (error != 0) { 349 device_printf(sc->bfe_dev, 350 "cannot create DMA map for Rx.\n"); 351 goto fail; 352 } 353 } 354 355fail: 356 return (error); 357} 358 359static void 360bfe_dma_free(struct bfe_softc *sc) 361{ 362 struct bfe_tx_data *td; 363 struct bfe_rx_data *rd; 364 int i; 365 366 /* Tx ring. */ 367 if (sc->bfe_tx_tag != NULL) { 368 if (sc->bfe_tx_map != NULL) 369 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 370 if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL) 371 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 372 sc->bfe_tx_map); 373 sc->bfe_tx_map = NULL; 374 sc->bfe_tx_list = NULL; 375 bus_dma_tag_destroy(sc->bfe_tx_tag); 376 sc->bfe_tx_tag = NULL; 377 } 378 379 /* Rx ring. */ 380 if (sc->bfe_rx_tag != NULL) { 381 if (sc->bfe_rx_map != NULL) 382 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 383 if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL) 384 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 385 sc->bfe_rx_map); 386 sc->bfe_rx_map = NULL; 387 sc->bfe_rx_list = NULL; 388 bus_dma_tag_destroy(sc->bfe_rx_tag); 389 sc->bfe_rx_tag = NULL; 390 } 391 392 /* Tx buffers. */ 393 if (sc->bfe_txmbuf_tag != NULL) { 394 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 395 td = &sc->bfe_tx_ring[i]; 396 if (td->bfe_map != NULL) { 397 bus_dmamap_destroy(sc->bfe_txmbuf_tag, 398 td->bfe_map); 399 td->bfe_map = NULL; 400 } 401 } 402 bus_dma_tag_destroy(sc->bfe_txmbuf_tag); 403 sc->bfe_txmbuf_tag = NULL; 404 } 405 406 /* Rx buffers. */ 407 if (sc->bfe_rxmbuf_tag != NULL) { 408 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 409 rd = &sc->bfe_rx_ring[i]; 410 if (rd->bfe_map != NULL) { 411 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 412 rd->bfe_map); 413 rd->bfe_map = NULL; 414 } 415 } 416 if (sc->bfe_rx_sparemap != NULL) { 417 bus_dmamap_destroy(sc->bfe_rxmbuf_tag, 418 sc->bfe_rx_sparemap); 419 sc->bfe_rx_sparemap = NULL; 420 } 421 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag); 422 sc->bfe_rxmbuf_tag = NULL; 423 } 424 425 if (sc->bfe_parent_tag != NULL) { 426 bus_dma_tag_destroy(sc->bfe_parent_tag); 427 sc->bfe_parent_tag = NULL; 428 } 429} 430 431static int 432bfe_attach(device_t dev) 433{ 434 struct ifnet *ifp = NULL; 435 struct bfe_softc *sc; 436 int error = 0, rid; 437 438 sc = device_get_softc(dev); 439 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 440 MTX_DEF); 441 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0); 442 443 sc->bfe_dev = dev; 444 445 /* 446 * Map control/status registers. 447 */ 448 pci_enable_busmaster(dev); 449 450 rid = PCIR_BAR(0); 451 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 452 RF_ACTIVE); 453 if (sc->bfe_res == NULL) { 454 device_printf(dev, "couldn't map memory\n"); 455 error = ENXIO; 456 goto fail; 457 } 458 459 /* Allocate interrupt */ 460 rid = 0; 461 462 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 463 RF_SHAREABLE | RF_ACTIVE); 464 if (sc->bfe_irq == NULL) { 465 device_printf(dev, "couldn't map interrupt\n"); 466 error = ENXIO; 467 goto fail; 468 } 469 470 if (bfe_dma_alloc(sc) != 0) { 471 device_printf(dev, "failed to allocate DMA resources\n"); 472 error = ENXIO; 473 goto fail; 474 } 475 476 /* Set up ifnet structure */ 477 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER); 478 if (ifp == NULL) { 479 device_printf(dev, "failed to if_alloc()\n"); 480 error = ENOSPC; 481 goto fail; 482 } 483 ifp->if_softc = sc; 484 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 485 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 486 ifp->if_ioctl = bfe_ioctl; 487 ifp->if_start = bfe_start; 488 ifp->if_init = bfe_init; 489 ifp->if_mtu = ETHERMTU; 490 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 491 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 492 IFQ_SET_READY(&ifp->if_snd); 493 494 bfe_get_config(sc); 495 496 /* Reset the chip and turn on the PHY */ 497 BFE_LOCK(sc); 498 bfe_chip_reset(sc); 499 BFE_UNLOCK(sc); 500 501 if (mii_phy_probe(dev, &sc->bfe_miibus, 502 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 503 device_printf(dev, "MII without any PHY!\n"); 504 error = ENXIO; 505 goto fail; 506 } 507 508 ether_ifattach(ifp, sc->bfe_enaddr); 509 510 /* 511 * Tell the upper layer(s) we support long frames. 512 */ 513 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 514 ifp->if_capabilities |= IFCAP_VLAN_MTU; 515 ifp->if_capenable |= IFCAP_VLAN_MTU; 516 517 /* 518 * Hook interrupt last to avoid having to lock softc 519 */ 520 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE, 521 NULL, bfe_intr, sc, &sc->bfe_intrhand); 522 523 if (error) { 524 device_printf(dev, "couldn't set up irq\n"); 525 goto fail; 526 } 527fail: 528 if (error != 0) 529 bfe_detach(dev); 530 return (error); 531} 532 533static int 534bfe_detach(device_t dev) 535{ 536 struct bfe_softc *sc; 537 struct ifnet *ifp; 538 539 sc = device_get_softc(dev); 540 541 ifp = sc->bfe_ifp; 542 543 if (device_is_attached(dev)) { 544 BFE_LOCK(sc); 545 bfe_stop(sc); 546 BFE_UNLOCK(sc); 547 callout_drain(&sc->bfe_stat_co); 548 if (ifp != NULL) 549 ether_ifdetach(ifp); 550 } 551 552 BFE_LOCK(sc); 553 bfe_chip_reset(sc); 554 BFE_UNLOCK(sc); 555 556 bus_generic_detach(dev); 557 if (sc->bfe_miibus != NULL) 558 device_delete_child(dev, sc->bfe_miibus); 559 560 bfe_release_resources(sc); 561 bfe_dma_free(sc); 562 mtx_destroy(&sc->bfe_mtx); 563 564 return (0); 565} 566 567/* 568 * Stop all chip I/O so that the kernel's probe routines don't 569 * get confused by errant DMAs when rebooting. 570 */ 571static int 572bfe_shutdown(device_t dev) 573{ 574 struct bfe_softc *sc; 575 576 sc = device_get_softc(dev); 577 BFE_LOCK(sc); 578 bfe_stop(sc); 579 580 BFE_UNLOCK(sc); 581 582 return (0); 583} 584 585static int 586bfe_suspend(device_t dev) 587{ 588 struct bfe_softc *sc; 589 590 sc = device_get_softc(dev); 591 BFE_LOCK(sc); 592 bfe_stop(sc); 593 BFE_UNLOCK(sc); 594 595 return (0); 596} 597 598static int 599bfe_resume(device_t dev) 600{ 601 struct bfe_softc *sc; 602 struct ifnet *ifp; 603 604 sc = device_get_softc(dev); 605 ifp = sc->bfe_ifp; 606 BFE_LOCK(sc); 607 bfe_chip_reset(sc); 608 if (ifp->if_flags & IFF_UP) { 609 bfe_init_locked(sc); 610 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 611 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 612 bfe_start_locked(ifp); 613 } 614 BFE_UNLOCK(sc); 615 616 return (0); 617} 618 619static int 620bfe_miibus_readreg(device_t dev, int phy, int reg) 621{ 622 struct bfe_softc *sc; 623 u_int32_t ret; 624 625 sc = device_get_softc(dev); 626 if (phy != sc->bfe_phyaddr) 627 return (0); 628 bfe_readphy(sc, reg, &ret); 629 630 return (ret); 631} 632 633static int 634bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 635{ 636 struct bfe_softc *sc; 637 638 sc = device_get_softc(dev); 639 if (phy != sc->bfe_phyaddr) 640 return (0); 641 bfe_writephy(sc, reg, val); 642 643 return (0); 644} 645 646static void 647bfe_miibus_statchg(device_t dev) 648{ 649 struct bfe_softc *sc; 650 struct mii_data *mii; 651 u_int32_t val, flow; 652 653 sc = device_get_softc(dev); 654 mii = device_get_softc(sc->bfe_miibus); 655 656 if ((mii->mii_media_status & IFM_ACTIVE) != 0) { 657 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 658 sc->bfe_link = 1; 659 } else 660 sc->bfe_link = 0; 661 662 /* XXX Should stop Rx/Tx engine prior to touching MAC. */ 663 val = CSR_READ_4(sc, BFE_TX_CTRL); 664 val &= ~BFE_TX_DUPLEX; 665 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 666 val |= BFE_TX_DUPLEX; 667 flow = 0; 668#ifdef notyet 669 flow = CSR_READ_4(sc, BFE_RXCONF); 670 flow &= ~BFE_RXCONF_FLOW; 671 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 672 IFM_ETH_RXPAUSE) != 0) 673 flow |= BFE_RXCONF_FLOW; 674 CSR_WRITE_4(sc, BFE_RXCONF, flow); 675 /* 676 * It seems that the hardware has Tx pause issues 677 * so enable only Rx pause. 678 */ 679 flow = CSR_READ_4(sc, BFE_MAC_FLOW); 680 flow &= ~BFE_FLOW_PAUSE_ENAB; 681 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow); 682#endif 683 } 684 CSR_WRITE_4(sc, BFE_TX_CTRL, val); 685} 686 687static void 688bfe_tx_ring_free(struct bfe_softc *sc) 689{ 690 int i; 691 692 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 693 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 694 bus_dmamap_sync(sc->bfe_txmbuf_tag, 695 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE); 696 bus_dmamap_unload(sc->bfe_txmbuf_tag, 697 sc->bfe_tx_ring[i].bfe_map); 698 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 699 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 700 } 701 } 702 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 703 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 704 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 705} 706 707static void 708bfe_rx_ring_free(struct bfe_softc *sc) 709{ 710 int i; 711 712 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 713 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 714 bus_dmamap_sync(sc->bfe_rxmbuf_tag, 715 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD); 716 bus_dmamap_unload(sc->bfe_rxmbuf_tag, 717 sc->bfe_rx_ring[i].bfe_map); 718 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 719 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 720 } 721 } 722 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 723 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 724 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 725} 726 727static int 728bfe_list_rx_init(struct bfe_softc *sc) 729{ 730 struct bfe_rx_data *rd; 731 int i; 732 733 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 734 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 735 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 736 rd = &sc->bfe_rx_ring[i]; 737 rd->bfe_mbuf = NULL; 738 rd->bfe_ctrl = 0; 739 if (bfe_list_newbuf(sc, i) != 0) 740 return (ENOBUFS); 741 } 742 743 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 744 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 745 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 746 747 return (0); 748} 749 750static void 751bfe_list_tx_init(struct bfe_softc *sc) 752{ 753 int i; 754 755 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 756 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 757 for (i = 0; i < BFE_TX_LIST_CNT; i++) 758 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 759 760 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 761 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 762} 763 764static void 765bfe_discard_buf(struct bfe_softc *sc, int c) 766{ 767 struct bfe_rx_data *r; 768 struct bfe_desc *d; 769 770 r = &sc->bfe_rx_ring[c]; 771 d = &sc->bfe_rx_list[c]; 772 d->bfe_ctrl = htole32(r->bfe_ctrl); 773} 774 775static int 776bfe_list_newbuf(struct bfe_softc *sc, int c) 777{ 778 struct bfe_rxheader *rx_header; 779 struct bfe_desc *d; 780 struct bfe_rx_data *r; 781 struct mbuf *m; 782 bus_dma_segment_t segs[1]; 783 bus_dmamap_t map; 784 u_int32_t ctrl; 785 int nsegs; 786 787 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 788 m->m_len = m->m_pkthdr.len = MCLBYTES; 789 790 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap, 791 m, segs, &nsegs, 0) != 0) { 792 m_freem(m); 793 return (ENOBUFS); 794 } 795 796 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 797 r = &sc->bfe_rx_ring[c]; 798 if (r->bfe_mbuf != NULL) { 799 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, 800 BUS_DMASYNC_POSTREAD); 801 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map); 802 } 803 map = r->bfe_map; 804 r->bfe_map = sc->bfe_rx_sparemap; 805 sc->bfe_rx_sparemap = map; 806 r->bfe_mbuf = m; 807 808 rx_header = mtod(m, struct bfe_rxheader *); 809 rx_header->len = 0; 810 rx_header->flags = 0; 811 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD); 812 813 ctrl = segs[0].ds_len & BFE_DESC_LEN; 814 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!", 815 __func__, ctrl)); 816 if (c == BFE_RX_LIST_CNT - 1) 817 ctrl |= BFE_DESC_EOT; 818 r->bfe_ctrl = ctrl; 819 820 d = &sc->bfe_rx_list[c]; 821 d->bfe_ctrl = htole32(ctrl); 822 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 823 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA); 824 825 return (0); 826} 827 828static void 829bfe_get_config(struct bfe_softc *sc) 830{ 831 u_int8_t eeprom[128]; 832 833 bfe_read_eeprom(sc, eeprom); 834 835 sc->bfe_enaddr[0] = eeprom[79]; 836 sc->bfe_enaddr[1] = eeprom[78]; 837 sc->bfe_enaddr[2] = eeprom[81]; 838 sc->bfe_enaddr[3] = eeprom[80]; 839 sc->bfe_enaddr[4] = eeprom[83]; 840 sc->bfe_enaddr[5] = eeprom[82]; 841 842 sc->bfe_phyaddr = eeprom[90] & 0x1f; 843 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 844 845 sc->bfe_core_unit = 0; 846 sc->bfe_dma_offset = BFE_PCI_DMA; 847} 848 849static void 850bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 851{ 852 u_int32_t bar_orig, pci_rev, val; 853 854 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 855 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 856 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 857 858 val = CSR_READ_4(sc, BFE_SBINTVEC); 859 val |= cores; 860 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 861 862 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 863 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 864 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 865 866 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 867} 868 869static void 870bfe_clear_stats(struct bfe_softc *sc) 871{ 872 u_long reg; 873 874 BFE_LOCK_ASSERT(sc); 875 876 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 877 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 878 CSR_READ_4(sc, reg); 879 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 880 CSR_READ_4(sc, reg); 881} 882 883static int 884bfe_resetphy(struct bfe_softc *sc) 885{ 886 u_int32_t val; 887 888 bfe_writephy(sc, 0, BMCR_RESET); 889 DELAY(100); 890 bfe_readphy(sc, 0, &val); 891 if (val & BMCR_RESET) { 892 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n"); 893 return (ENXIO); 894 } 895 return (0); 896} 897 898static void 899bfe_chip_halt(struct bfe_softc *sc) 900{ 901 BFE_LOCK_ASSERT(sc); 902 /* disable interrupts - not that it actually does..*/ 903 CSR_WRITE_4(sc, BFE_IMASK, 0); 904 CSR_READ_4(sc, BFE_IMASK); 905 906 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 907 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 908 909 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 910 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 911 DELAY(10); 912} 913 914static void 915bfe_chip_reset(struct bfe_softc *sc) 916{ 917 u_int32_t val; 918 919 BFE_LOCK_ASSERT(sc); 920 921 /* Set the interrupt vector for the enet core */ 922 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 923 924 /* is core up? */ 925 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 926 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 927 if (val == BFE_CLOCK) { 928 /* It is, so shut it down */ 929 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 930 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 931 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 932 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 933 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 934 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 935 100, 0); 936 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 937 } 938 939 bfe_core_reset(sc); 940 bfe_clear_stats(sc); 941 942 /* 943 * We want the phy registers to be accessible even when 944 * the driver is "downed" so initialize MDC preamble, frequency, 945 * and whether internal or external phy here. 946 */ 947 948 /* 4402 has 62.5Mhz SB clock and internal phy */ 949 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 950 951 /* Internal or external PHY? */ 952 val = CSR_READ_4(sc, BFE_DEVCTRL); 953 if (!(val & BFE_IPP)) 954 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 955 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 956 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 957 DELAY(100); 958 } 959 960 /* Enable CRC32 generation and set proper LED modes */ 961 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 962 963 /* Reset or clear powerdown control bit */ 964 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 965 966 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 967 BFE_LAZY_FC_MASK)); 968 969 /* 970 * We don't want lazy interrupts, so just send them at 971 * the end of a frame, please 972 */ 973 BFE_OR(sc, BFE_RCV_LAZY, 0); 974 975 /* Set max lengths, accounting for VLAN tags */ 976 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 977 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 978 979 /* Set watermark XXX - magic */ 980 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 981 982 /* 983 * Initialise DMA channels 984 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 985 */ 986 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 987 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 988 989 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 990 BFE_RX_CTRL_ENABLE); 991 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 992 993 bfe_resetphy(sc); 994 bfe_setupphy(sc); 995} 996 997static void 998bfe_core_disable(struct bfe_softc *sc) 999{ 1000 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 1001 return; 1002 1003 /* 1004 * Set reject, wait for it set, then wait for the core to stop 1005 * being busy, then set reset and reject and enable the clocks. 1006 */ 1007 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 1008 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 1009 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 1010 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 1011 BFE_RESET)); 1012 CSR_READ_4(sc, BFE_SBTMSLOW); 1013 DELAY(10); 1014 /* Leave reset and reject set */ 1015 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 1016 DELAY(10); 1017} 1018 1019static void 1020bfe_core_reset(struct bfe_softc *sc) 1021{ 1022 u_int32_t val; 1023 1024 /* Disable the core */ 1025 bfe_core_disable(sc); 1026 1027 /* and bring it back up */ 1028 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 1029 CSR_READ_4(sc, BFE_SBTMSLOW); 1030 DELAY(10); 1031 1032 /* Chip bug, clear SERR, IB and TO if they are set. */ 1033 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 1034 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 1035 val = CSR_READ_4(sc, BFE_SBIMSTATE); 1036 if (val & (BFE_IBE | BFE_TO)) 1037 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 1038 1039 /* Clear reset and allow it to move through the core */ 1040 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 1041 CSR_READ_4(sc, BFE_SBTMSLOW); 1042 DELAY(10); 1043 1044 /* Leave the clock set */ 1045 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 1046 CSR_READ_4(sc, BFE_SBTMSLOW); 1047 DELAY(10); 1048} 1049 1050static void 1051bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 1052{ 1053 u_int32_t val; 1054 1055 val = ((u_int32_t) data[2]) << 24; 1056 val |= ((u_int32_t) data[3]) << 16; 1057 val |= ((u_int32_t) data[4]) << 8; 1058 val |= ((u_int32_t) data[5]); 1059 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 1060 val = (BFE_CAM_HI_VALID | 1061 (((u_int32_t) data[0]) << 8) | 1062 (((u_int32_t) data[1]))); 1063 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 1064 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 1065 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 1066 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 1067} 1068 1069static void 1070bfe_set_rx_mode(struct bfe_softc *sc) 1071{ 1072 struct ifnet *ifp = sc->bfe_ifp; 1073 struct ifmultiaddr *ifma; 1074 u_int32_t val; 1075 int i = 0; 1076 1077 val = CSR_READ_4(sc, BFE_RXCONF); 1078 1079 if (ifp->if_flags & IFF_PROMISC) 1080 val |= BFE_RXCONF_PROMISC; 1081 else 1082 val &= ~BFE_RXCONF_PROMISC; 1083 1084 if (ifp->if_flags & IFF_BROADCAST) 1085 val &= ~BFE_RXCONF_DBCAST; 1086 else 1087 val |= BFE_RXCONF_DBCAST; 1088 1089 1090 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 1091 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++); 1092 1093 if (ifp->if_flags & IFF_ALLMULTI) 1094 val |= BFE_RXCONF_ALLMULTI; 1095 else { 1096 val &= ~BFE_RXCONF_ALLMULTI; 1097 IF_ADDR_LOCK(ifp); 1098 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1099 if (ifma->ifma_addr->sa_family != AF_LINK) 1100 continue; 1101 bfe_cam_write(sc, 1102 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 1103 } 1104 IF_ADDR_UNLOCK(ifp); 1105 } 1106 1107 CSR_WRITE_4(sc, BFE_RXCONF, val); 1108 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 1109} 1110 1111static void 1112bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1113{ 1114 struct bfe_dmamap_arg *ctx; 1115 1116 if (error != 0) 1117 return; 1118 1119 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg)); 1120 1121 ctx = (struct bfe_dmamap_arg *)arg; 1122 ctx->bfe_busaddr = segs[0].ds_addr; 1123} 1124 1125static void 1126bfe_release_resources(struct bfe_softc *sc) 1127{ 1128 1129 if (sc->bfe_intrhand != NULL) 1130 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand); 1131 1132 if (sc->bfe_irq != NULL) 1133 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq); 1134 1135 if (sc->bfe_res != NULL) 1136 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0), 1137 sc->bfe_res); 1138 1139 if (sc->bfe_ifp != NULL) 1140 if_free(sc->bfe_ifp); 1141} 1142 1143static void 1144bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 1145{ 1146 long i; 1147 u_int16_t *ptr = (u_int16_t *)data; 1148 1149 for(i = 0; i < 128; i += 2) 1150 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1151} 1152 1153static int 1154bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1155 u_long timeout, const int clear) 1156{ 1157 u_long i; 1158 1159 for (i = 0; i < timeout; i++) { 1160 u_int32_t val = CSR_READ_4(sc, reg); 1161 1162 if (clear && !(val & bit)) 1163 break; 1164 if (!clear && (val & bit)) 1165 break; 1166 DELAY(10); 1167 } 1168 if (i == timeout) { 1169 device_printf(sc->bfe_dev, 1170 "BUG! Timeout waiting for bit %08x of register " 1171 "%x to %s.\n", bit, reg, (clear ? "clear" : "set")); 1172 return (-1); 1173 } 1174 return (0); 1175} 1176 1177static int 1178bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1179{ 1180 int err; 1181 1182 /* Clear MII ISR */ 1183 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1184 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1185 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1186 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1187 (reg << BFE_MDIO_RA_SHIFT) | 1188 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1189 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1190 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1191 1192 return (err); 1193} 1194 1195static int 1196bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1197{ 1198 int status; 1199 1200 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1201 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1202 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1203 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1204 (reg << BFE_MDIO_RA_SHIFT) | 1205 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1206 (val & BFE_MDIO_DATA_DATA))); 1207 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1208 1209 return (status); 1210} 1211 1212/* 1213 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1214 * twice 1215 */ 1216static int 1217bfe_setupphy(struct bfe_softc *sc) 1218{ 1219 u_int32_t val; 1220 1221 /* Enable activity LED */ 1222 bfe_readphy(sc, 26, &val); 1223 bfe_writephy(sc, 26, val & 0x7fff); 1224 bfe_readphy(sc, 26, &val); 1225 1226 /* Enable traffic meter LED mode */ 1227 bfe_readphy(sc, 27, &val); 1228 bfe_writephy(sc, 27, val | (1 << 6)); 1229 1230 return (0); 1231} 1232 1233static void 1234bfe_stats_update(struct bfe_softc *sc) 1235{ 1236 u_long reg; 1237 u_int32_t *val; 1238 1239 val = &sc->bfe_hwstats.tx_good_octets; 1240 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1241 *val++ += CSR_READ_4(sc, reg); 1242 } 1243 val = &sc->bfe_hwstats.rx_good_octets; 1244 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1245 *val++ += CSR_READ_4(sc, reg); 1246 } 1247} 1248 1249static void 1250bfe_txeof(struct bfe_softc *sc) 1251{ 1252 struct bfe_tx_data *r; 1253 struct ifnet *ifp; 1254 int i, chipidx; 1255 1256 BFE_LOCK_ASSERT(sc); 1257 1258 ifp = sc->bfe_ifp; 1259 1260 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1261 chipidx /= sizeof(struct bfe_desc); 1262 1263 i = sc->bfe_tx_cons; 1264 if (i == chipidx) 1265 return; 1266 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1267 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1268 /* Go through the mbufs and free those that have been transmitted */ 1269 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) { 1270 r = &sc->bfe_tx_ring[i]; 1271 sc->bfe_tx_cnt--; 1272 if (r->bfe_mbuf == NULL) 1273 continue; 1274 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map, 1275 BUS_DMASYNC_POSTWRITE); 1276 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1277 1278 ifp->if_opackets++; 1279 m_freem(r->bfe_mbuf); 1280 r->bfe_mbuf = NULL; 1281 } 1282 1283 if (i != sc->bfe_tx_cons) { 1284 /* we freed up some mbufs */ 1285 sc->bfe_tx_cons = i; 1286 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1287 } 1288 1289 if (sc->bfe_tx_cnt == 0) 1290 sc->bfe_watchdog_timer = 0; 1291} 1292 1293/* Pass a received packet up the stack */ 1294static void 1295bfe_rxeof(struct bfe_softc *sc) 1296{ 1297 struct mbuf *m; 1298 struct ifnet *ifp; 1299 struct bfe_rxheader *rxheader; 1300 struct bfe_rx_data *r; 1301 int cons, prog; 1302 u_int32_t status, current, len, flags; 1303 1304 BFE_LOCK_ASSERT(sc); 1305 cons = sc->bfe_rx_cons; 1306 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1307 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1308 1309 ifp = sc->bfe_ifp; 1310 1311 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1312 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1313 1314 for (prog = 0; current != cons; prog++, 1315 BFE_INC(cons, BFE_RX_LIST_CNT)) { 1316 r = &sc->bfe_rx_ring[cons]; 1317 m = r->bfe_mbuf; 1318 /* 1319 * Rx status should be read from mbuf such that we can't 1320 * delay bus_dmamap_sync(9). This hardware limiation 1321 * results in inefficent mbuf usage as bfe(4) couldn't 1322 * reuse mapped buffer from errored frame. 1323 */ 1324 if (bfe_list_newbuf(sc, cons) != 0) { 1325 ifp->if_iqdrops++; 1326 bfe_discard_buf(sc, cons); 1327 continue; 1328 } 1329 rxheader = mtod(m, struct bfe_rxheader*); 1330 len = le16toh(rxheader->len); 1331 flags = le16toh(rxheader->flags); 1332 1333 /* Remove CRC bytes. */ 1334 len -= ETHER_CRC_LEN; 1335 1336 /* flag an error and try again */ 1337 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1338 ifp->if_ierrors++; 1339 if (flags & BFE_RX_FLAG_SERR) 1340 ifp->if_collisions++; 1341 m_freem(m); 1342 continue; 1343 } 1344 1345 /* Make sure to skip header bytes written by hardware. */ 1346 m_adj(m, BFE_RX_OFFSET); 1347 m->m_len = m->m_pkthdr.len = len; 1348 1349 ifp->if_ipackets++; 1350 m->m_pkthdr.rcvif = ifp; 1351 BFE_UNLOCK(sc); 1352 (*ifp->if_input)(ifp, m); 1353 BFE_LOCK(sc); 1354 } 1355 1356 if (prog > 0) { 1357 sc->bfe_rx_cons = cons; 1358 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, 1359 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1360 } 1361} 1362 1363static void 1364bfe_intr(void *xsc) 1365{ 1366 struct bfe_softc *sc = xsc; 1367 struct ifnet *ifp; 1368 u_int32_t istat, imask, flag; 1369 1370 ifp = sc->bfe_ifp; 1371 1372 BFE_LOCK(sc); 1373 1374 istat = CSR_READ_4(sc, BFE_ISTAT); 1375 imask = CSR_READ_4(sc, BFE_IMASK); 1376 1377 /* 1378 * Defer unsolicited interrupts - This is necessary because setting the 1379 * chips interrupt mask register to 0 doesn't actually stop the 1380 * interrupts 1381 */ 1382 istat &= imask; 1383 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1384 CSR_READ_4(sc, BFE_ISTAT); 1385 1386 /* not expecting this interrupt, disregard it */ 1387 if (istat == 0) { 1388 BFE_UNLOCK(sc); 1389 return; 1390 } 1391 1392 if (istat & BFE_ISTAT_ERRORS) { 1393 1394 if (istat & BFE_ISTAT_DSCE) { 1395 device_printf(sc->bfe_dev, "Descriptor Error\n"); 1396 bfe_stop(sc); 1397 BFE_UNLOCK(sc); 1398 return; 1399 } 1400 1401 if (istat & BFE_ISTAT_DPE) { 1402 device_printf(sc->bfe_dev, 1403 "Descriptor Protocol Error\n"); 1404 bfe_stop(sc); 1405 BFE_UNLOCK(sc); 1406 return; 1407 } 1408 1409 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1410 if (flag & BFE_STAT_EMASK) 1411 ifp->if_oerrors++; 1412 1413 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1414 if (flag & BFE_RX_FLAG_ERRORS) 1415 ifp->if_ierrors++; 1416 1417 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1418 bfe_init_locked(sc); 1419 } 1420 1421 /* A packet was received */ 1422 if (istat & BFE_ISTAT_RX) 1423 bfe_rxeof(sc); 1424 1425 /* A packet was sent */ 1426 if (istat & BFE_ISTAT_TX) 1427 bfe_txeof(sc); 1428 1429 /* We have packets pending, fire them out */ 1430 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1431 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1432 bfe_start_locked(ifp); 1433 1434 BFE_UNLOCK(sc); 1435} 1436 1437static int 1438bfe_encap(struct bfe_softc *sc, struct mbuf **m_head) 1439{ 1440 struct bfe_desc *d; 1441 struct bfe_tx_data *r, *r1; 1442 struct mbuf *m; 1443 bus_dmamap_t map; 1444 bus_dma_segment_t txsegs[BFE_MAXTXSEGS]; 1445 uint32_t cur, si; 1446 int error, i, nsegs; 1447 1448 BFE_LOCK_ASSERT(sc); 1449 1450 M_ASSERTPKTHDR((*m_head)); 1451 1452 si = cur = sc->bfe_tx_prod; 1453 r = &sc->bfe_tx_ring[cur]; 1454 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head, 1455 txsegs, &nsegs, 0); 1456 if (error == EFBIG) { 1457 m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS); 1458 if (m == NULL) { 1459 m_freem(*m_head); 1460 *m_head = NULL; 1461 return (ENOMEM); 1462 } 1463 *m_head = m; 1464 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, 1465 *m_head, txsegs, &nsegs, 0); 1466 if (error != 0) { 1467 m_freem(*m_head); 1468 *m_head = NULL; 1469 return (error); 1470 } 1471 } else if (error != 0) 1472 return (error); 1473 if (nsegs == 0) { 1474 m_freem(*m_head); 1475 *m_head = NULL; 1476 return (EIO); 1477 } 1478 1479 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) { 1480 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map); 1481 return (ENOBUFS); 1482 } 1483 1484 for (i = 0; i < nsegs; i++) { 1485 d = &sc->bfe_tx_list[cur]; 1486 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN); 1487 d->bfe_ctrl |= htole32(BFE_DESC_IOC); 1488 if (cur == BFE_TX_LIST_CNT - 1) 1489 /* 1490 * Tell the chip to wrap to the start of 1491 * the descriptor list. 1492 */ 1493 d->bfe_ctrl |= htole32(BFE_DESC_EOT); 1494 /* The chip needs all addresses to be added to BFE_PCI_DMA. */ 1495 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) + 1496 BFE_PCI_DMA); 1497 BFE_INC(cur, BFE_TX_LIST_CNT); 1498 } 1499 1500 /* Update producer index. */ 1501 sc->bfe_tx_prod = cur; 1502 1503 /* Set EOF on the last descriptor. */ 1504 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT; 1505 d = &sc->bfe_tx_list[cur]; 1506 d->bfe_ctrl |= htole32(BFE_DESC_EOF); 1507 1508 /* Lastly set SOF on the first descriptor to avoid races. */ 1509 d = &sc->bfe_tx_list[si]; 1510 d->bfe_ctrl |= htole32(BFE_DESC_SOF); 1511 1512 r1 = &sc->bfe_tx_ring[cur]; 1513 map = r->bfe_map; 1514 r->bfe_map = r1->bfe_map; 1515 r1->bfe_map = map; 1516 r1->bfe_mbuf = *m_head; 1517 sc->bfe_tx_cnt += nsegs; 1518 1519 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE); 1520 1521 return (0); 1522} 1523 1524/* 1525 * Set up to transmit a packet. 1526 */ 1527static void 1528bfe_start(struct ifnet *ifp) 1529{ 1530 BFE_LOCK((struct bfe_softc *)ifp->if_softc); 1531 bfe_start_locked(ifp); 1532 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc); 1533} 1534 1535/* 1536 * Set up to transmit a packet. The softc is already locked. 1537 */ 1538static void 1539bfe_start_locked(struct ifnet *ifp) 1540{ 1541 struct bfe_softc *sc; 1542 struct mbuf *m_head; 1543 int queued; 1544 1545 sc = ifp->if_softc; 1546 1547 BFE_LOCK_ASSERT(sc); 1548 1549 /* 1550 * Not much point trying to send if the link is down 1551 * or we have nothing to send. 1552 */ 1553 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1554 IFF_DRV_RUNNING || sc->bfe_link == 0) 1555 return; 1556 1557 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1558 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) { 1559 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1560 if (m_head == NULL) 1561 break; 1562 1563 /* 1564 * Pack the data into the tx ring. If we dont have 1565 * enough room, let the chip drain the ring. 1566 */ 1567 if (bfe_encap(sc, &m_head)) { 1568 if (m_head == NULL) 1569 break; 1570 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1571 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1572 break; 1573 } 1574 1575 queued++; 1576 1577 /* 1578 * If there's a BPF listener, bounce a copy of this frame 1579 * to him. 1580 */ 1581 BPF_MTAP(ifp, m_head); 1582 } 1583 1584 if (queued) { 1585 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, 1586 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1587 /* Transmit - twice due to apparent hardware bug */ 1588 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1589 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1590 /* 1591 * XXX It seems the following write is not necessary 1592 * to kick Tx command. What might be required would be 1593 * a way flushing PCI posted write. Reading the register 1594 * back ensures the flush operation. In addition, 1595 * hardware will execute PCI posted write in the long 1596 * run and watchdog timer for the kick command was set 1597 * to 5 seconds. Therefore I think the second write 1598 * access is not necessary or could be replaced with 1599 * read operation. 1600 */ 1601 CSR_WRITE_4(sc, BFE_DMATX_PTR, 1602 sc->bfe_tx_prod * sizeof(struct bfe_desc)); 1603 1604 /* 1605 * Set a timeout in case the chip goes out to lunch. 1606 */ 1607 sc->bfe_watchdog_timer = 5; 1608 } 1609} 1610 1611static void 1612bfe_init(void *xsc) 1613{ 1614 BFE_LOCK((struct bfe_softc *)xsc); 1615 bfe_init_locked(xsc); 1616 BFE_UNLOCK((struct bfe_softc *)xsc); 1617} 1618 1619static void 1620bfe_init_locked(void *xsc) 1621{ 1622 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1623 struct ifnet *ifp = sc->bfe_ifp; 1624 struct mii_data *mii; 1625 1626 BFE_LOCK_ASSERT(sc); 1627 1628 mii = device_get_softc(sc->bfe_miibus); 1629 1630 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1631 return; 1632 1633 bfe_stop(sc); 1634 bfe_chip_reset(sc); 1635 1636 if (bfe_list_rx_init(sc) == ENOBUFS) { 1637 device_printf(sc->bfe_dev, 1638 "%s: Not enough memory for list buffers\n", __func__); 1639 bfe_stop(sc); 1640 return; 1641 } 1642 bfe_list_tx_init(sc); 1643 1644 bfe_set_rx_mode(sc); 1645 1646 /* Enable the chip and core */ 1647 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1648 /* Enable interrupts */ 1649 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1650 1651 /* Clear link state and change media. */ 1652 sc->bfe_link = 0; 1653 mii_mediachg(mii); 1654 1655 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1656 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1657 1658 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1659} 1660 1661/* 1662 * Set media options. 1663 */ 1664static int 1665bfe_ifmedia_upd(struct ifnet *ifp) 1666{ 1667 struct bfe_softc *sc; 1668 struct mii_data *mii; 1669 int error; 1670 1671 sc = ifp->if_softc; 1672 BFE_LOCK(sc); 1673 1674 mii = device_get_softc(sc->bfe_miibus); 1675 if (mii->mii_instance) { 1676 struct mii_softc *miisc; 1677 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1678 miisc = LIST_NEXT(miisc, mii_list)) 1679 mii_phy_reset(miisc); 1680 } 1681 error = mii_mediachg(mii); 1682 BFE_UNLOCK(sc); 1683 1684 return (error); 1685} 1686 1687/* 1688 * Report current media status. 1689 */ 1690static void 1691bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1692{ 1693 struct bfe_softc *sc = ifp->if_softc; 1694 struct mii_data *mii; 1695 1696 BFE_LOCK(sc); 1697 mii = device_get_softc(sc->bfe_miibus); 1698 mii_pollstat(mii); 1699 ifmr->ifm_active = mii->mii_media_active; 1700 ifmr->ifm_status = mii->mii_media_status; 1701 BFE_UNLOCK(sc); 1702} 1703 1704static int 1705bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1706{ 1707 struct bfe_softc *sc = ifp->if_softc; 1708 struct ifreq *ifr = (struct ifreq *) data; 1709 struct mii_data *mii; 1710 int error = 0; 1711 1712 switch (command) { 1713 case SIOCSIFFLAGS: 1714 BFE_LOCK(sc); 1715 if (ifp->if_flags & IFF_UP) 1716 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1717 bfe_set_rx_mode(sc); 1718 else 1719 bfe_init_locked(sc); 1720 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1721 bfe_stop(sc); 1722 BFE_UNLOCK(sc); 1723 break; 1724 case SIOCADDMULTI: 1725 case SIOCDELMULTI: 1726 BFE_LOCK(sc); 1727 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1728 bfe_set_rx_mode(sc); 1729 BFE_UNLOCK(sc); 1730 break; 1731 case SIOCGIFMEDIA: 1732 case SIOCSIFMEDIA: 1733 mii = device_get_softc(sc->bfe_miibus); 1734 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1735 break; 1736 default: 1737 error = ether_ioctl(ifp, command, data); 1738 break; 1739 } 1740 1741 return (error); 1742} 1743 1744static void 1745bfe_watchdog(struct bfe_softc *sc) 1746{ 1747 struct ifnet *ifp; 1748 1749 BFE_LOCK_ASSERT(sc); 1750 1751 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer) 1752 return; 1753 1754 ifp = sc->bfe_ifp; 1755 1756 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n"); 1757 1758 ifp->if_oerrors++; 1759 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1760 bfe_init_locked(sc); 1761 1762 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1763 bfe_start_locked(ifp); 1764} 1765 1766static void 1767bfe_tick(void *xsc) 1768{ 1769 struct bfe_softc *sc = xsc; 1770 struct mii_data *mii; 1771 1772 BFE_LOCK_ASSERT(sc); 1773 1774 mii = device_get_softc(sc->bfe_miibus); 1775 mii_tick(mii); 1776 bfe_stats_update(sc); 1777 bfe_watchdog(sc); 1778 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc); 1779} 1780 1781/* 1782 * Stop the adapter and free any mbufs allocated to the 1783 * RX and TX lists. 1784 */ 1785static void 1786bfe_stop(struct bfe_softc *sc) 1787{ 1788 struct ifnet *ifp; 1789 1790 BFE_LOCK_ASSERT(sc); 1791 1792 ifp = sc->bfe_ifp; 1793 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1794 sc->bfe_link = 0; 1795 callout_stop(&sc->bfe_stat_co); 1796 sc->bfe_watchdog_timer = 0; 1797 1798 bfe_chip_halt(sc); 1799 bfe_tx_ring_free(sc); 1800 bfe_rx_ring_free(sc); 1801} 1802