if_bfe.c revision 131455
1/* 2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk> 3 * and Duncan Barclay<dmlb@dmlb.org> 4 */ 5 6/* 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/dev/bfe/if_bfe.c 131455 2004-07-02 12:16:02Z mlaier $"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/sockio.h> 36#include <sys/mbuf.h> 37#include <sys/malloc.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/socket.h> 41#include <sys/queue.h> 42 43#include <net/if.h> 44#include <net/if_arp.h> 45#include <net/ethernet.h> 46#include <net/if_dl.h> 47#include <net/if_media.h> 48 49#include <net/bpf.h> 50 51#include <net/if_types.h> 52#include <net/if_vlan_var.h> 53 54#include <netinet/in_systm.h> 55#include <netinet/in.h> 56#include <netinet/ip.h> 57 58#include <machine/clock.h> /* for DELAY */ 59#include <machine/bus_memio.h> 60#include <machine/bus.h> 61#include <machine/resource.h> 62#include <sys/bus.h> 63#include <sys/rman.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67#include "miidevs.h" 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/bfe/if_bfereg.h> 73 74MODULE_DEPEND(bfe, pci, 1, 1, 1); 75MODULE_DEPEND(bfe, ether, 1, 1, 1); 76MODULE_DEPEND(bfe, miibus, 1, 1, 1); 77 78/* "controller miibus0" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80 81#define BFE_DEVDESC_MAX 64 /* Maximum device description length */ 82 83static struct bfe_type bfe_devs[] = { 84 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401, 85 "Broadcom BCM4401 Fast Ethernet" }, 86 { 0, 0, NULL } 87}; 88 89static int bfe_probe (device_t); 90static int bfe_attach (device_t); 91static int bfe_detach (device_t); 92static void bfe_release_resources (struct bfe_softc *); 93static void bfe_intr (void *); 94static void bfe_start (struct ifnet *); 95static int bfe_ioctl (struct ifnet *, u_long, caddr_t); 96static void bfe_init (void *); 97static void bfe_stop (struct bfe_softc *); 98static void bfe_watchdog (struct ifnet *); 99static void bfe_shutdown (device_t); 100static void bfe_tick (void *); 101static void bfe_txeof (struct bfe_softc *); 102static void bfe_rxeof (struct bfe_softc *); 103static void bfe_set_rx_mode (struct bfe_softc *); 104static int bfe_list_rx_init (struct bfe_softc *); 105static int bfe_list_newbuf (struct bfe_softc *, int, struct mbuf*); 106static void bfe_rx_ring_free (struct bfe_softc *); 107 108static void bfe_pci_setup (struct bfe_softc *, u_int32_t); 109static int bfe_ifmedia_upd (struct ifnet *); 110static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *); 111static int bfe_miibus_readreg (device_t, int, int); 112static int bfe_miibus_writereg (device_t, int, int, int); 113static void bfe_miibus_statchg (device_t); 114static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t, 115 u_long, const int); 116static void bfe_get_config (struct bfe_softc *sc); 117static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *); 118static void bfe_stats_update (struct bfe_softc *); 119static void bfe_clear_stats (struct bfe_softc *); 120static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*); 121static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t); 122static int bfe_resetphy (struct bfe_softc *); 123static int bfe_setupphy (struct bfe_softc *); 124static void bfe_chip_reset (struct bfe_softc *); 125static void bfe_chip_halt (struct bfe_softc *); 126static void bfe_core_reset (struct bfe_softc *); 127static void bfe_core_disable (struct bfe_softc *); 128static int bfe_dma_alloc (device_t); 129static void bfe_dma_map_desc (void *, bus_dma_segment_t *, int, int); 130static void bfe_dma_map (void *, bus_dma_segment_t *, int, int); 131static void bfe_cam_write (struct bfe_softc *, u_char *, int); 132 133static device_method_t bfe_methods[] = { 134 /* Device interface */ 135 DEVMETHOD(device_probe, bfe_probe), 136 DEVMETHOD(device_attach, bfe_attach), 137 DEVMETHOD(device_detach, bfe_detach), 138 DEVMETHOD(device_shutdown, bfe_shutdown), 139 140 /* bus interface */ 141 DEVMETHOD(bus_print_child, bus_generic_print_child), 142 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 143 144 /* MII interface */ 145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg), 146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg), 147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg), 148 149 { 0, 0 } 150}; 151 152static driver_t bfe_driver = { 153 "bfe", 154 bfe_methods, 155 sizeof(struct bfe_softc) 156}; 157 158static devclass_t bfe_devclass; 159 160DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0); 161DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0); 162 163/* 164 * Probe for a Broadcom 4401 chip. 165 */ 166static int 167bfe_probe(device_t dev) 168{ 169 struct bfe_type *t; 170 struct bfe_softc *sc; 171 172 t = bfe_devs; 173 174 sc = device_get_softc(dev); 175 bzero(sc, sizeof(struct bfe_softc)); 176 sc->bfe_unit = device_get_unit(dev); 177 sc->bfe_dev = dev; 178 179 while(t->bfe_name != NULL) { 180 if ((pci_get_vendor(dev) == t->bfe_vid) && 181 (pci_get_device(dev) == t->bfe_did)) { 182 device_set_desc_copy(dev, t->bfe_name); 183 return(0); 184 } 185 t++; 186 } 187 188 return(ENXIO); 189} 190 191static int 192bfe_dma_alloc(device_t dev) 193{ 194 struct bfe_softc *sc; 195 int error, i; 196 197 sc = device_get_softc(dev); 198 199 /* parent tag */ 200 error = bus_dma_tag_create(NULL, /* parent */ 201 PAGE_SIZE, 0, /* alignment, boundary */ 202 BUS_SPACE_MAXADDR, /* lowaddr */ 203 BUS_SPACE_MAXADDR_32BIT, /* highaddr */ 204 NULL, NULL, /* filter, filterarg */ 205 MAXBSIZE, /* maxsize */ 206 BUS_SPACE_UNRESTRICTED, /* num of segments */ 207 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */ 208 BUS_DMA_ALLOCNOW, /* flags */ 209 NULL, NULL, /* lockfunc, lockarg */ 210 &sc->bfe_parent_tag); 211 212 /* tag for TX ring */ 213 error = bus_dma_tag_create(sc->bfe_parent_tag, 214 BFE_TX_LIST_SIZE, BFE_TX_LIST_SIZE, 215 BUS_SPACE_MAXADDR, 216 BUS_SPACE_MAXADDR, 217 NULL, NULL, 218 BFE_TX_LIST_SIZE, 219 1, 220 BUS_SPACE_MAXSIZE_32BIT, 221 0, 222 NULL, NULL, 223 &sc->bfe_tx_tag); 224 225 if (error) { 226 device_printf(dev, "could not allocate dma tag\n"); 227 return(ENOMEM); 228 } 229 230 /* tag for RX ring */ 231 error = bus_dma_tag_create(sc->bfe_parent_tag, 232 BFE_RX_LIST_SIZE, BFE_RX_LIST_SIZE, 233 BUS_SPACE_MAXADDR, 234 BUS_SPACE_MAXADDR, 235 NULL, NULL, 236 BFE_RX_LIST_SIZE, 237 1, 238 BUS_SPACE_MAXSIZE_32BIT, 239 0, 240 NULL, NULL, 241 &sc->bfe_rx_tag); 242 243 if (error) { 244 device_printf(dev, "could not allocate dma tag\n"); 245 return(ENOMEM); 246 } 247 248 /* tag for mbufs */ 249 error = bus_dma_tag_create(sc->bfe_parent_tag, 250 ETHER_ALIGN, 0, 251 BUS_SPACE_MAXADDR, 252 BUS_SPACE_MAXADDR, 253 NULL, NULL, 254 MCLBYTES, 255 1, 256 BUS_SPACE_MAXSIZE_32BIT, 257 0, 258 NULL, NULL, 259 &sc->bfe_tag); 260 261 if (error) { 262 device_printf(dev, "could not allocate dma tag\n"); 263 return(ENOMEM); 264 } 265 266 /* pre allocate dmamaps for RX list */ 267 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 268 error = bus_dmamap_create(sc->bfe_tag, 0, 269 &sc->bfe_rx_ring[i].bfe_map); 270 if (error) { 271 device_printf(dev, "cannot create DMA map for RX\n"); 272 return(ENOMEM); 273 } 274 } 275 276 /* pre allocate dmamaps for TX list */ 277 for (i = 0; i < BFE_TX_LIST_CNT; i++) { 278 error = bus_dmamap_create(sc->bfe_tag, 0, 279 &sc->bfe_tx_ring[i].bfe_map); 280 if (error) { 281 device_printf(dev, "cannot create DMA map for TX\n"); 282 return(ENOMEM); 283 } 284 } 285 286 /* Alloc dma for rx ring */ 287 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list, 288 BUS_DMA_NOWAIT, &sc->bfe_rx_map); 289 290 if(error) 291 return(ENOMEM); 292 293 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 294 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map, 295 sc->bfe_rx_list, sizeof(struct bfe_desc), 296 bfe_dma_map, &sc->bfe_rx_dma, 0); 297 298 if(error) 299 return(ENOMEM); 300 301 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 302 303 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list, 304 BUS_DMA_NOWAIT, &sc->bfe_tx_map); 305 if (error) 306 return(ENOMEM); 307 308 309 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map, 310 sc->bfe_tx_list, sizeof(struct bfe_desc), 311 bfe_dma_map, &sc->bfe_tx_dma, 0); 312 if(error) 313 return(ENOMEM); 314 315 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 316 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 317 318 return(0); 319} 320 321static int 322bfe_attach(device_t dev) 323{ 324 struct ifnet *ifp; 325 struct bfe_softc *sc; 326 int unit, error = 0, rid; 327 328 sc = device_get_softc(dev); 329 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 330 MTX_DEF | MTX_RECURSE); 331 332 unit = device_get_unit(dev); 333 sc->bfe_dev = dev; 334 sc->bfe_unit = unit; 335 336 /* 337 * Handle power management nonsense. 338 */ 339 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 340 u_int32_t membase, irq; 341 342 /* Save important PCI config data. */ 343 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4); 344 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4); 345 346 /* Reset the power state. */ 347 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n", 348 sc->bfe_unit, pci_get_powerstate(dev)); 349 350 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 351 352 /* Restore PCI config data. */ 353 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4); 354 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4); 355 } 356 357 /* 358 * Map control/status registers. 359 */ 360 pci_enable_busmaster(dev); 361 362 rid = BFE_PCI_MEMLO; 363 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 364 RF_ACTIVE); 365 if (sc->bfe_res == NULL) { 366 printf ("bfe%d: couldn't map memory\n", unit); 367 error = ENXIO; 368 goto fail; 369 } 370 371 sc->bfe_btag = rman_get_bustag(sc->bfe_res); 372 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res); 373 sc->bfe_vhandle = (vm_offset_t)rman_get_virtual(sc->bfe_res); 374 375 /* Allocate interrupt */ 376 rid = 0; 377 378 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 379 RF_SHAREABLE | RF_ACTIVE); 380 if (sc->bfe_irq == NULL) { 381 printf("bfe%d: couldn't map interrupt\n", unit); 382 error = ENXIO; 383 goto fail; 384 } 385 386 if (bfe_dma_alloc(dev)) { 387 printf("bfe%d: failed to allocate DMA resources\n", 388 sc->bfe_unit); 389 bfe_release_resources(sc); 390 error = ENXIO; 391 goto fail; 392 } 393 394 /* Set up ifnet structure */ 395 ifp = &sc->arpcom.ac_if; 396 ifp->if_softc = sc; 397 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 398 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 399 ifp->if_ioctl = bfe_ioctl; 400 ifp->if_start = bfe_start; 401 ifp->if_watchdog = bfe_watchdog; 402 ifp->if_init = bfe_init; 403 ifp->if_mtu = ETHERMTU; 404 ifp->if_baudrate = 100000000; 405 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN); 406 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN; 407 IFQ_SET_READY(&ifp->if_snd); 408 409 bfe_get_config(sc); 410 411 /* Reset the chip and turn on the PHY */ 412 bfe_chip_reset(sc); 413 414 if (mii_phy_probe(dev, &sc->bfe_miibus, 415 bfe_ifmedia_upd, bfe_ifmedia_sts)) { 416 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit); 417 error = ENXIO; 418 goto fail; 419 } 420 421 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 422 callout_handle_init(&sc->bfe_stat_ch); 423 424 /* 425 * Tell the upper layer(s) we support long frames. 426 */ 427 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 428 ifp->if_capabilities |= IFCAP_VLAN_MTU; 429 ifp->if_capenable |= IFCAP_VLAN_MTU; 430 431 /* 432 * Hook interrupt last to avoid having to lock softc 433 */ 434 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET, 435 bfe_intr, sc, &sc->bfe_intrhand); 436 437 if (error) { 438 bfe_release_resources(sc); 439 printf("bfe%d: couldn't set up irq\n", unit); 440 goto fail; 441 } 442fail: 443 if(error) 444 bfe_release_resources(sc); 445 return(error); 446} 447 448static int 449bfe_detach(device_t dev) 450{ 451 struct bfe_softc *sc; 452 struct ifnet *ifp; 453 454 sc = device_get_softc(dev); 455 456 KASSERT(mtx_initialized(&sc->bfe_mtx), ("bfe mutex not initialized")); 457 BFE_LOCK(scp); 458 459 ifp = &sc->arpcom.ac_if; 460 461 if (device_is_attached(dev)) { 462 bfe_stop(sc); 463 ether_ifdetach(ifp); 464 } 465 466 bfe_chip_reset(sc); 467 468 bus_generic_detach(dev); 469 if(sc->bfe_miibus != NULL) 470 device_delete_child(dev, sc->bfe_miibus); 471 472 bfe_release_resources(sc); 473 BFE_UNLOCK(sc); 474 mtx_destroy(&sc->bfe_mtx); 475 476 return(0); 477} 478 479/* 480 * Stop all chip I/O so that the kernel's probe routines don't 481 * get confused by errant DMAs when rebooting. 482 */ 483static void 484bfe_shutdown(device_t dev) 485{ 486 struct bfe_softc *sc; 487 488 sc = device_get_softc(dev); 489 BFE_LOCK(sc); 490 bfe_stop(sc); 491 492 BFE_UNLOCK(sc); 493 return; 494} 495 496static int 497bfe_miibus_readreg(device_t dev, int phy, int reg) 498{ 499 struct bfe_softc *sc; 500 u_int32_t ret; 501 502 sc = device_get_softc(dev); 503 if(phy != sc->bfe_phyaddr) 504 return(0); 505 bfe_readphy(sc, reg, &ret); 506 507 return(ret); 508} 509 510static int 511bfe_miibus_writereg(device_t dev, int phy, int reg, int val) 512{ 513 struct bfe_softc *sc; 514 515 sc = device_get_softc(dev); 516 if(phy != sc->bfe_phyaddr) 517 return(0); 518 bfe_writephy(sc, reg, val); 519 520 return(0); 521} 522 523static void 524bfe_miibus_statchg(device_t dev) 525{ 526 return; 527} 528 529static void 530bfe_tx_ring_free(struct bfe_softc *sc) 531{ 532 int i; 533 534 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 535 if(sc->bfe_tx_ring[i].bfe_mbuf != NULL) { 536 m_freem(sc->bfe_tx_ring[i].bfe_mbuf); 537 sc->bfe_tx_ring[i].bfe_mbuf = NULL; 538 bus_dmamap_unload(sc->bfe_tag, 539 sc->bfe_tx_ring[i].bfe_map); 540 bus_dmamap_destroy(sc->bfe_tag, 541 sc->bfe_tx_ring[i].bfe_map); 542 } 543 } 544 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE); 545 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 546} 547 548static void 549bfe_rx_ring_free(struct bfe_softc *sc) 550{ 551 int i; 552 553 for (i = 0; i < BFE_RX_LIST_CNT; i++) { 554 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) { 555 m_freem(sc->bfe_rx_ring[i].bfe_mbuf); 556 sc->bfe_rx_ring[i].bfe_mbuf = NULL; 557 bus_dmamap_unload(sc->bfe_tag, 558 sc->bfe_rx_ring[i].bfe_map); 559 bus_dmamap_destroy(sc->bfe_tag, 560 sc->bfe_rx_ring[i].bfe_map); 561 } 562 } 563 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE); 564 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 565} 566 567 568static int 569bfe_list_rx_init(struct bfe_softc *sc) 570{ 571 int i; 572 573 for(i = 0; i < BFE_RX_LIST_CNT; i++) { 574 if(bfe_list_newbuf(sc, i, NULL) == ENOBUFS) 575 return ENOBUFS; 576 } 577 578 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 579 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc))); 580 581 sc->bfe_rx_cons = 0; 582 583 return(0); 584} 585 586static int 587bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m) 588{ 589 struct bfe_rxheader *rx_header; 590 struct bfe_desc *d; 591 struct bfe_data *r; 592 u_int32_t ctrl; 593 594 if ((c < 0) || (c >= BFE_RX_LIST_CNT)) 595 return(EINVAL); 596 597 if(m == NULL) { 598 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 599 if(m == NULL) 600 return(ENOBUFS); 601 m->m_len = m->m_pkthdr.len = MCLBYTES; 602 } 603 else 604 m->m_data = m->m_ext.ext_buf; 605 606 rx_header = mtod(m, struct bfe_rxheader *); 607 rx_header->len = 0; 608 rx_header->flags = 0; 609 610 /* Map the mbuf into DMA */ 611 sc->bfe_rx_cnt = c; 612 d = &sc->bfe_rx_list[c]; 613 r = &sc->bfe_rx_ring[c]; 614 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *), 615 MCLBYTES, bfe_dma_map_desc, d, 0); 616 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE); 617 618 ctrl = ETHER_MAX_LEN + 32; 619 620 if(c == BFE_RX_LIST_CNT - 1) 621 ctrl |= BFE_DESC_EOT; 622 623 d->bfe_ctrl = ctrl; 624 r->bfe_mbuf = m; 625 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD); 626 return(0); 627} 628 629static void 630bfe_get_config(struct bfe_softc *sc) 631{ 632 u_int8_t eeprom[128]; 633 634 bfe_read_eeprom(sc, eeprom); 635 636 sc->arpcom.ac_enaddr[0] = eeprom[79]; 637 sc->arpcom.ac_enaddr[1] = eeprom[78]; 638 sc->arpcom.ac_enaddr[2] = eeprom[81]; 639 sc->arpcom.ac_enaddr[3] = eeprom[80]; 640 sc->arpcom.ac_enaddr[4] = eeprom[83]; 641 sc->arpcom.ac_enaddr[5] = eeprom[82]; 642 643 sc->bfe_phyaddr = eeprom[90] & 0x1f; 644 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1; 645 646 sc->bfe_core_unit = 0; 647 sc->bfe_dma_offset = BFE_PCI_DMA; 648} 649 650static void 651bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores) 652{ 653 u_int32_t bar_orig, pci_rev, val; 654 655 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4); 656 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4); 657 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; 658 659 val = CSR_READ_4(sc, BFE_SBINTVEC); 660 val |= cores; 661 CSR_WRITE_4(sc, BFE_SBINTVEC, val); 662 663 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); 664 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST; 665 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val); 666 667 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4); 668} 669 670static void 671bfe_clear_stats(struct bfe_softc *sc) 672{ 673 u_long reg; 674 675 BFE_LOCK(sc); 676 677 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ); 678 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) 679 CSR_READ_4(sc, reg); 680 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) 681 CSR_READ_4(sc, reg); 682 683 BFE_UNLOCK(sc); 684} 685 686static int 687bfe_resetphy(struct bfe_softc *sc) 688{ 689 u_int32_t val; 690 691 BFE_LOCK(sc); 692 bfe_writephy(sc, 0, BMCR_RESET); 693 DELAY(100); 694 bfe_readphy(sc, 0, &val); 695 if (val & BMCR_RESET) { 696 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit); 697 BFE_UNLOCK(sc); 698 return ENXIO; 699 } 700 BFE_UNLOCK(sc); 701 return 0; 702} 703 704static void 705bfe_chip_halt(struct bfe_softc *sc) 706{ 707 BFE_LOCK(sc); 708 /* disable interrupts - not that it actually does..*/ 709 CSR_WRITE_4(sc, BFE_IMASK, 0); 710 CSR_READ_4(sc, BFE_IMASK); 711 712 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 713 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1); 714 715 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 716 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 717 DELAY(10); 718 719 BFE_UNLOCK(sc); 720} 721 722static void 723bfe_chip_reset(struct bfe_softc *sc) 724{ 725 u_int32_t val; 726 727 BFE_LOCK(sc); 728 729 /* Set the interrupt vector for the enet core */ 730 bfe_pci_setup(sc, BFE_INTVEC_ENET0); 731 732 /* is core up? */ 733 val = CSR_READ_4(sc, BFE_SBTMSLOW) & 734 (BFE_RESET | BFE_REJECT | BFE_CLOCK); 735 if (val == BFE_CLOCK) { 736 /* It is, so shut it down */ 737 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0); 738 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE); 739 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1); 740 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0); 741 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0; 742 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK) 743 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 744 100, 0); 745 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0); 746 sc->bfe_rx_prod = sc->bfe_rx_cons = 0; 747 } 748 749 bfe_core_reset(sc); 750 bfe_clear_stats(sc); 751 752 /* 753 * We want the phy registers to be accessible even when 754 * the driver is "downed" so initialize MDC preamble, frequency, 755 * and whether internal or external phy here. 756 */ 757 758 /* 4402 has 62.5Mhz SB clock and internal phy */ 759 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d); 760 761 /* Internal or external PHY? */ 762 val = CSR_READ_4(sc, BFE_DEVCTRL); 763 if(!(val & BFE_IPP)) 764 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL); 765 else if(CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) { 766 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR); 767 DELAY(100); 768 } 769 770 /* Enable CRC32 generation and set proper LED modes */ 771 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED); 772 773 /* Reset or clear powerdown control bit */ 774 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN); 775 776 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) & 777 BFE_LAZY_FC_MASK)); 778 779 /* 780 * We don't want lazy interrupts, so just send them at 781 * the end of a frame, please 782 */ 783 BFE_OR(sc, BFE_RCV_LAZY, 0); 784 785 /* Set max lengths, accounting for VLAN tags */ 786 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32); 787 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32); 788 789 /* Set watermark XXX - magic */ 790 CSR_WRITE_4(sc, BFE_TX_WMARK, 56); 791 792 /* 793 * Initialise DMA channels 794 * - not forgetting dma addresses need to be added to BFE_PCI_DMA 795 */ 796 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE); 797 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA); 798 799 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) | 800 BFE_RX_CTRL_ENABLE); 801 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA); 802 803 bfe_resetphy(sc); 804 bfe_setupphy(sc); 805 806 BFE_UNLOCK(sc); 807} 808 809static void 810bfe_core_disable(struct bfe_softc *sc) 811{ 812 if((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET) 813 return; 814 815 /* 816 * Set reject, wait for it set, then wait for the core to stop 817 * being busy, then set reset and reject and enable the clocks. 818 */ 819 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK)); 820 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0); 821 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1); 822 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT | 823 BFE_RESET)); 824 CSR_READ_4(sc, BFE_SBTMSLOW); 825 DELAY(10); 826 /* Leave reset and reject set */ 827 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET)); 828 DELAY(10); 829} 830 831static void 832bfe_core_reset(struct bfe_softc *sc) 833{ 834 u_int32_t val; 835 836 /* Disable the core */ 837 bfe_core_disable(sc); 838 839 /* and bring it back up */ 840 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC)); 841 CSR_READ_4(sc, BFE_SBTMSLOW); 842 DELAY(10); 843 844 /* Chip bug, clear SERR, IB and TO if they are set. */ 845 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR) 846 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0); 847 val = CSR_READ_4(sc, BFE_SBIMSTATE); 848 if (val & (BFE_IBE | BFE_TO)) 849 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO)); 850 851 /* Clear reset and allow it to move through the core */ 852 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC)); 853 CSR_READ_4(sc, BFE_SBTMSLOW); 854 DELAY(10); 855 856 /* Leave the clock set */ 857 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK); 858 CSR_READ_4(sc, BFE_SBTMSLOW); 859 DELAY(10); 860} 861 862static void 863bfe_cam_write(struct bfe_softc *sc, u_char *data, int index) 864{ 865 u_int32_t val; 866 867 val = ((u_int32_t) data[2]) << 24; 868 val |= ((u_int32_t) data[3]) << 16; 869 val |= ((u_int32_t) data[4]) << 8; 870 val |= ((u_int32_t) data[5]); 871 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val); 872 val = (BFE_CAM_HI_VALID | 873 (((u_int32_t) data[0]) << 8) | 874 (((u_int32_t) data[1]))); 875 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val); 876 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE | 877 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT))); 878 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1); 879} 880 881static void 882bfe_set_rx_mode(struct bfe_softc *sc) 883{ 884 struct ifnet *ifp = &sc->arpcom.ac_if; 885 struct ifmultiaddr *ifma; 886 u_int32_t val; 887 int i = 0; 888 889 val = CSR_READ_4(sc, BFE_RXCONF); 890 891 if (ifp->if_flags & IFF_PROMISC) 892 val |= BFE_RXCONF_PROMISC; 893 else 894 val &= ~BFE_RXCONF_PROMISC; 895 896 if (ifp->if_flags & IFF_BROADCAST) 897 val &= ~BFE_RXCONF_DBCAST; 898 else 899 val |= BFE_RXCONF_DBCAST; 900 901 902 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0); 903 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++); 904 905 if (ifp->if_flags & IFF_ALLMULTI) 906 val |= BFE_RXCONF_ALLMULTI; 907 else { 908 val &= ~BFE_RXCONF_ALLMULTI; 909 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 910 if (ifma->ifma_addr->sa_family != AF_LINK) 911 continue; 912 bfe_cam_write(sc, 913 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++); 914 } 915 } 916 917 CSR_WRITE_4(sc, BFE_RXCONF, val); 918 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE); 919} 920 921static void 922bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error) 923{ 924 u_int32_t *ptr; 925 926 ptr = arg; 927 *ptr = segs->ds_addr; 928} 929 930static void 931bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error) 932{ 933 struct bfe_desc *d; 934 935 d = arg; 936 /* The chip needs all addresses to be added to BFE_PCI_DMA */ 937 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA; 938} 939 940static void 941bfe_release_resources(struct bfe_softc *sc) 942{ 943 device_t dev; 944 int i; 945 946 dev = sc->bfe_dev; 947 948 if (sc->bfe_vpd_prodname != NULL) 949 free(sc->bfe_vpd_prodname, M_DEVBUF); 950 951 if (sc->bfe_vpd_readonly != NULL) 952 free(sc->bfe_vpd_readonly, M_DEVBUF); 953 954 if (sc->bfe_intrhand != NULL) 955 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand); 956 957 if (sc->bfe_irq != NULL) 958 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq); 959 960 if (sc->bfe_res != NULL) 961 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res); 962 963 if(sc->bfe_tx_tag != NULL) { 964 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map); 965 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, 966 sc->bfe_tx_map); 967 bus_dma_tag_destroy(sc->bfe_tx_tag); 968 sc->bfe_tx_tag = NULL; 969 } 970 971 if(sc->bfe_rx_tag != NULL) { 972 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map); 973 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, 974 sc->bfe_rx_map); 975 bus_dma_tag_destroy(sc->bfe_rx_tag); 976 sc->bfe_rx_tag = NULL; 977 } 978 979 if(sc->bfe_tag != NULL) { 980 for(i = 0; i < BFE_TX_LIST_CNT; i++) { 981 bus_dmamap_destroy(sc->bfe_tag, 982 sc->bfe_tx_ring[i].bfe_map); 983 } 984 bus_dma_tag_destroy(sc->bfe_tag); 985 sc->bfe_tag = NULL; 986 } 987 988 if(sc->bfe_parent_tag != NULL) 989 bus_dma_tag_destroy(sc->bfe_parent_tag); 990 991 return; 992} 993 994static void 995bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data) 996{ 997 long i; 998 u_int16_t *ptr = (u_int16_t *)data; 999 1000 for(i = 0; i < 128; i += 2) 1001 ptr[i/2] = CSR_READ_4(sc, 4096 + i); 1002} 1003 1004static int 1005bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit, 1006 u_long timeout, const int clear) 1007{ 1008 u_long i; 1009 1010 for (i = 0; i < timeout; i++) { 1011 u_int32_t val = CSR_READ_4(sc, reg); 1012 1013 if (clear && !(val & bit)) 1014 break; 1015 if (!clear && (val & bit)) 1016 break; 1017 DELAY(10); 1018 } 1019 if (i == timeout) { 1020 printf("bfe%d: BUG! Timeout waiting for bit %08x of register " 1021 "%x to %s.\n", sc->bfe_unit, bit, reg, 1022 (clear ? "clear" : "set")); 1023 return -1; 1024 } 1025 return 0; 1026} 1027 1028static int 1029bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val) 1030{ 1031 int err; 1032 1033 BFE_LOCK(sc); 1034 /* Clear MII ISR */ 1035 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1036 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1037 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) | 1038 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1039 (reg << BFE_MDIO_RA_SHIFT) | 1040 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT))); 1041 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1042 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA; 1043 1044 BFE_UNLOCK(sc); 1045 return err; 1046} 1047 1048static int 1049bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val) 1050{ 1051 int status; 1052 1053 BFE_LOCK(sc); 1054 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII); 1055 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START | 1056 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) | 1057 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) | 1058 (reg << BFE_MDIO_RA_SHIFT) | 1059 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) | 1060 (val & BFE_MDIO_DATA_DATA))); 1061 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0); 1062 BFE_UNLOCK(sc); 1063 1064 return status; 1065} 1066 1067/* 1068 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it 1069 * twice 1070 */ 1071static int 1072bfe_setupphy(struct bfe_softc *sc) 1073{ 1074 u_int32_t val; 1075 BFE_LOCK(sc); 1076 1077 /* Enable activity LED */ 1078 bfe_readphy(sc, 26, &val); 1079 bfe_writephy(sc, 26, val & 0x7fff); 1080 bfe_readphy(sc, 26, &val); 1081 1082 /* Enable traffic meter LED mode */ 1083 bfe_readphy(sc, 27, &val); 1084 bfe_writephy(sc, 27, val | (1 << 6)); 1085 1086 BFE_UNLOCK(sc); 1087 return 0; 1088} 1089 1090static void 1091bfe_stats_update(struct bfe_softc *sc) 1092{ 1093 u_long reg; 1094 u_int32_t *val; 1095 1096 val = &sc->bfe_hwstats.tx_good_octets; 1097 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4) { 1098 *val++ += CSR_READ_4(sc, reg); 1099 } 1100 val = &sc->bfe_hwstats.rx_good_octets; 1101 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4) { 1102 *val++ += CSR_READ_4(sc, reg); 1103 } 1104} 1105 1106static void 1107bfe_txeof(struct bfe_softc *sc) 1108{ 1109 struct ifnet *ifp; 1110 int i, chipidx; 1111 1112 BFE_LOCK(sc); 1113 1114 ifp = &sc->arpcom.ac_if; 1115 1116 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK; 1117 chipidx /= sizeof(struct bfe_desc); 1118 1119 i = sc->bfe_tx_cons; 1120 /* Go through the mbufs and free those that have been transmitted */ 1121 while(i != chipidx) { 1122 struct bfe_data *r = &sc->bfe_tx_ring[i]; 1123 if(r->bfe_mbuf != NULL) { 1124 ifp->if_opackets++; 1125 m_freem(r->bfe_mbuf); 1126 r->bfe_mbuf = NULL; 1127 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1128 } 1129 sc->bfe_tx_cnt--; 1130 BFE_INC(i, BFE_TX_LIST_CNT); 1131 } 1132 1133 if(i != sc->bfe_tx_cons) { 1134 /* we freed up some mbufs */ 1135 sc->bfe_tx_cons = i; 1136 ifp->if_flags &= ~IFF_OACTIVE; 1137 } 1138 if(sc->bfe_tx_cnt == 0) 1139 ifp->if_timer = 0; 1140 else 1141 ifp->if_timer = 5; 1142 1143 BFE_UNLOCK(sc); 1144} 1145 1146/* Pass a received packet up the stack */ 1147static void 1148bfe_rxeof(struct bfe_softc *sc) 1149{ 1150 struct mbuf *m; 1151 struct ifnet *ifp; 1152 struct bfe_rxheader *rxheader; 1153 struct bfe_data *r; 1154 int cons; 1155 u_int32_t status, current, len, flags; 1156 1157 BFE_LOCK(sc); 1158 cons = sc->bfe_rx_cons; 1159 status = CSR_READ_4(sc, BFE_DMARX_STAT); 1160 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc); 1161 1162 ifp = &sc->arpcom.ac_if; 1163 1164 while(current != cons) { 1165 r = &sc->bfe_rx_ring[cons]; 1166 m = r->bfe_mbuf; 1167 rxheader = mtod(m, struct bfe_rxheader*); 1168 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE); 1169 len = rxheader->len; 1170 r->bfe_mbuf = NULL; 1171 1172 bus_dmamap_unload(sc->bfe_tag, r->bfe_map); 1173 flags = rxheader->flags; 1174 1175 len -= ETHER_CRC_LEN; 1176 1177 /* flag an error and try again */ 1178 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) { 1179 ifp->if_ierrors++; 1180 if (flags & BFE_RX_FLAG_SERR) 1181 ifp->if_collisions++; 1182 bfe_list_newbuf(sc, cons, m); 1183 BFE_INC(cons, BFE_RX_LIST_CNT); 1184 continue; 1185 } 1186 1187 /* Go past the rx header */ 1188 if (bfe_list_newbuf(sc, cons, NULL) == 0) { 1189 m_adj(m, BFE_RX_OFFSET); 1190 m->m_len = m->m_pkthdr.len = len; 1191 } else { 1192 bfe_list_newbuf(sc, cons, m); 1193 ifp->if_ierrors++; 1194 BFE_INC(cons, BFE_RX_LIST_CNT); 1195 continue; 1196 } 1197 1198 ifp->if_ipackets++; 1199 m->m_pkthdr.rcvif = ifp; 1200 BFE_UNLOCK(sc); 1201 (*ifp->if_input)(ifp, m); 1202 BFE_LOCK(sc); 1203 1204 BFE_INC(cons, BFE_RX_LIST_CNT); 1205 } 1206 sc->bfe_rx_cons = cons; 1207 BFE_UNLOCK(sc); 1208} 1209 1210static void 1211bfe_intr(void *xsc) 1212{ 1213 struct bfe_softc *sc = xsc; 1214 struct ifnet *ifp; 1215 u_int32_t istat, imask, flag; 1216 1217 ifp = &sc->arpcom.ac_if; 1218 1219 BFE_LOCK(sc); 1220 1221 istat = CSR_READ_4(sc, BFE_ISTAT); 1222 imask = CSR_READ_4(sc, BFE_IMASK); 1223 1224 /* 1225 * Defer unsolicited interrupts - This is necessary because setting the 1226 * chips interrupt mask register to 0 doesn't actually stop the 1227 * interrupts 1228 */ 1229 istat &= imask; 1230 CSR_WRITE_4(sc, BFE_ISTAT, istat); 1231 CSR_READ_4(sc, BFE_ISTAT); 1232 1233 /* not expecting this interrupt, disregard it */ 1234 if(istat == 0) { 1235 BFE_UNLOCK(sc); 1236 return; 1237 } 1238 1239 if(istat & BFE_ISTAT_ERRORS) { 1240 flag = CSR_READ_4(sc, BFE_DMATX_STAT); 1241 if(flag & BFE_STAT_EMASK) 1242 ifp->if_oerrors++; 1243 1244 flag = CSR_READ_4(sc, BFE_DMARX_STAT); 1245 if(flag & BFE_RX_FLAG_ERRORS) 1246 ifp->if_ierrors++; 1247 1248 ifp->if_flags &= ~IFF_RUNNING; 1249 bfe_init(sc); 1250 } 1251 1252 /* A packet was received */ 1253 if(istat & BFE_ISTAT_RX) 1254 bfe_rxeof(sc); 1255 1256 /* A packet was sent */ 1257 if(istat & BFE_ISTAT_TX) 1258 bfe_txeof(sc); 1259 1260 /* We have packets pending, fire them out */ 1261 if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1262 bfe_start(ifp); 1263 1264 BFE_UNLOCK(sc); 1265} 1266 1267static int 1268bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 1269{ 1270 struct bfe_desc *d = NULL; 1271 struct bfe_data *r = NULL; 1272 struct mbuf *m; 1273 u_int32_t frag, cur, cnt = 0; 1274 int chainlen = 0; 1275 1276 if(BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2) 1277 return(ENOBUFS); 1278 1279 /* 1280 * Count the number of frags in this chain to see if 1281 * we need to m_defrag. Since the descriptor list is shared 1282 * by all packets, we'll m_defrag long chains so that they 1283 * do not use up the entire list, even if they would fit. 1284 */ 1285 for(m = m_head; m != NULL; m = m->m_next) 1286 chainlen++; 1287 1288 1289 if ((chainlen > BFE_TX_LIST_CNT / 4) || 1290 ((BFE_TX_LIST_CNT - (chainlen + sc->bfe_tx_cnt)) < 2)) { 1291 m = m_defrag(m_head, M_DONTWAIT); 1292 if (m == NULL) 1293 return(ENOBUFS); 1294 m_head = m; 1295 } 1296 1297 /* 1298 * Start packing the mbufs in this chain into 1299 * the fragment pointers. Stop when we run out 1300 * of fragments or hit the end of the mbuf chain. 1301 */ 1302 m = m_head; 1303 cur = frag = *txidx; 1304 cnt = 0; 1305 1306 for(m = m_head; m != NULL; m = m->m_next) { 1307 if(m->m_len != 0) { 1308 if((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2) 1309 return(ENOBUFS); 1310 1311 d = &sc->bfe_tx_list[cur]; 1312 r = &sc->bfe_tx_ring[cur]; 1313 d->bfe_ctrl = BFE_DESC_LEN & m->m_len; 1314 /* always intterupt on completion */ 1315 d->bfe_ctrl |= BFE_DESC_IOC; 1316 if(cnt == 0) 1317 /* Set start of frame */ 1318 d->bfe_ctrl |= BFE_DESC_SOF; 1319 if(cur == BFE_TX_LIST_CNT - 1) 1320 /* 1321 * Tell the chip to wrap to the start of 1322 * the descriptor list 1323 */ 1324 d->bfe_ctrl |= BFE_DESC_EOT; 1325 1326 bus_dmamap_load(sc->bfe_tag, 1327 r->bfe_map, mtod(m, void*), m->m_len, 1328 bfe_dma_map_desc, d, 0); 1329 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, 1330 BUS_DMASYNC_PREREAD); 1331 1332 frag = cur; 1333 BFE_INC(cur, BFE_TX_LIST_CNT); 1334 cnt++; 1335 } 1336 } 1337 1338 if (m != NULL) 1339 return(ENOBUFS); 1340 1341 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF; 1342 sc->bfe_tx_ring[frag].bfe_mbuf = m_head; 1343 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD); 1344 1345 *txidx = cur; 1346 sc->bfe_tx_cnt += cnt; 1347 return (0); 1348} 1349 1350/* 1351 * Set up to transmit a packet 1352 */ 1353static void 1354bfe_start(struct ifnet *ifp) 1355{ 1356 struct bfe_softc *sc; 1357 struct mbuf *m_head = NULL; 1358 int idx; 1359 1360 sc = ifp->if_softc; 1361 idx = sc->bfe_tx_prod; 1362 1363 BFE_LOCK(sc); 1364 1365 /* 1366 * Not much point trying to send if the link is down 1367 * or we have nothing to send. 1368 */ 1369 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) { 1370 BFE_UNLOCK(sc); 1371 return; 1372 } 1373 1374 if (ifp->if_flags & IFF_OACTIVE) { 1375 BFE_UNLOCK(sc); 1376 return; 1377 } 1378 1379 while(sc->bfe_tx_ring[idx].bfe_mbuf == NULL) { 1380 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1381 if(m_head == NULL) 1382 break; 1383 1384 /* 1385 * Pack the data into the tx ring. If we dont have 1386 * enough room, let the chip drain the ring. 1387 */ 1388 if(bfe_encap(sc, m_head, &idx)) { 1389 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1390 ifp->if_flags |= IFF_OACTIVE; 1391 break; 1392 } 1393 1394 /* 1395 * If there's a BPF listener, bounce a copy of this frame 1396 * to him. 1397 */ 1398 BPF_MTAP(ifp, m_head); 1399 } 1400 1401 sc->bfe_tx_prod = idx; 1402 /* Transmit - twice due to apparent hardware bug */ 1403 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1404 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc)); 1405 1406 /* 1407 * Set a timeout in case the chip goes out to lunch. 1408 */ 1409 ifp->if_timer = 5; 1410 BFE_UNLOCK(sc); 1411} 1412 1413static void 1414bfe_init(void *xsc) 1415{ 1416 struct bfe_softc *sc = (struct bfe_softc*)xsc; 1417 struct ifnet *ifp = &sc->arpcom.ac_if; 1418 1419 BFE_LOCK(sc); 1420 1421 if (ifp->if_flags & IFF_RUNNING) { 1422 BFE_UNLOCK(sc); 1423 return; 1424 } 1425 1426 bfe_stop(sc); 1427 bfe_chip_reset(sc); 1428 1429 if (bfe_list_rx_init(sc) == ENOBUFS) { 1430 printf("bfe%d: bfe_init: Not enough memory for list buffers\n", 1431 sc->bfe_unit); 1432 bfe_stop(sc); 1433 return; 1434 } 1435 1436 bfe_set_rx_mode(sc); 1437 1438 /* Enable the chip and core */ 1439 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE); 1440 /* Enable interrupts */ 1441 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF); 1442 1443 bfe_ifmedia_upd(ifp); 1444 ifp->if_flags |= IFF_RUNNING; 1445 ifp->if_flags &= ~IFF_OACTIVE; 1446 1447 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1448 BFE_UNLOCK(sc); 1449} 1450 1451/* 1452 * Set media options. 1453 */ 1454static int 1455bfe_ifmedia_upd(struct ifnet *ifp) 1456{ 1457 struct bfe_softc *sc; 1458 struct mii_data *mii; 1459 1460 sc = ifp->if_softc; 1461 1462 BFE_LOCK(sc); 1463 1464 mii = device_get_softc(sc->bfe_miibus); 1465 sc->bfe_link = 0; 1466 if (mii->mii_instance) { 1467 struct mii_softc *miisc; 1468 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1469 miisc = LIST_NEXT(miisc, mii_list)) 1470 mii_phy_reset(miisc); 1471 } 1472 mii_mediachg(mii); 1473 1474 BFE_UNLOCK(sc); 1475 return(0); 1476} 1477 1478/* 1479 * Report current media status. 1480 */ 1481static void 1482bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1483{ 1484 struct bfe_softc *sc = ifp->if_softc; 1485 struct mii_data *mii; 1486 1487 BFE_LOCK(sc); 1488 1489 mii = device_get_softc(sc->bfe_miibus); 1490 mii_pollstat(mii); 1491 ifmr->ifm_active = mii->mii_media_active; 1492 ifmr->ifm_status = mii->mii_media_status; 1493 1494 BFE_UNLOCK(sc); 1495} 1496 1497static int 1498bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1499{ 1500 struct bfe_softc *sc = ifp->if_softc; 1501 struct ifreq *ifr = (struct ifreq *) data; 1502 struct mii_data *mii; 1503 int error = 0; 1504 1505 BFE_LOCK(sc); 1506 1507 switch(command) { 1508 case SIOCSIFFLAGS: 1509 if(ifp->if_flags & IFF_UP) 1510 if(ifp->if_flags & IFF_RUNNING) 1511 bfe_set_rx_mode(sc); 1512 else 1513 bfe_init(sc); 1514 else if(ifp->if_flags & IFF_RUNNING) 1515 bfe_stop(sc); 1516 break; 1517 case SIOCADDMULTI: 1518 case SIOCDELMULTI: 1519 if(ifp->if_flags & IFF_RUNNING) 1520 bfe_set_rx_mode(sc); 1521 break; 1522 case SIOCGIFMEDIA: 1523 case SIOCSIFMEDIA: 1524 mii = device_get_softc(sc->bfe_miibus); 1525 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1526 command); 1527 break; 1528 default: 1529 error = ether_ioctl(ifp, command, data); 1530 break; 1531 } 1532 1533 BFE_UNLOCK(sc); 1534 return error; 1535} 1536 1537static void 1538bfe_watchdog(struct ifnet *ifp) 1539{ 1540 struct bfe_softc *sc; 1541 1542 sc = ifp->if_softc; 1543 1544 BFE_LOCK(sc); 1545 1546 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit); 1547 1548 ifp->if_flags &= ~IFF_RUNNING; 1549 bfe_init(sc); 1550 1551 ifp->if_oerrors++; 1552 1553 BFE_UNLOCK(sc); 1554} 1555 1556static void 1557bfe_tick(void *xsc) 1558{ 1559 struct bfe_softc *sc = xsc; 1560 struct mii_data *mii; 1561 1562 if (sc == NULL) 1563 return; 1564 1565 BFE_LOCK(sc); 1566 1567 mii = device_get_softc(sc->bfe_miibus); 1568 1569 bfe_stats_update(sc); 1570 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz); 1571 1572 if(sc->bfe_link) { 1573 BFE_UNLOCK(sc); 1574 return; 1575 } 1576 1577 mii_tick(mii); 1578 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE && 1579 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 1580 sc->bfe_link++; 1581 1582 BFE_UNLOCK(sc); 1583} 1584 1585/* 1586 * Stop the adapter and free any mbufs allocated to the 1587 * RX and TX lists. 1588 */ 1589static void 1590bfe_stop(struct bfe_softc *sc) 1591{ 1592 struct ifnet *ifp; 1593 1594 BFE_LOCK(sc); 1595 1596 untimeout(bfe_tick, sc, sc->bfe_stat_ch); 1597 1598 ifp = &sc->arpcom.ac_if; 1599 1600 bfe_chip_halt(sc); 1601 bfe_tx_ring_free(sc); 1602 bfe_rx_ring_free(sc); 1603 1604 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1605 1606 BFE_UNLOCK(sc); 1607} 1608