if_bcereg.h revision 179695
1/*-
2 * Copyright (c) 2006-2008 Broadcom Corporation
3 *	David Christensen <davidch@broadcom.com>.  All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
14 *    may be used to endorse or promote products derived from this software
15 *    without specific prior written consent.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/dev/bce/if_bcereg.h 179695 2008-06-10 02:19:11Z davidch $
30 */
31
32#ifndef	_BCE_H_DEFINED
33#define _BCE_H_DEFINED
34
35#include <sys/param.h>
36#include <sys/endian.h>
37#include <sys/systm.h>
38#include <sys/sockio.h>
39#include <sys/mbuf.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/module.h>
43#include <sys/socket.h>
44#include <sys/sysctl.h>
45#include <sys/queue.h>
46
47#include <net/bpf.h>
48#include <net/ethernet.h>
49#include <net/if.h>
50#include <net/if_arp.h>
51#include <net/if_dl.h>
52#include <net/if_media.h>
53
54#include <net/if_types.h>
55#include <net/if_vlan_var.h>
56
57#include <netinet/in_systm.h>
58#include <netinet/in.h>
59#include <netinet/if_ether.h>
60#include <netinet/ip.h>
61#include <netinet/ip6.h>
62#include <netinet/tcp.h>
63#include <netinet/udp.h>
64
65#include <machine/bus.h>
66#include <machine/resource.h>
67#include <sys/bus.h>
68#include <sys/rman.h>
69
70#include <dev/mii/mii.h>
71#include <dev/mii/miivar.h>
72#include "miidevs.h"
73#include <dev/mii/brgphyreg.h>
74
75#include <dev/pci/pcireg.h>
76#include <dev/pci/pcivar.h>
77
78#include "miibus_if.h"
79
80/****************************************************************************/
81/* Conversion to FreeBSD type definitions.                                  */
82/****************************************************************************/
83#define u64 uint64_t
84#define u32	uint32_t
85#define u16	uint16_t
86#define u8	uint8_t
87
88#if BYTE_ORDER == BIG_ENDIAN
89#define __BIG_ENDIAN 1
90#undef  __LITTLE_ENDIAN
91#else
92#undef  __BIG_ENDIAN
93#define __LITTLE_ENDIAN 1
94#endif
95
96#define BCE_DWORD_PRINTFB	\
97	"\020"					\
98	"\40b31"				\
99	"\37b30"				\
100	"\36b29"				\
101	"\35b28"				\
102	"\34b27"				\
103	"\33b26"				\
104	"\32b25"				\
105	"\31b24"				\
106	"\30b23"				\
107	"\27b22"				\
108	"\26b21"				\
109	"\25b20"				\
110	"\24b19"				\
111	"\23b18"				\
112	"\22b17"				\
113	"\21b16"				\
114	"\20b15"				\
115	"\17b14"				\
116	"\16b13"				\
117	"\15b12"				\
118	"\14b11"				\
119	"\13b10"				\
120	"\12b9"					\
121	"\11b8"					\
122	"\10b7"					\
123	"\07b6"					\
124	"\06b5"					\
125	"\05b4"					\
126	"\04b3"					\
127	"\03b2"					\
128	"\02b1"					\
129	"\01b0"
130
131
132/****************************************************************************/
133/* Debugging macros and definitions.                                        */
134/****************************************************************************/
135/* #define BCE_DEBUG 1 */
136
137#define BCE_CP_LOAD 			0x00000001
138#define BCE_CP_SEND		 		0x00000002
139#define BCE_CP_RECV				0x00000004
140#define BCE_CP_INTR				0x00000008
141#define BCE_CP_UNLOAD			0x00000010
142#define BCE_CP_RESET			0x00000020
143#define BCE_CP_PHY				0x00000040
144#define BCE_CP_NVRAM			0x00000080
145#define BCE_CP_FIRMWARE			0x00000100
146#define BCE_CP_MISC				0x00400000
147#define BCE_CP_SPECIAL			0x00800000
148#define BCE_CP_ALL				0x00FFFFFF
149
150#define BCE_CP_MASK				0x00FFFFFF
151
152#define BCE_LEVEL_FATAL			0x00000000
153#define BCE_LEVEL_WARN			0x01000000
154#define BCE_LEVEL_INFO			0x02000000
155#define BCE_LEVEL_VERBOSE		0x03000000
156#define BCE_LEVEL_EXCESSIVE		0x04000000
157
158#define BCE_LEVEL_MASK			0xFF000000
159
160#define BCE_WARN_LOAD			(BCE_CP_LOAD | BCE_LEVEL_WARN)
161#define BCE_INFO_LOAD			(BCE_CP_LOAD | BCE_LEVEL_INFO)
162#define BCE_VERBOSE_LOAD		(BCE_CP_LOAD | BCE_LEVEL_VERBOSE)
163#define BCE_EXCESSIVE_LOAD		(BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE)
164
165#define BCE_WARN_SEND			(BCE_CP_SEND | BCE_LEVEL_WARN)
166#define BCE_INFO_SEND			(BCE_CP_SEND | BCE_LEVEL_INFO)
167#define BCE_VERBOSE_SEND		(BCE_CP_SEND | BCE_LEVEL_VERBOSE)
168#define BCE_EXCESSIVE_SEND		(BCE_CP_SEND | BCE_LEVEL_EXCESSIVE)
169
170#define BCE_WARN_RECV			(BCE_CP_RECV | BCE_LEVEL_WARN)
171#define BCE_INFO_RECV			(BCE_CP_RECV | BCE_LEVEL_INFO)
172#define BCE_VERBOSE_RECV		(BCE_CP_RECV | BCE_LEVEL_VERBOSE)
173#define BCE_EXCESSIVE_RECV		(BCE_CP_RECV | BCE_LEVEL_EXCESSIVE)
174
175#define BCE_WARN_INTR			(BCE_CP_INTR | BCE_LEVEL_WARN)
176#define BCE_INFO_INTR			(BCE_CP_INTR | BCE_LEVEL_INFO)
177#define BCE_VERBOSE_INTR		(BCE_CP_INTR | BCE_LEVEL_VERBOSE)
178#define BCE_EXCESSIVE_INTR		(BCE_CP_INTR | BCE_LEVEL_EXCESSIVE)
179
180#define BCE_WARN_UNLOAD			(BCE_CP_UNLOAD | BCE_LEVEL_WARN)
181#define BCE_INFO_UNLOAD			(BCE_CP_UNLOAD | BCE_LEVEL_INFO)
182#define BCE_VERBOSE_UNLOAD		(BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE)
183#define BCE_EXCESSIVE_UNLOAD	(BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE)
184
185#define BCE_WARN_RESET			(BCE_CP_RESET | BCE_LEVEL_WARN)
186#define BCE_INFO_RESET			(BCE_CP_RESET | BCE_LEVEL_INFO)
187#define BCE_VERBOSE_RESET		(BCE_CP_RESET | BCE_LEVEL_VERBOSE)
188#define BCE_EXCESSIVE_RESET		(BCE_CP_RESET | BCE_LEVEL_EXCESSIVE)
189
190#define BCE_WARN_PHY			(BCE_CP_PHY | BCE_LEVEL_WARN)
191#define BCE_INFO_PHY			(BCE_CP_PHY | BCE_LEVEL_INFO)
192#define BCE_VERBOSE_PHY			(BCE_CP_PHY | BCE_LEVEL_VERBOSE)
193#define BCE_EXCESSIVE_PHY		(BCE_CP_PHY | BCE_LEVEL_EXCESSIVE)
194
195#define BCE_WARN_NVRAM			(BCE_CP_NVRAM | BCE_LEVEL_WARN)
196#define BCE_INFO_NVRAM			(BCE_CP_NVRAM | BCE_LEVEL_INFO)
197#define BCE_VERBOSE_NVRAM		(BCE_CP_NVRAM | BCE_LEVEL_VERBOSE)
198#define BCE_EXCESSIVE_NVRAM		(BCE_CP_NVRAM | BCE_LEVEL_EXCESSIVE)
199
200#define BCE_WARN_FIRMWARE		(BCE_CP_FIRMWARE | BCE_LEVEL_WARN)
201#define BCE_INFO_FIRMWARE		(BCE_CP_FIRMWARE | BCE_LEVEL_INFO)
202#define BCE_VERBOSE_FIRMWARE		(BCE_CP_FIRMWARE | BCE_LEVEL_VERBOSE)
203#define BCE_EXCESSIVE_FIRMWARE		(BCE_CP_FIRMWARE | BCE_LEVEL_EXCESSIVE)
204
205#define BCE_WARN_MISC			(BCE_CP_MISC | BCE_LEVEL_WARN)
206#define BCE_INFO_MISC			(BCE_CP_MISC | BCE_LEVEL_INFO)
207#define BCE_VERBOSE_MISC		(BCE_CP_MISC | BCE_LEVEL_VERBOSE)
208#define BCE_EXCESSIVE_MISC		(BCE_CP_MISC | BCE_LEVEL_EXCESSIVE)
209
210#define BCE_WARN_SPECIAL		(BCE_CP_SPECIAL | BCE_LEVEL_WARN)
211#define BCE_INFO_SPECIAL		(BCE_CP_SPECIAL | BCE_LEVEL_INFO)
212#define BCE_VERBOSE_SPECIAL		(BCE_CP_SPECIAL | BCE_LEVEL_VERBOSE)
213#define BCE_EXCESSIVE_SPECIAL		(BCE_CP_SPECIAL | BCE_LEVEL_EXCESSIVE)
214
215#define BCE_FATAL				(BCE_CP_ALL | BCE_LEVEL_FATAL)
216#define BCE_WARN				(BCE_CP_ALL | BCE_LEVEL_WARN)
217#define BCE_INFO				(BCE_CP_ALL | BCE_LEVEL_INFO)
218#define BCE_VERBOSE				(BCE_CP_ALL | BCE_LEVEL_VERBOSE)
219#define BCE_EXCESSIVE			(BCE_CP_ALL | BCE_LEVEL_EXCESSIVE)
220
221#define BCE_CODE_PATH(cp)		((cp & BCE_CP_MASK) & bce_debug)
222#define BCE_MSG_LEVEL(lv)		((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK))
223#define BCE_LOG_MSG(m)			(BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m))
224
225#ifdef BCE_DEBUG
226
227/*
228 * Calculate the time delta between two reads
229 * of the 25MHz free running clock.
230 */
231#define BCE_TIME_DELTA(start, end)	(start > end ? (start - end) : \
232	(~start + end + 1))
233
234/* Print a message based on the logging level and code path. */
235#define DBPRINT(sc, level, format, args...)					\
236	if (BCE_LOG_MSG(level)) {							\
237		device_printf(sc->bce_dev, format, ## args);						\
238	}
239
240/* Runs a particular command when debugging is enabled. */
241#define DBRUN(args...)			\
242	do {						\
243		args;					\
244	} while (0)
245
246/* Runs a particular command based on the logging level and code path. */
247#define DBRUNMSG(msg, args...)	\
248	if (BCE_LOG_MSG(msg)) {		\
249		args;					\
250	}
251
252/* Runs a particular command based on the logging level. */
253#define DBRUNLV(level, args...) \
254	if (BCE_MSG_LEVEL(level)) { \
255		args;					\
256	}
257
258/* Runs a particular command based on the code path. */
259#define DBRUNCP(cp, args...) 	\
260	if (BCE_CODE_PATH(cp)) { 	\
261		args; 					\
262	}
263
264/* Runs a particular command based on a condition. */
265#define DBRUNIF(cond, args...)	\
266	if (cond) {					\
267		args;					\
268	}
269
270/* Needed for random() function which is only used in debugging. */
271#include <sys/random.h>
272
273/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
274#define DB_RANDOMFALSE(defects)        (random() > defects)
275#define DB_OR_RANDOMFALSE(defects)  || (random() > defects)
276#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
277
278/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
279#define DB_RANDOMTRUE(defects)         (random() < defects)
280#define DB_OR_RANDOMTRUE(defects)   || (random() < defects)
281#define DB_AND_RANDOMTRUE(defects)  && (random() < defects)
282
283#else
284
285#define DBPRINT(level, format, args...)
286#define DBRUN(args...)
287#define DBRUNMSG(msg, args...)
288#define DBRUNLV(level, args...)
289#define DBRUNCP(cp, args...)
290#define DBRUNIF(cond, args...)
291#define DB_RANDOMFALSE(defects)
292#define DB_OR_RANDOMFALSE(percent)
293#define DB_AND_RANDOMFALSE(percent)
294#define DB_RANDOMTRUE(defects)
295#define DB_OR_RANDOMTRUE(percent)
296#define DB_AND_RANDOMTRUE(percent)
297
298#endif /* BCE_DEBUG */
299
300
301/****************************************************************************/
302/* Device identification definitions.                                       */
303/****************************************************************************/
304#define BRCM_VENDORID				0x14E4
305#define BRCM_DEVICEID_BCM5706		0x164A
306#define BRCM_DEVICEID_BCM5706S		0x16AA
307#define BRCM_DEVICEID_BCM5708		0x164C
308#define BRCM_DEVICEID_BCM5708S		0x16AC
309
310#define HP_VENDORID					0x103C
311
312#define PCI_ANY_ID					(u_int16_t) (~0U)
313
314/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
315
316#define BCE_CHIP_NUM(sc)			(((sc)->bce_chipid) & 0xffff0000)
317#define BCE_CHIP_NUM_5706			0x57060000
318#define BCE_CHIP_NUM_5708			0x57080000
319
320#define BCE_CHIP_REV(sc)			(((sc)->bce_chipid) & 0x0000f000)
321#define BCE_CHIP_REV_Ax				0x00000000
322#define BCE_CHIP_REV_Bx				0x00001000
323#define BCE_CHIP_REV_Cx				0x00002000
324
325#define BCE_CHIP_METAL(sc)			(((sc)->bce_chipid) & 0x00000ff0)
326#define BCE_CHIP_BOND(bp)			(((sc)->bce_chipid) & 0x0000000f)
327
328#define BCE_CHIP_ID(sc)				(((sc)->bce_chipid) & 0xfffffff0)
329#define BCE_CHIP_ID_5706_A0			0x57060000
330#define BCE_CHIP_ID_5706_A1			0x57060010
331#define BCE_CHIP_ID_5706_A2			0x57060020
332#define BCE_CHIP_ID_5706_A3			0x57060030
333#define BCE_CHIP_ID_5708_A0			0x57080000
334#define BCE_CHIP_ID_5708_B0			0x57081000
335#define BCE_CHIP_ID_5708_B1			0x57081010
336#define BCE_CHIP_ID_5708_B2			0x57081020
337
338#define BCE_CHIP_BOND_ID(sc)		(((sc)->bce_chipid) & 0xf)
339
340/* A serdes chip will have the first bit of the bond id set. */
341#define BCE_CHIP_BOND_ID_SERDES_BIT		0x01
342
343
344/* shorthand one */
345#define BCE_ASICREV(x)			((x) >> 28)
346#define BCE_ASICREV_BCM5700		0x06
347
348/* chip revisions */
349#define BCE_CHIPREV(x)			((x) >> 24)
350#define BCE_CHIPREV_5700_AX		0x70
351#define BCE_CHIPREV_5700_BX		0x71
352#define BCE_CHIPREV_5700_CX		0x72
353#define BCE_CHIPREV_5701_AX		0x00
354
355struct bce_type {
356	u_int16_t		bce_vid;
357	u_int16_t		bce_did;
358	u_int16_t		bce_svid;
359	u_int16_t		bce_sdid;
360	char			*bce_name;
361};
362
363/****************************************************************************/
364/* Byte order conversions.                                                  */
365/****************************************************************************/
366#if __FreeBSD_version >= 500000
367#define bce_htobe16(x) htobe16(x)
368#define bce_htobe32(x) htobe32(x)
369#define bce_htobe64(x) htobe64(x)
370#define bce_htole16(x) htole16(x)
371#define bce_htole32(x) htole32(x)
372#define bce_htole64(x) htole64(x)
373
374#define bce_be16toh(x) be16toh(x)
375#define bce_be32toh(x) be32toh(x)
376#define bce_be64toh(x) be64toh(x)
377#define bce_le16toh(x) le16toh(x)
378#define bce_le32toh(x) le32toh(x)
379#define bce_le64toh(x) le64toh(x)
380#else
381#define bce_htobe16(x) (x)
382#define bce_htobe32(x) (x)
383#define bce_htobe64(x) (x)
384#define bce_htole16(x) (x)
385#define bce_htole32(x) (x)
386#define bce_htole64(x) (x)
387
388#define bce_be16toh(x) (x)
389#define bce_be32toh(x) (x)
390#define bce_be64toh(x) (x)
391#define bce_le16toh(x) (x)
392#define bce_le32toh(x) (x)
393#define bce_le64toh(x) (x)
394#endif
395
396
397/****************************************************************************/
398/* NVRAM Access                                                             */
399/****************************************************************************/
400
401/* Buffered flash (Atmel: AT45DB011B) specific information */
402#define SEEPROM_PAGE_BITS				2
403#define SEEPROM_PHY_PAGE_SIZE			(1 << SEEPROM_PAGE_BITS)
404#define SEEPROM_BYTE_ADDR_MASK			(SEEPROM_PHY_PAGE_SIZE-1)
405#define SEEPROM_PAGE_SIZE				4
406#define SEEPROM_TOTAL_SIZE				65536
407
408#define BUFFERED_FLASH_PAGE_BITS		9
409#define BUFFERED_FLASH_PHY_PAGE_SIZE	(1 << BUFFERED_FLASH_PAGE_BITS)
410#define BUFFERED_FLASH_BYTE_ADDR_MASK	(BUFFERED_FLASH_PHY_PAGE_SIZE-1)
411#define BUFFERED_FLASH_PAGE_SIZE		264
412#define BUFFERED_FLASH_TOTAL_SIZE		0x21000
413
414#define SAIFUN_FLASH_PAGE_BITS			8
415#define SAIFUN_FLASH_PHY_PAGE_SIZE		(1 << SAIFUN_FLASH_PAGE_BITS)
416#define SAIFUN_FLASH_BYTE_ADDR_MASK		(SAIFUN_FLASH_PHY_PAGE_SIZE-1)
417#define SAIFUN_FLASH_PAGE_SIZE			256
418#define SAIFUN_FLASH_BASE_TOTAL_SIZE	65536
419
420#define ST_MICRO_FLASH_PAGE_BITS		8
421#define ST_MICRO_FLASH_PHY_PAGE_SIZE	(1 << ST_MICRO_FLASH_PAGE_BITS)
422#define ST_MICRO_FLASH_BYTE_ADDR_MASK	(ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
423#define ST_MICRO_FLASH_PAGE_SIZE		256
424#define ST_MICRO_FLASH_BASE_TOTAL_SIZE	65536
425
426#define NVRAM_TIMEOUT_COUNT				30000
427#define BCE_FLASHDESC_MAX				64
428
429#define FLASH_STRAP_MASK				(BCE_NVM_CFG1_FLASH_MODE | \
430										 BCE_NVM_CFG1_BUFFER_MODE  | \
431										 BCE_NVM_CFG1_PROTECT_MODE | \
432										 BCE_NVM_CFG1_FLASH_SIZE)
433
434#define FLASH_BACKUP_STRAP_MASK			(0xf << 26)
435
436struct flash_spec {
437	u32 strapping;
438	u32 config1;
439	u32 config2;
440	u32 config3;
441	u32 write1;
442	u32 buffered;
443	u32 page_bits;
444	u32 page_size;
445	u32 addr_mask;
446	u32 total_size;
447	u8  *name;
448};
449
450
451/****************************************************************************/
452/* Shared Memory layout                                                     */
453/* The BCE bootcode will initialize this data area with port configurtion   */
454/* information which can be accessed by the driver.                         */
455/****************************************************************************/
456
457/*
458 * This value (in milliseconds) determines the frequency of the driver
459 * issuing the PULSE message code.  The firmware monitors this periodic
460 * pulse to determine when to switch to an OS-absent mode.
461 */
462#define DRV_PULSE_PERIOD_MS                 250
463
464/*
465 * This value (in milliseconds) determines how long the driver should
466 * wait for an acknowledgement from the firmware before timing out.  Once
467 * the firmware has timed out, the driver will assume there is no firmware
468 * running and there won't be any firmware-driver synchronization during a
469 * driver reset.
470 */
471#define FW_ACK_TIME_OUT_MS                  1000
472
473
474#define BCE_DRV_RESET_SIGNATURE				0x00000000
475#define BCE_DRV_RESET_SIGNATURE_MAGIC		0x4841564b /* HAVK */
476
477#define BCE_DRV_MB							0x00000004
478#define BCE_DRV_MSG_CODE			 		0xff000000
479#define BCE_DRV_MSG_CODE_RESET			 	0x01000000
480#define BCE_DRV_MSG_CODE_UNLOAD		 		0x02000000
481#define BCE_DRV_MSG_CODE_SHUTDOWN		 	0x03000000
482#define BCE_DRV_MSG_CODE_SUSPEND_WOL		0x04000000
483#define BCE_DRV_MSG_CODE_FW_TIMEOUT		 	0x05000000
484#define BCE_DRV_MSG_CODE_PULSE			 	0x06000000
485#define BCE_DRV_MSG_CODE_DIAG			 	0x07000000
486#define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL	 	0x09000000
487#define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN		0x0b000000
488#define BCE_DRV_MSG_CODE_CMD_SET_LINK		0x10000000
489
490#define BCE_DRV_MSG_DATA			 		0x00ff0000
491#define BCE_DRV_MSG_DATA_WAIT0			 	0x00010000
492#define BCE_DRV_MSG_DATA_WAIT1				0x00020000
493#define BCE_DRV_MSG_DATA_WAIT2				0x00030000
494#define BCE_DRV_MSG_DATA_WAIT3				0x00040000
495
496#define BCE_DRV_MSG_SEQ						0x0000ffff
497
498#define BCE_FW_MB				0x00000008
499#define BCE_FW_MSG_ACK				 0x0000ffff
500#define BCE_FW_MSG_STATUS_MASK			 0x00ff0000
501#define BCE_FW_MSG_STATUS_OK			 0x00000000
502#define BCE_FW_MSG_STATUS_FAILURE		 0x00ff0000
503
504#define BCE_LINK_STATUS			0x0000000c
505#define BCE_LINK_STATUS_INIT_VALUE		 0xffffffff
506#define BCE_LINK_STATUS_LINK_UP		 0x1
507#define BCE_LINK_STATUS_LINK_DOWN		 0x0
508#define BCE_LINK_STATUS_SPEED_MASK		 0x1e
509#define BCE_LINK_STATUS_AN_INCOMPLETE		 (0<<1)
510#define BCE_LINK_STATUS_10HALF			 (1<<1)
511#define BCE_LINK_STATUS_10FULL			 (2<<1)
512#define BCE_LINK_STATUS_100HALF		 (3<<1)
513#define BCE_LINK_STATUS_100BASE_T4		 (4<<1)
514#define BCE_LINK_STATUS_100FULL		 (5<<1)
515#define BCE_LINK_STATUS_1000HALF		 (6<<1)
516#define BCE_LINK_STATUS_1000FULL		 (7<<1)
517#define BCE_LINK_STATUS_2500HALF		 (8<<1)
518#define BCE_LINK_STATUS_2500FULL		 (9<<1)
519#define BCE_LINK_STATUS_AN_ENABLED		 (1<<5)
520#define BCE_LINK_STATUS_AN_COMPLETE		 (1<<6)
521#define BCE_LINK_STATUS_PARALLEL_DET		 (1<<7)
522#define BCE_LINK_STATUS_RESERVED		 (1<<8)
523#define BCE_LINK_STATUS_PARTNER_AD_1000FULL	 (1<<9)
524#define BCE_LINK_STATUS_PARTNER_AD_1000HALF	 (1<<10)
525#define BCE_LINK_STATUS_PARTNER_AD_100BT4	 (1<<11)
526#define BCE_LINK_STATUS_PARTNER_AD_100FULL	 (1<<12)
527#define BCE_LINK_STATUS_PARTNER_AD_100HALF	 (1<<13)
528#define BCE_LINK_STATUS_PARTNER_AD_10FULL	 (1<<14)
529#define BCE_LINK_STATUS_PARTNER_AD_10HALF	 (1<<15)
530#define BCE_LINK_STATUS_TX_FC_ENABLED		 (1<<16)
531#define BCE_LINK_STATUS_RX_FC_ENABLED		 (1<<17)
532#define BCE_LINK_STATUS_PARTNER_SYM_PAUSE_CAP	 (1<<18)
533#define BCE_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP	 (1<<19)
534#define BCE_LINK_STATUS_SERDES_LINK		 (1<<20)
535#define BCE_LINK_STATUS_PARTNER_AD_2500FULL	 (1<<21)
536#define BCE_LINK_STATUS_PARTNER_AD_2500HALF	 (1<<22)
537
538#define BCE_DRV_PULSE_MB			0x00000010
539#define BCE_DRV_PULSE_SEQ_MASK			 0x00007fff
540
541#define BCE_MB_ARGS_0				0x00000014
542#define BCE_MB_ARGS_1				0x00000018
543
544/* Indicate to the firmware not to go into the
545 * OS absent when it is not getting driver pulse.
546 * This is used for debugging. */
547#define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE	 0x00080000
548
549#define BCE_DEV_INFO_SIGNATURE			0x00000020
550#define BCE_DEV_INFO_SIGNATURE_MAGIC		 0x44564900
551#define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK	 0xffffff00
552#define BCE_DEV_INFO_FEATURE_CFG_VALID		 0x01
553#define BCE_DEV_INFO_SECONDARY_PORT		 0x80
554#define BCE_DEV_INFO_DRV_ALWAYS_ALIVE		 0x40
555
556#define BCE_SHARED_HW_CFG_PART_NUM		0x00000024
557
558#define BCE_SHARED_HW_CFG_POWER_DISSIPATED	0x00000034
559#define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK	 0xff000000
560#define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK	 0xff0000
561#define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK	 0xff00
562#define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK	 0xff
563
564#define BCE_SHARED_HW_CFG_POWER_CONSUMED	0x00000038
565#define BCE_SHARED_HW_CFG_CONFIG		0x0000003c
566#define BCE_SHARED_HW_CFG_DESIGN_NIC		 0
567#define BCE_SHARED_HW_CFG_DESIGN_LOM		 0x1
568#define BCE_SHARED_HW_CFG_PHY_COPPER		 0
569#define BCE_SHARED_HW_CFG_PHY_FIBER		 0x2
570#define BCE_SHARED_HW_CFG_PHY_2_5G		 0x20
571#define BCE_SHARED_HW_CFG_PHY_BACKPLANE	 0x40
572#define BCE_SHARED_HW_CFG_LED_MODE_SHIFT_BITS	 8
573#define BCE_SHARED_HW_CFG_LED_MODE_MASK	 0x300
574#define BCE_SHARED_HW_CFG_LED_MODE_MAC		 0
575#define BCE_SHARED_HW_CFG_LED_MODE_GPHY1	 0x100
576#define BCE_SHARED_HW_CFG_LED_MODE_GPHY2	 0x200
577
578#define BCE_SHARED_HW_CFG_CONFIG2		0x00000040
579#define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK	 0x00fff000
580
581#define BCE_DEV_INFO_BC_REV			0x0000004c
582
583#define BCE_PORT_HW_CFG_MAC_UPPER		0x00000050
584#define BCE_PORT_HW_CFG_UPPERMAC_MASK		 0xffff
585
586#define BCE_PORT_HW_CFG_MAC_LOWER		0x00000054
587#define BCE_PORT_HW_CFG_CONFIG			0x00000058
588#define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK	 0x0000ffff
589#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK	 0x001f0000
590#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN	 0x00000000
591#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G	 0x00030000
592#define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G	 0x00040000
593
594#define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER	0x00000068
595#define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER	0x0000006c
596#define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER	0x00000070
597#define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER	0x00000074
598#define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER	0x00000078
599#define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER	0x0000007c
600
601#define BCE_DEV_INFO_PER_PORT_HW_CONFIG2	0x000000b4
602
603#define BCE_DEV_INFO_FORMAT_REV		0x000000c4
604#define BCE_DEV_INFO_FORMAT_REV_MASK		 0xff000000
605#define BCE_DEV_INFO_FORMAT_REV_ID		 ('A' << 24)
606
607#define BCE_SHARED_FEATURE			0x000000c8
608#define BCE_SHARED_FEATURE_MASK		 0xffffffff
609
610#define BCE_PORT_FEATURE			0x000000d8
611#define BCE_PORT2_FEATURE			0x00000014c
612#define BCE_PORT_FEATURE_WOL_ENABLED		 0x01000000
613#define BCE_PORT_FEATURE_MBA_ENABLED		 0x02000000
614#define BCE_PORT_FEATURE_ASF_ENABLED		 0x04000000
615#define BCE_PORT_FEATURE_IMD_ENABLED		 0x08000000
616#define BCE_PORT_FEATURE_BAR1_SIZE_MASK	 0xf
617#define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED	 0x0
618#define BCE_PORT_FEATURE_BAR1_SIZE_64K		 0x1
619#define BCE_PORT_FEATURE_BAR1_SIZE_128K	 0x2
620#define BCE_PORT_FEATURE_BAR1_SIZE_256K	 0x3
621#define BCE_PORT_FEATURE_BAR1_SIZE_512K	 0x4
622#define BCE_PORT_FEATURE_BAR1_SIZE_1M		 0x5
623#define BCE_PORT_FEATURE_BAR1_SIZE_2M		 0x6
624#define BCE_PORT_FEATURE_BAR1_SIZE_4M		 0x7
625#define BCE_PORT_FEATURE_BAR1_SIZE_8M		 0x8
626#define BCE_PORT_FEATURE_BAR1_SIZE_16M		 0x9
627#define BCE_PORT_FEATURE_BAR1_SIZE_32M		 0xa
628#define BCE_PORT_FEATURE_BAR1_SIZE_64M		 0xb
629#define BCE_PORT_FEATURE_BAR1_SIZE_128M	 0xc
630#define BCE_PORT_FEATURE_BAR1_SIZE_256M	 0xd
631#define BCE_PORT_FEATURE_BAR1_SIZE_512M	 0xe
632#define BCE_PORT_FEATURE_BAR1_SIZE_1G		 0xf
633
634#define BCE_PORT_FEATURE_WOL			0xdc
635#define BCE_PORT2_FEATURE_WOL			0x150
636#define BCE_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS	 4
637#define BCE_PORT_FEATURE_WOL_DEFAULT_MASK	 0x30
638#define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE	 0
639#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC	 0x10
640#define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI	 0x20
641#define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI	 0x30
642#define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK	 0xf
643#define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG	 0
644#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10HALF	 1
645#define BCE_PORT_FEATURE_WOL_LINK_SPEED_10FULL	 2
646#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
647#define BCE_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
648#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000HALF	 5
649#define BCE_PORT_FEATURE_WOL_LINK_SPEED_1000FULL	 6
650#define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000	 0x40
651#define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
652#define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP	 0x800
653
654#define BCE_PORT_FEATURE_MBA			0xe0
655#define BCE_PORT2_FEATURE_MBA			0x154
656#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS	 0
657#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK	 0x3
658#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE	 0
659#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL	 1
660#define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP	 2
661#define BCE_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS	 2
662#define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK	 0x3c
663#define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG	 0
664#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF	 0x4
665#define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL	 0x8
666#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF	 0xc
667#define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL	 0x10
668#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF	 0x14
669#define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL	 0x18
670#define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE	 0x40
671#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S	 0
672#define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B	 0x80
673#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS	 8
674#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK	 0xff00
675#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED	 0
676#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K	 0x100
677#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K	 0x200
678#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K	 0x300
679#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K	 0x400
680#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K	 0x500
681#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K	 0x600
682#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K	 0x700
683#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K	 0x800
684#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K	 0x900
685#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K	 0xa00
686#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M	 0xb00
687#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M	 0xc00
688#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M	 0xd00
689#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M	 0xe00
690#define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M	 0xf00
691#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS	 16
692#define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK	 0xf0000
693#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS	 20
694#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK	 0x300000
695#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO	 0
696#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS	 0x100000
697#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H	 0x200000
698#define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H	 0x300000
699
700#define BCE_PORT_FEATURE_IMD			0xe4
701#define BCE_PORT2_FEATURE_IMD			0x158
702#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT	 0
703#define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE	 1
704
705#define BCE_PORT_FEATURE_VLAN			0xe8
706#define BCE_PORT2_FEATURE_VLAN			0x15c
707#define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK	 0xffff
708#define BCE_PORT_FEATURE_MBA_VLAN_ENABLE	 0x10000
709
710#define BCE_BC_STATE_RESET_TYPE		0x000001c0
711#define BCE_BC_STATE_RESET_TYPE_SIG		 0x00005254
712#define BCE_BC_STATE_RESET_TYPE_SIG_MASK	 0x0000ffff
713#define BCE_BC_STATE_RESET_TYPE_NONE	 (BCE_BC_STATE_RESET_TYPE_SIG | \
714					  0x00010000)
715#define BCE_BC_STATE_RESET_TYPE_PCI	 (BCE_BC_STATE_RESET_TYPE_SIG | \
716					  0x00020000)
717#define BCE_BC_STATE_RESET_TYPE_VAUX	 (BCE_BC_STATE_RESET_TYPE_SIG | \
718					  0x00030000)
719#define BCE_BC_STATE_RESET_TYPE_DRV_MASK	 DRV_MSG_CODE
720#define BCE_BC_STATE_RESET_TYPE_DRV_RESET (BCE_BC_STATE_RESET_TYPE_SIG | \
721					    DRV_MSG_CODE_RESET)
722#define BCE_BC_STATE_RESET_TYPE_DRV_UNLOAD (BCE_BC_STATE_RESET_TYPE_SIG | \
723					     DRV_MSG_CODE_UNLOAD)
724#define BCE_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BCE_BC_STATE_RESET_TYPE_SIG | \
725					       DRV_MSG_CODE_SHUTDOWN)
726#define BCE_BC_STATE_RESET_TYPE_DRV_WOL (BCE_BC_STATE_RESET_TYPE_SIG | \
727					  DRV_MSG_CODE_WOL)
728#define BCE_BC_STATE_RESET_TYPE_DRV_DIAG (BCE_BC_STATE_RESET_TYPE_SIG | \
729					   DRV_MSG_CODE_DIAG)
730#define BCE_BC_STATE_RESET_TYPE_VALUE(msg) (BCE_BC_STATE_RESET_TYPE_SIG | \
731					     (msg))
732
733#define BCE_BC_RESET_TYPE				0x000001c0
734
735#define BCE_BC_STATE					0x000001c4
736#define BCE_BC_STATE_ERR_MASK			0x0000ff00
737#define BCE_BC_STATE_SIGN				0x42530000
738#define BCE_BC_STATE_SIGN_MASK			0xffff0000
739#define BCE_BC_STATE_BC1_START			(BCE_BC_STATE_SIGN | 0x1)
740#define BCE_BC_STATE_GET_NVM_CFG1		(BCE_BC_STATE_SIGN | 0x2)
741#define BCE_BC_STATE_PROG_BAR			(BCE_BC_STATE_SIGN | 0x3)
742#define BCE_BC_STATE_INIT_VID			(BCE_BC_STATE_SIGN | 0x4)
743#define BCE_BC_STATE_GET_NVM_CFG2		(BCE_BC_STATE_SIGN | 0x5)
744#define BCE_BC_STATE_APPLY_WKARND		(BCE_BC_STATE_SIGN | 0x6)
745#define BCE_BC_STATE_LOAD_BC2			(BCE_BC_STATE_SIGN | 0x7)
746#define BCE_BC_STATE_GOING_BC2			(BCE_BC_STATE_SIGN | 0x8)
747#define BCE_BC_STATE_GOING_DIAG			(BCE_BC_STATE_SIGN | 0x9)
748#define BCE_BC_STATE_RT_FINAL_INIT		(BCE_BC_STATE_SIGN | 0x81)
749#define BCE_BC_STATE_RT_WKARND			(BCE_BC_STATE_SIGN | 0x82)
750#define BCE_BC_STATE_RT_DRV_PULSE		(BCE_BC_STATE_SIGN | 0x83)
751#define BCE_BC_STATE_RT_FIOEVTS			(BCE_BC_STATE_SIGN | 0x84)
752#define BCE_BC_STATE_RT_DRV_CMD			(BCE_BC_STATE_SIGN | 0x85)
753#define BCE_BC_STATE_RT_LOW_POWER		(BCE_BC_STATE_SIGN | 0x86)
754#define BCE_BC_STATE_RT_SET_WOL			(BCE_BC_STATE_SIGN | 0x87)
755#define BCE_BC_STATE_RT_OTHER_FW		(BCE_BC_STATE_SIGN | 0x88)
756#define BCE_BC_STATE_RT_GOING_D3		(BCE_BC_STATE_SIGN | 0x89)
757#define BCE_BC_STATE_ERR_BAD_VERSION	(BCE_BC_STATE_SIGN | 0x0100)
758#define BCE_BC_STATE_ERR_BAD_BC2_CRC	(BCE_BC_STATE_SIGN | 0x0200)
759#define BCE_BC_STATE_ERR_BC1_LOOP		(BCE_BC_STATE_SIGN | 0x0300)
760#define BCE_BC_STATE_ERR_UNKNOWN_CMD	(BCE_BC_STATE_SIGN | 0x0400)
761#define BCE_BC_STATE_ERR_DRV_DEAD		(BCE_BC_STATE_SIGN | 0x0500)
762#define BCE_BC_STATE_ERR_NO_RXP			(BCE_BC_STATE_SIGN | 0x0600)
763#define BCE_BC_STATE_ERR_TOO_MANY_RBUF	(BCE_BC_STATE_SIGN | 0x0700)
764
765#define BCE_BC_CONDITION				0x000001c8
766
767#define BCE_BC_STATE_DEBUG_CMD					0x1dc
768#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE		0x42440000
769#define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK	0xffff0000
770#define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK	0xffff
771#define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE	0xffff
772
773#define HOST_VIEW_SHMEM_BASE			0x167c00
774
775/*
776 * PCI registers defined in the PCI 2.2 spec.
777 */
778#define BCE_PCI_PCIX_CMD		0x42
779
780
781/****************************************************************************/
782/* Convenience definitions.                                                 */
783/****************************************************************************/
784#define BCE_PRINTF(fmt, args...)	device_printf(sc->bce_dev, fmt, ##args)
785
786#define	BCE_LOCK_INIT(_sc, _name)	mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
787#define	BCE_LOCK(_sc)				mtx_lock(&(_sc)->bce_mtx)
788#define	BCE_LOCK_ASSERT(_sc)		mtx_assert(&(_sc)->bce_mtx, MA_OWNED)
789#define	BCE_UNLOCK(_sc)				mtx_unlock(&(_sc)->bce_mtx)
790#define	BCE_LOCK_DESTROY(_sc)		mtx_destroy(&(_sc)->bce_mtx)
791
792#define REG_WR(sc, reg, val)		bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val)
793#define REG_WR16(sc, reg, val)		bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val)
794#define REG_RD(sc, reg)				bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg)
795#define REG_RD_IND(sc, offset)		bce_reg_rd_ind(sc, offset)
796#define REG_WR_IND(sc, offset, val)	bce_reg_wr_ind(sc, offset, val)
797#define CTX_WR(sc, cid_addr, offset, val)	bce_ctx_wr(sc, cid_addr, offset, val)
798#define CTX_RD(sc, cid_addr, offset)		bce_ctx_rd(sc, cid_addr, offset)
799#define BCE_SETBIT(sc, reg, x)		REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
800#define BCE_CLRBIT(sc, reg, x)		REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
801#define PCI_SETBIT(dev, reg, x, s)	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
802#define PCI_CLRBIT(dev, reg, x, s)	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
803
804#define BCE_STATS(x)			(u_long) stats->stat_ ## x ## _lo
805#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
806#define BCE_ADDR_LO(y)			((u64) (y) & 0xFFFFFFFF)
807#define BCE_ADDR_HI(y)			((u64) (y) >> 32)
808#else
809#define BCE_ADDR_LO(y)			((u32)y)
810#define BCE_ADDR_HI(y)			(0)
811#endif
812
813
814/*
815 * The following data structures are generated from RTL code.
816 * Do not modify any values below this line.
817 */
818
819/****************************************************************************/
820/* Do not modify any of the following data structures, they are generated   */
821/* from RTL code.                                                           */
822/*                                                                          */
823/* Begin machine generated definitions.                                     */
824/****************************************************************************/
825
826/*
827 *  tx_bd definition
828 */
829struct tx_bd {
830	u32 tx_bd_haddr_hi;
831	u32 tx_bd_haddr_lo;
832	u32 tx_bd_mss_nbytes;
833	u16 tx_bd_flags;
834	u16 tx_bd_vlan_tag;
835		#define TX_BD_FLAGS_CONN_FAULT		(1<<0)
836		#define TX_BD_FLAGS_TCP_UDP_CKSUM	(1<<1)
837		#define TX_BD_FLAGS_IP_CKSUM		(1<<2)
838		#define TX_BD_FLAGS_VLAN_TAG		(1<<3)
839		#define TX_BD_FLAGS_COAL_NOW		(1<<4)
840		#define TX_BD_FLAGS_DONT_GEN_CRC	(1<<5)
841		#define TX_BD_FLAGS_END			(1<<6)
842		#define TX_BD_FLAGS_START		(1<<7)
843		#define TX_BD_FLAGS_SW_OPTION_WORD	(0x1f<<8)
844		#define TX_BD_FLAGS_SW_FLAGS		(1<<13)
845		#define TX_BD_FLAGS_SW_SNAP		(1<<14)
846		#define TX_BD_FLAGS_SW_LSO		(1<<15)
847
848};
849
850
851/*
852 *  rx_bd definition
853 */
854struct rx_bd {
855	u32 rx_bd_haddr_hi;
856	u32 rx_bd_haddr_lo;
857	u32 rx_bd_len;
858	u32 rx_bd_flags;
859		#define RX_BD_FLAGS_NOPUSH		(1<<0)
860		#define RX_BD_FLAGS_DUMMY		(1<<1)
861		#define RX_BD_FLAGS_END			(1<<2)
862		#define RX_BD_FLAGS_START		(1<<3)
863
864};
865
866
867/*
868 *  status_block definition
869 */
870struct status_block {
871	u32 status_attn_bits;
872		#define STATUS_ATTN_BITS_LINK_STATE		(1L<<0)
873		#define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT	(1L<<1)
874		#define STATUS_ATTN_BITS_TX_BD_READ_ABORT	(1L<<2)
875		#define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT	(1L<<3)
876		#define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT	(1L<<4)
877		#define STATUS_ATTN_BITS_TX_DMA_ABORT		(1L<<5)
878		#define STATUS_ATTN_BITS_TX_PATCHUP_ABORT	(1L<<6)
879		#define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT	(1L<<7)
880		#define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT	(1L<<8)
881		#define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT	(1L<<9)
882		#define STATUS_ATTN_BITS_RX_MBUF_ABORT		(1L<<10)
883		#define STATUS_ATTN_BITS_RX_LOOKUP_ABORT	(1L<<11)
884		#define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT	(1L<<12)
885		#define STATUS_ATTN_BITS_RX_V2P_ABORT		(1L<<13)
886		#define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT	(1L<<14)
887		#define STATUS_ATTN_BITS_RX_DMA_ABORT		(1L<<15)
888		#define STATUS_ATTN_BITS_COMPLETION_ABORT	(1L<<16)
889		#define STATUS_ATTN_BITS_HOST_COALESCE_ABORT	(1L<<17)
890		#define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT	(1L<<18)
891		#define STATUS_ATTN_BITS_CONTEXT_ABORT		(1L<<19)
892		#define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT	(1L<<20)
893		#define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT	(1L<<21)
894		#define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT	(1L<<22)
895		#define STATUS_ATTN_BITS_MAC_ABORT		(1L<<23)
896		#define STATUS_ATTN_BITS_TIMER_ABORT		(1L<<24)
897		#define STATUS_ATTN_BITS_DMAE_ABORT		(1L<<25)
898		#define STATUS_ATTN_BITS_FLSH_ABORT		(1L<<26)
899		#define STATUS_ATTN_BITS_GRC_ABORT		(1L<<27)
900		#define STATUS_ATTN_BITS_PARITY_ERROR		(1L<<31)
901
902	u32 status_attn_bits_ack;
903#if defined(__BIG_ENDIAN)
904	u16 status_tx_quick_consumer_index0;
905	u16 status_tx_quick_consumer_index1;
906	u16 status_tx_quick_consumer_index2;
907	u16 status_tx_quick_consumer_index3;
908	u16 status_rx_quick_consumer_index0;
909	u16 status_rx_quick_consumer_index1;
910	u16 status_rx_quick_consumer_index2;
911	u16 status_rx_quick_consumer_index3;
912	u16 status_rx_quick_consumer_index4;
913	u16 status_rx_quick_consumer_index5;
914	u16 status_rx_quick_consumer_index6;
915	u16 status_rx_quick_consumer_index7;
916	u16 status_rx_quick_consumer_index8;
917	u16 status_rx_quick_consumer_index9;
918	u16 status_rx_quick_consumer_index10;
919	u16 status_rx_quick_consumer_index11;
920	u16 status_rx_quick_consumer_index12;
921	u16 status_rx_quick_consumer_index13;
922	u16 status_rx_quick_consumer_index14;
923	u16 status_rx_quick_consumer_index15;
924	u16 status_completion_producer_index;
925	u16 status_cmd_consumer_index;
926	u16 status_idx;
927	u16 status_unused;
928#elif defined(__LITTLE_ENDIAN)
929	u16 status_tx_quick_consumer_index1;
930	u16 status_tx_quick_consumer_index0;
931	u16 status_tx_quick_consumer_index3;
932	u16 status_tx_quick_consumer_index2;
933	u16 status_rx_quick_consumer_index1;
934	u16 status_rx_quick_consumer_index0;
935	u16 status_rx_quick_consumer_index3;
936	u16 status_rx_quick_consumer_index2;
937	u16 status_rx_quick_consumer_index5;
938	u16 status_rx_quick_consumer_index4;
939	u16 status_rx_quick_consumer_index7;
940	u16 status_rx_quick_consumer_index6;
941	u16 status_rx_quick_consumer_index9;
942	u16 status_rx_quick_consumer_index8;
943	u16 status_rx_quick_consumer_index11;
944	u16 status_rx_quick_consumer_index10;
945	u16 status_rx_quick_consumer_index13;
946	u16 status_rx_quick_consumer_index12;
947	u16 status_rx_quick_consumer_index15;
948	u16 status_rx_quick_consumer_index14;
949	u16 status_cmd_consumer_index;
950	u16 status_completion_producer_index;
951	u16 status_unused;
952	u16 status_idx;
953#endif
954};
955
956
957/*
958 *  statistics_block definition
959 */
960struct statistics_block {
961	u32 stat_IfHCInOctets_hi;
962	u32 stat_IfHCInOctets_lo;
963	u32 stat_IfHCInBadOctets_hi;
964	u32 stat_IfHCInBadOctets_lo;
965	u32 stat_IfHCOutOctets_hi;
966	u32 stat_IfHCOutOctets_lo;
967	u32 stat_IfHCOutBadOctets_hi;
968	u32 stat_IfHCOutBadOctets_lo;
969	u32 stat_IfHCInUcastPkts_hi;
970	u32 stat_IfHCInUcastPkts_lo;
971	u32 stat_IfHCInMulticastPkts_hi;
972	u32 stat_IfHCInMulticastPkts_lo;
973	u32 stat_IfHCInBroadcastPkts_hi;
974	u32 stat_IfHCInBroadcastPkts_lo;
975	u32 stat_IfHCOutUcastPkts_hi;
976	u32 stat_IfHCOutUcastPkts_lo;
977	u32 stat_IfHCOutMulticastPkts_hi;
978	u32 stat_IfHCOutMulticastPkts_lo;
979	u32 stat_IfHCOutBroadcastPkts_hi;
980	u32 stat_IfHCOutBroadcastPkts_lo;
981	u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
982	u32 stat_Dot3StatsCarrierSenseErrors;
983	u32 stat_Dot3StatsFCSErrors;
984	u32 stat_Dot3StatsAlignmentErrors;
985	u32 stat_Dot3StatsSingleCollisionFrames;
986	u32 stat_Dot3StatsMultipleCollisionFrames;
987	u32 stat_Dot3StatsDeferredTransmissions;
988	u32 stat_Dot3StatsExcessiveCollisions;
989	u32 stat_Dot3StatsLateCollisions;
990	u32 stat_EtherStatsCollisions;
991	u32 stat_EtherStatsFragments;
992	u32 stat_EtherStatsJabbers;
993	u32 stat_EtherStatsUndersizePkts;
994	u32 stat_EtherStatsOverrsizePkts;
995	u32 stat_EtherStatsPktsRx64Octets;
996	u32 stat_EtherStatsPktsRx65Octetsto127Octets;
997	u32 stat_EtherStatsPktsRx128Octetsto255Octets;
998	u32 stat_EtherStatsPktsRx256Octetsto511Octets;
999	u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
1000	u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
1001	u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
1002	u32 stat_EtherStatsPktsTx64Octets;
1003	u32 stat_EtherStatsPktsTx65Octetsto127Octets;
1004	u32 stat_EtherStatsPktsTx128Octetsto255Octets;
1005	u32 stat_EtherStatsPktsTx256Octetsto511Octets;
1006	u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
1007	u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
1008	u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
1009	u32 stat_XonPauseFramesReceived;
1010	u32 stat_XoffPauseFramesReceived;
1011	u32 stat_OutXonSent;
1012	u32 stat_OutXoffSent;
1013	u32 stat_FlowControlDone;
1014	u32 stat_MacControlFramesReceived;
1015	u32 stat_XoffStateEntered;
1016	u32 stat_IfInFramesL2FilterDiscards;
1017	u32 stat_IfInRuleCheckerDiscards;
1018	u32 stat_IfInFTQDiscards;
1019	u32 stat_IfInMBUFDiscards;
1020	u32 stat_IfInRuleCheckerP4Hit;
1021	u32 stat_CatchupInRuleCheckerDiscards;
1022	u32 stat_CatchupInFTQDiscards;
1023	u32 stat_CatchupInMBUFDiscards;
1024	u32 stat_CatchupInRuleCheckerP4Hit;
1025	u32 stat_GenStat00;
1026	u32 stat_GenStat01;
1027	u32 stat_GenStat02;
1028	u32 stat_GenStat03;
1029	u32 stat_GenStat04;
1030	u32 stat_GenStat05;
1031	u32 stat_GenStat06;
1032	u32 stat_GenStat07;
1033	u32 stat_GenStat08;
1034	u32 stat_GenStat09;
1035	u32 stat_GenStat10;
1036	u32 stat_GenStat11;
1037	u32 stat_GenStat12;
1038	u32 stat_GenStat13;
1039	u32 stat_GenStat14;
1040	u32 stat_GenStat15;
1041};
1042
1043
1044/*
1045 *  l2_fhdr definition
1046 */
1047struct l2_fhdr {
1048	u32 l2_fhdr_status;
1049		#define L2_FHDR_STATUS_RULE_CLASS	(0x7<<0)
1050		#define L2_FHDR_STATUS_RULE_P2		(1<<3)
1051		#define L2_FHDR_STATUS_RULE_P3		(1<<4)
1052		#define L2_FHDR_STATUS_RULE_P4		(1<<5)
1053		#define L2_FHDR_STATUS_L2_VLAN_TAG	(1<<6)
1054		#define L2_FHDR_STATUS_L2_LLC_SNAP	(1<<7)
1055		#define L2_FHDR_STATUS_RSS_HASH		(1<<8)
1056		#define L2_FHDR_STATUS_IP_DATAGRAM	(1<<13)
1057		#define L2_FHDR_STATUS_TCP_SEGMENT	(1<<14)
1058		#define L2_FHDR_STATUS_UDP_DATAGRAM	(1<<15)
1059
1060		#define L2_FHDR_STATUS_SPLIT		(1<<16)
1061		#define L2_FHDR_ERRORS_BAD_CRC		(1<<17)
1062		#define L2_FHDR_ERRORS_PHY_DECODE	(1<<18)
1063		#define L2_FHDR_ERRORS_ALIGNMENT	(1<<19)
1064		#define L2_FHDR_ERRORS_TOO_SHORT	(1<<20)
1065		#define L2_FHDR_ERRORS_GIANT_FRAME	(1<<21)
1066		#define L2_FHDR_ERRORS_TCP_XSUM		(1<<28)
1067		#define L2_FHDR_ERRORS_UDP_XSUM		(1<<31)
1068
1069	u32 l2_fhdr_hash;
1070#if defined(__BIG_ENDIAN)
1071	u16 l2_fhdr_pkt_len;
1072	u16 l2_fhdr_vlan_tag;
1073	u16 l2_fhdr_ip_xsum;
1074	u16 l2_fhdr_tcp_udp_xsum;
1075#elif defined(__LITTLE_ENDIAN)
1076	u16 l2_fhdr_vlan_tag;
1077	u16 l2_fhdr_pkt_len;
1078	u16 l2_fhdr_tcp_udp_xsum;
1079	u16 l2_fhdr_ip_xsum;
1080#endif
1081};
1082
1083#define BCE_L2FHDR_PRINTFB	\
1084	"\20"					\
1085	"\40UDP_XSUM_ERR"		\
1086	"\37b30"				\
1087	"\36b29"				\
1088	"\35TCP_XSUM_ERR"		\
1089	"\34b27"				\
1090	"\33b26"				\
1091	"\32b25"				\
1092	"\31b24"				\
1093	"\30b23"				\
1094	"\27b22"				\
1095	"\26GIANT_ERR"			\
1096	"\25SHORT_ERR"			\
1097	"\24ALIGN_ERR"			\
1098	"\23PHY_ERR"			\
1099	"\22CRC_ERR"			\
1100	"\21SPLIT"				\
1101	"\20UDP"				\
1102	"\17TCP"				\
1103	"\16IP"					\
1104	"\15b12"				\
1105	"\14b11"				\
1106	"\13b10"				\
1107	"\12b09"				\
1108	"\11RSS"				\
1109	"\10SNAP"				\
1110	"\07VLAN"				\
1111	"\06P4"					\
1112	"\05P3"					\
1113	"\04P2"
1114
1115
1116/*
1117 *  l2_context definition
1118 */
1119#define BCE_L2CTX_TYPE					0x00000000
1120#define BCE_L2CTX_TYPE_SIZE_L2			((0xc0/0x20)<<16)
1121#define BCE_L2CTX_TYPE_TYPE				(0xf<<28)
1122#define BCE_L2CTX_TYPE_TYPE_EMPTY		(0<<28)
1123#define BCE_L2CTX_TYPE_TYPE_L2			(1<<28)
1124
1125#define BCE_L2CTX_TX_HOST_BIDX	 		0x00000088
1126#define BCE_L2CTX_EST_NBD				0x00000088
1127#define BCE_L2CTX_CMD_TYPE				0x00000088
1128#define BCE_L2CTX_CMD_TYPE_TYPE	 		(0xf<<24)
1129#define BCE_L2CTX_CMD_TYPE_TYPE_L2		(0<<24)
1130#define BCE_L2CTX_CMD_TYPE_TYPE_TCP		(1<<24)
1131
1132#define BCE_L2CTX_TX_HOST_BSEQ			0x00000090
1133#define BCE_L2CTX_TSCH_BSEQ				0x00000094
1134#define BCE_L2CTX_TBDR_BSEQ				0x00000098
1135#define BCE_L2CTX_TBDR_BOFF				0x0000009c
1136#define BCE_L2CTX_TBDR_BIDX				0x0000009c
1137#define BCE_L2CTX_TBDR_BHADDR_HI		0x000000a0
1138#define BCE_L2CTX_TBDR_BHADDR_LO		0x000000a4
1139#define BCE_L2CTX_TXP_BOFF				0x000000a8
1140#define BCE_L2CTX_TXP_BIDX				0x000000a8
1141#define BCE_L2CTX_TXP_BSEQ				0x000000ac
1142
1143
1144/*
1145 *  l2_bd_chain_context definition
1146 */
1147#define BCE_L2CTX_BD_PRE_READ			0x00000000
1148#define BCE_L2CTX_CTX_SIZE				0x00000000
1149#define BCE_L2CTX_CTX_TYPE				0x00000000
1150#define BCE_L2CTX_LO_WATER_MARK_DEFAULT	32
1151#define BCE_L2CTX_LO_WATER_MARK_SCALE	4
1152#define BCE_L2CTX_LO_WATER_MARK_DIS		0
1153#define BCE_L2CTX_HI_WATER_MARK_SHIFT	4
1154#define BCE_L2CTX_HI_WATER_MARK_SCALE	16
1155#define BCE_L2CTX_WATER_MARKS_MSK		0x000000ff
1156
1157#define BCE_L2CTX_CTX_TYPE_SIZE_L2		((0x20/20)<<16)
1158#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE	(0xf<<28)
1159#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED	(0<<28)
1160#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE	(1<<28)
1161
1162#define BCE_L2CTX_HOST_BDIDX			0x00000004
1163#define BCE_L2CTX_HOST_BSEQ				0x00000008
1164#define BCE_L2CTX_NX_BSEQ				0x0000000c
1165#define BCE_L2CTX_NX_BDHADDR_HI			0x00000010
1166#define BCE_L2CTX_NX_BDHADDR_LO			0x00000014
1167#define BCE_L2CTX_NX_BDIDX				0x00000018
1168
1169/* Page Buffer Descriptor Index */
1170#define BCE_L2CTX_HOST_PG_BDIDX			0x00000044
1171/* SKB and Page Buffer Size */
1172#define BCE_L2CTX_PG_BUF_SIZE			0x00000048
1173/* Page Chain BD Context */
1174#define BCE_L2CTX_RBDC_KEY				0x0000004c
1175#define BCE_L2CTX_RBDC_JUMBO_KEY		0x3ffe
1176/* Page Chain Next BD Host Address */
1177#define BCE_L2CTX_NX_PG_BDHADDR_HI		0x00000050
1178#define BCE_L2CTX_NX_PG_BDHADDR_LO		0x00000054
1179#define BCE_L2CTX_NX_PG_BDIDX			0x00000058
1180
1181
1182/*
1183 *  pci_config_l definition
1184 *  offset: 0000
1185 */
1186#define BCE_PCICFG_MISC_CONFIG							0x00000068
1187#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP	 		(1L<<2)
1188#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP	 (1L<<3)
1189#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA		 (1L<<5)
1190#define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP	 (1L<<6)
1191#define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA		 (1L<<7)
1192#define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ		 (1L<<8)
1193#define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY		 (1L<<9)
1194#define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV		 (0xffL<<16)
1195#define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV		 (0xfL<<24)
1196#define BCE_PCICFG_MISC_CONFIG_ASIC_ID			 (0xfL<<28)
1197#define BCE_PCICFG_MISC_CONFIG_ASIC_REV			 (0xffffL<<16)
1198
1199#define BCE_PCICFG_MISC_STATUS				0x0000006c
1200#define BCE_PCICFG_MISC_STATUS_INTA_VALUE		 (1L<<0)
1201#define BCE_PCICFG_MISC_STATUS_32BIT_DET		 (1L<<1)
1202#define BCE_PCICFG_MISC_STATUS_M66EN			 (1L<<2)
1203#define BCE_PCICFG_MISC_STATUS_PCIX_DET		 (1L<<3)
1204#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED		 (0x3L<<4)
1205#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66		 (0L<<4)
1206#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100		 (1L<<4)
1207#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133		 (2L<<4)
1208#define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE	 (3L<<4)
1209
1210#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS		0x00000070
1211#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)
1212#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1213#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1214#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1215#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1216#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1217#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1218#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1219#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
1220#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)
1221#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)
1222#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT	 (1L<<7)
1223#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)
1224#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
1225#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)
1226#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)
1227#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)
1228#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD	 (1L<<11)
1229#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)
1230#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
1231#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)
1232#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)
1233#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)
1234#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)
1235#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)
1236#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP	 (1L<<17)
1237#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18	 (1L<<18)
1238#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET	 (1L<<19)
1239#define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED	 (0xfffL<<20)
1240
1241#define BCE_PCICFG_REG_WINDOW_ADDRESS			0x00000078
1242#define BCE_PCICFG_REG_WINDOW				0x00000080
1243#define BCE_PCICFG_INT_ACK_CMD				0x00000084
1244#define BCE_PCICFG_INT_ACK_CMD_INDEX			 (0xffffL<<0)
1245#define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID		 (1L<<16)
1246#define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM	 (1L<<17)
1247#define BCE_PCICFG_INT_ACK_CMD_MASK_INT		 (1L<<18)
1248
1249#define BCE_PCICFG_STATUS_BIT_SET_CMD			0x00000088
1250#define BCE_PCICFG_STATUS_BIT_CLEAR_CMD		0x0000008c
1251#define BCE_PCICFG_MAILBOX_QUEUE_ADDR			0x00000090
1252#define BCE_PCICFG_MAILBOX_QUEUE_DATA			0x00000094
1253
1254
1255/*
1256 *  pci_reg definition
1257 *  offset: 0x400
1258 */
1259#define BCE_PCI_GRC_WINDOW_ADDR			0x00000400
1260#define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE	 (0x3ffffL<<8)
1261
1262#define BCE_PCI_CONFIG_1				0x00000404
1263#define BCE_PCI_CONFIG_1_READ_BOUNDARY			 (0x7L<<8)
1264#define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF		 (0L<<8)
1265#define BCE_PCI_CONFIG_1_READ_BOUNDARY_16		 (1L<<8)
1266#define BCE_PCI_CONFIG_1_READ_BOUNDARY_32		 (2L<<8)
1267#define BCE_PCI_CONFIG_1_READ_BOUNDARY_64		 (3L<<8)
1268#define BCE_PCI_CONFIG_1_READ_BOUNDARY_128		 (4L<<8)
1269#define BCE_PCI_CONFIG_1_READ_BOUNDARY_256		 (5L<<8)
1270#define BCE_PCI_CONFIG_1_READ_BOUNDARY_512		 (6L<<8)
1271#define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024		 (7L<<8)
1272#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY		 (0x7L<<11)
1273#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF		 (0L<<11)
1274#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16		 (1L<<11)
1275#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32		 (2L<<11)
1276#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64		 (3L<<11)
1277#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128		 (4L<<11)
1278#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256		 (5L<<11)
1279#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512		 (6L<<11)
1280#define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024		 (7L<<11)
1281
1282#define BCE_PCI_CONFIG_2				0x00000408
1283#define BCE_PCI_CONFIG_2_BAR1_SIZE			 (0xfL<<0)
1284#define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED		 (0L<<0)
1285#define BCE_PCI_CONFIG_2_BAR1_SIZE_64K			 (1L<<0)
1286#define BCE_PCI_CONFIG_2_BAR1_SIZE_128K		 (2L<<0)
1287#define BCE_PCI_CONFIG_2_BAR1_SIZE_256K		 (3L<<0)
1288#define BCE_PCI_CONFIG_2_BAR1_SIZE_512K		 (4L<<0)
1289#define BCE_PCI_CONFIG_2_BAR1_SIZE_1M			 (5L<<0)
1290#define BCE_PCI_CONFIG_2_BAR1_SIZE_2M			 (6L<<0)
1291#define BCE_PCI_CONFIG_2_BAR1_SIZE_4M			 (7L<<0)
1292#define BCE_PCI_CONFIG_2_BAR1_SIZE_8M			 (8L<<0)
1293#define BCE_PCI_CONFIG_2_BAR1_SIZE_16M			 (9L<<0)
1294#define BCE_PCI_CONFIG_2_BAR1_SIZE_32M			 (10L<<0)
1295#define BCE_PCI_CONFIG_2_BAR1_SIZE_64M			 (11L<<0)
1296#define BCE_PCI_CONFIG_2_BAR1_SIZE_128M		 (12L<<0)
1297#define BCE_PCI_CONFIG_2_BAR1_SIZE_256M		 (13L<<0)
1298#define BCE_PCI_CONFIG_2_BAR1_SIZE_512M		 (14L<<0)
1299#define BCE_PCI_CONFIG_2_BAR1_SIZE_1G			 (15L<<0)
1300#define BCE_PCI_CONFIG_2_BAR1_64ENA			 (1L<<4)
1301#define BCE_PCI_CONFIG_2_EXP_ROM_RETRY			 (1L<<5)
1302#define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY		 (1L<<6)
1303#define BCE_PCI_CONFIG_2_FIRST_CFG_DONE		 (1L<<7)
1304#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE			 (0xffL<<8)
1305#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED		 (0L<<8)
1306#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K		 (1L<<8)
1307#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K		 (2L<<8)
1308#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K		 (3L<<8)
1309#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K		 (4L<<8)
1310#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K		 (5L<<8)
1311#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K		 (6L<<8)
1312#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K		 (7L<<8)
1313#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K		 (8L<<8)
1314#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K		 (9L<<8)
1315#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K		 (10L<<8)
1316#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M		 (11L<<8)
1317#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M		 (12L<<8)
1318#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M		 (13L<<8)
1319#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M		 (14L<<8)
1320#define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M		 (15L<<8)
1321#define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT		 (0x1fL<<16)
1322#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT		 (0x3L<<21)
1323#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512		 (0L<<21)
1324#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K		 (1L<<21)
1325#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K		 (2L<<21)
1326#define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K		 (3L<<21)
1327#define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR		 (1L<<23)
1328#define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT		 (1L<<24)
1329#define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT		 (1L<<25)
1330
1331#define BCE_PCI_CONFIG_3				0x0000040c
1332#define BCE_PCI_CONFIG_3_STICKY_BYTE			 (0xffL<<0)
1333#define BCE_PCI_CONFIG_3_FORCE_PME			 (1L<<24)
1334#define BCE_PCI_CONFIG_3_PME_STATUS			 (1L<<25)
1335#define BCE_PCI_CONFIG_3_PME_ENABLE			 (1L<<26)
1336#define BCE_PCI_CONFIG_3_PM_STATE			 (0x3L<<27)
1337#define BCE_PCI_CONFIG_3_VAUX_PRESET			 (1L<<30)
1338#define BCE_PCI_CONFIG_3_PCI_POWER			 (1L<<31)
1339
1340#define BCE_PCI_PM_DATA_A				0x00000410
1341#define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG		 (0xffL<<0)
1342#define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG		 (0xffL<<8)
1343#define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG		 (0xffL<<16)
1344#define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG		 (0xffL<<24)
1345
1346#define BCE_PCI_PM_DATA_B				0x00000414
1347#define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG		 (0xffL<<0)
1348#define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG		 (0xffL<<8)
1349#define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG		 (0xffL<<16)
1350#define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG		 (0xffL<<24)
1351
1352#define BCE_PCI_SWAP_DIAG0				0x00000418
1353#define BCE_PCI_SWAP_DIAG1				0x0000041c
1354#define BCE_PCI_EXP_ROM_ADDR				0x00000420
1355#define BCE_PCI_EXP_ROM_ADDR_ADDRESS			 (0x3fffffL<<2)
1356#define BCE_PCI_EXP_ROM_ADDR_REQ			 (1L<<31)
1357
1358#define BCE_PCI_EXP_ROM_DATA				0x00000424
1359#define BCE_PCI_VPD_INTF				0x00000428
1360#define BCE_PCI_VPD_INTF_INTF_REQ			 (1L<<0)
1361
1362#define BCE_PCI_VPD_ADDR_FLAG				0x0000042c
1363#define BCE_PCI_VPD_ADDR_FLAG_ADDRESS			 (0x1fff<<2)
1364#define BCE_PCI_VPD_ADDR_FLAG_WR			 (1<<15)
1365
1366#define BCE_PCI_VPD_DATA				0x00000430
1367#define BCE_PCI_ID_VAL1				0x00000434
1368#define BCE_PCI_ID_VAL1_DEVICE_ID			 (0xffffL<<0)
1369#define BCE_PCI_ID_VAL1_VENDOR_ID			 (0xffffL<<16)
1370
1371#define BCE_PCI_ID_VAL2				0x00000438
1372#define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID		 (0xffffL<<0)
1373#define BCE_PCI_ID_VAL2_SUBSYSTEM_ID			 (0xffffL<<16)
1374
1375#define BCE_PCI_ID_VAL3				0x0000043c
1376#define BCE_PCI_ID_VAL3_CLASS_CODE			 (0xffffffL<<0)
1377#define BCE_PCI_ID_VAL3_REVISION_ID			 (0xffL<<24)
1378
1379#define BCE_PCI_ID_VAL4				0x00000440
1380#define BCE_PCI_ID_VAL4_CAP_ENA			 (0xfL<<0)
1381#define BCE_PCI_ID_VAL4_CAP_ENA_0			 (0L<<0)
1382#define BCE_PCI_ID_VAL4_CAP_ENA_1			 (1L<<0)
1383#define BCE_PCI_ID_VAL4_CAP_ENA_2			 (2L<<0)
1384#define BCE_PCI_ID_VAL4_CAP_ENA_3			 (3L<<0)
1385#define BCE_PCI_ID_VAL4_CAP_ENA_4			 (4L<<0)
1386#define BCE_PCI_ID_VAL4_CAP_ENA_5			 (5L<<0)
1387#define BCE_PCI_ID_VAL4_CAP_ENA_6			 (6L<<0)
1388#define BCE_PCI_ID_VAL4_CAP_ENA_7			 (7L<<0)
1389#define BCE_PCI_ID_VAL4_CAP_ENA_8			 (8L<<0)
1390#define BCE_PCI_ID_VAL4_CAP_ENA_9			 (9L<<0)
1391#define BCE_PCI_ID_VAL4_CAP_ENA_10			 (10L<<0)
1392#define BCE_PCI_ID_VAL4_CAP_ENA_11			 (11L<<0)
1393#define BCE_PCI_ID_VAL4_CAP_ENA_12			 (12L<<0)
1394#define BCE_PCI_ID_VAL4_CAP_ENA_13			 (13L<<0)
1395#define BCE_PCI_ID_VAL4_CAP_ENA_14			 (14L<<0)
1396#define BCE_PCI_ID_VAL4_CAP_ENA_15			 (15L<<0)
1397#define BCE_PCI_ID_VAL4_PM_SCALE_PRG			 (0x3L<<6)
1398#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0			 (0L<<6)
1399#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1			 (1L<<6)
1400#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2			 (2L<<6)
1401#define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3			 (3L<<6)
1402#define BCE_PCI_ID_VAL4_MSI_LIMIT			 (0x7L<<9)
1403#define BCE_PCI_ID_VAL4_MSI_ADVERTIZE			 (0x7L<<12)
1404#define BCE_PCI_ID_VAL4_MSI_ENABLE			 (1L<<15)
1405#define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE		 (1L<<16)
1406#define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE		 (1L<<17)
1407#define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE		 (0x3L<<21)
1408#define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE			 (0x7L<<23)
1409#define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE		 (0x7L<<26)
1410
1411#define BCE_PCI_ID_VAL5				0x00000444
1412#define BCE_PCI_ID_VAL5_D1_SUPPORT			 (1L<<0)
1413#define BCE_PCI_ID_VAL5_D2_SUPPORT			 (1L<<1)
1414#define BCE_PCI_ID_VAL5_PME_IN_D0			 (1L<<2)
1415#define BCE_PCI_ID_VAL5_PME_IN_D1			 (1L<<3)
1416#define BCE_PCI_ID_VAL5_PME_IN_D2			 (1L<<4)
1417#define BCE_PCI_ID_VAL5_PME_IN_D3_HOT			 (1L<<5)
1418
1419#define BCE_PCI_PCIX_EXTENDED_STATUS			0x00000448
1420#define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP		 (1L<<8)
1421#define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST	 (1L<<9)
1422#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS	 (0xfL<<16)
1423#define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX	 (0xffL<<24)
1424
1425#define BCE_PCI_ID_VAL6				0x0000044c
1426#define BCE_PCI_ID_VAL6_MAX_LAT			 (0xffL<<0)
1427#define BCE_PCI_ID_VAL6_MIN_GNT			 (0xffL<<8)
1428#define BCE_PCI_ID_VAL6_BIST				 (0xffL<<16)
1429
1430#define BCE_PCI_MSI_DATA				0x00000450
1431#define BCE_PCI_MSI_DATA_PCI_MSI_DATA			 (0xffffL<<0)
1432
1433#define BCE_PCI_MSI_ADDR_H				0x00000454
1434#define BCE_PCI_MSI_ADDR_L				0x00000458
1435
1436
1437/*
1438 *  misc_reg definition
1439 *  offset: 0x800
1440 */
1441#define BCE_MISC_COMMAND				0x00000800
1442#define BCE_MISC_COMMAND_ENABLE_ALL			 (1L<<0)
1443#define BCE_MISC_COMMAND_DISABLE_ALL			 (1L<<1)
1444#define BCE_MISC_COMMAND_CORE_RESET			 (1L<<4)
1445#define BCE_MISC_COMMAND_HARD_RESET			 (1L<<5)
1446#define BCE_MISC_COMMAND_PAR_ERROR			 (1L<<8)
1447#define BCE_MISC_COMMAND_PAR_ERR_RAM			 (0x7fL<<16)
1448
1449#define BCE_MISC_CFG					0x00000804
1450#define BCE_MISC_CFG_PCI_GRC_TMOUT			 (1L<<0)
1451#define BCE_MISC_CFG_NVM_WR_EN				 (0x3L<<1)
1452#define BCE_MISC_CFG_NVM_WR_EN_PROTECT			 (0L<<1)
1453#define BCE_MISC_CFG_NVM_WR_EN_PCI			 (1L<<1)
1454#define BCE_MISC_CFG_NVM_WR_EN_ALLOW			 (2L<<1)
1455#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2			 (3L<<1)
1456#define BCE_MISC_CFG_BIST_EN				 (1L<<3)
1457#define BCE_MISC_CFG_CK25_OUT_ALT_SRC			 (1L<<4)
1458#define BCE_MISC_CFG_BYPASS_BSCAN			 (1L<<5)
1459#define BCE_MISC_CFG_BYPASS_EJTAG			 (1L<<6)
1460#define BCE_MISC_CFG_CLK_CTL_OVERRIDE			 (1L<<7)
1461#define BCE_MISC_CFG_LEDMODE				 (0x3L<<8)
1462#define BCE_MISC_CFG_LEDMODE_MAC			 (0L<<8)
1463#define BCE_MISC_CFG_LEDMODE_GPHY1			 (1L<<8)
1464#define BCE_MISC_CFG_LEDMODE_GPHY2			 (2L<<8)
1465
1466#define BCE_MISC_ID					0x00000808
1467#define BCE_MISC_ID_BOND_ID				 (0xfL<<0)
1468#define BCE_MISC_ID_CHIP_METAL				 (0xffL<<4)
1469#define BCE_MISC_ID_CHIP_REV				 (0xfL<<12)
1470#define BCE_MISC_ID_CHIP_NUM				 (0xffffL<<16)
1471
1472#define BCE_MISC_ENABLE_STATUS_BITS			0x0000080c
1473#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1474#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1475#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1476#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1477#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE	 (1L<<4)
1478#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1479#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1480#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1481#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1482#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE	 (1L<<9)
1483#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1484#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1485#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE	 (1L<<12)
1486#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1487#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1488#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE	 (1L<<15)
1489#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1490#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE	 (1L<<17)
1491#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE	 (1L<<18)
1492#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1493#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1494#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE	 (1L<<21)
1495#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1496#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1497#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1498#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE	 (1L<<25)
1499#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1500#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE		 (1L<<27)
1501
1502#define BCE_MISC_ENABLE_SET_BITS			0x00000810
1503#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1504#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1505#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1506#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1507#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE		 (1L<<4)
1508#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1509#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1510#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1511#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1512#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE		 (1L<<9)
1513#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1514#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1515#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE	 (1L<<12)
1516#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1517#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1518#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE		 (1L<<15)
1519#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1520#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE		 (1L<<17)
1521#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE	 (1L<<18)
1522#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1523#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1524#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE	 (1L<<21)
1525#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1526#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1527#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1528#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE		 (1L<<25)
1529#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1530#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE		 (1L<<27)
1531
1532#define BCE_MISC_ENABLE_CLR_BITS			0x00000814
1533#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1534#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1535#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1536#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1537#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE		 (1L<<4)
1538#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1539#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1540#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1541#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1542#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE		 (1L<<9)
1543#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1544#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1545#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE	 (1L<<12)
1546#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1547#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1548#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE		 (1L<<15)
1549#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1550#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE		 (1L<<17)
1551#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE	 (1L<<18)
1552#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1553#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1554#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE	 (1L<<21)
1555#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1556#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1557#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1558#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE		 (1L<<25)
1559#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1560#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE		 (1L<<27)
1561
1562#define BCE_MISC_CLOCK_CONTROL_BITS			0x00000818
1563#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)
1564#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1565#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1566#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1567#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1568#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1569#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1570#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1571#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
1572#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)
1573#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE	 (1L<<6)
1574#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT	 (1L<<7)
1575#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)
1576#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
1577#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12	 (1L<<8)
1578#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6	 (2L<<8)
1579#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62	 (4L<<8)
1580#define BCE_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD		 (1L<<11)
1581#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)
1582#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
1583#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80	 (1L<<12)
1584#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50	 (2L<<12)
1585#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40	 (4L<<12)
1586#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25	 (8L<<12)
1587#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP	 (1L<<16)
1588#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP	 (1L<<17)
1589#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18	 (1L<<18)
1590#define BCE_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET	 (1L<<19)
1591#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED		 (0xfffL<<20)
1592
1593#define BCE_MISC_GPIO					0x0000081c
1594#define BCE_MISC_GPIO_VALUE				 (0xffL<<0)
1595#define BCE_MISC_GPIO_SET				 (0xffL<<8)
1596#define BCE_MISC_GPIO_CLR				 (0xffL<<16)
1597#define BCE_MISC_GPIO_FLOAT				 (0xffL<<24)
1598
1599#define BCE_MISC_GPIO_INT				0x00000820
1600#define BCE_MISC_GPIO_INT_INT_STATE			 (0xfL<<0)
1601#define BCE_MISC_GPIO_INT_OLD_VALUE			 (0xfL<<8)
1602#define BCE_MISC_GPIO_INT_OLD_SET			 (0xfL<<16)
1603#define BCE_MISC_GPIO_INT_OLD_CLR			 (0xfL<<24)
1604
1605#define BCE_MISC_CONFIG_LFSR				0x00000824
1606#define BCE_MISC_CONFIG_LFSR_DIV			 (0xffffL<<0)
1607
1608#define BCE_MISC_LFSR_MASK_BITS			0x00000828
1609#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1610#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE	 (1L<<1)
1611#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE	 (1L<<2)
1612#define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE	 (1L<<3)
1613#define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE		 (1L<<4)
1614#define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE	 (1L<<5)
1615#define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE	 (1L<<6)
1616#define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE	 (1L<<7)
1617#define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE	 (1L<<8)
1618#define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE		 (1L<<9)
1619#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE	 (1L<<10)
1620#define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE	 (1L<<11)
1621#define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE		 (1L<<12)
1622#define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE	 (1L<<13)
1623#define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE	 (1L<<14)
1624#define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE		 (1L<<15)
1625#define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE	 (1L<<16)
1626#define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE		 (1L<<17)
1627#define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE	 (1L<<18)
1628#define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE	 (1L<<19)
1629#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE	 (1L<<20)
1630#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE		 (1L<<21)
1631#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE	 (1L<<22)
1632#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE	 (1L<<23)
1633#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE	 (1L<<24)
1634#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE		 (1L<<25)
1635#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE	 (1L<<26)
1636#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE		 (1L<<27)
1637
1638#define BCE_MISC_ARB_REQ0				0x0000082c
1639#define BCE_MISC_ARB_REQ1				0x00000830
1640#define BCE_MISC_ARB_REQ2				0x00000834
1641#define BCE_MISC_ARB_REQ3				0x00000838
1642#define BCE_MISC_ARB_REQ4				0x0000083c
1643#define BCE_MISC_ARB_FREE0				0x00000840
1644#define BCE_MISC_ARB_FREE1				0x00000844
1645#define BCE_MISC_ARB_FREE2				0x00000848
1646#define BCE_MISC_ARB_FREE3				0x0000084c
1647#define BCE_MISC_ARB_FREE4				0x00000850
1648#define BCE_MISC_ARB_REQ_STATUS0			0x00000854
1649#define BCE_MISC_ARB_REQ_STATUS1			0x00000858
1650#define BCE_MISC_ARB_REQ_STATUS2			0x0000085c
1651#define BCE_MISC_ARB_REQ_STATUS3			0x00000860
1652#define BCE_MISC_ARB_REQ_STATUS4			0x00000864
1653#define BCE_MISC_ARB_GNT0				0x00000868
1654#define BCE_MISC_ARB_GNT0_0				 (0x7L<<0)
1655#define BCE_MISC_ARB_GNT0_1				 (0x7L<<4)
1656#define BCE_MISC_ARB_GNT0_2				 (0x7L<<8)
1657#define BCE_MISC_ARB_GNT0_3				 (0x7L<<12)
1658#define BCE_MISC_ARB_GNT0_4				 (0x7L<<16)
1659#define BCE_MISC_ARB_GNT0_5				 (0x7L<<20)
1660#define BCE_MISC_ARB_GNT0_6				 (0x7L<<24)
1661#define BCE_MISC_ARB_GNT0_7				 (0x7L<<28)
1662
1663#define BCE_MISC_ARB_GNT1				0x0000086c
1664#define BCE_MISC_ARB_GNT1_8				 (0x7L<<0)
1665#define BCE_MISC_ARB_GNT1_9				 (0x7L<<4)
1666#define BCE_MISC_ARB_GNT1_10				 (0x7L<<8)
1667#define BCE_MISC_ARB_GNT1_11				 (0x7L<<12)
1668#define BCE_MISC_ARB_GNT1_12				 (0x7L<<16)
1669#define BCE_MISC_ARB_GNT1_13				 (0x7L<<20)
1670#define BCE_MISC_ARB_GNT1_14				 (0x7L<<24)
1671#define BCE_MISC_ARB_GNT1_15				 (0x7L<<28)
1672
1673#define BCE_MISC_ARB_GNT2				0x00000870
1674#define BCE_MISC_ARB_GNT2_16				 (0x7L<<0)
1675#define BCE_MISC_ARB_GNT2_17				 (0x7L<<4)
1676#define BCE_MISC_ARB_GNT2_18				 (0x7L<<8)
1677#define BCE_MISC_ARB_GNT2_19				 (0x7L<<12)
1678#define BCE_MISC_ARB_GNT2_20				 (0x7L<<16)
1679#define BCE_MISC_ARB_GNT2_21				 (0x7L<<20)
1680#define BCE_MISC_ARB_GNT2_22				 (0x7L<<24)
1681#define BCE_MISC_ARB_GNT2_23				 (0x7L<<28)
1682
1683#define BCE_MISC_ARB_GNT3				0x00000874
1684#define BCE_MISC_ARB_GNT3_24				 (0x7L<<0)
1685#define BCE_MISC_ARB_GNT3_25				 (0x7L<<4)
1686#define BCE_MISC_ARB_GNT3_26				 (0x7L<<8)
1687#define BCE_MISC_ARB_GNT3_27				 (0x7L<<12)
1688#define BCE_MISC_ARB_GNT3_28				 (0x7L<<16)
1689#define BCE_MISC_ARB_GNT3_29				 (0x7L<<20)
1690#define BCE_MISC_ARB_GNT3_30				 (0x7L<<24)
1691#define BCE_MISC_ARB_GNT3_31				 (0x7L<<28)
1692
1693#define BCE_MISC_PRBS_CONTROL				0x00000878
1694#define BCE_MISC_PRBS_CONTROL_EN			 (1L<<0)
1695#define BCE_MISC_PRBS_CONTROL_RSTB			 (1L<<1)
1696#define BCE_MISC_PRBS_CONTROL_INV			 (1L<<2)
1697#define BCE_MISC_PRBS_CONTROL_ERR_CLR			 (1L<<3)
1698#define BCE_MISC_PRBS_CONTROL_ORDER			 (0x3L<<4)
1699#define BCE_MISC_PRBS_CONTROL_ORDER_7TH		 (0L<<4)
1700#define BCE_MISC_PRBS_CONTROL_ORDER_15TH		 (1L<<4)
1701#define BCE_MISC_PRBS_CONTROL_ORDER_23RD		 (2L<<4)
1702#define BCE_MISC_PRBS_CONTROL_ORDER_31ST		 (3L<<4)
1703
1704#define BCE_MISC_PRBS_STATUS				0x0000087c
1705#define BCE_MISC_PRBS_STATUS_LOCK			 (1L<<0)
1706#define BCE_MISC_PRBS_STATUS_STKY			 (1L<<1)
1707#define BCE_MISC_PRBS_STATUS_ERRORS			 (0x3fffL<<2)
1708#define BCE_MISC_PRBS_STATUS_STATE			 (0xfL<<16)
1709
1710#define BCE_MISC_SM_ASF_CONTROL			0x00000880
1711#define BCE_MISC_SM_ASF_CONTROL_ASF_RST		 (1L<<0)
1712#define BCE_MISC_SM_ASF_CONTROL_TSC_EN			 (1L<<1)
1713#define BCE_MISC_SM_ASF_CONTROL_WG_TO			 (1L<<2)
1714#define BCE_MISC_SM_ASF_CONTROL_HB_TO			 (1L<<3)
1715#define BCE_MISC_SM_ASF_CONTROL_PA_TO			 (1L<<4)
1716#define BCE_MISC_SM_ASF_CONTROL_PL_TO			 (1L<<5)
1717#define BCE_MISC_SM_ASF_CONTROL_RT_TO			 (1L<<6)
1718#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT		 (1L<<7)
1719#define BCE_MISC_SM_ASF_CONTROL_RES			 (0xfL<<8)
1720#define BCE_MISC_SM_ASF_CONTROL_SMB_EN			 (1L<<12)
1721#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN		 (1L<<13)
1722#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT	 (1L<<14)
1723#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD		 (1L<<15)
1724#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1		 (0x3fL<<16)
1725#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2		 (0x3fL<<24)
1726#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0	 (1L<<30)
1727#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN		 (1L<<31)
1728
1729#define BCE_MISC_SMB_IN				0x00000884
1730#define BCE_MISC_SMB_IN_DAT_IN				 (0xffL<<0)
1731#define BCE_MISC_SMB_IN_RDY				 (1L<<8)
1732#define BCE_MISC_SMB_IN_DONE				 (1L<<9)
1733#define BCE_MISC_SMB_IN_FIRSTBYTE			 (1L<<10)
1734#define BCE_MISC_SMB_IN_STATUS				 (0x7L<<11)
1735#define BCE_MISC_SMB_IN_STATUS_OK			 (0x0L<<11)
1736#define BCE_MISC_SMB_IN_STATUS_PEC			 (0x1L<<11)
1737#define BCE_MISC_SMB_IN_STATUS_OFLOW			 (0x2L<<11)
1738#define BCE_MISC_SMB_IN_STATUS_STOP			 (0x3L<<11)
1739#define BCE_MISC_SMB_IN_STATUS_TIMEOUT			 (0x4L<<11)
1740
1741#define BCE_MISC_SMB_OUT				0x00000888
1742#define BCE_MISC_SMB_OUT_DAT_OUT			 (0xffL<<0)
1743#define BCE_MISC_SMB_OUT_RDY				 (1L<<8)
1744#define BCE_MISC_SMB_OUT_START				 (1L<<9)
1745#define BCE_MISC_SMB_OUT_LAST				 (1L<<10)
1746#define BCE_MISC_SMB_OUT_ACC_TYPE			 (1L<<11)
1747#define BCE_MISC_SMB_OUT_ENB_PEC			 (1L<<12)
1748#define BCE_MISC_SMB_OUT_GET_RX_LEN			 (1L<<13)
1749#define BCE_MISC_SMB_OUT_SMB_READ_LEN			 (0x3fL<<14)
1750#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS		 (0xfL<<20)
1751#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK		 (0L<<20)
1752#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK	 (1L<<20)
1753#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK	 (9L<<20)
1754#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW		 (2L<<20)
1755#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP		 (3L<<20)
1756#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT	 (4L<<20)
1757#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST	 (5L<<20)
1758#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST	 (0xdL<<20)
1759#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK		 (0x6L<<20)
1760#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE		 (1L<<24)
1761#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN		 (1L<<25)
1762#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN		 (1L<<26)
1763#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN		 (1L<<27)
1764#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN		 (1L<<28)
1765
1766#define BCE_MISC_SMB_WATCHDOG				0x0000088c
1767#define BCE_MISC_SMB_WATCHDOG_WATCHDOG			 (0xffffL<<0)
1768
1769#define BCE_MISC_SMB_HEARTBEAT				0x00000890
1770#define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT		 (0xffffL<<0)
1771
1772#define BCE_MISC_SMB_POLL_ASF				0x00000894
1773#define BCE_MISC_SMB_POLL_ASF_POLL_ASF			 (0xffffL<<0)
1774
1775#define BCE_MISC_SMB_POLL_LEGACY			0x00000898
1776#define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY		 (0xffffL<<0)
1777
1778#define BCE_MISC_SMB_RETRAN				0x0000089c
1779#define BCE_MISC_SMB_RETRAN_RETRAN			 (0xffL<<0)
1780
1781#define BCE_MISC_SMB_TIMESTAMP				0x000008a0
1782#define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP		 (0xffffffffL<<0)
1783
1784#define BCE_MISC_PERR_ENA0				0x000008a4
1785#define BCE_MISC_PERR_ENA0_COM_MISC_CTXC		 (1L<<0)
1786#define BCE_MISC_PERR_ENA0_COM_MISC_REGF		 (1L<<1)
1787#define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD		 (1L<<2)
1788#define BCE_MISC_PERR_ENA0_CP_MISC_CTXC		 (1L<<3)
1789#define BCE_MISC_PERR_ENA0_CP_MISC_REGF		 (1L<<4)
1790#define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD		 (1L<<5)
1791#define BCE_MISC_PERR_ENA0_CS_MISC_TMEM		 (1L<<6)
1792#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0		 (1L<<7)
1793#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1		 (1L<<8)
1794#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2		 (1L<<9)
1795#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3		 (1L<<10)
1796#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4		 (1L<<11)
1797#define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5		 (1L<<12)
1798#define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL		 (1L<<13)
1799#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0		 (1L<<14)
1800#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1		 (1L<<15)
1801#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2		 (1L<<16)
1802#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3		 (1L<<17)
1803#define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4		 (1L<<18)
1804#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0		 (1L<<19)
1805#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1		 (1L<<20)
1806#define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2		 (1L<<21)
1807#define BCE_MISC_PERR_ENA0_HC_MISC_DMA			 (1L<<22)
1808#define BCE_MISC_PERR_ENA0_MCP_MISC_REGF		 (1L<<23)
1809#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD		 (1L<<24)
1810#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX			 (1L<<25)
1811#define BCE_MISC_PERR_ENA0_RBDC_MISC			 (1L<<26)
1812#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB		 (1L<<27)
1813#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR		 (1L<<28)
1814#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC		 (1L<<29)
1815#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM		 (1L<<30)
1816#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS		 (1L<<31)
1817
1818#define BCE_MISC_PERR_ENA1				0x000008a8
1819#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS		 (1L<<0)
1820#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM		 (1L<<1)
1821#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM		 (1L<<2)
1822#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC		 (1L<<3)
1823#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF		 (1L<<4)
1824#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD		 (1L<<5)
1825#define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC		 (1L<<6)
1826#define BCE_MISC_PERR_ENA1_TBDC_MISC			 (1L<<7)
1827#define BCE_MISC_PERR_ENA1_TDMA_MISC			 (1L<<8)
1828#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0		 (1L<<9)
1829#define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1		 (1L<<10)
1830#define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF		 (1L<<11)
1831#define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD		 (1L<<12)
1832#define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB		 (1L<<13)
1833#define BCE_MISC_PERR_ENA1_TSCH_MISC_LR		 (1L<<14)
1834#define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC		 (1L<<15)
1835#define BCE_MISC_PERR_ENA1_TXP_MISC_REGF		 (1L<<16)
1836#define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD		 (1L<<17)
1837#define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX		 (1L<<18)
1838#define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX		 (1L<<19)
1839#define BCE_MISC_PERR_ENA1_UMP_MISC_RX			 (1L<<20)
1840#define BCE_MISC_PERR_ENA1_UMP_MISC_TX			 (1L<<21)
1841#define BCE_MISC_PERR_ENA1_RDMAQ_MISC			 (1L<<22)
1842#define BCE_MISC_PERR_ENA1_CSQ_MISC			 (1L<<23)
1843#define BCE_MISC_PERR_ENA1_CPQ_MISC			 (1L<<24)
1844#define BCE_MISC_PERR_ENA1_MCPQ_MISC			 (1L<<25)
1845#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC			 (1L<<26)
1846#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC			 (1L<<27)
1847#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC			 (1L<<28)
1848#define BCE_MISC_PERR_ENA1_RXPQ_MISC			 (1L<<29)
1849#define BCE_MISC_PERR_ENA1_RXPCQ_MISC			 (1L<<30)
1850#define BCE_MISC_PERR_ENA1_RLUPQ_MISC			 (1L<<31)
1851
1852#define BCE_MISC_PERR_ENA2				0x000008ac
1853#define BCE_MISC_PERR_ENA2_COMQ_MISC			 (1L<<0)
1854#define BCE_MISC_PERR_ENA2_COMXQ_MISC			 (1L<<1)
1855#define BCE_MISC_PERR_ENA2_COMTQ_MISC			 (1L<<2)
1856#define BCE_MISC_PERR_ENA2_TSCHQ_MISC			 (1L<<3)
1857#define BCE_MISC_PERR_ENA2_TBDRQ_MISC			 (1L<<4)
1858#define BCE_MISC_PERR_ENA2_TXPQ_MISC			 (1L<<5)
1859#define BCE_MISC_PERR_ENA2_TDMAQ_MISC			 (1L<<6)
1860#define BCE_MISC_PERR_ENA2_TPATQ_MISC			 (1L<<7)
1861#define BCE_MISC_PERR_ENA2_TASQ_MISC			 (1L<<8)
1862
1863#define BCE_MISC_DEBUG_VECTOR_SEL			0x000008b0
1864#define BCE_MISC_DEBUG_VECTOR_SEL_0			 (0xfffL<<0)
1865#define BCE_MISC_DEBUG_VECTOR_SEL_1			 (0xfffL<<12)
1866
1867#define BCE_MISC_VREG_CONTROL				0x000008b4
1868#define BCE_MISC_VREG_CONTROL_1_2			 (0xfL<<0)
1869#define BCE_MISC_VREG_CONTROL_2_5			 (0xfL<<4)
1870
1871#define BCE_MISC_FINAL_CLK_CTL_VAL			0x000008b8
1872#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL	 (0x3ffffffL<<6)
1873
1874#define BCE_MISC_UNUSED0				0x000008bc
1875
1876
1877/*
1878 *  nvm_reg definition
1879 *  offset: 0x6400
1880 */
1881#define BCE_NVM_COMMAND				0x00006400
1882#define BCE_NVM_COMMAND_RST				 (1L<<0)
1883#define BCE_NVM_COMMAND_DONE				 (1L<<3)
1884#define BCE_NVM_COMMAND_DOIT				 (1L<<4)
1885#define BCE_NVM_COMMAND_WR				 (1L<<5)
1886#define BCE_NVM_COMMAND_ERASE				 (1L<<6)
1887#define BCE_NVM_COMMAND_FIRST				 (1L<<7)
1888#define BCE_NVM_COMMAND_LAST				 (1L<<8)
1889#define BCE_NVM_COMMAND_WREN				 (1L<<16)
1890#define BCE_NVM_COMMAND_WRDI				 (1L<<17)
1891#define BCE_NVM_COMMAND_EWSR				 (1L<<18)
1892#define BCE_NVM_COMMAND_WRSR				 (1L<<19)
1893
1894#define BCE_NVM_STATUS					0x00006404
1895#define BCE_NVM_STATUS_PI_FSM_STATE			 (0xfL<<0)
1896#define BCE_NVM_STATUS_EE_FSM_STATE			 (0xfL<<4)
1897#define BCE_NVM_STATUS_EQ_FSM_STATE			 (0xfL<<8)
1898
1899#define BCE_NVM_WRITE					0x00006408
1900#define BCE_NVM_WRITE_NVM_WRITE_VALUE			 (0xffffffffL<<0)
1901#define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG		 (0L<<0)
1902#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK		 (1L<<0)
1903#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA		 (2L<<0)
1904#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK		 (4L<<0)
1905#define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B		 (8L<<0)
1906#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO		 (16L<<0)
1907#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI		 (32L<<0)
1908
1909#define BCE_NVM_ADDR					0x0000640c
1910#define BCE_NVM_ADDR_NVM_ADDR_VALUE			 (0xffffffL<<0)
1911#define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG		 (0L<<0)
1912#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK		 (1L<<0)
1913#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA		 (2L<<0)
1914#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK		 (4L<<0)
1915#define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B		 (8L<<0)
1916#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO			 (16L<<0)
1917#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI			 (32L<<0)
1918
1919#define BCE_NVM_READ					0x00006410
1920#define BCE_NVM_READ_NVM_READ_VALUE			 (0xffffffffL<<0)
1921#define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG		 (0L<<0)
1922#define BCE_NVM_READ_NVM_READ_VALUE_EECLK		 (1L<<0)
1923#define BCE_NVM_READ_NVM_READ_VALUE_EEDATA		 (2L<<0)
1924#define BCE_NVM_READ_NVM_READ_VALUE_SCLK		 (4L<<0)
1925#define BCE_NVM_READ_NVM_READ_VALUE_CS_B		 (8L<<0)
1926#define BCE_NVM_READ_NVM_READ_VALUE_SO			 (16L<<0)
1927#define BCE_NVM_READ_NVM_READ_VALUE_SI			 (32L<<0)
1928
1929#define BCE_NVM_CFG1					0x00006414
1930#define BCE_NVM_CFG1_FLASH_MODE			 (1L<<0)
1931#define BCE_NVM_CFG1_BUFFER_MODE			 (1L<<1)
1932#define BCE_NVM_CFG1_PASS_MODE				 (1L<<2)
1933#define BCE_NVM_CFG1_BITBANG_MODE			 (1L<<3)
1934#define BCE_NVM_CFG1_STATUS_BIT			 (0x7L<<4)
1935#define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY		 (0L<<4)
1936#define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY		 (7L<<4)
1937#define BCE_NVM_CFG1_SPI_CLK_DIV			 (0xfL<<7)
1938#define BCE_NVM_CFG1_SEE_CLK_DIV			 (0x7ffL<<11)
1939#define BCE_NVM_CFG1_PROTECT_MODE			 (1L<<24)
1940#define BCE_NVM_CFG1_FLASH_SIZE			 (1L<<25)
1941#define BCE_NVM_CFG1_COMPAT_BYPASSS			 (1L<<31)
1942
1943#define BCE_NVM_CFG2					0x00006418
1944#define BCE_NVM_CFG2_ERASE_CMD				 (0xffL<<0)
1945#define BCE_NVM_CFG2_DUMMY				 (0xffL<<8)
1946#define BCE_NVM_CFG2_STATUS_CMD			 (0xffL<<16)
1947
1948#define BCE_NVM_CFG3					0x0000641c
1949#define BCE_NVM_CFG3_BUFFER_RD_CMD			 (0xffL<<0)
1950#define BCE_NVM_CFG3_WRITE_CMD				 (0xffL<<8)
1951#define BCE_NVM_CFG3_BUFFER_WRITE_CMD			 (0xffL<<16)
1952#define BCE_NVM_CFG3_READ_CMD				 (0xffL<<24)
1953
1954#define BCE_NVM_SW_ARB					0x00006420
1955#define BCE_NVM_SW_ARB_ARB_REQ_SET0			 (1L<<0)
1956#define BCE_NVM_SW_ARB_ARB_REQ_SET1			 (1L<<1)
1957#define BCE_NVM_SW_ARB_ARB_REQ_SET2			 (1L<<2)
1958#define BCE_NVM_SW_ARB_ARB_REQ_SET3			 (1L<<3)
1959#define BCE_NVM_SW_ARB_ARB_REQ_CLR0			 (1L<<4)
1960#define BCE_NVM_SW_ARB_ARB_REQ_CLR1			 (1L<<5)
1961#define BCE_NVM_SW_ARB_ARB_REQ_CLR2			 (1L<<6)
1962#define BCE_NVM_SW_ARB_ARB_REQ_CLR3			 (1L<<7)
1963#define BCE_NVM_SW_ARB_ARB_ARB0			 (1L<<8)
1964#define BCE_NVM_SW_ARB_ARB_ARB1			 (1L<<9)
1965#define BCE_NVM_SW_ARB_ARB_ARB2			 (1L<<10)
1966#define BCE_NVM_SW_ARB_ARB_ARB3			 (1L<<11)
1967#define BCE_NVM_SW_ARB_REQ0				 (1L<<12)
1968#define BCE_NVM_SW_ARB_REQ1				 (1L<<13)
1969#define BCE_NVM_SW_ARB_REQ2				 (1L<<14)
1970#define BCE_NVM_SW_ARB_REQ3				 (1L<<15)
1971
1972#define BCE_NVM_ACCESS_ENABLE				0x00006424
1973#define BCE_NVM_ACCESS_ENABLE_EN			 (1L<<0)
1974#define BCE_NVM_ACCESS_ENABLE_WR_EN			 (1L<<1)
1975
1976#define BCE_NVM_WRITE1					0x00006428
1977#define BCE_NVM_WRITE1_WREN_CMD			 (0xffL<<0)
1978#define BCE_NVM_WRITE1_WRDI_CMD			 (0xffL<<8)
1979#define BCE_NVM_WRITE1_SR_DATA				 (0xffL<<16)
1980
1981
1982
1983/*
1984 *  dma_reg definition
1985 *  offset: 0xc00
1986 */
1987#define BCE_DMA_COMMAND				0x00000c00
1988#define BCE_DMA_COMMAND_ENABLE				 (1L<<0)
1989
1990#define BCE_DMA_STATUS					0x00000c04
1991#define BCE_DMA_STATUS_PAR_ERROR_STATE			 (1L<<0)
1992#define BCE_DMA_STATUS_READ_TRANSFERS_STAT		 (1L<<16)
1993#define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT	 (1L<<17)
1994#define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT		 (1L<<18)
1995#define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT	 (1L<<19)
1996#define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT	 (1L<<20)
1997#define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT		 (1L<<21)
1998#define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<22)
1999#define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT	 (1L<<23)
2000#define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT	 (1L<<24)
2001#define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT	 (1L<<25)
2002
2003#define BCE_DMA_CONFIG					0x00000c08
2004#define BCE_DMA_CONFIG_DATA_BYTE_SWAP			 (1L<<0)
2005#define BCE_DMA_CONFIG_DATA_WORD_SWAP			 (1L<<1)
2006#define BCE_DMA_CONFIG_CNTL_BYTE_SWAP			 (1L<<4)
2007#define BCE_DMA_CONFIG_CNTL_WORD_SWAP			 (1L<<5)
2008#define BCE_DMA_CONFIG_ONE_DMA				 (1L<<6)
2009#define BCE_DMA_CONFIG_CNTL_TWO_DMA			 (1L<<7)
2010#define BCE_DMA_CONFIG_CNTL_FPGA_MODE			 (1L<<8)
2011#define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA		 (1L<<10)
2012#define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY		 (1L<<11)
2013#define BCE_DMA_CONFIG_NO_RCHANS_IN_USE		 (0xfL<<12)
2014#define BCE_DMA_CONFIG_NO_WCHANS_IN_USE		 (0xfL<<16)
2015#define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS		 (0x7L<<20)
2016#define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP		 (1L<<23)
2017#define BCE_DMA_CONFIG_BIG_SIZE			 (0xfL<<24)
2018#define BCE_DMA_CONFIG_BIG_SIZE_NONE			 (0x0L<<24)
2019#define BCE_DMA_CONFIG_BIG_SIZE_64			 (0x1L<<24)
2020#define BCE_DMA_CONFIG_BIG_SIZE_128			 (0x2L<<24)
2021#define BCE_DMA_CONFIG_BIG_SIZE_256			 (0x4L<<24)
2022#define BCE_DMA_CONFIG_BIG_SIZE_512			 (0x8L<<24)
2023
2024#define BCE_DMA_BLACKOUT				0x00000c0c
2025#define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT		 (0xffL<<0)
2026#define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT		 (0xffL<<8)
2027#define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT		 (0xffL<<16)
2028
2029#define BCE_DMA_RCHAN_STAT				0x00000c30
2030#define BCE_DMA_RCHAN_STAT_COMP_CODE_0			 (0x7L<<0)
2031#define BCE_DMA_RCHAN_STAT_PAR_ERR_0			 (1L<<3)
2032#define BCE_DMA_RCHAN_STAT_COMP_CODE_1			 (0x7L<<4)
2033#define BCE_DMA_RCHAN_STAT_PAR_ERR_1			 (1L<<7)
2034#define BCE_DMA_RCHAN_STAT_COMP_CODE_2			 (0x7L<<8)
2035#define BCE_DMA_RCHAN_STAT_PAR_ERR_2			 (1L<<11)
2036#define BCE_DMA_RCHAN_STAT_COMP_CODE_3			 (0x7L<<12)
2037#define BCE_DMA_RCHAN_STAT_PAR_ERR_3			 (1L<<15)
2038#define BCE_DMA_RCHAN_STAT_COMP_CODE_4			 (0x7L<<16)
2039#define BCE_DMA_RCHAN_STAT_PAR_ERR_4			 (1L<<19)
2040#define BCE_DMA_RCHAN_STAT_COMP_CODE_5			 (0x7L<<20)
2041#define BCE_DMA_RCHAN_STAT_PAR_ERR_5			 (1L<<23)
2042#define BCE_DMA_RCHAN_STAT_COMP_CODE_6			 (0x7L<<24)
2043#define BCE_DMA_RCHAN_STAT_PAR_ERR_6			 (1L<<27)
2044#define BCE_DMA_RCHAN_STAT_COMP_CODE_7			 (0x7L<<28)
2045#define BCE_DMA_RCHAN_STAT_PAR_ERR_7			 (1L<<31)
2046
2047#define BCE_DMA_WCHAN_STAT				0x00000c34
2048#define BCE_DMA_WCHAN_STAT_COMP_CODE_0			 (0x7L<<0)
2049#define BCE_DMA_WCHAN_STAT_PAR_ERR_0			 (1L<<3)
2050#define BCE_DMA_WCHAN_STAT_COMP_CODE_1			 (0x7L<<4)
2051#define BCE_DMA_WCHAN_STAT_PAR_ERR_1			 (1L<<7)
2052#define BCE_DMA_WCHAN_STAT_COMP_CODE_2			 (0x7L<<8)
2053#define BCE_DMA_WCHAN_STAT_PAR_ERR_2			 (1L<<11)
2054#define BCE_DMA_WCHAN_STAT_COMP_CODE_3			 (0x7L<<12)
2055#define BCE_DMA_WCHAN_STAT_PAR_ERR_3			 (1L<<15)
2056#define BCE_DMA_WCHAN_STAT_COMP_CODE_4			 (0x7L<<16)
2057#define BCE_DMA_WCHAN_STAT_PAR_ERR_4			 (1L<<19)
2058#define BCE_DMA_WCHAN_STAT_COMP_CODE_5			 (0x7L<<20)
2059#define BCE_DMA_WCHAN_STAT_PAR_ERR_5			 (1L<<23)
2060#define BCE_DMA_WCHAN_STAT_COMP_CODE_6			 (0x7L<<24)
2061#define BCE_DMA_WCHAN_STAT_PAR_ERR_6			 (1L<<27)
2062#define BCE_DMA_WCHAN_STAT_COMP_CODE_7			 (0x7L<<28)
2063#define BCE_DMA_WCHAN_STAT_PAR_ERR_7			 (1L<<31)
2064
2065#define BCE_DMA_RCHAN_ASSIGNMENT			0x00000c38
2066#define BCE_DMA_RCHAN_ASSIGNMENT_0			 (0xfL<<0)
2067#define BCE_DMA_RCHAN_ASSIGNMENT_1			 (0xfL<<4)
2068#define BCE_DMA_RCHAN_ASSIGNMENT_2			 (0xfL<<8)
2069#define BCE_DMA_RCHAN_ASSIGNMENT_3			 (0xfL<<12)
2070#define BCE_DMA_RCHAN_ASSIGNMENT_4			 (0xfL<<16)
2071#define BCE_DMA_RCHAN_ASSIGNMENT_5			 (0xfL<<20)
2072#define BCE_DMA_RCHAN_ASSIGNMENT_6			 (0xfL<<24)
2073#define BCE_DMA_RCHAN_ASSIGNMENT_7			 (0xfL<<28)
2074
2075#define BCE_DMA_WCHAN_ASSIGNMENT			0x00000c3c
2076#define BCE_DMA_WCHAN_ASSIGNMENT_0			 (0xfL<<0)
2077#define BCE_DMA_WCHAN_ASSIGNMENT_1			 (0xfL<<4)
2078#define BCE_DMA_WCHAN_ASSIGNMENT_2			 (0xfL<<8)
2079#define BCE_DMA_WCHAN_ASSIGNMENT_3			 (0xfL<<12)
2080#define BCE_DMA_WCHAN_ASSIGNMENT_4			 (0xfL<<16)
2081#define BCE_DMA_WCHAN_ASSIGNMENT_5			 (0xfL<<20)
2082#define BCE_DMA_WCHAN_ASSIGNMENT_6			 (0xfL<<24)
2083#define BCE_DMA_WCHAN_ASSIGNMENT_7			 (0xfL<<28)
2084
2085#define BCE_DMA_RCHAN_STAT_00				0x00000c40
2086#define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW	 (0xffffffffL<<0)
2087
2088#define BCE_DMA_RCHAN_STAT_01				0x00000c44
2089#define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH	 (0xffffffffL<<0)
2090
2091#define BCE_DMA_RCHAN_STAT_02				0x00000c48
2092#define BCE_DMA_RCHAN_STAT_02_LENGTH			 (0xffffL<<0)
2093#define BCE_DMA_RCHAN_STAT_02_WORD_SWAP		 (1L<<16)
2094#define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP		 (1L<<17)
2095#define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL		 (1L<<18)
2096
2097#define BCE_DMA_RCHAN_STAT_10				0x00000c4c
2098#define BCE_DMA_RCHAN_STAT_11				0x00000c50
2099#define BCE_DMA_RCHAN_STAT_12				0x00000c54
2100#define BCE_DMA_RCHAN_STAT_20				0x00000c58
2101#define BCE_DMA_RCHAN_STAT_21				0x00000c5c
2102#define BCE_DMA_RCHAN_STAT_22				0x00000c60
2103#define BCE_DMA_RCHAN_STAT_30				0x00000c64
2104#define BCE_DMA_RCHAN_STAT_31				0x00000c68
2105#define BCE_DMA_RCHAN_STAT_32				0x00000c6c
2106#define BCE_DMA_RCHAN_STAT_40				0x00000c70
2107#define BCE_DMA_RCHAN_STAT_41				0x00000c74
2108#define BCE_DMA_RCHAN_STAT_42				0x00000c78
2109#define BCE_DMA_RCHAN_STAT_50				0x00000c7c
2110#define BCE_DMA_RCHAN_STAT_51				0x00000c80
2111#define BCE_DMA_RCHAN_STAT_52				0x00000c84
2112#define BCE_DMA_RCHAN_STAT_60				0x00000c88
2113#define BCE_DMA_RCHAN_STAT_61				0x00000c8c
2114#define BCE_DMA_RCHAN_STAT_62				0x00000c90
2115#define BCE_DMA_RCHAN_STAT_70				0x00000c94
2116#define BCE_DMA_RCHAN_STAT_71				0x00000c98
2117#define BCE_DMA_RCHAN_STAT_72				0x00000c9c
2118#define BCE_DMA_WCHAN_STAT_00				0x00000ca0
2119#define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW	 (0xffffffffL<<0)
2120
2121#define BCE_DMA_WCHAN_STAT_01				0x00000ca4
2122#define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH	 (0xffffffffL<<0)
2123
2124#define BCE_DMA_WCHAN_STAT_02				0x00000ca8
2125#define BCE_DMA_WCHAN_STAT_02_LENGTH			 (0xffffL<<0)
2126#define BCE_DMA_WCHAN_STAT_02_WORD_SWAP		 (1L<<16)
2127#define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP		 (1L<<17)
2128#define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL		 (1L<<18)
2129
2130#define BCE_DMA_WCHAN_STAT_10				0x00000cac
2131#define BCE_DMA_WCHAN_STAT_11				0x00000cb0
2132#define BCE_DMA_WCHAN_STAT_12				0x00000cb4
2133#define BCE_DMA_WCHAN_STAT_20				0x00000cb8
2134#define BCE_DMA_WCHAN_STAT_21				0x00000cbc
2135#define BCE_DMA_WCHAN_STAT_22				0x00000cc0
2136#define BCE_DMA_WCHAN_STAT_30				0x00000cc4
2137#define BCE_DMA_WCHAN_STAT_31				0x00000cc8
2138#define BCE_DMA_WCHAN_STAT_32				0x00000ccc
2139#define BCE_DMA_WCHAN_STAT_40				0x00000cd0
2140#define BCE_DMA_WCHAN_STAT_41				0x00000cd4
2141#define BCE_DMA_WCHAN_STAT_42				0x00000cd8
2142#define BCE_DMA_WCHAN_STAT_50				0x00000cdc
2143#define BCE_DMA_WCHAN_STAT_51				0x00000ce0
2144#define BCE_DMA_WCHAN_STAT_52				0x00000ce4
2145#define BCE_DMA_WCHAN_STAT_60				0x00000ce8
2146#define BCE_DMA_WCHAN_STAT_61				0x00000cec
2147#define BCE_DMA_WCHAN_STAT_62				0x00000cf0
2148#define BCE_DMA_WCHAN_STAT_70				0x00000cf4
2149#define BCE_DMA_WCHAN_STAT_71				0x00000cf8
2150#define BCE_DMA_WCHAN_STAT_72				0x00000cfc
2151#define BCE_DMA_ARB_STAT_00				0x00000d00
2152#define BCE_DMA_ARB_STAT_00_MASTER			 (0xffffL<<0)
2153#define BCE_DMA_ARB_STAT_00_MASTER_ENC			 (0xffL<<16)
2154#define BCE_DMA_ARB_STAT_00_CUR_BINMSTR		 (0xffL<<24)
2155
2156#define BCE_DMA_ARB_STAT_01				0x00000d04
2157#define BCE_DMA_ARB_STAT_01_LPR_RPTR			 (0xfL<<0)
2158#define BCE_DMA_ARB_STAT_01_LPR_WPTR			 (0xfL<<4)
2159#define BCE_DMA_ARB_STAT_01_LPB_RPTR			 (0xfL<<8)
2160#define BCE_DMA_ARB_STAT_01_LPB_WPTR			 (0xfL<<12)
2161#define BCE_DMA_ARB_STAT_01_HPR_RPTR			 (0xfL<<16)
2162#define BCE_DMA_ARB_STAT_01_HPR_WPTR			 (0xfL<<20)
2163#define BCE_DMA_ARB_STAT_01_HPB_RPTR			 (0xfL<<24)
2164#define BCE_DMA_ARB_STAT_01_HPB_WPTR			 (0xfL<<28)
2165
2166#define BCE_DMA_FUSE_CTRL0_CMD				0x00000f00
2167#define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE		 (1L<<0)
2168#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE		 (1L<<1)
2169#define BCE_DMA_FUSE_CTRL0_CMD_SHIFT			 (1L<<2)
2170#define BCE_DMA_FUSE_CTRL0_CMD_LOAD			 (1L<<3)
2171#define BCE_DMA_FUSE_CTRL0_CMD_SEL			 (0xfL<<8)
2172
2173#define BCE_DMA_FUSE_CTRL0_DATA			0x00000f04
2174#define BCE_DMA_FUSE_CTRL1_CMD				0x00000f08
2175#define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE		 (1L<<0)
2176#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE		 (1L<<1)
2177#define BCE_DMA_FUSE_CTRL1_CMD_SHIFT			 (1L<<2)
2178#define BCE_DMA_FUSE_CTRL1_CMD_LOAD			 (1L<<3)
2179#define BCE_DMA_FUSE_CTRL1_CMD_SEL			 (0xfL<<8)
2180
2181#define BCE_DMA_FUSE_CTRL1_DATA			0x00000f0c
2182#define BCE_DMA_FUSE_CTRL2_CMD				0x00000f10
2183#define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE		 (1L<<0)
2184#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE		 (1L<<1)
2185#define BCE_DMA_FUSE_CTRL2_CMD_SHIFT			 (1L<<2)
2186#define BCE_DMA_FUSE_CTRL2_CMD_LOAD			 (1L<<3)
2187#define BCE_DMA_FUSE_CTRL2_CMD_SEL			 (0xfL<<8)
2188
2189#define BCE_DMA_FUSE_CTRL2_DATA			0x00000f14
2190
2191
2192/*
2193 *  context_reg definition
2194 *  offset: 0x1000
2195 */
2196#define BCE_CTX_COMMAND				0x00001000
2197#define BCE_CTX_COMMAND_ENABLED			 (1L<<0)
2198
2199#define BCE_CTX_STATUS					0x00001004
2200#define BCE_CTX_STATUS_LOCK_WAIT			 (1L<<0)
2201#define BCE_CTX_STATUS_READ_STAT			 (1L<<16)
2202#define BCE_CTX_STATUS_WRITE_STAT			 (1L<<17)
2203#define BCE_CTX_STATUS_ACC_STALL_STAT			 (1L<<18)
2204#define BCE_CTX_STATUS_LOCK_STALL_STAT			 (1L<<19)
2205
2206#define BCE_CTX_VIRT_ADDR				0x00001008
2207#define BCE_CTX_VIRT_ADDR_VIRT_ADDR			 (0x7fffL<<6)
2208
2209#define BCE_CTX_PAGE_TBL				0x0000100c
2210#define BCE_CTX_PAGE_TBL_PAGE_TBL			 (0x3fffL<<6)
2211
2212#define BCE_CTX_DATA_ADR				0x00001010
2213#define BCE_CTX_DATA_ADR_DATA_ADR			 (0x7ffffL<<2)
2214
2215#define BCE_CTX_DATA					0x00001014
2216#define BCE_CTX_LOCK					0x00001018
2217#define BCE_CTX_LOCK_TYPE				 (0x7L<<0)
2218#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID		 (0x0L<<0)
2219#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE		 (0x7L<<0)
2220#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL		 (0x1L<<0)
2221#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX			 (0x2L<<0)
2222#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER		 (0x4L<<0)
2223#define BCE_CTX_LOCK_CID_VALUE				 (0x3fffL<<7)
2224#define BCE_CTX_LOCK_GRANTED				 (1L<<26)
2225#define BCE_CTX_LOCK_MODE				 (0x7L<<27)
2226#define BCE_CTX_LOCK_MODE_UNLOCK			 (0x0L<<27)
2227#define BCE_CTX_LOCK_MODE_IMMEDIATE			 (0x1L<<27)
2228#define BCE_CTX_LOCK_MODE_SURE				 (0x2L<<27)
2229#define BCE_CTX_LOCK_STATUS				 (1L<<30)
2230#define BCE_CTX_LOCK_REQ				 (1L<<31)
2231
2232#define BCE_CTX_ACCESS_STATUS				0x00001040
2233#define BCE_CTX_ACCESS_STATUS_MASTERENCODED		 (0xfL<<0)
2234#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM		 (0x3L<<10)
2235#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM		 (0x3L<<12)
2236#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM	 (0x3L<<14)
2237#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST	 (0x7ffL<<17)
2238
2239#define BCE_CTX_DBG_LOCK_STATUS			0x00001044
2240#define BCE_CTX_DBG_LOCK_STATUS_SM			 (0x3ffL<<0)
2241#define BCE_CTX_DBG_LOCK_STATUS_MATCH			 (0x3ffL<<22)
2242
2243#define BCE_CTX_CHNL_LOCK_STATUS_0			0x00001080
2244#define BCE_CTX_CHNL_LOCK_STATUS_0_CID			 (0x3fffL<<0)
2245#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE		 (0x3L<<14)
2246#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE		 (1L<<16)
2247
2248#define BCE_CTX_CHNL_LOCK_STATUS_1			0x00001084
2249#define BCE_CTX_CHNL_LOCK_STATUS_2			0x00001088
2250#define BCE_CTX_CHNL_LOCK_STATUS_3			0x0000108c
2251#define BCE_CTX_CHNL_LOCK_STATUS_4			0x00001090
2252#define BCE_CTX_CHNL_LOCK_STATUS_5			0x00001094
2253#define BCE_CTX_CHNL_LOCK_STATUS_6			0x00001098
2254#define BCE_CTX_CHNL_LOCK_STATUS_7			0x0000109c
2255#define BCE_CTX_CHNL_LOCK_STATUS_8			0x000010a0
2256
2257
2258/*
2259 *  emac_reg definition
2260 *  offset: 0x1400
2261 */
2262#define BCE_EMAC_MODE					0x00001400
2263#define BCE_EMAC_MODE_RESET				 (1L<<0)
2264#define BCE_EMAC_MODE_HALF_DUPLEX			 (1L<<1)
2265#define BCE_EMAC_MODE_PORT				 (0x3L<<2)
2266#define BCE_EMAC_MODE_PORT_NONE			 (0L<<2)
2267#define BCE_EMAC_MODE_PORT_MII				 (1L<<2)
2268#define BCE_EMAC_MODE_PORT_GMII			 (2L<<2)
2269#define BCE_EMAC_MODE_PORT_MII_10			 (3L<<2)
2270#define BCE_EMAC_MODE_MAC_LOOP				 (1L<<4)
2271#define BCE_EMAC_MODE_25G				 (1L<<5)
2272#define BCE_EMAC_MODE_TAGGED_MAC_CTL			 (1L<<7)
2273#define BCE_EMAC_MODE_TX_BURST				 (1L<<8)
2274#define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA		 (1L<<9)
2275#define BCE_EMAC_MODE_EXT_LINK_POL			 (1L<<10)
2276#define BCE_EMAC_MODE_FORCE_LINK			 (1L<<11)
2277#define BCE_EMAC_MODE_MPKT				 (1L<<18)
2278#define BCE_EMAC_MODE_MPKT_RCVD			 (1L<<19)
2279#define BCE_EMAC_MODE_ACPI_RCVD			 (1L<<20)
2280
2281#define BCE_EMAC_STATUS				0x00001404
2282#define BCE_EMAC_STATUS_LINK				 (1L<<11)
2283#define BCE_EMAC_STATUS_LINK_CHANGE			 (1L<<12)
2284#define BCE_EMAC_STATUS_MI_COMPLETE			 (1L<<22)
2285#define BCE_EMAC_STATUS_MI_INT				 (1L<<23)
2286#define BCE_EMAC_STATUS_AP_ERROR			 (1L<<24)
2287#define BCE_EMAC_STATUS_PARITY_ERROR_STATE		 (1L<<31)
2288
2289#define BCE_EMAC_ATTENTION_ENA				0x00001408
2290#define BCE_EMAC_ATTENTION_ENA_LINK			 (1L<<11)
2291#define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE		 (1L<<22)
2292#define BCE_EMAC_ATTENTION_ENA_MI_INT			 (1L<<23)
2293#define BCE_EMAC_ATTENTION_ENA_AP_ERROR		 (1L<<24)
2294
2295#define BCE_EMAC_LED					0x0000140c
2296#define BCE_EMAC_LED_OVERRIDE				 (1L<<0)
2297#define BCE_EMAC_LED_1000MB_OVERRIDE			 (1L<<1)
2298#define BCE_EMAC_LED_100MB_OVERRIDE			 (1L<<2)
2299#define BCE_EMAC_LED_10MB_OVERRIDE			 (1L<<3)
2300#define BCE_EMAC_LED_TRAFFIC_OVERRIDE			 (1L<<4)
2301#define BCE_EMAC_LED_BLNK_TRAFFIC			 (1L<<5)
2302#define BCE_EMAC_LED_TRAFFIC				 (1L<<6)
2303#define BCE_EMAC_LED_1000MB				 (1L<<7)
2304#define BCE_EMAC_LED_100MB				 (1L<<8)
2305#define BCE_EMAC_LED_10MB				 (1L<<9)
2306#define BCE_EMAC_LED_TRAFFIC_STAT			 (1L<<10)
2307#define BCE_EMAC_LED_BLNK_RATE				 (0xfffL<<19)
2308#define BCE_EMAC_LED_BLNK_RATE_ENA			 (1L<<31)
2309
2310#define BCE_EMAC_MAC_MATCH0				0x00001410
2311#define BCE_EMAC_MAC_MATCH1				0x00001414
2312#define BCE_EMAC_MAC_MATCH2				0x00001418
2313#define BCE_EMAC_MAC_MATCH3				0x0000141c
2314#define BCE_EMAC_MAC_MATCH4				0x00001420
2315#define BCE_EMAC_MAC_MATCH5				0x00001424
2316#define BCE_EMAC_MAC_MATCH6				0x00001428
2317#define BCE_EMAC_MAC_MATCH7				0x0000142c
2318#define BCE_EMAC_MAC_MATCH8				0x00001430
2319#define BCE_EMAC_MAC_MATCH9				0x00001434
2320#define BCE_EMAC_MAC_MATCH10				0x00001438
2321#define BCE_EMAC_MAC_MATCH11				0x0000143c
2322#define BCE_EMAC_MAC_MATCH12				0x00001440
2323#define BCE_EMAC_MAC_MATCH13				0x00001444
2324#define BCE_EMAC_MAC_MATCH14				0x00001448
2325#define BCE_EMAC_MAC_MATCH15				0x0000144c
2326#define BCE_EMAC_MAC_MATCH16				0x00001450
2327#define BCE_EMAC_MAC_MATCH17				0x00001454
2328#define BCE_EMAC_MAC_MATCH18				0x00001458
2329#define BCE_EMAC_MAC_MATCH19				0x0000145c
2330#define BCE_EMAC_MAC_MATCH20				0x00001460
2331#define BCE_EMAC_MAC_MATCH21				0x00001464
2332#define BCE_EMAC_MAC_MATCH22				0x00001468
2333#define BCE_EMAC_MAC_MATCH23				0x0000146c
2334#define BCE_EMAC_MAC_MATCH24				0x00001470
2335#define BCE_EMAC_MAC_MATCH25				0x00001474
2336#define BCE_EMAC_MAC_MATCH26				0x00001478
2337#define BCE_EMAC_MAC_MATCH27				0x0000147c
2338#define BCE_EMAC_MAC_MATCH28				0x00001480
2339#define BCE_EMAC_MAC_MATCH29				0x00001484
2340#define BCE_EMAC_MAC_MATCH30				0x00001488
2341#define BCE_EMAC_MAC_MATCH31				0x0000148c
2342#define BCE_EMAC_BACKOFF_SEED				0x00001498
2343#define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED	 (0x3ffL<<0)
2344
2345#define BCE_EMAC_RX_MTU_SIZE				0x0000149c
2346#define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE			 (0xffffL<<0)
2347#define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA			 (1L<<31)
2348
2349#define BCE_EMAC_SERDES_CNTL				0x000014a4
2350#define BCE_EMAC_SERDES_CNTL_RXR			 (0x7L<<0)
2351#define BCE_EMAC_SERDES_CNTL_RXG			 (0x3L<<3)
2352#define BCE_EMAC_SERDES_CNTL_RXCKSEL			 (1L<<6)
2353#define BCE_EMAC_SERDES_CNTL_TXBIAS			 (0x7L<<7)
2354#define BCE_EMAC_SERDES_CNTL_BGMAX			 (1L<<10)
2355#define BCE_EMAC_SERDES_CNTL_BGMIN			 (1L<<11)
2356#define BCE_EMAC_SERDES_CNTL_TXMODE			 (1L<<12)
2357#define BCE_EMAC_SERDES_CNTL_TXEDGE			 (1L<<13)
2358#define BCE_EMAC_SERDES_CNTL_SERDES_MODE		 (1L<<14)
2359#define BCE_EMAC_SERDES_CNTL_PLLTEST			 (1L<<15)
2360#define BCE_EMAC_SERDES_CNTL_CDET_EN			 (1L<<16)
2361#define BCE_EMAC_SERDES_CNTL_TBI_LBK			 (1L<<17)
2362#define BCE_EMAC_SERDES_CNTL_REMOTE_LBK		 (1L<<18)
2363#define BCE_EMAC_SERDES_CNTL_REV_PHASE			 (1L<<19)
2364#define BCE_EMAC_SERDES_CNTL_REGCTL12			 (0x3L<<20)
2365#define BCE_EMAC_SERDES_CNTL_REGCTL25			 (0x3L<<22)
2366
2367#define BCE_EMAC_SERDES_STATUS				0x000014a8
2368#define BCE_EMAC_SERDES_STATUS_RX_STAT			 (0xffL<<0)
2369#define BCE_EMAC_SERDES_STATUS_COMMA_DET		 (1L<<8)
2370
2371#define BCE_EMAC_MDIO_COMM				0x000014ac
2372#define BCE_EMAC_MDIO_COMM_DATA			 (0xffffL<<0)
2373#define BCE_EMAC_MDIO_COMM_REG_ADDR			 (0x1fL<<16)
2374#define BCE_EMAC_MDIO_COMM_PHY_ADDR			 (0x1fL<<21)
2375#define BCE_EMAC_MDIO_COMM_COMMAND			 (0x3L<<26)
2376#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0		 (0L<<26)
2377#define BCE_EMAC_MDIO_COMM_COMMAND_WRITE		 (1L<<26)
2378#define BCE_EMAC_MDIO_COMM_COMMAND_READ		 (2L<<26)
2379#define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3		 (3L<<26)
2380#define BCE_EMAC_MDIO_COMM_FAIL			 (1L<<28)
2381#define BCE_EMAC_MDIO_COMM_START_BUSY			 (1L<<29)
2382#define BCE_EMAC_MDIO_COMM_DISEXT			 (1L<<30)
2383
2384#define BCE_EMAC_MDIO_STATUS				0x000014b0
2385#define BCE_EMAC_MDIO_STATUS_LINK			 (1L<<0)
2386#define BCE_EMAC_MDIO_STATUS_10MB			 (1L<<1)
2387
2388#define BCE_EMAC_MDIO_MODE				0x000014b4
2389#define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE		 (1L<<1)
2390#define BCE_EMAC_MDIO_MODE_AUTO_POLL			 (1L<<4)
2391#define BCE_EMAC_MDIO_MODE_BIT_BANG			 (1L<<8)
2392#define BCE_EMAC_MDIO_MODE_MDIO			 (1L<<9)
2393#define BCE_EMAC_MDIO_MODE_MDIO_OE			 (1L<<10)
2394#define BCE_EMAC_MDIO_MODE_MDC				 (1L<<11)
2395#define BCE_EMAC_MDIO_MODE_MDINT			 (1L<<12)
2396#define BCE_EMAC_MDIO_MODE_CLOCK_CNT			 (0x1fL<<16)
2397
2398#define BCE_EMAC_MDIO_AUTO_STATUS			0x000014b8
2399#define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR		 (1L<<0)
2400
2401#define BCE_EMAC_TX_MODE				0x000014bc
2402#define BCE_EMAC_TX_MODE_RESET				 (1L<<0)
2403#define BCE_EMAC_TX_MODE_EXT_PAUSE_EN			 (1L<<3)
2404#define BCE_EMAC_TX_MODE_FLOW_EN			 (1L<<4)
2405#define BCE_EMAC_TX_MODE_BIG_BACKOFF			 (1L<<5)
2406#define BCE_EMAC_TX_MODE_LONG_PAUSE			 (1L<<6)
2407#define BCE_EMAC_TX_MODE_LINK_AWARE			 (1L<<7)
2408
2409#define BCE_EMAC_TX_STATUS				0x000014c0
2410#define BCE_EMAC_TX_STATUS_XOFFED			 (1L<<0)
2411#define BCE_EMAC_TX_STATUS_XOFF_SENT			 (1L<<1)
2412#define BCE_EMAC_TX_STATUS_XON_SENT			 (1L<<2)
2413#define BCE_EMAC_TX_STATUS_LINK_UP			 (1L<<3)
2414#define BCE_EMAC_TX_STATUS_UNDERRUN			 (1L<<4)
2415
2416#define BCE_EMAC_TX_LENGTHS				0x000014c4
2417#define BCE_EMAC_TX_LENGTHS_SLOT			 (0xffL<<0)
2418#define BCE_EMAC_TX_LENGTHS_IPG			 (0xfL<<8)
2419#define BCE_EMAC_TX_LENGTHS_IPG_CRS			 (0x3L<<12)
2420
2421#define BCE_EMAC_RX_MODE				0x000014c8
2422#define BCE_EMAC_RX_MODE_RESET				 (1L<<0)
2423#define BCE_EMAC_RX_MODE_FLOW_EN			 (1L<<2)
2424#define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL		 (1L<<3)
2425#define BCE_EMAC_RX_MODE_KEEP_PAUSE			 (1L<<4)
2426#define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE		 (1L<<5)
2427#define BCE_EMAC_RX_MODE_ACCEPT_RUNTS			 (1L<<6)
2428#define BCE_EMAC_RX_MODE_LLC_CHK			 (1L<<7)
2429#define BCE_EMAC_RX_MODE_PROMISCUOUS			 (1L<<8)
2430#define BCE_EMAC_RX_MODE_NO_CRC_CHK			 (1L<<9)
2431#define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG			 (1L<<10)
2432#define BCE_EMAC_RX_MODE_FILT_BROADCAST		 (1L<<11)
2433#define BCE_EMAC_RX_MODE_SORT_MODE			 (1L<<12)
2434
2435#define BCE_EMAC_RX_STATUS				0x000014cc
2436#define BCE_EMAC_RX_STATUS_FFED			 (1L<<0)
2437#define BCE_EMAC_RX_STATUS_FF_RECEIVED			 (1L<<1)
2438#define BCE_EMAC_RX_STATUS_N_RECEIVED			 (1L<<2)
2439
2440#define BCE_EMAC_MULTICAST_HASH0			0x000014d0
2441#define BCE_EMAC_MULTICAST_HASH1			0x000014d4
2442#define BCE_EMAC_MULTICAST_HASH2			0x000014d8
2443#define BCE_EMAC_MULTICAST_HASH3			0x000014dc
2444#define BCE_EMAC_MULTICAST_HASH4			0x000014e0
2445#define BCE_EMAC_MULTICAST_HASH5			0x000014e4
2446#define BCE_EMAC_MULTICAST_HASH6			0x000014e8
2447#define BCE_EMAC_MULTICAST_HASH7			0x000014ec
2448#define BCE_EMAC_RX_STAT_IFHCINOCTETS			0x00001500
2449#define BCE_EMAC_RX_STAT_IFHCINBADOCTETS		0x00001504
2450#define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS		0x00001508
2451#define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS		0x0000150c
2452#define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS		0x00001510
2453#define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS		0x00001514
2454#define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS		0x00001518
2455#define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS	0x0000151c
2456#define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS	0x00001520
2457#define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED	0x00001524
2458#define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED	0x00001528
2459#define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED	0x0000152c
2460#define BCE_EMAC_RX_STAT_XOFFSTATEENTERED		0x00001530
2461#define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG	0x00001534
2462#define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS		0x00001538
2463#define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS	0x0000153c
2464#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS	0x00001540
2465#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x00001544
2466#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x00001548
2467#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x0000154c
2468#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x00001550
2469#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x00001554
2470#define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS	0x00001558
2471#define BCE_EMAC_RXMAC_DEBUG0				0x0000155c
2472#define BCE_EMAC_RXMAC_DEBUG1				0x00001560
2473#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT	 (1L<<0)
2474#define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE		 (1L<<1)
2475#define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC			 (1L<<2)
2476#define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR			 (1L<<3)
2477#define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR		 (1L<<4)
2478#define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA		 (1L<<5)
2479#define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START		 (1L<<6)
2480#define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT		 (0xffffL<<7)
2481#define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME		 (0xffL<<23)
2482
2483#define BCE_EMAC_RXMAC_DEBUG2				0x00001564
2484#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE			 (0x7L<<0)
2485#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE		 (0x0L<<0)
2486#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD		 (0x1L<<0)
2487#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA		 (0x2L<<0)
2488#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP		 (0x3L<<0)
2489#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT		 (0x4L<<0)
2490#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP		 (0x5L<<0)
2491#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP		 (0x6L<<0)
2492#define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC		 (0x7L<<0)
2493#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE		 (0xfL<<3)
2494#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE		 (0x0L<<3)
2495#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0		 (0x1L<<3)
2496#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1		 (0x2L<<3)
2497#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2		 (0x3L<<3)
2498#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3		 (0x4L<<3)
2499#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT		 (0x5L<<3)
2500#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT		 (0x6L<<3)
2501#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS		 (0x7L<<3)
2502#define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST		 (0x8L<<3)
2503#define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN			 (0xffL<<7)
2504#define BCE_EMAC_RXMAC_DEBUG2_FALSEC			 (1L<<15)
2505#define BCE_EMAC_RXMAC_DEBUG2_TAGGED			 (1L<<16)
2506#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE		 (1L<<18)
2507#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE		 (0L<<18)
2508#define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED	 (1L<<18)
2509#define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER		 (0xfL<<19)
2510#define BCE_EMAC_RXMAC_DEBUG2_QUANTA			 (0x1fL<<23)
2511
2512#define BCE_EMAC_RXMAC_DEBUG3				0x00001568
2513#define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR		 (0xffffL<<0)
2514#define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR		 (0xffffL<<16)
2515
2516#define BCE_EMAC_RXMAC_DEBUG4				0x0000156c
2517#define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD		 (0xffffL<<0)
2518#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE		 (0x3fL<<16)
2519#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE		 (0x0L<<16)
2520#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2		 (0x1L<<16)
2521#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3		 (0x2L<<16)
2522#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI		 (0x3L<<16)
2523#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2		 (0x7L<<16)
2524#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3		 (0x5L<<16)
2525#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1		 (0x6L<<16)
2526#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2		 (0x7L<<16)
2527#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3		 (0x8L<<16)
2528#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2		 (0x9L<<16)
2529#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3		 (0xaL<<16)
2530#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1	 (0xeL<<16)
2531#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2	 (0xfL<<16)
2532#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK	 (0x10L<<16)
2533#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC		 (0x11L<<16)
2534#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2		 (0x12L<<16)
2535#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3		 (0x13L<<16)
2536#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1		 (0x14L<<16)
2537#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2		 (0x15L<<16)
2538#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3		 (0x16L<<16)
2539#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE		 (0x17L<<16)
2540#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC		 (0x18L<<16)
2541#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE		 (0x19L<<16)
2542#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD		 (0x1aL<<16)
2543#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC		 (0x1bL<<16)
2544#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH		 (0x1cL<<16)
2545#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF		 (0x1dL<<16)
2546#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON		 (0x1eL<<16)
2547#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED	 (0x1fL<<16)
2548#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED	 (0x20L<<16)
2549#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE		 (0x21L<<16)
2550#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL		 (0x22L<<16)
2551#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1		 (0x23L<<16)
2552#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2		 (0x24L<<16)
2553#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3		 (0x25L<<16)
2554#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE		 (0x26L<<16)
2555#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE	 (0x27L<<16)
2556#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL		 (0x28L<<16)
2557#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE		 (0x29L<<16)
2558#define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP		 (0x2aL<<16)
2559#define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT			 (1L<<22)
2560#define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED		 (1L<<23)
2561#define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER		 (1L<<24)
2562#define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA		 (1L<<25)
2563#define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND		 (1L<<26)
2564#define BCE_EMAC_RXMAC_DEBUG4_ADVANCE			 (1L<<27)
2565#define BCE_EMAC_RXMAC_DEBUG4_START			 (1L<<28)
2566
2567#define BCE_EMAC_RXMAC_DEBUG5				0x00001570
2568#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM			 (0x7L<<0)
2569#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE		 (0L<<0)
2570#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF	 (1L<<0)
2571#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT	 (2L<<0)
2572#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC	 (3L<<0)
2573#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE	 (4L<<0)
2574#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL	 (5L<<0)
2575#define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT	 (6L<<0)
2576#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1		 (0x7L<<4)
2577#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW		 (0x0L<<4)
2578#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT		 (0x1L<<4)
2579#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF		 (0x2L<<4)
2580#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF		 (0x3L<<4)
2581#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF		 (0x4L<<4)
2582#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF		 (0x6L<<4)
2583#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF		 (0x7L<<4)
2584#define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED		 (1L<<7)
2585#define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0		 (0x7L<<8)
2586#define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL	 (1L<<11)
2587#define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE		 (1L<<12)
2588#define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA		 (1L<<13)
2589#define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT		 (1L<<14)
2590#define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT			 (1L<<15)
2591#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE		 (0x3L<<16)
2592#define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT		 (1L<<19)
2593#define BCE_EMAC_RXMAC_DEBUG5_FMLEN			 (0xfffL<<20)
2594
2595#define BCE_EMAC_RX_STAT_AC0				0x00001580
2596#define BCE_EMAC_RX_STAT_AC1				0x00001584
2597#define BCE_EMAC_RX_STAT_AC2				0x00001588
2598#define BCE_EMAC_RX_STAT_AC3				0x0000158c
2599#define BCE_EMAC_RX_STAT_AC4				0x00001590
2600#define BCE_EMAC_RX_STAT_AC5				0x00001594
2601#define BCE_EMAC_RX_STAT_AC6				0x00001598
2602#define BCE_EMAC_RX_STAT_AC7				0x0000159c
2603#define BCE_EMAC_RX_STAT_AC8				0x000015a0
2604#define BCE_EMAC_RX_STAT_AC9				0x000015a4
2605#define BCE_EMAC_RX_STAT_AC10				0x000015a8
2606#define BCE_EMAC_RX_STAT_AC11				0x000015ac
2607#define BCE_EMAC_RX_STAT_AC12				0x000015b0
2608#define BCE_EMAC_RX_STAT_AC13				0x000015b4
2609#define BCE_EMAC_RX_STAT_AC14				0x000015b8
2610#define BCE_EMAC_RX_STAT_AC15				0x000015bc
2611#define BCE_EMAC_RX_STAT_AC16				0x000015c0
2612#define BCE_EMAC_RX_STAT_AC17				0x000015c4
2613#define BCE_EMAC_RX_STAT_AC18				0x000015c8
2614#define BCE_EMAC_RX_STAT_AC19				0x000015cc
2615#define BCE_EMAC_RX_STAT_AC20				0x000015d0
2616#define BCE_EMAC_RX_STAT_AC21				0x000015d4
2617#define BCE_EMAC_RX_STAT_AC22				0x000015d8
2618#define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC		0x000015dc
2619#define BCE_EMAC_TX_STAT_IFHCOUTOCTETS			0x00001600
2620#define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS		0x00001604
2621#define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS		0x00001608
2622#define BCE_EMAC_TX_STAT_OUTXONSENT			0x0000160c
2623#define BCE_EMAC_TX_STAT_OUTXOFFSENT			0x00001610
2624#define BCE_EMAC_TX_STAT_FLOWCONTROLDONE		0x00001614
2625#define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES	0x00001618
2626#define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES	0x0000161c
2627#define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS	0x00001620
2628#define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS	0x00001624
2629#define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS	0x00001628
2630#define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS		0x0000162c
2631#define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS		0x00001630
2632#define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS		0x00001634
2633#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS	0x00001638
2634#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x0000163c
2635#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x00001640
2636#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x00001644
2637#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x00001648
2638#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x0000164c
2639#define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS	0x00001650
2640#define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS	0x00001654
2641#define BCE_EMAC_TXMAC_DEBUG0				0x00001658
2642#define BCE_EMAC_TXMAC_DEBUG1				0x0000165c
2643#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE		 (0xfL<<0)
2644#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE		 (0x0L<<0)
2645#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0		 (0x1L<<0)
2646#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0		 (0x4L<<0)
2647#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1		 (0x5L<<0)
2648#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2		 (0x6L<<0)
2649#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3		 (0x7L<<0)
2650#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0		 (0x8L<<0)
2651#define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1		 (0x9L<<0)
2652#define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE		 (1L<<4)
2653#define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC			 (1L<<5)
2654#define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER		 (0xfL<<6)
2655#define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE		 (1L<<10)
2656#define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION		 (1L<<11)
2657#define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER		 (1L<<12)
2658#define BCE_EMAC_TXMAC_DEBUG1_DEFERRED			 (1L<<13)
2659#define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE			 (1L<<14)
2660#define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME			 (0xfL<<15)
2661#define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME		 (0xffL<<19)
2662
2663#define BCE_EMAC_TXMAC_DEBUG2				0x00001660
2664#define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF			 (0x3ffL<<0)
2665#define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT		 (0xffffL<<10)
2666#define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT		 (0x1fL<<26)
2667#define BCE_EMAC_TXMAC_DEBUG2_COL_BIT			 (1L<<31)
2668
2669#define BCE_EMAC_TXMAC_DEBUG3				0x00001664
2670#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE			 (0xfL<<0)
2671#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE		 (0x0L<<0)
2672#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1		 (0x1L<<0)
2673#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2		 (0x2L<<0)
2674#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD		 (0x3L<<0)
2675#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA		 (0x4L<<0)
2676#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1		 (0x5L<<0)
2677#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2		 (0x6L<<0)
2678#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT		 (0x7L<<0)
2679#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB		 (0x8L<<0)
2680#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG		 (0x9L<<0)
2681#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM		 (0xaL<<0)
2682#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM		 (0xbL<<0)
2683#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM		 (0xcL<<0)
2684#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT		 (0xdL<<0)
2685#define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF		 (0xeL<<0)
2686#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE		 (0x7L<<4)
2687#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE		 (0x0L<<4)
2688#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT		 (0x1L<<4)
2689#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI		 (0x2L<<4)
2690#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC		 (0x3L<<4)
2691#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2		 (0x4L<<4)
2692#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3		 (0x5L<<4)
2693#define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC		 (0x6L<<4)
2694#define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE			 (1L<<7)
2695#define BCE_EMAC_TXMAC_DEBUG3_XOFF			 (1L<<8)
2696#define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER		 (0xfL<<9)
2697#define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER		 (0x1fL<<13)
2698
2699#define BCE_EMAC_TXMAC_DEBUG4				0x00001668
2700#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER		 (0xffffL<<0)
2701#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE		 (0xfL<<16)
2702#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE		 (0x0L<<16)
2703#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1		 (0x2L<<16)
2704#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2		 (0x3L<<16)
2705#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3		 (0x6L<<16)
2706#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1		 (0x7L<<16)
2707#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2		 (0x5L<<16)
2708#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3		 (0x4L<<16)
2709#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE		 (0xcL<<16)
2710#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD		 (0xeL<<16)
2711#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME		 (0xaL<<16)
2712#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1		 (0x8L<<16)
2713#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2		 (0x9L<<16)
2714#define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT		 (0xdL<<16)
2715#define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID		 (1L<<20)
2716#define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC		 (1L<<21)
2717#define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED		 (1L<<22)
2718#define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER		 (1L<<23)
2719#define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND		 (1L<<24)
2720#define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING		 (1L<<25)
2721#define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC			 (1L<<26)
2722#define BCE_EMAC_TXMAC_DEBUG4_COLLIDING		 (1L<<27)
2723#define BCE_EMAC_TXMAC_DEBUG4_COL_IN			 (1L<<28)
2724#define BCE_EMAC_TXMAC_DEBUG4_BURSTING			 (1L<<29)
2725#define BCE_EMAC_TXMAC_DEBUG4_ADVANCE			 (1L<<30)
2726#define BCE_EMAC_TXMAC_DEBUG4_GO			 (1L<<31)
2727
2728#define BCE_EMAC_TX_STAT_AC0				0x00001680
2729#define BCE_EMAC_TX_STAT_AC1				0x00001684
2730#define BCE_EMAC_TX_STAT_AC2				0x00001688
2731#define BCE_EMAC_TX_STAT_AC3				0x0000168c
2732#define BCE_EMAC_TX_STAT_AC4				0x00001690
2733#define BCE_EMAC_TX_STAT_AC5				0x00001694
2734#define BCE_EMAC_TX_STAT_AC6				0x00001698
2735#define BCE_EMAC_TX_STAT_AC7				0x0000169c
2736#define BCE_EMAC_TX_STAT_AC8				0x000016a0
2737#define BCE_EMAC_TX_STAT_AC9				0x000016a4
2738#define BCE_EMAC_TX_STAT_AC10				0x000016a8
2739#define BCE_EMAC_TX_STAT_AC11				0x000016ac
2740#define BCE_EMAC_TX_STAT_AC12				0x000016b0
2741#define BCE_EMAC_TX_STAT_AC13				0x000016b4
2742#define BCE_EMAC_TX_STAT_AC14				0x000016b8
2743#define BCE_EMAC_TX_STAT_AC15				0x000016bc
2744#define BCE_EMAC_TX_STAT_AC16				0x000016c0
2745#define BCE_EMAC_TX_STAT_AC17				0x000016c4
2746#define BCE_EMAC_TX_STAT_AC18				0x000016c8
2747#define BCE_EMAC_TX_STAT_AC19				0x000016cc
2748#define BCE_EMAC_TX_STAT_AC20				0x000016d0
2749#define BCE_EMAC_TX_STAT_AC21				0x000016d4
2750#define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC		0x000016d8
2751
2752
2753/*
2754 *  rpm_reg definition
2755 *  offset: 0x1800
2756 */
2757#define BCE_RPM_COMMAND				0x00001800
2758#define BCE_RPM_COMMAND_ENABLED			 (1L<<0)
2759#define BCE_RPM_COMMAND_OVERRUN_ABORT			 (1L<<4)
2760
2761#define BCE_RPM_STATUS					0x00001804
2762#define BCE_RPM_STATUS_MBUF_WAIT			 (1L<<0)
2763#define BCE_RPM_STATUS_FREE_WAIT			 (1L<<1)
2764
2765#define BCE_RPM_CONFIG					0x00001808
2766#define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM		 (1L<<0)
2767#define BCE_RPM_CONFIG_ACPI_ENA			 (1L<<1)
2768#define BCE_RPM_CONFIG_ACPI_KEEP			 (1L<<2)
2769#define BCE_RPM_CONFIG_MP_KEEP				 (1L<<3)
2770#define BCE_RPM_CONFIG_SORT_VECT_VAL			 (0xfL<<4)
2771#define BCE_RPM_CONFIG_IGNORE_VLAN			 (1L<<31)
2772
2773#define BCE_RPM_VLAN_MATCH0				0x00001810
2774#define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE	 (0xfffL<<0)
2775
2776#define BCE_RPM_VLAN_MATCH1				0x00001814
2777#define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE	 (0xfffL<<0)
2778
2779#define BCE_RPM_VLAN_MATCH2				0x00001818
2780#define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE	 (0xfffL<<0)
2781
2782#define BCE_RPM_VLAN_MATCH3				0x0000181c
2783#define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE	 (0xfffL<<0)
2784
2785#define BCE_RPM_SORT_USER0				0x00001820
2786#define BCE_RPM_SORT_USER0_PM_EN			 (0xffffL<<0)
2787#define BCE_RPM_SORT_USER0_BC_EN			 (1L<<16)
2788#define BCE_RPM_SORT_USER0_MC_EN			 (1L<<17)
2789#define BCE_RPM_SORT_USER0_MC_HSH_EN			 (1L<<18)
2790#define BCE_RPM_SORT_USER0_PROM_EN			 (1L<<19)
2791#define BCE_RPM_SORT_USER0_VLAN_EN			 (0xfL<<20)
2792#define BCE_RPM_SORT_USER0_PROM_VLAN			 (1L<<24)
2793#define BCE_RPM_SORT_USER0_ENA				 (1L<<31)
2794
2795#define BCE_RPM_SORT_USER1				0x00001824
2796#define BCE_RPM_SORT_USER1_PM_EN			 (0xffffL<<0)
2797#define BCE_RPM_SORT_USER1_BC_EN			 (1L<<16)
2798#define BCE_RPM_SORT_USER1_MC_EN			 (1L<<17)
2799#define BCE_RPM_SORT_USER1_MC_HSH_EN			 (1L<<18)
2800#define BCE_RPM_SORT_USER1_PROM_EN			 (1L<<19)
2801#define BCE_RPM_SORT_USER1_VLAN_EN			 (0xfL<<20)
2802#define BCE_RPM_SORT_USER1_PROM_VLAN			 (1L<<24)
2803#define BCE_RPM_SORT_USER1_ENA				 (1L<<31)
2804
2805#define BCE_RPM_SORT_USER2				0x00001828
2806#define BCE_RPM_SORT_USER2_PM_EN			 (0xffffL<<0)
2807#define BCE_RPM_SORT_USER2_BC_EN			 (1L<<16)
2808#define BCE_RPM_SORT_USER2_MC_EN			 (1L<<17)
2809#define BCE_RPM_SORT_USER2_MC_HSH_EN			 (1L<<18)
2810#define BCE_RPM_SORT_USER2_PROM_EN			 (1L<<19)
2811#define BCE_RPM_SORT_USER2_VLAN_EN			 (0xfL<<20)
2812#define BCE_RPM_SORT_USER2_PROM_VLAN			 (1L<<24)
2813#define BCE_RPM_SORT_USER2_ENA				 (1L<<31)
2814
2815#define BCE_RPM_SORT_USER3				0x0000182c
2816#define BCE_RPM_SORT_USER3_PM_EN			 (0xffffL<<0)
2817#define BCE_RPM_SORT_USER3_BC_EN			 (1L<<16)
2818#define BCE_RPM_SORT_USER3_MC_EN			 (1L<<17)
2819#define BCE_RPM_SORT_USER3_MC_HSH_EN			 (1L<<18)
2820#define BCE_RPM_SORT_USER3_PROM_EN			 (1L<<19)
2821#define BCE_RPM_SORT_USER3_VLAN_EN			 (0xfL<<20)
2822#define BCE_RPM_SORT_USER3_PROM_VLAN			 (1L<<24)
2823#define BCE_RPM_SORT_USER3_ENA				 (1L<<31)
2824
2825#define BCE_RPM_STAT_L2_FILTER_DISCARDS		0x00001840
2826#define BCE_RPM_STAT_RULE_CHECKER_DISCARDS		0x00001844
2827#define BCE_RPM_STAT_IFINFTQDISCARDS			0x00001848
2828#define BCE_RPM_STAT_IFINMBUFDISCARD			0x0000184c
2829#define BCE_RPM_STAT_RULE_CHECKER_P4_HIT		0x00001850
2830#define BCE_RPM_STAT_AC0				0x00001880
2831#define BCE_RPM_STAT_AC1				0x00001884
2832#define BCE_RPM_STAT_AC2				0x00001888
2833#define BCE_RPM_STAT_AC3				0x0000188c
2834#define BCE_RPM_STAT_AC4				0x00001890
2835#define BCE_RPM_RC_CNTL_0				0x00001900
2836#define BCE_RPM_RC_CNTL_0_OFFSET			 (0xffL<<0)
2837#define BCE_RPM_RC_CNTL_0_CLASS			 (0x7L<<8)
2838#define BCE_RPM_RC_CNTL_0_PRIORITY			 (1L<<11)
2839#define BCE_RPM_RC_CNTL_0_P4				 (1L<<12)
2840#define BCE_RPM_RC_CNTL_0_HDR_TYPE			 (0x7L<<13)
2841#define BCE_RPM_RC_CNTL_0_HDR_TYPE_START		 (0L<<13)
2842#define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP			 (1L<<13)
2843#define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP			 (2L<<13)
2844#define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP			 (3L<<13)
2845#define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA		 (4L<<13)
2846#define BCE_RPM_RC_CNTL_0_COMP				 (0x3L<<16)
2847#define BCE_RPM_RC_CNTL_0_COMP_EQUAL			 (0L<<16)
2848#define BCE_RPM_RC_CNTL_0_COMP_NEQUAL			 (1L<<16)
2849#define BCE_RPM_RC_CNTL_0_COMP_GREATER			 (2L<<16)
2850#define BCE_RPM_RC_CNTL_0_COMP_LESS			 (3L<<16)
2851#define BCE_RPM_RC_CNTL_0_SBIT				 (1L<<19)
2852#define BCE_RPM_RC_CNTL_0_CMDSEL			 (0xfL<<20)
2853#define BCE_RPM_RC_CNTL_0_MAP				 (1L<<24)
2854#define BCE_RPM_RC_CNTL_0_DISCARD			 (1L<<25)
2855#define BCE_RPM_RC_CNTL_0_MASK				 (1L<<26)
2856#define BCE_RPM_RC_CNTL_0_P1				 (1L<<27)
2857#define BCE_RPM_RC_CNTL_0_P2				 (1L<<28)
2858#define BCE_RPM_RC_CNTL_0_P3				 (1L<<29)
2859#define BCE_RPM_RC_CNTL_0_NBIT				 (1L<<30)
2860
2861#define BCE_RPM_RC_VALUE_MASK_0			0x00001904
2862#define BCE_RPM_RC_VALUE_MASK_0_VALUE			 (0xffffL<<0)
2863#define BCE_RPM_RC_VALUE_MASK_0_MASK			 (0xffffL<<16)
2864
2865#define BCE_RPM_RC_CNTL_1				0x00001908
2866#define BCE_RPM_RC_CNTL_1_A				 (0x3ffffL<<0)
2867#define BCE_RPM_RC_CNTL_1_B				 (0xfffL<<19)
2868
2869#define BCE_RPM_RC_VALUE_MASK_1			0x0000190c
2870#define BCE_RPM_RC_CNTL_2				0x00001910
2871#define BCE_RPM_RC_CNTL_2_A				 (0x3ffffL<<0)
2872#define BCE_RPM_RC_CNTL_2_B				 (0xfffL<<19)
2873
2874#define BCE_RPM_RC_VALUE_MASK_2			0x00001914
2875#define BCE_RPM_RC_CNTL_3				0x00001918
2876#define BCE_RPM_RC_CNTL_3_A				 (0x3ffffL<<0)
2877#define BCE_RPM_RC_CNTL_3_B				 (0xfffL<<19)
2878
2879#define BCE_RPM_RC_VALUE_MASK_3			0x0000191c
2880#define BCE_RPM_RC_CNTL_4				0x00001920
2881#define BCE_RPM_RC_CNTL_4_A				 (0x3ffffL<<0)
2882#define BCE_RPM_RC_CNTL_4_B				 (0xfffL<<19)
2883
2884#define BCE_RPM_RC_VALUE_MASK_4			0x00001924
2885#define BCE_RPM_RC_CNTL_5				0x00001928
2886#define BCE_RPM_RC_CNTL_5_A				 (0x3ffffL<<0)
2887#define BCE_RPM_RC_CNTL_5_B				 (0xfffL<<19)
2888
2889#define BCE_RPM_RC_VALUE_MASK_5			0x0000192c
2890#define BCE_RPM_RC_CNTL_6				0x00001930
2891#define BCE_RPM_RC_CNTL_6_A				 (0x3ffffL<<0)
2892#define BCE_RPM_RC_CNTL_6_B				 (0xfffL<<19)
2893
2894#define BCE_RPM_RC_VALUE_MASK_6			0x00001934
2895#define BCE_RPM_RC_CNTL_7				0x00001938
2896#define BCE_RPM_RC_CNTL_7_A				 (0x3ffffL<<0)
2897#define BCE_RPM_RC_CNTL_7_B				 (0xfffL<<19)
2898
2899#define BCE_RPM_RC_VALUE_MASK_7			0x0000193c
2900#define BCE_RPM_RC_CNTL_8				0x00001940
2901#define BCE_RPM_RC_CNTL_8_A				 (0x3ffffL<<0)
2902#define BCE_RPM_RC_CNTL_8_B				 (0xfffL<<19)
2903
2904#define BCE_RPM_RC_VALUE_MASK_8			0x00001944
2905#define BCE_RPM_RC_CNTL_9				0x00001948
2906#define BCE_RPM_RC_CNTL_9_A				 (0x3ffffL<<0)
2907#define BCE_RPM_RC_CNTL_9_B				 (0xfffL<<19)
2908
2909#define BCE_RPM_RC_VALUE_MASK_9			0x0000194c
2910#define BCE_RPM_RC_CNTL_10				0x00001950
2911#define BCE_RPM_RC_CNTL_10_A				 (0x3ffffL<<0)
2912#define BCE_RPM_RC_CNTL_10_B				 (0xfffL<<19)
2913
2914#define BCE_RPM_RC_VALUE_MASK_10			0x00001954
2915#define BCE_RPM_RC_CNTL_11				0x00001958
2916#define BCE_RPM_RC_CNTL_11_A				 (0x3ffffL<<0)
2917#define BCE_RPM_RC_CNTL_11_B				 (0xfffL<<19)
2918
2919#define BCE_RPM_RC_VALUE_MASK_11			0x0000195c
2920#define BCE_RPM_RC_CNTL_12				0x00001960
2921#define BCE_RPM_RC_CNTL_12_A				 (0x3ffffL<<0)
2922#define BCE_RPM_RC_CNTL_12_B				 (0xfffL<<19)
2923
2924#define BCE_RPM_RC_VALUE_MASK_12			0x00001964
2925#define BCE_RPM_RC_CNTL_13				0x00001968
2926#define BCE_RPM_RC_CNTL_13_A				 (0x3ffffL<<0)
2927#define BCE_RPM_RC_CNTL_13_B				 (0xfffL<<19)
2928
2929#define BCE_RPM_RC_VALUE_MASK_13			0x0000196c
2930#define BCE_RPM_RC_CNTL_14				0x00001970
2931#define BCE_RPM_RC_CNTL_14_A				 (0x3ffffL<<0)
2932#define BCE_RPM_RC_CNTL_14_B				 (0xfffL<<19)
2933
2934#define BCE_RPM_RC_VALUE_MASK_14			0x00001974
2935#define BCE_RPM_RC_CNTL_15				0x00001978
2936#define BCE_RPM_RC_CNTL_15_A				 (0x3ffffL<<0)
2937#define BCE_RPM_RC_CNTL_15_B				 (0xfffL<<19)
2938
2939#define BCE_RPM_RC_VALUE_MASK_15			0x0000197c
2940#define BCE_RPM_RC_CONFIG				0x00001980
2941#define BCE_RPM_RC_CONFIG_RULE_ENABLE			 (0xffffL<<0)
2942#define BCE_RPM_RC_CONFIG_DEF_CLASS			 (0x7L<<24)
2943
2944#define BCE_RPM_DEBUG0					0x00001984
2945#define BCE_RPM_DEBUG0_FM_BCNT				 (0xffffL<<0)
2946#define BCE_RPM_DEBUG0_T_DATA_OFST_VLD			 (1L<<16)
2947#define BCE_RPM_DEBUG0_T_UDP_OFST_VLD			 (1L<<17)
2948#define BCE_RPM_DEBUG0_T_TCP_OFST_VLD			 (1L<<18)
2949#define BCE_RPM_DEBUG0_T_IP_OFST_VLD			 (1L<<19)
2950#define BCE_RPM_DEBUG0_IP_MORE_FRGMT			 (1L<<20)
2951#define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR		 (1L<<21)
2952#define BCE_RPM_DEBUG0_LLC_SNAP			 (1L<<22)
2953#define BCE_RPM_DEBUG0_FM_STARTED			 (1L<<23)
2954#define BCE_RPM_DEBUG0_DONE				 (1L<<24)
2955#define BCE_RPM_DEBUG0_WAIT_4_DONE			 (1L<<25)
2956#define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM			 (1L<<26)
2957#define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM		 (1L<<27)
2958#define BCE_RPM_DEBUG0_IGNORE_VLAN			 (1L<<28)
2959#define BCE_RPM_DEBUG0_RP_ENA_ACTIVE			 (1L<<31)
2960
2961#define BCE_RPM_DEBUG1					0x00001988
2962#define BCE_RPM_DEBUG1_FSM_CUR_ST			 (0xffffL<<0)
2963#define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE			 (0L<<0)
2964#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL		 (1L<<0)
2965#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC	 (2L<<0)
2966#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP		 (4L<<0)
2967#define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP		 (8L<<0)
2968#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START		 (16L<<0)
2969#define BCE_RPM_DEBUG1_FSM_CUR_ST_IP			 (32L<<0)
2970#define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP			 (64L<<0)
2971#define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP			 (128L<<0)
2972#define BCE_RPM_DEBUG1_FSM_CUR_ST_AH			 (256L<<0)
2973#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP			 (512L<<0)
2974#define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD		 (1024L<<0)
2975#define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA			 (2048L<<0)
2976#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY		 (0x2000L<<0)
2977#define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT		 (0x4000L<<0)
2978#define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT		 (0x8000L<<0)
2979#define BCE_RPM_DEBUG1_HDR_BCNT			 (0x7ffL<<16)
2980#define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D			 (1L<<28)
2981#define BCE_RPM_DEBUG1_VLAN_REMOVED_D2			 (1L<<29)
2982#define BCE_RPM_DEBUG1_VLAN_REMOVED_D1			 (1L<<30)
2983#define BCE_RPM_DEBUG1_EOF_0XTRA_WD			 (1L<<31)
2984
2985#define BCE_RPM_DEBUG2					0x0000198c
2986#define BCE_RPM_DEBUG2_CMD_HIT_VEC			 (0xffffL<<0)
2987#define BCE_RPM_DEBUG2_IP_BCNT				 (0xffL<<16)
2988#define BCE_RPM_DEBUG2_THIS_CMD_M4			 (1L<<24)
2989#define BCE_RPM_DEBUG2_THIS_CMD_M3			 (1L<<25)
2990#define BCE_RPM_DEBUG2_THIS_CMD_M2			 (1L<<26)
2991#define BCE_RPM_DEBUG2_THIS_CMD_M1			 (1L<<27)
2992#define BCE_RPM_DEBUG2_IPIPE_EMPTY			 (1L<<28)
2993#define BCE_RPM_DEBUG2_FM_DISCARD			 (1L<<29)
2994#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2		 (1L<<30)
2995#define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1		 (1L<<31)
2996
2997#define BCE_RPM_DEBUG3					0x00001990
2998#define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR			 (0x1ffL<<0)
2999#define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT		 (1L<<9)
3000#define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT		 (1L<<10)
3001#define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT		 (1L<<11)
3002#define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ		 (1L<<12)
3003#define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ		 (1L<<13)
3004#define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL		 (1L<<14)
3005#define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP		 (1L<<15)
3006#define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT		 (0xfL<<16)
3007#define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL		 (1L<<21)
3008#define BCE_RPM_DEBUG3_DROP_NXT_VLD			 (1L<<22)
3009#define BCE_RPM_DEBUG3_DROP_NXT			 (1L<<23)
3010#define BCE_RPM_DEBUG3_FTQ_FSM				 (0x3L<<24)
3011#define BCE_RPM_DEBUG3_FTQ_FSM_IDLE			 (0x0L<<24)
3012#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK		 (0x1L<<24)
3013#define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE		 (0x2L<<24)
3014#define BCE_RPM_DEBUG3_MBWRITE_FSM			 (0x3L<<26)
3015#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF		 (0x0L<<26)
3016#define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF		 (0x1L<<26)
3017#define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA		 (0x2L<<26)
3018#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA		 (0x3L<<26)
3019#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF		 (0x4L<<26)
3020#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK		 (0x5L<<26)
3021#define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD	 (0x6L<<26)
3022#define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE		 (0x7L<<26)
3023#define BCE_RPM_DEBUG3_MBFREE_FSM			 (1L<<29)
3024#define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE			 (0L<<29)
3025#define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK		 (1L<<29)
3026#define BCE_RPM_DEBUG3_MBALLOC_FSM			 (1L<<30)
3027#define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF		 (0x0L<<30)
3028#define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF		 (0x1L<<30)
3029#define BCE_RPM_DEBUG3_CCODE_EOF_ERROR			 (1L<<31)
3030
3031#define BCE_RPM_DEBUG4					0x00001994
3032#define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER		 (0x1ffffffL<<0)
3033#define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE			 (0x7L<<25)
3034#define BCE_RPM_DEBUG4_MBWRITE_FSM			 (0x7L<<28)
3035#define BCE_RPM_DEBUG4_DFIFO_EMPTY			 (1L<<31)
3036
3037#define BCE_RPM_DEBUG5					0x00001998
3038#define BCE_RPM_DEBUG5_RDROP_WPTR			 (0x1fL<<0)
3039#define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR			 (0x1fL<<5)
3040#define BCE_RPM_DEBUG5_RDROP_MC_RPTR			 (0x1fL<<10)
3041#define BCE_RPM_DEBUG5_RDROP_RC_RPTR			 (0x1fL<<15)
3042#define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY		 (1L<<20)
3043#define BCE_RPM_DEBUG5_RDROP_MC_EMPTY			 (1L<<21)
3044#define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR	 (1L<<22)
3045#define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT		 (1L<<23)
3046#define BCE_RPM_DEBUG5_HOLDREG_DISCARD			 (1L<<24)
3047#define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL		 (1L<<25)
3048#define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY		 (1L<<26)
3049#define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY		 (1L<<27)
3050#define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY		 (1L<<28)
3051#define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY		 (1L<<29)
3052#define BCE_RPM_DEBUG5_HOLDREG_FULL_T			 (1L<<30)
3053#define BCE_RPM_DEBUG5_HOLDREG_RD			 (1L<<31)
3054
3055#define BCE_RPM_DEBUG6					0x0000199c
3056#define BCE_RPM_DEBUG6_ACPI_VEC			 (0xffffL<<0)
3057#define BCE_RPM_DEBUG6_VEC				 (0xffffL<<16)
3058
3059#define BCE_RPM_DEBUG7					0x000019a0
3060#define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC		 (0xffffffffL<<0)
3061
3062#define BCE_RPM_DEBUG8					0x000019a4
3063#define BCE_RPM_DEBUG8_PS_ACPI_FSM			 (0xfL<<0)
3064#define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE		 (0L<<0)
3065#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR		 (1L<<0)
3066#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR		 (2L<<0)
3067#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR		 (3L<<0)
3068#define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF	 (4L<<0)
3069#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA		 (5L<<0)
3070#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR		 (6L<<0)
3071#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR		 (7L<<0)
3072#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR		 (8L<<0)
3073#define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR		 (9L<<0)
3074#define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF		 (10L<<0)
3075#define BCE_RPM_DEBUG8_COMPARE_AT_W0			 (1L<<4)
3076#define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA		 (1L<<5)
3077#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT		 (1L<<6)
3078#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3		 (1L<<7)
3079#define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2		 (1L<<8)
3080#define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES		 (1L<<9)
3081#define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES		 (1L<<10)
3082#define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES		 (1L<<11)
3083#define BCE_RPM_DEBUG8_EOF_DET				 (1L<<12)
3084#define BCE_RPM_DEBUG8_SOF_DET				 (1L<<13)
3085#define BCE_RPM_DEBUG8_WAIT_4_SOF			 (1L<<14)
3086#define BCE_RPM_DEBUG8_ALL_DONE			 (1L<<15)
3087#define BCE_RPM_DEBUG8_THBUF_ADDR			 (0x7fL<<16)
3088#define BCE_RPM_DEBUG8_BYTE_CTR			 (0xffL<<24)
3089
3090#define BCE_RPM_DEBUG9					0x000019a8
3091#define BCE_RPM_DEBUG9_OUTFIFO_COUNT			 (0x7L<<0)
3092#define BCE_RPM_DEBUG9_RDE_ACPI_RDY			 (1L<<3)
3093#define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT			 (0x7L<<4)
3094#define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED	 (1L<<28)
3095#define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED		 (1L<<29)
3096#define BCE_RPM_DEBUG9_ACPI_MATCH_INT			 (1L<<30)
3097#define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN			 (1L<<31)
3098
3099#define BCE_RPM_ACPI_DBG_BUF_W00			0x000019c0
3100#define BCE_RPM_ACPI_DBG_BUF_W01			0x000019c4
3101#define BCE_RPM_ACPI_DBG_BUF_W02			0x000019c8
3102#define BCE_RPM_ACPI_DBG_BUF_W03			0x000019cc
3103#define BCE_RPM_ACPI_DBG_BUF_W10			0x000019d0
3104#define BCE_RPM_ACPI_DBG_BUF_W11			0x000019d4
3105#define BCE_RPM_ACPI_DBG_BUF_W12			0x000019d8
3106#define BCE_RPM_ACPI_DBG_BUF_W13			0x000019dc
3107#define BCE_RPM_ACPI_DBG_BUF_W20			0x000019e0
3108#define BCE_RPM_ACPI_DBG_BUF_W21			0x000019e4
3109#define BCE_RPM_ACPI_DBG_BUF_W22			0x000019e8
3110#define BCE_RPM_ACPI_DBG_BUF_W23			0x000019ec
3111#define BCE_RPM_ACPI_DBG_BUF_W30			0x000019f0
3112#define BCE_RPM_ACPI_DBG_BUF_W31			0x000019f4
3113#define BCE_RPM_ACPI_DBG_BUF_W32			0x000019f8
3114#define BCE_RPM_ACPI_DBG_BUF_W33			0x000019fc
3115
3116
3117/*
3118 *  rlup_reg definition
3119 *  offset: 0x2000
3120 */
3121#define BCE_RLUP_FTQ_CMD					0x000023f8
3122#define BCE_RLUP_FTQ_CTL					0x000023fc
3123#define BCE_RLUP_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
3124#define BCE_RLUP_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
3125
3126
3127
3128/*
3129 *  rdma_reg definition
3130 *  offset: 0x2c00
3131 */
3132#define BCE_RDMA_FTQ_CMD					0x00002ff8
3133#define BCE_RDMA_FTQ_CTL					0x00002ffc
3134#define BCE_RDMA_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
3135#define BCE_RDMA_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
3136
3137
3138
3139/*
3140 *  timer_reg definition
3141 *  offset: 0x4400
3142 */
3143
3144#define BCE_TIMER_COMMAND					0x00004400
3145#define BCE_TIMER_COMMAND_ENABLED			(1L<<0)
3146
3147#define BCE_TIMER_STATUS					0x00004404
3148#define BCE_TIMER_STATUS_CMP_FTQ_WAIT 		(1L<<0)
3149#define BCE_TIMER_STATUS_POLL_PASS_CNT		(1L<<8)
3150#define BCE_TIMER_STATUS_TMR1_CNT			(1L<<9)
3151#define BCE_TIMER_STATUS_TMR2_CNT			(1L<<10)
3152#define BCE_TIMER_STATUS_TMR3_CNT			(1L<<11)
3153#define BCE_TIMER_STATUS_TMR4_CNT			(1L<<12)
3154#define BCE_TIMER_STATUS_TMR5_CNT			(1L<<13)
3155
3156#define BCE_TIMER_25MHZ_FREE_RUN			0x00004448
3157
3158
3159/*
3160 *  tsch_reg definition
3161 *  offset: 0x4c00
3162 */
3163
3164#define BCE_TSCH_FTQ_CMD					0x00004ff8
3165#define BCE_TSCH_FTQ_CTL					0x00004ffc
3166#define BCE_TSCH_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
3167#define BCE_TSCH_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
3168
3169
3170
3171/*
3172 *  rbuf_reg definition
3173 *  offset: 0x200000
3174 */
3175#define BCE_RBUF_COMMAND				0x00200000
3176#define BCE_RBUF_COMMAND_ENABLED			 (1L<<0)
3177#define BCE_RBUF_COMMAND_FREE_INIT			 (1L<<1)
3178#define BCE_RBUF_COMMAND_RAM_INIT			 (1L<<2)
3179#define BCE_RBUF_COMMAND_OVER_FREE			 (1L<<4)
3180#define BCE_RBUF_COMMAND_ALLOC_REQ			 (1L<<5)
3181
3182#define BCE_RBUF_STATUS1				0x00200004
3183#define BCE_RBUF_STATUS1_FREE_COUNT			 (0x3ffL<<0)
3184
3185#define BCE_RBUF_STATUS2				0x00200008
3186#define BCE_RBUF_STATUS2_FREE_TAIL			 (0x3ffL<<0)
3187#define BCE_RBUF_STATUS2_FREE_HEAD			 (0x3ffL<<16)
3188
3189#define BCE_RBUF_CONFIG				0x0020000c
3190#define BCE_RBUF_CONFIG_XOFF_TRIP			 (0x3ffL<<0)
3191#define BCE_RBUF_CONFIG_XON_TRIP			 (0x3ffL<<16)
3192
3193#define BCE_RBUF_FW_BUF_ALLOC				0x00200010
3194#define BCE_RBUF_FW_BUF_ALLOC_VALUE			 (0x1ffL<<7)
3195
3196#define BCE_RBUF_FW_BUF_FREE				0x00200014
3197#define BCE_RBUF_FW_BUF_FREE_COUNT			 (0x7fL<<0)
3198#define BCE_RBUF_FW_BUF_FREE_TAIL			 (0x1ffL<<7)
3199#define BCE_RBUF_FW_BUF_FREE_HEAD			 (0x1ffL<<16)
3200
3201#define BCE_RBUF_FW_BUF_SEL				0x00200018
3202#define BCE_RBUF_FW_BUF_SEL_COUNT			 (0x7fL<<0)
3203#define BCE_RBUF_FW_BUF_SEL_TAIL			 (0x1ffL<<7)
3204#define BCE_RBUF_FW_BUF_SEL_HEAD			 (0x1ffL<<16)
3205
3206#define BCE_RBUF_CONFIG2				0x0020001c
3207#define BCE_RBUF_CONFIG2_MAC_DROP_TRIP			 (0x3ffL<<0)
3208#define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP			 (0x3ffL<<16)
3209
3210#define BCE_RBUF_CONFIG3				0x00200020
3211#define BCE_RBUF_CONFIG3_CU_DROP_TRIP			 (0x3ffL<<0)
3212#define BCE_RBUF_CONFIG3_CU_KEEP_TRIP			 (0x3ffL<<16)
3213
3214#define BCE_RBUF_PKT_DATA				0x00208000
3215#define BCE_RBUF_CLIST_DATA				0x00210000
3216#define BCE_RBUF_BUF_DATA				0x00220000
3217
3218
3219/*
3220 *  rv2p_reg definition
3221 *  offset: 0x2800
3222 */
3223#define BCE_RV2P_COMMAND				0x00002800
3224#define BCE_RV2P_COMMAND_ENABLED			 (1L<<0)
3225#define BCE_RV2P_COMMAND_PROC1_INTRPT			 (1L<<1)
3226#define BCE_RV2P_COMMAND_PROC2_INTRPT			 (1L<<2)
3227#define BCE_RV2P_COMMAND_ABORT0			 (1L<<4)
3228#define BCE_RV2P_COMMAND_ABORT1			 (1L<<5)
3229#define BCE_RV2P_COMMAND_ABORT2			 (1L<<6)
3230#define BCE_RV2P_COMMAND_ABORT3			 (1L<<7)
3231#define BCE_RV2P_COMMAND_ABORT4			 (1L<<8)
3232#define BCE_RV2P_COMMAND_ABORT5			 (1L<<9)
3233#define BCE_RV2P_COMMAND_PROC1_RESET			 (1L<<16)
3234#define BCE_RV2P_COMMAND_PROC2_RESET			 (1L<<17)
3235#define BCE_RV2P_COMMAND_CTXIF_RESET			 (1L<<18)
3236
3237#define BCE_RV2P_STATUS				0x00002804
3238#define BCE_RV2P_STATUS_ALWAYS_0			 (1L<<0)
3239#define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT		 (1L<<8)
3240#define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT		 (1L<<9)
3241#define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT		 (1L<<10)
3242#define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT		 (1L<<11)
3243#define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT		 (1L<<12)
3244#define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT		 (1L<<13)
3245
3246#define BCE_RV2P_CONFIG				0x00002808
3247#define BCE_RV2P_CONFIG_STALL_PROC1			 (1L<<0)
3248#define BCE_RV2P_CONFIG_STALL_PROC2			 (1L<<1)
3249#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0		 (1L<<8)
3250#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1		 (1L<<9)
3251#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2		 (1L<<10)
3252#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3		 (1L<<11)
3253#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4		 (1L<<12)
3254#define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5		 (1L<<13)
3255#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0		 (1L<<16)
3256#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1		 (1L<<17)
3257#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2		 (1L<<18)
3258#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3		 (1L<<19)
3259#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4		 (1L<<20)
3260#define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5		 (1L<<21)
3261#define BCE_RV2P_CONFIG_PAGE_SIZE			 (0xfL<<24)
3262#define BCE_RV2P_CONFIG_PAGE_SIZE_256			 (0L<<24)
3263#define BCE_RV2P_CONFIG_PAGE_SIZE_512			 (1L<<24)
3264#define BCE_RV2P_CONFIG_PAGE_SIZE_1K			 (2L<<24)
3265#define BCE_RV2P_CONFIG_PAGE_SIZE_2K			 (3L<<24)
3266#define BCE_RV2P_CONFIG_PAGE_SIZE_4K			 (4L<<24)
3267#define BCE_RV2P_CONFIG_PAGE_SIZE_8K			 (5L<<24)
3268#define BCE_RV2P_CONFIG_PAGE_SIZE_16K			 (6L<<24)
3269#define BCE_RV2P_CONFIG_PAGE_SIZE_32K			 (7L<<24)
3270#define BCE_RV2P_CONFIG_PAGE_SIZE_64K			 (8L<<24)
3271#define BCE_RV2P_CONFIG_PAGE_SIZE_128K			 (9L<<24)
3272#define BCE_RV2P_CONFIG_PAGE_SIZE_256K			 (10L<<24)
3273#define BCE_RV2P_CONFIG_PAGE_SIZE_512K			 (11L<<24)
3274#define BCE_RV2P_CONFIG_PAGE_SIZE_1M			 (12L<<24)
3275
3276#define BCE_RV2P_GEN_BFR_ADDR_0			0x00002810
3277#define BCE_RV2P_GEN_BFR_ADDR_0_VALUE			 (0xffffL<<16)
3278
3279#define BCE_RV2P_GEN_BFR_ADDR_1			0x00002814
3280#define BCE_RV2P_GEN_BFR_ADDR_1_VALUE			 (0xffffL<<16)
3281
3282#define BCE_RV2P_GEN_BFR_ADDR_2			0x00002818
3283#define BCE_RV2P_GEN_BFR_ADDR_2_VALUE			 (0xffffL<<16)
3284
3285#define BCE_RV2P_GEN_BFR_ADDR_3			0x0000281c
3286#define BCE_RV2P_GEN_BFR_ADDR_3_VALUE			 (0xffffL<<16)
3287
3288#define BCE_RV2P_INSTR_HIGH				0x00002830
3289#define BCE_RV2P_INSTR_HIGH_HIGH			 (0x1fL<<0)
3290
3291#define BCE_RV2P_INSTR_LOW				0x00002834
3292#define BCE_RV2P_PROC1_ADDR_CMD			0x00002838
3293#define BCE_RV2P_PROC1_ADDR_CMD_ADD			 (0x3ffL<<0)
3294#define BCE_RV2P_PROC1_ADDR_CMD_RDWR			 (1L<<31)
3295
3296#define BCE_RV2P_PROC2_ADDR_CMD			0x0000283c
3297#define BCE_RV2P_PROC2_ADDR_CMD_ADD			 (0x3ffL<<0)
3298#define BCE_RV2P_PROC2_ADDR_CMD_RDWR			 (1L<<31)
3299
3300#define BCE_RV2P_PROC1_GRC_DEBUG			0x00002840
3301#define BCE_RV2P_PROC2_GRC_DEBUG			0x00002844
3302#define BCE_RV2P_GRC_PROC_DEBUG			0x00002848
3303#define BCE_RV2P_DEBUG_VECT_PEEK			0x0000284c
3304#define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
3305#define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
3306#define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)
3307#define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
3308#define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
3309#define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)
3310
3311#define BCE_RV2P_PFTQ_DATA				0x00002b40
3312#define BCE_RV2P_PFTQ_CMD				0x00002b78
3313#define BCE_RV2P_PFTQ_CMD_OFFSET			 (0x3ffL<<0)
3314#define BCE_RV2P_PFTQ_CMD_WR_TOP			 (1L<<10)
3315#define BCE_RV2P_PFTQ_CMD_WR_TOP_0			 (0L<<10)
3316#define BCE_RV2P_PFTQ_CMD_WR_TOP_1			 (1L<<10)
3317#define BCE_RV2P_PFTQ_CMD_SFT_RESET			 (1L<<25)
3318#define BCE_RV2P_PFTQ_CMD_RD_DATA			 (1L<<26)
3319#define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN			 (1L<<27)
3320#define BCE_RV2P_PFTQ_CMD_ADD_DATA			 (1L<<28)
3321#define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR		 (1L<<29)
3322#define BCE_RV2P_PFTQ_CMD_POP				 (1L<<30)
3323#define BCE_RV2P_PFTQ_CMD_BUSY				 (1L<<31)
3324
3325#define BCE_RV2P_PFTQ_CTL				0x00002b7c
3326#define BCE_RV2P_PFTQ_CTL_INTERVENE			 (1L<<0)
3327#define BCE_RV2P_PFTQ_CTL_OVERFLOW			 (1L<<1)
3328#define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3329#define BCE_RV2P_PFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
3330#define BCE_RV2P_PFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
3331
3332#define BCE_RV2P_TFTQ_DATA				0x00002b80
3333#define BCE_RV2P_TFTQ_CMD				0x00002bb8
3334#define BCE_RV2P_TFTQ_CMD_OFFSET			 (0x3ffL<<0)
3335#define BCE_RV2P_TFTQ_CMD_WR_TOP			 (1L<<10)
3336#define BCE_RV2P_TFTQ_CMD_WR_TOP_0			 (0L<<10)
3337#define BCE_RV2P_TFTQ_CMD_WR_TOP_1			 (1L<<10)
3338#define BCE_RV2P_TFTQ_CMD_SFT_RESET			 (1L<<25)
3339#define BCE_RV2P_TFTQ_CMD_RD_DATA			 (1L<<26)
3340#define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN			 (1L<<27)
3341#define BCE_RV2P_TFTQ_CMD_ADD_DATA			 (1L<<28)
3342#define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR		 (1L<<29)
3343#define BCE_RV2P_TFTQ_CMD_POP				 (1L<<30)
3344#define BCE_RV2P_TFTQ_CMD_BUSY				 (1L<<31)
3345
3346#define BCE_RV2P_TFTQ_CTL				0x00002bbc
3347#define BCE_RV2P_TFTQ_CTL_INTERVENE			 (1L<<0)
3348#define BCE_RV2P_TFTQ_CTL_OVERFLOW			 (1L<<1)
3349#define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3350#define BCE_RV2P_TFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
3351#define BCE_RV2P_TFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
3352
3353#define BCE_RV2P_MFTQ_DATA				0x00002bc0
3354#define BCE_RV2P_MFTQ_CMD				0x00002bf8
3355#define BCE_RV2P_MFTQ_CMD_OFFSET			 (0x3ffL<<0)
3356#define BCE_RV2P_MFTQ_CMD_WR_TOP			 (1L<<10)
3357#define BCE_RV2P_MFTQ_CMD_WR_TOP_0			 (0L<<10)
3358#define BCE_RV2P_MFTQ_CMD_WR_TOP_1			 (1L<<10)
3359#define BCE_RV2P_MFTQ_CMD_SFT_RESET			 (1L<<25)
3360#define BCE_RV2P_MFTQ_CMD_RD_DATA			 (1L<<26)
3361#define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN			 (1L<<27)
3362#define BCE_RV2P_MFTQ_CMD_ADD_DATA			 (1L<<28)
3363#define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR		 (1L<<29)
3364#define BCE_RV2P_MFTQ_CMD_POP				 (1L<<30)
3365#define BCE_RV2P_MFTQ_CMD_BUSY				 (1L<<31)
3366
3367#define BCE_RV2P_MFTQ_CTL				0x00002bfc
3368#define BCE_RV2P_MFTQ_CTL_INTERVENE			 (1L<<0)
3369#define BCE_RV2P_MFTQ_CTL_OVERFLOW			 (1L<<1)
3370#define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3371#define BCE_RV2P_MFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
3372#define BCE_RV2P_MFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
3373
3374
3375
3376/*
3377 *  mq_reg definition
3378 *  offset: 0x3c00
3379 */
3380#define BCE_MQ_COMMAND					0x00003c00
3381#define BCE_MQ_COMMAND_ENABLED				 (1L<<0)
3382#define BCE_MQ_COMMAND_OVERFLOW			 (1L<<4)
3383#define BCE_MQ_COMMAND_WR_ERROR			 (1L<<5)
3384#define BCE_MQ_COMMAND_RD_ERROR			 (1L<<6)
3385
3386#define BCE_MQ_STATUS					0x00003c04
3387#define BCE_MQ_STATUS_CTX_ACCESS_STAT			 (1L<<16)
3388#define BCE_MQ_STATUS_CTX_ACCESS64_STAT		 (1L<<17)
3389#define BCE_MQ_STATUS_PCI_STALL_STAT			 (1L<<18)
3390
3391#define BCE_MQ_CONFIG					0x00003c08
3392#define BCE_MQ_CONFIG_TX_HIGH_PRI			 (1L<<0)
3393#define BCE_MQ_CONFIG_HALT_DIS				 (1L<<1)
3394#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE			 (0x7L<<4)
3395#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256		 (0L<<4)
3396#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512		 (1L<<4)
3397#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K		 (2L<<4)
3398#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K		 (3L<<4)
3399#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K		 (4L<<4)
3400#define BCE_MQ_CONFIG_MAX_DEPTH			 (0x7fL<<8)
3401#define BCE_MQ_CONFIG_CUR_DEPTH			 (0x7fL<<20)
3402
3403#define BCE_MQ_ENQUEUE1				0x00003c0c
3404#define BCE_MQ_ENQUEUE1_OFFSET				 (0x3fL<<2)
3405#define BCE_MQ_ENQUEUE1_CID				 (0x3fffL<<8)
3406#define BCE_MQ_ENQUEUE1_BYTE_MASK			 (0xfL<<24)
3407#define BCE_MQ_ENQUEUE1_KNL_MODE			 (1L<<28)
3408
3409#define BCE_MQ_ENQUEUE2				0x00003c10
3410#define BCE_MQ_BAD_WR_ADDR				0x00003c14
3411#define BCE_MQ_BAD_RD_ADDR				0x00003c18
3412#define BCE_MQ_KNL_BYP_WIND_START			0x00003c1c
3413#define BCE_MQ_KNL_BYP_WIND_START_VALUE		 (0xfffffL<<12)
3414
3415#define BCE_MQ_KNL_WIND_END				0x00003c20
3416#define BCE_MQ_KNL_WIND_END_VALUE			 (0xffffffL<<8)
3417
3418#define BCE_MQ_KNL_WRITE_MASK1				0x00003c24
3419#define BCE_MQ_KNL_TX_MASK1				0x00003c28
3420#define BCE_MQ_KNL_CMD_MASK1				0x00003c2c
3421#define BCE_MQ_KNL_COND_ENQUEUE_MASK1			0x00003c30
3422#define BCE_MQ_KNL_RX_V2P_MASK1			0x00003c34
3423#define BCE_MQ_KNL_WRITE_MASK2				0x00003c38
3424#define BCE_MQ_KNL_TX_MASK2				0x00003c3c
3425#define BCE_MQ_KNL_CMD_MASK2				0x00003c40
3426#define BCE_MQ_KNL_COND_ENQUEUE_MASK2			0x00003c44
3427#define BCE_MQ_KNL_RX_V2P_MASK2			0x00003c48
3428#define BCE_MQ_KNL_BYP_WRITE_MASK1			0x00003c4c
3429#define BCE_MQ_KNL_BYP_TX_MASK1			0x00003c50
3430#define BCE_MQ_KNL_BYP_CMD_MASK1			0x00003c54
3431#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1		0x00003c58
3432#define BCE_MQ_KNL_BYP_RX_V2P_MASK1			0x00003c5c
3433#define BCE_MQ_KNL_BYP_WRITE_MASK2			0x00003c60
3434#define BCE_MQ_KNL_BYP_TX_MASK2			0x00003c64
3435#define BCE_MQ_KNL_BYP_CMD_MASK2			0x00003c68
3436#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2		0x00003c6c
3437#define BCE_MQ_KNL_BYP_RX_V2P_MASK2			0x00003c70
3438#define BCE_MQ_MEM_WR_ADDR				0x00003c74
3439#define BCE_MQ_MEM_WR_ADDR_VALUE			 (0x3fL<<0)
3440
3441#define BCE_MQ_MEM_WR_DATA0				0x00003c78
3442#define BCE_MQ_MEM_WR_DATA0_VALUE			 (0xffffffffL<<0)
3443
3444#define BCE_MQ_MEM_WR_DATA1				0x00003c7c
3445#define BCE_MQ_MEM_WR_DATA1_VALUE			 (0xffffffffL<<0)
3446
3447#define BCE_MQ_MEM_WR_DATA2				0x00003c80
3448#define BCE_MQ_MEM_WR_DATA2_VALUE			 (0x3fffffffL<<0)
3449
3450#define BCE_MQ_MEM_RD_ADDR				0x00003c84
3451#define BCE_MQ_MEM_RD_ADDR_VALUE			 (0x3fL<<0)
3452
3453#define BCE_MQ_MEM_RD_DATA0				0x00003c88
3454#define BCE_MQ_MEM_RD_DATA0_VALUE			 (0xffffffffL<<0)
3455
3456#define BCE_MQ_MEM_RD_DATA1				0x00003c8c
3457#define BCE_MQ_MEM_RD_DATA1_VALUE			 (0xffffffffL<<0)
3458
3459#define BCE_MQ_MEM_RD_DATA2				0x00003c90
3460#define BCE_MQ_MEM_RD_DATA2_VALUE			 (0x3fffffffL<<0)
3461
3462
3463/*
3464 *  csch_reg definition
3465 *  offset: 0x4000
3466 */
3467#define BCE_CSCH_COMMAND				0x00004000
3468#define BCE_CSCH_CH_FTQ_CMD				0x000043f8
3469#define BCE_CSCH_CH_FTQ_CTL				0x000043fc
3470#define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH	(0x3ffL<<12)
3471#define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH	(0x3ffL<<22)
3472
3473
3474/*
3475 *  tbdr_reg definition
3476 *  offset: 0x5000
3477 */
3478#define BCE_TBDR_COMMAND				0x00005000
3479#define BCE_TBDR_COMMAND_ENABLE			 (1L<<0)
3480#define BCE_TBDR_COMMAND_SOFT_RST			 (1L<<1)
3481#define BCE_TBDR_COMMAND_MSTR_ABORT			 (1L<<4)
3482
3483#define BCE_TBDR_STATUS				0x00005004
3484#define BCE_TBDR_STATUS_DMA_WAIT			 (1L<<0)
3485#define BCE_TBDR_STATUS_FTQ_WAIT			 (1L<<1)
3486#define BCE_TBDR_STATUS_FIFO_OVERFLOW			 (1L<<2)
3487#define BCE_TBDR_STATUS_FIFO_UNDERFLOW			 (1L<<3)
3488#define BCE_TBDR_STATUS_SEARCHMISS_ERROR		 (1L<<4)
3489#define BCE_TBDR_STATUS_FTQ_ENTRY_CNT			 (1L<<5)
3490#define BCE_TBDR_STATUS_BURST_CNT			 (1L<<6)
3491
3492#define BCE_TBDR_CONFIG				0x00005008
3493#define BCE_TBDR_CONFIG_MAX_BDS			 (0xffL<<0)
3494#define BCE_TBDR_CONFIG_SWAP_MODE			 (1L<<8)
3495#define BCE_TBDR_CONFIG_PRIORITY			 (1L<<9)
3496#define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS		 (1L<<10)
3497#define BCE_TBDR_CONFIG_PAGE_SIZE			 (0xfL<<24)
3498#define BCE_TBDR_CONFIG_PAGE_SIZE_256			 (0L<<24)
3499#define BCE_TBDR_CONFIG_PAGE_SIZE_512			 (1L<<24)
3500#define BCE_TBDR_CONFIG_PAGE_SIZE_1K			 (2L<<24)
3501#define BCE_TBDR_CONFIG_PAGE_SIZE_2K			 (3L<<24)
3502#define BCE_TBDR_CONFIG_PAGE_SIZE_4K			 (4L<<24)
3503#define BCE_TBDR_CONFIG_PAGE_SIZE_8K			 (5L<<24)
3504#define BCE_TBDR_CONFIG_PAGE_SIZE_16K			 (6L<<24)
3505#define BCE_TBDR_CONFIG_PAGE_SIZE_32K			 (7L<<24)
3506#define BCE_TBDR_CONFIG_PAGE_SIZE_64K			 (8L<<24)
3507#define BCE_TBDR_CONFIG_PAGE_SIZE_128K			 (9L<<24)
3508#define BCE_TBDR_CONFIG_PAGE_SIZE_256K			 (10L<<24)
3509#define BCE_TBDR_CONFIG_PAGE_SIZE_512K			 (11L<<24)
3510#define BCE_TBDR_CONFIG_PAGE_SIZE_1M			 (12L<<24)
3511
3512#define BCE_TBDR_DEBUG_VECT_PEEK			0x0000500c
3513#define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
3514#define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
3515#define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)
3516#define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
3517#define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
3518#define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)
3519
3520#define BCE_TBDR_FTQ_DATA				0x000053c0
3521#define BCE_TBDR_FTQ_CMD				0x000053f8
3522#define BCE_TBDR_FTQ_CMD_OFFSET			 (0x3ffL<<0)
3523#define BCE_TBDR_FTQ_CMD_WR_TOP			 (1L<<10)
3524#define BCE_TBDR_FTQ_CMD_WR_TOP_0			 (0L<<10)
3525#define BCE_TBDR_FTQ_CMD_WR_TOP_1			 (1L<<10)
3526#define BCE_TBDR_FTQ_CMD_SFT_RESET			 (1L<<25)
3527#define BCE_TBDR_FTQ_CMD_RD_DATA			 (1L<<26)
3528#define BCE_TBDR_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
3529#define BCE_TBDR_FTQ_CMD_ADD_DATA			 (1L<<28)
3530#define BCE_TBDR_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
3531#define BCE_TBDR_FTQ_CMD_POP				 (1L<<30)
3532#define BCE_TBDR_FTQ_CMD_BUSY				 (1L<<31)
3533
3534#define BCE_TBDR_FTQ_CTL				0x000053fc
3535#define BCE_TBDR_FTQ_CTL_INTERVENE			 (1L<<0)
3536#define BCE_TBDR_FTQ_CTL_OVERFLOW			 (1L<<1)
3537#define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3538#define BCE_TBDR_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
3539#define BCE_TBDR_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
3540
3541
3542
3543/*
3544 *  tdma_reg definition
3545 *  offset: 0x5c00
3546 */
3547#define BCE_TDMA_COMMAND				0x00005c00
3548#define BCE_TDMA_COMMAND_ENABLED			 (1L<<0)
3549#define BCE_TDMA_COMMAND_MASTER_ABORT			 (1L<<4)
3550#define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT		 (1L<<7)
3551
3552#define BCE_TDMA_STATUS				0x00005c04
3553#define BCE_TDMA_STATUS_DMA_WAIT			 (1L<<0)
3554#define BCE_TDMA_STATUS_PAYLOAD_WAIT			 (1L<<1)
3555#define BCE_TDMA_STATUS_PATCH_FTQ_WAIT			 (1L<<2)
3556#define BCE_TDMA_STATUS_LOCK_WAIT			 (1L<<3)
3557#define BCE_TDMA_STATUS_FTQ_ENTRY_CNT			 (1L<<16)
3558#define BCE_TDMA_STATUS_BURST_CNT			 (1L<<17)
3559
3560#define BCE_TDMA_CONFIG				0x00005c08
3561#define BCE_TDMA_CONFIG_ONE_DMA			 (1L<<0)
3562#define BCE_TDMA_CONFIG_ONE_RECORD			 (1L<<1)
3563#define BCE_TDMA_CONFIG_LIMIT_SZ			 (0xfL<<4)
3564#define BCE_TDMA_CONFIG_LIMIT_SZ_64			 (0L<<4)
3565#define BCE_TDMA_CONFIG_LIMIT_SZ_128			 (0x4L<<4)
3566#define BCE_TDMA_CONFIG_LIMIT_SZ_256			 (0x6L<<4)
3567#define BCE_TDMA_CONFIG_LIMIT_SZ_512			 (0x8L<<4)
3568#define BCE_TDMA_CONFIG_LINE_SZ			 (0xfL<<8)
3569#define BCE_TDMA_CONFIG_LINE_SZ_64			 (0L<<8)
3570#define BCE_TDMA_CONFIG_LINE_SZ_128			 (4L<<8)
3571#define BCE_TDMA_CONFIG_LINE_SZ_256			 (6L<<8)
3572#define BCE_TDMA_CONFIG_LINE_SZ_512			 (8L<<8)
3573#define BCE_TDMA_CONFIG_ALIGN_ENA			 (1L<<15)
3574#define BCE_TDMA_CONFIG_CHK_L2_BD			 (1L<<16)
3575#define BCE_TDMA_CONFIG_FIFO_CMP			 (0xfL<<20)
3576
3577#define BCE_TDMA_PAYLOAD_PROD				0x00005c0c
3578#define BCE_TDMA_PAYLOAD_PROD_VALUE			 (0x1fffL<<3)
3579
3580#define BCE_TDMA_DBG_WATCHDOG				0x00005c10
3581#define BCE_TDMA_DBG_TRIGGER				0x00005c14
3582#define BCE_TDMA_DMAD_FSM				0x00005c80
3583#define BCE_TDMA_DMAD_FSM_BD_INVLD			 (1L<<0)
3584#define BCE_TDMA_DMAD_FSM_PUSH				 (0xfL<<4)
3585#define BCE_TDMA_DMAD_FSM_ARB_TBDC			 (0x3L<<8)
3586#define BCE_TDMA_DMAD_FSM_ARB_CTX			 (1L<<12)
3587#define BCE_TDMA_DMAD_FSM_DR_INTF			 (1L<<16)
3588#define BCE_TDMA_DMAD_FSM_DMAD				 (0x7L<<20)
3589#define BCE_TDMA_DMAD_FSM_BD				 (0xfL<<24)
3590
3591#define BCE_TDMA_DMAD_STATUS				0x00005c84
3592#define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY		 (0x3L<<0)
3593#define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY		 (0x3L<<4)
3594#define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY		 (0x3L<<8)
3595#define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM			 (0xfL<<12)
3596
3597#define BCE_TDMA_DR_INTF_FSM				0x00005c88
3598#define BCE_TDMA_DR_INTF_FSM_L2_COMP			 (0x3L<<0)
3599#define BCE_TDMA_DR_INTF_FSM_TPATQ			 (0x7L<<4)
3600#define BCE_TDMA_DR_INTF_FSM_TPBUF			 (0x3L<<8)
3601#define BCE_TDMA_DR_INTF_FSM_DR_BUF			 (0x7L<<12)
3602#define BCE_TDMA_DR_INTF_FSM_DMAD			 (0x7L<<16)
3603
3604#define BCE_TDMA_DR_INTF_STATUS			0x00005c8c
3605#define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE		 (0x7L<<0)
3606#define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL		 (0x3L<<4)
3607#define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR		 (0x7L<<8)
3608#define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR		 (0xfL<<12)
3609#define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT		 (0x7L<<16)
3610
3611#define BCE_TDMA_FTQ_DATA				0x00005fc0
3612#define BCE_TDMA_FTQ_CMD				0x00005ff8
3613#define BCE_TDMA_FTQ_CMD_OFFSET			 (0x3ffL<<0)
3614#define BCE_TDMA_FTQ_CMD_WR_TOP			 (1L<<10)
3615#define BCE_TDMA_FTQ_CMD_WR_TOP_0			 (0L<<10)
3616#define BCE_TDMA_FTQ_CMD_WR_TOP_1			 (1L<<10)
3617#define BCE_TDMA_FTQ_CMD_SFT_RESET			 (1L<<25)
3618#define BCE_TDMA_FTQ_CMD_RD_DATA			 (1L<<26)
3619#define BCE_TDMA_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
3620#define BCE_TDMA_FTQ_CMD_ADD_DATA			 (1L<<28)
3621#define BCE_TDMA_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
3622#define BCE_TDMA_FTQ_CMD_POP				 (1L<<30)
3623#define BCE_TDMA_FTQ_CMD_BUSY				 (1L<<31)
3624
3625#define BCE_TDMA_FTQ_CTL				0x00005ffc
3626#define BCE_TDMA_FTQ_CTL_INTERVENE			 (1L<<0)
3627#define BCE_TDMA_FTQ_CTL_OVERFLOW			 (1L<<1)
3628#define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
3629#define BCE_TDMA_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
3630#define BCE_TDMA_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
3631
3632
3633
3634/*
3635 *  hc_reg definition
3636 *  offset: 0x6800
3637 */
3638#define BCE_HC_COMMAND					0x00006800
3639#define BCE_HC_COMMAND_ENABLE				 (1L<<0)
3640#define BCE_HC_COMMAND_SKIP_ABORT			 (1L<<4)
3641#define BCE_HC_COMMAND_COAL_NOW			 (1L<<16)
3642#define BCE_HC_COMMAND_COAL_NOW_WO_INT			 (1L<<17)
3643#define BCE_HC_COMMAND_STATS_NOW			 (1L<<18)
3644#define BCE_HC_COMMAND_FORCE_INT			 (0x3L<<19)
3645#define BCE_HC_COMMAND_FORCE_INT_NULL			 (0L<<19)
3646#define BCE_HC_COMMAND_FORCE_INT_HIGH			 (1L<<19)
3647#define BCE_HC_COMMAND_FORCE_INT_LOW			 (2L<<19)
3648#define BCE_HC_COMMAND_FORCE_INT_FREE			 (3L<<19)
3649#define BCE_HC_COMMAND_CLR_STAT_NOW			 (1L<<21)
3650
3651#define BCE_HC_STATUS					0x00006804
3652#define BCE_HC_STATUS_MASTER_ABORT			 (1L<<0)
3653#define BCE_HC_STATUS_PARITY_ERROR_STATE		 (1L<<1)
3654#define BCE_HC_STATUS_PCI_CLK_CNT_STAT			 (1L<<16)
3655#define BCE_HC_STATUS_CORE_CLK_CNT_STAT		 (1L<<17)
3656#define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT		 (1L<<18)
3657#define BCE_HC_STATUS_NUM_INT_GEN_STAT			 (1L<<19)
3658#define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT		 (1L<<20)
3659#define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT	 (1L<<23)
3660#define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT	 (1L<<24)
3661#define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT	 (1L<<25)
3662
3663#define BCE_HC_CONFIG					0x00006808
3664#define BCE_HC_CONFIG_COLLECT_STATS			 (1L<<0)
3665#define BCE_HC_CONFIG_RX_TMR_MODE			 (1L<<1)
3666#define BCE_HC_CONFIG_TX_TMR_MODE			 (1L<<2)
3667#define BCE_HC_CONFIG_COM_TMR_MODE			 (1L<<3)
3668#define BCE_HC_CONFIG_CMD_TMR_MODE			 (1L<<4)
3669#define BCE_HC_CONFIG_STATISTIC_PRIORITY		 (1L<<5)
3670#define BCE_HC_CONFIG_STATUS_PRIORITY			 (1L<<6)
3671#define BCE_HC_CONFIG_STAT_MEM_ADDR			 (0xffL<<8)
3672
3673#define BCE_HC_ATTN_BITS_ENABLE			0x0000680c
3674#define BCE_HC_STATUS_ADDR_L				0x00006810
3675#define BCE_HC_STATUS_ADDR_H				0x00006814
3676#define BCE_HC_STATISTICS_ADDR_L			0x00006818
3677#define BCE_HC_STATISTICS_ADDR_H			0x0000681c
3678#define BCE_HC_TX_QUICK_CONS_TRIP			0x00006820
3679#define BCE_HC_TX_QUICK_CONS_TRIP_VALUE		 (0xffL<<0)
3680#define BCE_HC_TX_QUICK_CONS_TRIP_INT			 (0xffL<<16)
3681
3682#define BCE_HC_COMP_PROD_TRIP				0x00006824
3683#define BCE_HC_COMP_PROD_TRIP_VALUE			 (0xffL<<0)
3684#define BCE_HC_COMP_PROD_TRIP_INT			 (0xffL<<16)
3685
3686#define BCE_HC_RX_QUICK_CONS_TRIP			0x00006828
3687#define BCE_HC_RX_QUICK_CONS_TRIP_VALUE		 (0xffL<<0)
3688#define BCE_HC_RX_QUICK_CONS_TRIP_INT			 (0xffL<<16)
3689
3690#define BCE_HC_RX_TICKS				0x0000682c
3691#define BCE_HC_RX_TICKS_VALUE				 (0x3ffL<<0)
3692#define BCE_HC_RX_TICKS_INT				 (0x3ffL<<16)
3693
3694#define BCE_HC_TX_TICKS				0x00006830
3695#define BCE_HC_TX_TICKS_VALUE				 (0x3ffL<<0)
3696#define BCE_HC_TX_TICKS_INT				 (0x3ffL<<16)
3697
3698#define BCE_HC_COM_TICKS				0x00006834
3699#define BCE_HC_COM_TICKS_VALUE				 (0x3ffL<<0)
3700#define BCE_HC_COM_TICKS_INT				 (0x3ffL<<16)
3701
3702#define BCE_HC_CMD_TICKS				0x00006838
3703#define BCE_HC_CMD_TICKS_VALUE				 (0x3ffL<<0)
3704#define BCE_HC_CMD_TICKS_INT				 (0x3ffL<<16)
3705
3706#define BCE_HC_PERIODIC_TICKS				0x0000683c
3707#define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS	 (0xffffL<<0)
3708
3709#define BCE_HC_STAT_COLLECT_TICKS			0x00006840
3710#define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS	 (0xffL<<4)
3711
3712#define BCE_HC_STATS_TICKS				0x00006844
3713#define BCE_HC_STATS_TICKS_HC_STAT_TICKS		 (0xffffL<<8)
3714
3715#define BCE_HC_STAT_MEM_DATA				0x0000684c
3716#define BCE_HC_STAT_GEN_SEL_0				0x00006850
3717#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0		 (0x7fL<<0)
3718#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0	 (0L<<0)
3719#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1	 (1L<<0)
3720#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2	 (2L<<0)
3721#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3	 (3L<<0)
3722#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4	 (4L<<0)
3723#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5	 (5L<<0)
3724#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6	 (6L<<0)
3725#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7	 (7L<<0)
3726#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8	 (8L<<0)
3727#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9	 (9L<<0)
3728#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10	 (10L<<0)
3729#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11	 (11L<<0)
3730#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0	 (12L<<0)
3731#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1	 (13L<<0)
3732#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2	 (14L<<0)
3733#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3	 (15L<<0)
3734#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4	 (16L<<0)
3735#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5	 (17L<<0)
3736#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6	 (18L<<0)
3737#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7	 (19L<<0)
3738#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0	 (20L<<0)
3739#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1	 (21L<<0)
3740#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2	 (22L<<0)
3741#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3	 (23L<<0)
3742#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4	 (24L<<0)
3743#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5	 (25L<<0)
3744#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6	 (26L<<0)
3745#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7	 (27L<<0)
3746#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8	 (28L<<0)
3747#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9	 (29L<<0)
3748#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10	 (30L<<0)
3749#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11	 (31L<<0)
3750#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0	 (32L<<0)
3751#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1	 (33L<<0)
3752#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2	 (34L<<0)
3753#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3	 (35L<<0)
3754#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0	 (36L<<0)
3755#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1	 (37L<<0)
3756#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2	 (38L<<0)
3757#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3	 (39L<<0)
3758#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4	 (40L<<0)
3759#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5	 (41L<<0)
3760#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6	 (42L<<0)
3761#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7	 (43L<<0)
3762#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0	 (44L<<0)
3763#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1	 (45L<<0)
3764#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2	 (46L<<0)
3765#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3	 (47L<<0)
3766#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4	 (48L<<0)
3767#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5	 (49L<<0)
3768#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6	 (50L<<0)
3769#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7	 (51L<<0)
3770#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT	 (52L<<0)
3771#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT	 (53L<<0)
3772#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS	 (54L<<0)
3773#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN	 (55L<<0)
3774#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR	 (56L<<0)
3775#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK	 (59L<<0)
3776#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK	 (60L<<0)
3777#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK	 (61L<<0)
3778#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT	 (62L<<0)
3779#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT	 (63L<<0)
3780#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT	 (64L<<0)
3781#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT	 (65L<<0)
3782#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT	 (66L<<0)
3783#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT	 (67L<<0)
3784#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT	 (68L<<0)
3785#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT	 (69L<<0)
3786#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT	 (70L<<0)
3787#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT	 (71L<<0)
3788#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT	 (72L<<0)
3789#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT	 (73L<<0)
3790#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT	 (74L<<0)
3791#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT	 (75L<<0)
3792#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT	 (76L<<0)
3793#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT	 (77L<<0)
3794#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT	 (78L<<0)
3795#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT	 (79L<<0)
3796#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT	 (80L<<0)
3797#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT	 (81L<<0)
3798#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT	 (82L<<0)
3799#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT	 (83L<<0)
3800#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT	 (84L<<0)
3801#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT	 (85L<<0)
3802#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT	 (86L<<0)
3803#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT	 (87L<<0)
3804#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT	 (88L<<0)
3805#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT	 (89L<<0)
3806#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT	 (90L<<0)
3807#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT	 (91L<<0)
3808#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT	 (92L<<0)
3809#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT	 (93L<<0)
3810#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT	 (94L<<0)
3811#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64	 (95L<<0)
3812#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64	 (96L<<0)
3813#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS	 (97L<<0)
3814#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS	 (98L<<0)
3815#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT	 (99L<<0)
3816#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT	 (100L<<0)
3817#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT	 (101L<<0)
3818#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT	 (102L<<0)
3819#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT	 (103L<<0)
3820#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT	 (104L<<0)
3821#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT	 (105L<<0)
3822#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT	 (106L<<0)
3823#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT	 (107L<<0)
3824#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT	 (108L<<0)
3825#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT	 (109L<<0)
3826#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT	 (110L<<0)
3827#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT	 (111L<<0)
3828#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT	 (112L<<0)
3829#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT	 (113L<<0)
3830#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT	 (114L<<0)
3831#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0	 (115L<<0)
3832#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1	 (116L<<0)
3833#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2	 (117L<<0)
3834#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3	 (118L<<0)
3835#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4	 (119L<<0)
3836#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5	 (120L<<0)
3837#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS	 (121L<<0)
3838#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS	 (122L<<0)
3839#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT	 (127L<<0)
3840#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1		 (0x7fL<<8)
3841#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2		 (0x7fL<<16)
3842#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3		 (0x7fL<<24)
3843
3844#define BCE_HC_STAT_GEN_SEL_1				0x00006854
3845#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4		 (0x7fL<<0)
3846#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5		 (0x7fL<<8)
3847#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6		 (0x7fL<<16)
3848#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7		 (0x7fL<<24)
3849
3850#define BCE_HC_STAT_GEN_SEL_2				0x00006858
3851#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8		 (0x7fL<<0)
3852#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9		 (0x7fL<<8)
3853#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10		 (0x7fL<<16)
3854#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11		 (0x7fL<<24)
3855
3856#define BCE_HC_STAT_GEN_SEL_3				0x0000685c
3857#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12		 (0x7fL<<0)
3858#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13		 (0x7fL<<8)
3859#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14		 (0x7fL<<16)
3860#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15		 (0x7fL<<24)
3861
3862#define BCE_HC_STAT_GEN_STAT0				0x00006888
3863#define BCE_HC_STAT_GEN_STAT1				0x0000688c
3864#define BCE_HC_STAT_GEN_STAT2				0x00006890
3865#define BCE_HC_STAT_GEN_STAT3				0x00006894
3866#define BCE_HC_STAT_GEN_STAT4				0x00006898
3867#define BCE_HC_STAT_GEN_STAT5				0x0000689c
3868#define BCE_HC_STAT_GEN_STAT6				0x000068a0
3869#define BCE_HC_STAT_GEN_STAT7				0x000068a4
3870#define BCE_HC_STAT_GEN_STAT8				0x000068a8
3871#define BCE_HC_STAT_GEN_STAT9				0x000068ac
3872#define BCE_HC_STAT_GEN_STAT10				0x000068b0
3873#define BCE_HC_STAT_GEN_STAT11				0x000068b4
3874#define BCE_HC_STAT_GEN_STAT12				0x000068b8
3875#define BCE_HC_STAT_GEN_STAT13				0x000068bc
3876#define BCE_HC_STAT_GEN_STAT14				0x000068c0
3877#define BCE_HC_STAT_GEN_STAT15				0x000068c4
3878#define BCE_HC_STAT_GEN_STAT_AC0			0x000068c8
3879#define BCE_HC_STAT_GEN_STAT_AC1			0x000068cc
3880#define BCE_HC_STAT_GEN_STAT_AC2			0x000068d0
3881#define BCE_HC_STAT_GEN_STAT_AC3			0x000068d4
3882#define BCE_HC_STAT_GEN_STAT_AC4			0x000068d8
3883#define BCE_HC_STAT_GEN_STAT_AC5			0x000068dc
3884#define BCE_HC_STAT_GEN_STAT_AC6			0x000068e0
3885#define BCE_HC_STAT_GEN_STAT_AC7			0x000068e4
3886#define BCE_HC_STAT_GEN_STAT_AC8			0x000068e8
3887#define BCE_HC_STAT_GEN_STAT_AC9			0x000068ec
3888#define BCE_HC_STAT_GEN_STAT_AC10			0x000068f0
3889#define BCE_HC_STAT_GEN_STAT_AC11			0x000068f4
3890#define BCE_HC_STAT_GEN_STAT_AC12			0x000068f8
3891#define BCE_HC_STAT_GEN_STAT_AC13			0x000068fc
3892#define BCE_HC_STAT_GEN_STAT_AC14			0x00006900
3893#define BCE_HC_STAT_GEN_STAT_AC15			0x00006904
3894#define BCE_HC_VIS					0x00006908
3895#define BCE_HC_VIS_STAT_BUILD_STATE			 (0xfL<<0)
3896#define BCE_HC_VIS_STAT_BUILD_STATE_IDLE		 (0L<<0)
3897#define BCE_HC_VIS_STAT_BUILD_STATE_START		 (1L<<0)
3898#define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST		 (2L<<0)
3899#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64		 (3L<<0)
3900#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32		 (4L<<0)
3901#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE	 (5L<<0)
3902#define BCE_HC_VIS_STAT_BUILD_STATE_DMA		 (6L<<0)
3903#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL	 (7L<<0)
3904#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW		 (8L<<0)
3905#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH		 (9L<<0)
3906#define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA		 (10L<<0)
3907#define BCE_HC_VIS_DMA_STAT_STATE			 (0xfL<<8)
3908#define BCE_HC_VIS_DMA_STAT_STATE_IDLE			 (0L<<8)
3909#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM		 (1L<<8)
3910#define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA		 (2L<<8)
3911#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP		 (3L<<8)
3912#define BCE_HC_VIS_DMA_STAT_STATE_COMP			 (4L<<8)
3913#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM	 (5L<<8)
3914#define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA	 (6L<<8)
3915#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1		 (7L<<8)
3916#define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2		 (8L<<8)
3917#define BCE_HC_VIS_DMA_STAT_STATE_WAIT			 (9L<<8)
3918#define BCE_HC_VIS_DMA_STAT_STATE_ABORT		 (15L<<8)
3919#define BCE_HC_VIS_DMA_MSI_STATE			 (0x7L<<12)
3920#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE		 (0x3L<<15)
3921#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE		 (0L<<15)
3922#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT	 (1L<<15)
3923#define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START	 (2L<<15)
3924
3925#define BCE_HC_VIS_1					0x0000690c
3926#define BCE_HC_VIS_1_HW_INTACK_STATE			 (1L<<4)
3927#define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE		 (0L<<4)
3928#define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT		 (1L<<4)
3929#define BCE_HC_VIS_1_SW_INTACK_STATE			 (1L<<5)
3930#define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE		 (0L<<5)
3931#define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT		 (1L<<5)
3932#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE		 (1L<<6)
3933#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE	 (0L<<6)
3934#define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT	 (1L<<6)
3935#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE		 (1L<<7)
3936#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE		 (0L<<7)
3937#define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT		 (1L<<7)
3938#define BCE_HC_VIS_1_RAM_RD_ARB_STATE			 (0xfL<<17)
3939#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE		 (0L<<17)
3940#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA		 (1L<<17)
3941#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE		 (2L<<17)
3942#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN		 (3L<<17)
3943#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT		 (4L<<17)
3944#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE	 (5L<<17)
3945#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN	 (6L<<17)
3946#define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT		 (7L<<17)
3947#define BCE_HC_VIS_1_RAM_WR_ARB_STATE			 (0x3L<<21)
3948#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL		 (0L<<21)
3949#define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR		 (1L<<21)
3950#define BCE_HC_VIS_1_INT_GEN_STATE			 (1L<<23)
3951#define BCE_HC_VIS_1_INT_GEN_STATE_DLE			 (0L<<23)
3952#define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT		 (1L<<23)
3953#define BCE_HC_VIS_1_STAT_CHAN_ID			 (0x7L<<24)
3954#define BCE_HC_VIS_1_INT_B				 (1L<<27)
3955
3956#define BCE_HC_DEBUG_VECT_PEEK				0x00006910
3957#define BCE_HC_DEBUG_VECT_PEEK_1_VALUE			 (0x7ffL<<0)
3958#define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
3959#define BCE_HC_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)
3960#define BCE_HC_DEBUG_VECT_PEEK_2_VALUE			 (0x7ffL<<16)
3961#define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
3962#define BCE_HC_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)
3963
3964
3965
3966/*
3967 *  txp_reg definition
3968 *  offset: 0x40000
3969 */
3970#define BCE_TXP_CPU_MODE				0x00045000
3971#define BCE_TXP_CPU_MODE_LOCAL_RST			 (1L<<0)
3972#define BCE_TXP_CPU_MODE_STEP_ENA			 (1L<<1)
3973#define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
3974#define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
3975#define BCE_TXP_CPU_MODE_MSG_BIT1			 (1L<<6)
3976#define BCE_TXP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
3977#define BCE_TXP_CPU_MODE_SOFT_HALT			 (1L<<10)
3978#define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
3979#define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
3980#define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
3981#define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
3982
3983#define BCE_TXP_CPU_STATE				0x00045004
3984#define BCE_TXP_CPU_STATE_BREAKPOINT			 (1L<<0)
3985#define BCE_TXP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
3986#define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
3987#define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
3988#define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
3989#define BCE_TXP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
3990#define BCE_TXP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
3991#define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
3992#define BCE_TXP_CPU_STATE_SOFT_HALTED			 (1L<<10)
3993#define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
3994#define BCE_TXP_CPU_STATE_INTERRRUPT			 (1L<<12)
3995#define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
3996#define BCE_TXP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
3997#define BCE_TXP_CPU_STATE_BLOCKED_READ			 (1L<<31)
3998
3999#define BCE_TXP_CPU_EVENT_MASK				0x00045008
4000#define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4001#define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4002#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4003#define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4004#define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4005#define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4006#define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4007#define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4008#define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4009#define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4010#define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4011
4012#define BCE_TXP_CPU_PROGRAM_COUNTER			0x0004501c
4013#define BCE_TXP_CPU_INSTRUCTION			0x00045020
4014#define BCE_TXP_CPU_DATA_ACCESS			0x00045024
4015#define BCE_TXP_CPU_INTERRUPT_ENABLE			0x00045028
4016#define BCE_TXP_CPU_INTERRUPT_VECTOR			0x0004502c
4017#define BCE_TXP_CPU_INTERRUPT_SAVED_PC			0x00045030
4018#define BCE_TXP_CPU_HW_BREAKPOINT			0x00045034
4019#define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4020#define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
4021
4022#define BCE_TXP_CPU_DEBUG_VECT_PEEK			0x00045038
4023#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
4024#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4025#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)
4026#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
4027#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4028#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)
4029
4030#define BCE_TXP_CPU_LAST_BRANCH_ADDR			0x00045048
4031#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4032#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
4033#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4034#define BCE_TXP_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)
4035
4036#define BCE_TXP_CPU_REG_FILE				0x00045200
4037#define BCE_TXP_FTQ_DATA				0x000453c0
4038#define BCE_TXP_FTQ_CMD				0x000453f8
4039#define BCE_TXP_FTQ_CMD_OFFSET				 (0x3ffL<<0)
4040#define BCE_TXP_FTQ_CMD_WR_TOP				 (1L<<10)
4041#define BCE_TXP_FTQ_CMD_WR_TOP_0			 (0L<<10)
4042#define BCE_TXP_FTQ_CMD_WR_TOP_1			 (1L<<10)
4043#define BCE_TXP_FTQ_CMD_SFT_RESET			 (1L<<25)
4044#define BCE_TXP_FTQ_CMD_RD_DATA			 (1L<<26)
4045#define BCE_TXP_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
4046#define BCE_TXP_FTQ_CMD_ADD_DATA			 (1L<<28)
4047#define BCE_TXP_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
4048#define BCE_TXP_FTQ_CMD_POP				 (1L<<30)
4049#define BCE_TXP_FTQ_CMD_BUSY				 (1L<<31)
4050
4051#define BCE_TXP_FTQ_CTL				0x000453fc
4052#define BCE_TXP_FTQ_CTL_INTERVENE			 (1L<<0)
4053#define BCE_TXP_FTQ_CTL_OVERFLOW			 (1L<<1)
4054#define BCE_TXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4055#define BCE_TXP_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4056#define BCE_TXP_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4057
4058#define BCE_TXP_SCRATCH				0x00060000
4059
4060
4061/*
4062 *  tpat_reg definition
4063 *  offset: 0x80000
4064 */
4065#define BCE_TPAT_CPU_MODE				0x00085000
4066#define BCE_TPAT_CPU_MODE_LOCAL_RST			 (1L<<0)
4067#define BCE_TPAT_CPU_MODE_STEP_ENA			 (1L<<1)
4068#define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4069#define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4070#define BCE_TPAT_CPU_MODE_MSG_BIT1			 (1L<<6)
4071#define BCE_TPAT_CPU_MODE_INTERRUPT_ENA		 (1L<<7)
4072#define BCE_TPAT_CPU_MODE_SOFT_HALT			 (1L<<10)
4073#define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4074#define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4075#define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4076#define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4077
4078#define BCE_TPAT_CPU_STATE				0x00085004
4079#define BCE_TPAT_CPU_STATE_BREAKPOINT			 (1L<<0)
4080#define BCE_TPAT_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
4081#define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
4082#define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
4083#define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED	 (1L<<5)
4084#define BCE_TPAT_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4085#define BCE_TPAT_CPU_STATE_ALIGN_HALTED		 (1L<<7)
4086#define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
4087#define BCE_TPAT_CPU_STATE_SOFT_HALTED			 (1L<<10)
4088#define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4089#define BCE_TPAT_CPU_STATE_INTERRRUPT			 (1L<<12)
4090#define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
4091#define BCE_TPAT_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4092#define BCE_TPAT_CPU_STATE_BLOCKED_READ		 (1L<<31)
4093
4094#define BCE_TPAT_CPU_EVENT_MASK			0x00085008
4095#define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK	 (1L<<0)
4096#define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4097#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4098#define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4099#define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4100#define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4101#define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4102#define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4103#define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4104#define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4105#define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4106
4107#define BCE_TPAT_CPU_PROGRAM_COUNTER			0x0008501c
4108#define BCE_TPAT_CPU_INSTRUCTION			0x00085020
4109#define BCE_TPAT_CPU_DATA_ACCESS			0x00085024
4110#define BCE_TPAT_CPU_INTERRUPT_ENABLE			0x00085028
4111#define BCE_TPAT_CPU_INTERRUPT_VECTOR			0x0008502c
4112#define BCE_TPAT_CPU_INTERRUPT_SAVED_PC		0x00085030
4113#define BCE_TPAT_CPU_HW_BREAKPOINT			0x00085034
4114#define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4115#define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
4116
4117#define BCE_TPAT_CPU_DEBUG_VECT_PEEK			0x00085038
4118#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
4119#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4120#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)
4121#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
4122#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4123#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)
4124
4125#define BCE_TPAT_CPU_LAST_BRANCH_ADDR			0x00085048
4126#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4127#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP	 (0L<<1)
4128#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4129#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)
4130
4131#define BCE_TPAT_CPU_REG_FILE				0x00085200
4132#define BCE_TPAT_FTQ_DATA				0x000853c0
4133#define BCE_TPAT_FTQ_CMD				0x000853f8
4134#define BCE_TPAT_FTQ_CMD_OFFSET			 (0x3ffL<<0)
4135#define BCE_TPAT_FTQ_CMD_WR_TOP			 (1L<<10)
4136#define BCE_TPAT_FTQ_CMD_WR_TOP_0			 (0L<<10)
4137#define BCE_TPAT_FTQ_CMD_WR_TOP_1			 (1L<<10)
4138#define BCE_TPAT_FTQ_CMD_SFT_RESET			 (1L<<25)
4139#define BCE_TPAT_FTQ_CMD_RD_DATA			 (1L<<26)
4140#define BCE_TPAT_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
4141#define BCE_TPAT_FTQ_CMD_ADD_DATA			 (1L<<28)
4142#define BCE_TPAT_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
4143#define BCE_TPAT_FTQ_CMD_POP				 (1L<<30)
4144#define BCE_TPAT_FTQ_CMD_BUSY				 (1L<<31)
4145
4146#define BCE_TPAT_FTQ_CTL				0x000853fc
4147#define BCE_TPAT_FTQ_CTL_INTERVENE			 (1L<<0)
4148#define BCE_TPAT_FTQ_CTL_OVERFLOW			 (1L<<1)
4149#define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4150#define BCE_TPAT_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4151#define BCE_TPAT_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4152
4153#define BCE_TPAT_SCRATCH				0x000a0000
4154
4155
4156/*
4157 *  rxp_reg definition
4158 *  offset: 0xc0000
4159 */
4160#define BCE_RXP_CPU_MODE				0x000c5000
4161#define BCE_RXP_CPU_MODE_LOCAL_RST			 (1L<<0)
4162#define BCE_RXP_CPU_MODE_STEP_ENA			 (1L<<1)
4163#define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4164#define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4165#define BCE_RXP_CPU_MODE_MSG_BIT1			 (1L<<6)
4166#define BCE_RXP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
4167#define BCE_RXP_CPU_MODE_SOFT_HALT			 (1L<<10)
4168#define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4169#define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4170#define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4171#define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4172
4173#define BCE_RXP_CPU_STATE				0x000c5004
4174#define BCE_RXP_CPU_STATE_BREAKPOINT			 (1L<<0)
4175#define BCE_RXP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
4176#define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
4177#define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
4178#define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
4179#define BCE_RXP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4180#define BCE_RXP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
4181#define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
4182#define BCE_RXP_CPU_STATE_SOFT_HALTED			 (1L<<10)
4183#define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4184#define BCE_RXP_CPU_STATE_INTERRRUPT			 (1L<<12)
4185#define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
4186#define BCE_RXP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4187#define BCE_RXP_CPU_STATE_BLOCKED_READ			 (1L<<31)
4188
4189#define BCE_RXP_CPU_EVENT_MASK				0x000c5008
4190#define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4191#define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4192#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4193#define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4194#define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4195#define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4196#define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4197#define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4198#define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4199#define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4200#define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4201
4202#define BCE_RXP_CPU_PROGRAM_COUNTER			0x000c501c
4203#define BCE_RXP_CPU_INSTRUCTION			0x000c5020
4204#define BCE_RXP_CPU_DATA_ACCESS			0x000c5024
4205#define BCE_RXP_CPU_INTERRUPT_ENABLE			0x000c5028
4206#define BCE_RXP_CPU_INTERRUPT_VECTOR			0x000c502c
4207#define BCE_RXP_CPU_INTERRUPT_SAVED_PC			0x000c5030
4208#define BCE_RXP_CPU_HW_BREAKPOINT			0x000c5034
4209#define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4210#define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
4211
4212#define BCE_RXP_CPU_DEBUG_VECT_PEEK			0x000c5038
4213#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
4214#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4215#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)
4216#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
4217#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4218#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)
4219
4220#define BCE_RXP_CPU_LAST_BRANCH_ADDR			0x000c5048
4221#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4222#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
4223#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4224#define BCE_RXP_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)
4225
4226#define BCE_RXP_CPU_REG_FILE				0x000c5200
4227#define BCE_RXP_CFTQ_DATA				0x000c5380
4228#define BCE_RXP_CFTQ_CMD				0x000c53b8
4229#define BCE_RXP_CFTQ_CMD_OFFSET			 (0x3ffL<<0)
4230#define BCE_RXP_CFTQ_CMD_WR_TOP			 (1L<<10)
4231#define BCE_RXP_CFTQ_CMD_WR_TOP_0			 (0L<<10)
4232#define BCE_RXP_CFTQ_CMD_WR_TOP_1			 (1L<<10)
4233#define BCE_RXP_CFTQ_CMD_SFT_RESET			 (1L<<25)
4234#define BCE_RXP_CFTQ_CMD_RD_DATA			 (1L<<26)
4235#define BCE_RXP_CFTQ_CMD_ADD_INTERVEN			 (1L<<27)
4236#define BCE_RXP_CFTQ_CMD_ADD_DATA			 (1L<<28)
4237#define BCE_RXP_CFTQ_CMD_INTERVENE_CLR			 (1L<<29)
4238#define BCE_RXP_CFTQ_CMD_POP				 (1L<<30)
4239#define BCE_RXP_CFTQ_CMD_BUSY				 (1L<<31)
4240
4241#define BCE_RXP_CFTQ_CTL				0x000c53bc
4242#define BCE_RXP_CFTQ_CTL_INTERVENE			 (1L<<0)
4243#define BCE_RXP_CFTQ_CTL_OVERFLOW			 (1L<<1)
4244#define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4245#define BCE_RXP_CFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4246#define BCE_RXP_CFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4247
4248#define BCE_RXP_FTQ_DATA				0x000c53c0
4249#define BCE_RXP_FTQ_CMD				0x000c53f8
4250#define BCE_RXP_FTQ_CMD_OFFSET				 (0x3ffL<<0)
4251#define BCE_RXP_FTQ_CMD_WR_TOP				 (1L<<10)
4252#define BCE_RXP_FTQ_CMD_WR_TOP_0			 (0L<<10)
4253#define BCE_RXP_FTQ_CMD_WR_TOP_1			 (1L<<10)
4254#define BCE_RXP_FTQ_CMD_SFT_RESET			 (1L<<25)
4255#define BCE_RXP_FTQ_CMD_RD_DATA			 (1L<<26)
4256#define BCE_RXP_FTQ_CMD_ADD_INTERVEN			 (1L<<27)
4257#define BCE_RXP_FTQ_CMD_ADD_DATA			 (1L<<28)
4258#define BCE_RXP_FTQ_CMD_INTERVENE_CLR			 (1L<<29)
4259#define BCE_RXP_FTQ_CMD_POP				 (1L<<30)
4260#define BCE_RXP_FTQ_CMD_BUSY				 (1L<<31)
4261
4262#define BCE_RXP_FTQ_CTL				0x000c53fc
4263#define BCE_RXP_FTQ_CTL_INTERVENE			 (1L<<0)
4264#define BCE_RXP_FTQ_CTL_OVERFLOW			 (1L<<1)
4265#define BCE_RXP_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4266#define BCE_RXP_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4267#define BCE_RXP_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4268
4269#define BCE_RXP_SCRATCH				0x000e0000
4270
4271
4272/*
4273 *  com_reg definition
4274 *  offset: 0x100000
4275 */
4276#define BCE_COM_CPU_MODE				0x00105000
4277#define BCE_COM_CPU_MODE_LOCAL_RST			 (1L<<0)
4278#define BCE_COM_CPU_MODE_STEP_ENA			 (1L<<1)
4279#define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4280#define BCE_COM_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4281#define BCE_COM_CPU_MODE_MSG_BIT1			 (1L<<6)
4282#define BCE_COM_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
4283#define BCE_COM_CPU_MODE_SOFT_HALT			 (1L<<10)
4284#define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4285#define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4286#define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4287#define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4288
4289#define BCE_COM_CPU_STATE				0x00105004
4290#define BCE_COM_CPU_STATE_BREAKPOINT			 (1L<<0)
4291#define BCE_COM_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
4292#define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
4293#define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
4294#define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
4295#define BCE_COM_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4296#define BCE_COM_CPU_STATE_ALIGN_HALTED			 (1L<<7)
4297#define BCE_COM_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
4298#define BCE_COM_CPU_STATE_SOFT_HALTED			 (1L<<10)
4299#define BCE_COM_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4300#define BCE_COM_CPU_STATE_INTERRRUPT			 (1L<<12)
4301#define BCE_COM_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
4302#define BCE_COM_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4303#define BCE_COM_CPU_STATE_BLOCKED_READ			 (1L<<31)
4304
4305#define BCE_COM_CPU_EVENT_MASK				0x00105008
4306#define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4307#define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4308#define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4309#define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4310#define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4311#define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4312#define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4313#define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4314#define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4315#define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4316#define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4317
4318#define BCE_COM_CPU_PROGRAM_COUNTER			0x0010501c
4319#define BCE_COM_CPU_INSTRUCTION			0x00105020
4320#define BCE_COM_CPU_DATA_ACCESS			0x00105024
4321#define BCE_COM_CPU_INTERRUPT_ENABLE			0x00105028
4322#define BCE_COM_CPU_INTERRUPT_VECTOR			0x0010502c
4323#define BCE_COM_CPU_INTERRUPT_SAVED_PC			0x00105030
4324#define BCE_COM_CPU_HW_BREAKPOINT			0x00105034
4325#define BCE_COM_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4326#define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
4327
4328#define BCE_COM_CPU_DEBUG_VECT_PEEK			0x00105038
4329#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
4330#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4331#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)
4332#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
4333#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4334#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)
4335
4336#define BCE_COM_CPU_LAST_BRANCH_ADDR			0x00105048
4337#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4338#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
4339#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4340#define BCE_COM_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)
4341
4342#define BCE_COM_CPU_REG_FILE				0x00105200
4343#define BCE_COM_COMXQ_FTQ_DATA				0x00105340
4344#define BCE_COM_COMXQ_FTQ_CMD				0x00105378
4345#define BCE_COM_COMXQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
4346#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP			 (1L<<10)
4347#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4348#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4349#define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET		 (1L<<25)
4350#define BCE_COM_COMXQ_FTQ_CMD_RD_DATA			 (1L<<26)
4351#define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4352#define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4353#define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4354#define BCE_COM_COMXQ_FTQ_CMD_POP			 (1L<<30)
4355#define BCE_COM_COMXQ_FTQ_CMD_BUSY			 (1L<<31)
4356
4357#define BCE_COM_COMXQ_FTQ_CTL				0x0010537c
4358#define BCE_COM_COMXQ_FTQ_CTL_INTERVENE		 (1L<<0)
4359#define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4360#define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4361#define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4362#define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4363
4364#define BCE_COM_COMTQ_FTQ_DATA				0x00105380
4365#define BCE_COM_COMTQ_FTQ_CMD				0x001053b8
4366#define BCE_COM_COMTQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
4367#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP			 (1L<<10)
4368#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4369#define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4370#define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET		 (1L<<25)
4371#define BCE_COM_COMTQ_FTQ_CMD_RD_DATA			 (1L<<26)
4372#define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4373#define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4374#define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4375#define BCE_COM_COMTQ_FTQ_CMD_POP			 (1L<<30)
4376#define BCE_COM_COMTQ_FTQ_CMD_BUSY			 (1L<<31)
4377
4378#define BCE_COM_COMTQ_FTQ_CTL				0x001053bc
4379#define BCE_COM_COMTQ_FTQ_CTL_INTERVENE		 (1L<<0)
4380#define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4381#define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4382#define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
4383#define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
4384
4385#define BCE_COM_COMQ_FTQ_DATA				0x001053c0
4386#define BCE_COM_COMQ_FTQ_CMD				0x001053f8
4387#define BCE_COM_COMQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
4388#define BCE_COM_COMQ_FTQ_CMD_WR_TOP			 (1L<<10)
4389#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4390#define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4391#define BCE_COM_COMQ_FTQ_CMD_SFT_RESET			 (1L<<25)
4392#define BCE_COM_COMQ_FTQ_CMD_RD_DATA			 (1L<<26)
4393#define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4394#define BCE_COM_COMQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4395#define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4396#define BCE_COM_COMQ_FTQ_CMD_POP			 (1L<<30)
4397#define BCE_COM_COMQ_FTQ_CMD_BUSY			 (1L<<31)
4398
4399#define BCE_COM_COMQ_FTQ_CTL				0x001053fc
4400#define BCE_COM_COMQ_FTQ_CTL_INTERVENE			 (1L<<0)
4401#define BCE_COM_COMQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4402#define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4403#define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4404#define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4405
4406#define BCE_COM_SCRATCH				0x00120000
4407
4408
4409/*
4410 *  cp_reg definition
4411 *  offset: 0x180000
4412 */
4413#define BCE_CP_CPU_MODE				0x00185000
4414#define BCE_CP_CPU_MODE_LOCAL_RST			 (1L<<0)
4415#define BCE_CP_CPU_MODE_STEP_ENA			 (1L<<1)
4416#define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4417#define BCE_CP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4418#define BCE_CP_CPU_MODE_MSG_BIT1			 (1L<<6)
4419#define BCE_CP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
4420#define BCE_CP_CPU_MODE_SOFT_HALT			 (1L<<10)
4421#define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4422#define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4423#define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4424#define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4425
4426#define BCE_CP_CPU_STATE				0x00185004
4427#define BCE_CP_CPU_STATE_BREAKPOINT			 (1L<<0)
4428#define BCE_CP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
4429#define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
4430#define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
4431#define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
4432#define BCE_CP_CPU_STATE_BAD_pc_HALTED			 (1L<<6)
4433#define BCE_CP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
4434#define BCE_CP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
4435#define BCE_CP_CPU_STATE_SOFT_HALTED			 (1L<<10)
4436#define BCE_CP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4437#define BCE_CP_CPU_STATE_INTERRRUPT			 (1L<<12)
4438#define BCE_CP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
4439#define BCE_CP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4440#define BCE_CP_CPU_STATE_BLOCKED_READ			 (1L<<31)
4441
4442#define BCE_CP_CPU_EVENT_MASK				0x00185008
4443#define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4444#define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4445#define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4446#define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4447#define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4448#define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4449#define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4450#define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4451#define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK		 (1L<<10)
4452#define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4453#define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4454
4455#define BCE_CP_CPU_PROGRAM_COUNTER			0x0018501c
4456#define BCE_CP_CPU_INSTRUCTION				0x00185020
4457#define BCE_CP_CPU_DATA_ACCESS				0x00185024
4458#define BCE_CP_CPU_INTERRUPT_ENABLE			0x00185028
4459#define BCE_CP_CPU_INTERRUPT_VECTOR			0x0018502c
4460#define BCE_CP_CPU_INTERRUPT_SAVED_PC			0x00185030
4461#define BCE_CP_CPU_HW_BREAKPOINT			0x00185034
4462#define BCE_CP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4463#define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
4464
4465#define BCE_CP_CPU_DEBUG_VECT_PEEK			0x00185038
4466#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
4467#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4468#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)
4469#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
4470#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4471#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)
4472
4473#define BCE_CP_CPU_LAST_BRANCH_ADDR			0x00185048
4474#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4475#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
4476#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4477#define BCE_CP_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)
4478
4479#define BCE_CP_CPU_REG_FILE				0x00185200
4480#define BCE_CP_CPQ_FTQ_DATA				0x001853c0
4481#define BCE_CP_CPQ_FTQ_CMD				0x001853f8
4482#define BCE_CP_CPQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
4483#define BCE_CP_CPQ_FTQ_CMD_WR_TOP			 (1L<<10)
4484#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4485#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4486#define BCE_CP_CPQ_FTQ_CMD_SFT_RESET			 (1L<<25)
4487#define BCE_CP_CPQ_FTQ_CMD_RD_DATA			 (1L<<26)
4488#define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4489#define BCE_CP_CPQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4490#define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4491#define BCE_CP_CPQ_FTQ_CMD_POP				 (1L<<30)
4492#define BCE_CP_CPQ_FTQ_CMD_BUSY			 (1L<<31)
4493
4494#define BCE_CP_CPQ_FTQ_CTL				0x001853fc
4495#define BCE_CP_CPQ_FTQ_CTL_INTERVENE			 (1L<<0)
4496#define BCE_CP_CPQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4497#define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4498#define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4499#define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4500
4501#define BCE_CP_SCRATCH					0x001a0000
4502
4503
4504/*
4505 *  tas_reg definition
4506 *  offset: 0x1c0000
4507 */
4508#define BCE_TAS_FTQ_CMD						0x001c03f8
4509#define BCE_TAS_FTQ_CTL						0x001c03fc
4510#define BCE_TAS_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4511#define BCE_TAS_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4512
4513
4514/*
4515 *  mcp_reg definition
4516 *  offset: 0x140000
4517 */
4518#define BCE_MCP_CPU_MODE				0x00145000
4519#define BCE_MCP_CPU_MODE_LOCAL_RST			 (1L<<0)
4520#define BCE_MCP_CPU_MODE_STEP_ENA			 (1L<<1)
4521#define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA		 (1L<<2)
4522#define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA		 (1L<<3)
4523#define BCE_MCP_CPU_MODE_MSG_BIT1			 (1L<<6)
4524#define BCE_MCP_CPU_MODE_INTERRUPT_ENA			 (1L<<7)
4525#define BCE_MCP_CPU_MODE_SOFT_HALT			 (1L<<10)
4526#define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA		 (1L<<11)
4527#define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA		 (1L<<12)
4528#define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA		 (1L<<13)
4529#define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA	 (1L<<15)
4530
4531#define BCE_MCP_CPU_STATE				0x00145004
4532#define BCE_MCP_CPU_STATE_BREAKPOINT			 (1L<<0)
4533#define BCE_MCP_CPU_STATE_BAD_INST_HALTED		 (1L<<2)
4534#define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED		 (1L<<3)
4535#define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED		 (1L<<4)
4536#define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED		 (1L<<5)
4537#define BCE_MCP_CPU_STATE_BAD_pc_HALTED		 (1L<<6)
4538#define BCE_MCP_CPU_STATE_ALIGN_HALTED			 (1L<<7)
4539#define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED		 (1L<<8)
4540#define BCE_MCP_CPU_STATE_SOFT_HALTED			 (1L<<10)
4541#define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW		 (1L<<11)
4542#define BCE_MCP_CPU_STATE_INTERRRUPT			 (1L<<12)
4543#define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL		 (1L<<14)
4544#define BCE_MCP_CPU_STATE_INST_FETCH_STALL		 (1L<<15)
4545#define BCE_MCP_CPU_STATE_BLOCKED_READ			 (1L<<31)
4546
4547#define BCE_MCP_CPU_EVENT_MASK				0x00145008
4548#define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
4549#define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK	 (1L<<2)
4550#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK	 (1L<<3)
4551#define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK	 (1L<<4)
4552#define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK	 (1L<<5)
4553#define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK	 (1L<<6)
4554#define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK	 (1L<<7)
4555#define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK		 (1L<<8)
4556#define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK	 (1L<<10)
4557#define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK	 (1L<<11)
4558#define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK		 (1L<<12)
4559
4560#define BCE_MCP_CPU_PROGRAM_COUNTER			0x0014501c
4561#define BCE_MCP_CPU_INSTRUCTION			0x00145020
4562#define BCE_MCP_CPU_DATA_ACCESS			0x00145024
4563#define BCE_MCP_CPU_INTERRUPT_ENABLE			0x00145028
4564#define BCE_MCP_CPU_INTERRUPT_VECTOR			0x0014502c
4565#define BCE_MCP_CPU_INTERRUPT_SAVED_PC			0x00145030
4566#define BCE_MCP_CPU_HW_BREAKPOINT			0x00145034
4567#define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
4568#define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
4569
4570#define BCE_MCP_CPU_DEBUG_VECT_PEEK			0x00145038
4571#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
4572#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN		 (1L<<11)
4573#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_SEL		 (0xfL<<12)
4574#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
4575#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN		 (1L<<27)
4576#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_SEL		 (0xfL<<28)
4577
4578#define BCE_MCP_CPU_LAST_BRANCH_ADDR			0x00145048
4579#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE		 (1L<<1)
4580#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP		 (0L<<1)
4581#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH	 (1L<<1)
4582#define BCE_MCP_CPU_LAST_BRANCH_ADDR_LBA		 (0x3fffffffL<<2)
4583
4584#define BCE_MCP_CPU_REG_FILE				0x00145200
4585#define BCE_MCP_MCPQ_FTQ_DATA				0x001453c0
4586#define BCE_MCP_MCPQ_FTQ_CMD				0x001453f8
4587#define BCE_MCP_MCPQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
4588#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP			 (1L<<10)
4589#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
4590#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1			 (1L<<10)
4591#define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET			 (1L<<25)
4592#define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA			 (1L<<26)
4593#define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN		 (1L<<27)
4594#define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA			 (1L<<28)
4595#define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR		 (1L<<29)
4596#define BCE_MCP_MCPQ_FTQ_CMD_POP			 (1L<<30)
4597#define BCE_MCP_MCPQ_FTQ_CMD_BUSY			 (1L<<31)
4598
4599#define BCE_MCP_MCPQ_FTQ_CTL				0x001453fc
4600#define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE			 (1L<<0)
4601#define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW			 (1L<<1)
4602#define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE		 (1L<<2)
4603#define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4604#define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4605
4606#define BCE_MCP_ROM								0x00150000
4607#define BCE_MCP_SCRATCH							0x00160000
4608
4609#define BCE_SHM_HDR_SIGNATURE					BCE_MCP_SCRATCH
4610#define BCE_SHM_HDR_SIGNATURE_SIG_MASK			0xffff0000
4611#define BCE_SHM_HDR_SIGNATURE_SIG				0x53530000
4612#define BCE_SHM_HDR_SIGNATURE_VER_MASK			0x000000ff
4613#define BCE_SHM_HDR_SIGNATURE_VER_ONE			0x00000001
4614
4615#define BCE_SHM_HDR_ADDR_0				BCE_MCP_SCRATCH + 4
4616#define BCE_SHM_HDR_ADDR_1				BCE_MCP_SCRATCH + 8
4617
4618/****************************************************************************/
4619/* End machine generated definitions.                                     */
4620/****************************************************************************/
4621
4622/****************************************************************************/
4623/* Begin firmware definitions.                                              */
4624/****************************************************************************/
4625/* The following definitions refer to pre-defined locations in processor    */
4626/* memory space which allows the driver to enable particular functionality  */
4627/* within the firmware or read specfic information about the running        */
4628/* firmware.                                                                */
4629/****************************************************************************/
4630
4631/*
4632 * Perfect match control register.
4633 * 0 = Default.  All received unicst packets matching MAC address
4634 *     BCE_EMAC_MAC_MATCH[0:1,8:9,10:11,12:13,14:15] are sent to receive queue
4635 *     0, all other perfect match registers are reserved.
4636 * 1 = All received unicast packets matching MAC address
4637 *     BCE_EMAC_MAC_MATCH[0:1] are mapped to receive queue 0,
4638 *     BCE_EMAC_MAC_MATCH[2:3] is mapped to receive queue 1, etc.
4639 * 2 = All received unicast packets matching any BCE_EMAC_MAC_MATCH[] register
4640 *     are sent to receive queue 0.
4641 */
4642#define BCE_RXP_PM_CTRL			0x0e00d0
4643
4644/*
4645 * This firmware statistic records the number of frames that
4646 * were dropped because there were no buffers available in the
4647 * receive chain.
4648 */
4649#define BCE_COM_NO_BUFFERS		0x120084
4650/****************************************************************************/
4651/* End firmware definitions.                                                */
4652/****************************************************************************/
4653
4654#define NUM_MC_HASH_REGISTERS   8
4655
4656
4657/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0.  */
4658#define PHY_BCM5706_PHY_ID                          0x00206160
4659
4660#define PHY_ID(id)                                  ((id) & 0xfffffff0)
4661#define PHY_REV_ID(id)                              ((id) & 0xf)
4662
4663/* 5708 Serdes PHY registers */
4664
4665#define BCM5708S_UP1				0xb
4666
4667#define BCM5708S_UP1_2G5			0x1
4668
4669#define BCM5708S_BLK_ADDR			0x1f
4670
4671#define BCM5708S_BLK_ADDR_DIG			0x0000
4672#define BCM5708S_BLK_ADDR_DIG3			0x0002
4673#define BCM5708S_BLK_ADDR_TX_MISC		0x0005
4674
4675/* Digital Block */
4676#define BCM5708S_1000X_CTL1			0x10
4677
4678#define BCM5708S_1000X_CTL1_FIBER_MODE		0x0001
4679#define BCM5708S_1000X_CTL1_AUTODET_EN		0x0010
4680
4681#define BCM5708S_1000X_CTL2			0x11
4682
4683#define BCM5708S_1000X_CTL2_PLLEL_DET_EN	0x0001
4684
4685#define BCM5708S_1000X_STAT1			0x14
4686
4687#define BCM5708S_1000X_STAT1_SGMII		0x0001
4688#define BCM5708S_1000X_STAT1_LINK		0x0002
4689#define BCM5708S_1000X_STAT1_FD			0x0004
4690#define BCM5708S_1000X_STAT1_SPEED_MASK		0x0018
4691#define BCM5708S_1000X_STAT1_SPEED_10		0x0000
4692#define BCM5708S_1000X_STAT1_SPEED_100		0x0008
4693#define BCM5708S_1000X_STAT1_SPEED_1G		0x0010
4694#define BCM5708S_1000X_STAT1_SPEED_2G5		0x0018
4695#define BCM5708S_1000X_STAT1_TX_PAUSE		0x0020
4696#define BCM5708S_1000X_STAT1_RX_PAUSE		0x0040
4697
4698/* Digital3 Block */
4699#define BCM5708S_DIG_3_0			0x10
4700
4701#define BCM5708S_DIG_3_0_USE_IEEE		0x0001
4702
4703/* Tx/Misc Block */
4704#define BCM5708S_TX_ACTL1			0x15
4705
4706#define BCM5708S_TX_ACTL1_DRIVER_VCM		0x30
4707
4708#define BCM5708S_TX_ACTL3			0x17
4709
4710#define RX_COPY_THRESH			92
4711
4712#define DMA_READ_CHANS	5
4713#define DMA_WRITE_CHANS	3
4714
4715/* Use the natural page size of the host CPU. */
4716/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */
4717#define BCM_PAGE_BITS	PAGE_SHIFT
4718#define BCM_PAGE_SIZE	PAGE_SIZE
4719#define BCM_PAGE_MASK	(BCM_PAGE_SIZE - 1)
4720#define BCM_PAGES(x)	((((x) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) >> BCM_PAGE_BITS)
4721
4722/*
4723 * Page count must remain a power of 2 for all
4724 * of the math to work correctly.
4725 */
4726#define TX_PAGES	2
4727#define TOTAL_TX_BD_PER_PAGE  (BCM_PAGE_SIZE / sizeof(struct tx_bd))
4728#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1)
4729#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES)
4730#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES)
4731#define MAX_TX_BD (TOTAL_TX_BD - 1)
4732
4733#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) ==	\
4734		(USABLE_TX_BD_PER_PAGE - 1)) ?					  	\
4735		(x) + 2 : (x) + 1
4736
4737#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD)
4738
4739#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4740#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
4741
4742/*
4743 * Page count must remain a power of 2 for all
4744 * of the math to work correctly.
4745 */
4746#define RX_PAGES	2
4747#define TOTAL_RX_BD_PER_PAGE  (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4748#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1)
4749#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES)
4750#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES)
4751#define MAX_RX_BD (TOTAL_RX_BD - 1)
4752
4753#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) ==	\
4754		(USABLE_RX_BD_PER_PAGE - 1)) ?					\
4755		(x) + 2 : (x) + 1
4756
4757#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD)
4758
4759#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4760#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE)
4761
4762/*
4763 * To accomodate jumbo frames, the page chain should
4764 * be 4 times larger than the receive chain.
4765 */
4766#define PG_PAGES	(RX_PAGES * 4)
4767#define TOTAL_PG_BD_PER_PAGE  (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4768#define USABLE_PG_BD_PER_PAGE (TOTAL_PG_BD_PER_PAGE - 1)
4769#define TOTAL_PG_BD (TOTAL_PG_BD_PER_PAGE * PG_PAGES)
4770#define USABLE_PG_BD (USABLE_PG_BD_PER_PAGE * PG_PAGES)
4771#define MAX_PG_BD (TOTAL_PG_BD - 1)
4772
4773#define NEXT_PG_BD(x) (((x) & USABLE_PG_BD_PER_PAGE) ==	\
4774		(USABLE_PG_BD_PER_PAGE - 1)) ?					\
4775		(x) + 2 : (x) + 1
4776
4777#define PG_CHAIN_IDX(x) ((x) & MAX_PG_BD)
4778
4779#define PG_PAGE(x) (((x) & ~USABLE_PG_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4780#define PG_IDX(x) ((x) & USABLE_PG_BD_PER_PAGE)
4781
4782/* Context size. */
4783#define CTX_SHIFT                   7
4784#define CTX_SIZE                    (1 << CTX_SHIFT)
4785#define CTX_MASK                    (CTX_SIZE - 1)
4786#define GET_CID_ADDR(_cid)          ((_cid) << CTX_SHIFT)
4787#define GET_CID(_cid_addr)          ((_cid_addr) >> CTX_SHIFT)
4788
4789#define PHY_CTX_SHIFT               6
4790#define PHY_CTX_SIZE                (1 << PHY_CTX_SHIFT)
4791#define PHY_CTX_MASK                (PHY_CTX_SIZE - 1)
4792#define GET_PCID_ADDR(_pcid)        ((_pcid) << PHY_CTX_SHIFT)
4793#define GET_PCID(_pcid_addr)        ((_pcid_addr) >> PHY_CTX_SHIFT)
4794
4795#define MB_KERNEL_CTX_SHIFT         8
4796#define MB_KERNEL_CTX_SIZE          (1 << MB_KERNEL_CTX_SHIFT)
4797#define MB_KERNEL_CTX_MASK          (MB_KERNEL_CTX_SIZE - 1)
4798#define MB_GET_CID_ADDR(_cid)       (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
4799
4800#define MAX_CID_CNT                 0x4000
4801#define MAX_CID_ADDR                (GET_CID_ADDR(MAX_CID_CNT))
4802#define INVALID_CID_ADDR            0xffffffff
4803
4804#define TX_CID		16
4805#define RX_CID		0
4806
4807#define MB_TX_CID_ADDR	MB_GET_CID_ADDR(TX_CID)
4808#define MB_RX_CID_ADDR	MB_GET_CID_ADDR(RX_CID)
4809
4810/****************************************************************************/
4811/* BCE Processor Firmwware Load Definitions                                 */
4812/****************************************************************************/
4813
4814struct cpu_reg {
4815	u32 mode;
4816	u32 mode_value_halt;
4817	u32 mode_value_sstep;
4818
4819	u32 state;
4820	u32 state_value_clear;
4821
4822	u32 gpr0;
4823	u32 evmask;
4824	u32 pc;
4825	u32 inst;
4826	u32 bp;
4827
4828	u32 spad_base;
4829
4830	u32 mips_view_base;
4831};
4832
4833struct fw_info {
4834	u32 ver_major;
4835	u32 ver_minor;
4836	u32 ver_fix;
4837
4838	u32 start_addr;
4839
4840	/* Text section. */
4841	u32 text_addr;
4842	u32 text_len;
4843	u32 text_index;
4844	u32 *text;
4845
4846	/* Data section. */
4847	u32 data_addr;
4848	u32 data_len;
4849	u32 data_index;
4850	u32 *data;
4851
4852	/* SBSS section. */
4853	u32 sbss_addr;
4854	u32 sbss_len;
4855	u32 sbss_index;
4856	u32 *sbss;
4857
4858	/* BSS section. */
4859	u32 bss_addr;
4860	u32 bss_len;
4861	u32 bss_index;
4862	u32 *bss;
4863
4864	/* Read-only section. */
4865	u32 rodata_addr;
4866	u32 rodata_len;
4867	u32 rodata_index;
4868	u32 *rodata;
4869};
4870
4871#define RV2P_PROC1                              0
4872#define RV2P_PROC2                              1
4873
4874#define BCE_MIREG(x)	((x & 0x1F) << 16)
4875#define BCE_MIPHY(x)	((x & 0x1F) << 21)
4876#define BCE_PHY_TIMEOUT	50
4877
4878#define BCE_NVRAM_SIZE 					0x200
4879#define BCE_NVRAM_MAGIC					0x669955aa
4880#define BCE_CRC32_RESIDUAL				0xdebb20e3
4881
4882#define BCE_TX_TIMEOUT					5
4883
4884#define BCE_MAX_SEGMENTS				32
4885#define BCE_TSO_MAX_SIZE				65536
4886#define BCE_TSO_MAX_SEG_SIZE			4096
4887
4888#define BCE_DMA_ALIGN		 			8
4889#define BCE_DMA_BOUNDARY				0
4890
4891/* The BCM5708 has a problem with addresses greater that 40bits. */
4892/* Handle the sizing issue in an architecture agnostic fashion.  */
4893#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
4894#define BCE_BUS_SPACE_MAXADDR		BUS_SPACE_MAXADDR
4895#else
4896#define BCE_BUS_SPACE_MAXADDR		0xFFFFFFFFFF
4897#endif
4898
4899/*
4900 * XXX Checksum offload involving IP fragments seems to cause problems on
4901 * transmit.  Disable it for now, hopefully there will be a more elegant
4902 * solution later.
4903 */
4904#ifdef BCE_IP_CSUM
4905#define BCE_IF_HWASSIST	(CSUM_IP | CSUM_TCP | CSUM_UDP)
4906#else
4907#define BCE_IF_HWASSIST	(CSUM_TCP | CSUM_UDP)
4908#endif
4909
4910#if __FreeBSD_version < 700000
4911#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
4912							IFCAP_HWCSUM | IFCAP_JUMBO_MTU)
4913#else
4914#define BCE_IF_CAPABILITIES (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | \
4915							IFCAP_HWCSUM | IFCAP_JUMBO_MTU | IFCAP_VLAN_HWCSUM)
4916#endif
4917
4918#define BCE_MIN_MTU						60
4919#define BCE_MIN_ETHER_MTU				64
4920
4921#define BCE_MAX_STD_MTU					1500
4922#define BCE_MAX_STD_ETHER_MTU			1518
4923#define BCE_MAX_STD_ETHER_MTU_VLAN		1522
4924
4925#define BCE_MAX_JUMBO_MTU			 	9000
4926#define BCE_MAX_JUMBO_ETHER_MTU			9018
4927#define BCE_MAX_JUMBO_ETHER_MTU_VLAN 	9022
4928
4929
4930/****************************************************************************/
4931/* BCE Device State Data Structure                                          */
4932/****************************************************************************/
4933
4934#define BCE_STATUS_BLK_SZ		sizeof(struct status_block)
4935#define BCE_STATS_BLK_SZ		sizeof(struct statistics_block)
4936#define BCE_TX_CHAIN_PAGE_SZ	BCM_PAGE_SIZE
4937#define BCE_RX_CHAIN_PAGE_SZ	BCM_PAGE_SIZE
4938#define BCE_PG_CHAIN_PAGE_SZ	BCM_PAGE_SIZE
4939
4940struct bce_softc
4941{
4942	/* MUST start with ifnet pointer (see definition of miibus_statchg()) */
4943	struct ifnet		*bce_ifp;			/* Interface info */
4944	device_t			bce_dev;			/* Parent device handle */
4945	u_int8_t			bce_unit;			/* Interface number */
4946	struct resource		*bce_res_mem;  		/* Device resource handle */
4947	struct ifmedia		bce_ifmedia;		/* TBI media info */
4948	bus_space_tag_t		bce_btag;			/* Device bus tag */
4949	bus_space_handle_t	bce_bhandle;		/* Device bus handle */
4950	vm_offset_t			bce_vhandle;		/* Device virtual memory handle */
4951	struct resource		*bce_res_irq;		/* IRQ Resource Handle */
4952	struct mtx			bce_mtx;			/* Mutex */
4953	void				*bce_intrhand;		/* Interrupt handler */
4954
4955	/* ASIC Chip ID. */
4956	u32					bce_chipid;
4957
4958	/* General controller flags. */
4959	u32					bce_flags;
4960#define BCE_PCIX_FLAG				0x00000001
4961#define BCE_PCI_32BIT_FLAG 			0x00000002
4962#define BCE_ONE_TDMA_FLAG			0x00000004		/* Deprecated */
4963#define BCE_NO_WOL_FLAG				0x00000008
4964#define BCE_USING_DAC_FLAG			0x00000010
4965#define BCE_USING_MSI_FLAG 			0x00000020
4966#define BCE_MFW_ENABLE_FLAG			0x00000040
4967
4968	/* PHY specific flags. */
4969	u32					bce_phy_flags;
4970#define BCE_PHY_SERDES_FLAG					0x00000001
4971#define BCE_PHY_CRC_FIX_FLAG				0x00000002
4972#define BCE_PHY_PARALLEL_DETECT_FLAG		0x00000004
4973#define BCE_PHY_2_5G_CAPABLE_FLAG			0x00000008
4974#define BCE_PHY_INT_MODE_MASK_FLAG			0x00000300
4975#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG	0x00000100
4976#define BCE_PHY_INT_MODE_LINK_READY_FLAG	0x00000200
4977
4978	/* Values that need to be shared with the PHY driver. */
4979	u32					bce_shared_hw_cfg;
4980	u32					bce_port_hw_cfg;
4981
4982	bus_addr_t			max_bus_addr;
4983	u16					bus_speed_mhz;		/* PCI bus speed */
4984	struct flash_spec	*bce_flash_info;	/* Flash NVRAM settings */
4985	u32					bce_flash_size;		/* Flash NVRAM size */
4986	u32					bce_shmem_base;		/* Shared Memory base address */
4987	char *				bce_name;			/* Name string */
4988
4989	/* Tracks the version of bootcode firmware. */
4990	u32					bce_fw_ver;
4991
4992	/* Tracks the state of the firmware.  0 = Running while any     */
4993	/* other value indicates that the firmware is not responding.   */
4994	u16					bce_fw_timed_out;
4995
4996	/* An incrementing sequence used to coordinate messages passed   */
4997	/* from the driver to the firmware.                              */
4998	u16					bce_fw_wr_seq;
4999
5000	/* An incrementing sequence used to let the firmware know that   */
5001	/* the driver is still operating.  Without the pulse, management */
5002	/* firmware such as IPMI or UMP will operate in OS absent state. */
5003	u16					bce_fw_drv_pulse_wr_seq;
5004
5005	/* Ethernet MAC address. */
5006	u_char				eaddr[6];
5007
5008	/* These setting are used by the host coalescing (HC) block to   */
5009	/* to control how often the status block, statistics block and   */
5010	/* interrupts are generated.                                     */
5011	u16					bce_tx_quick_cons_trip_int;
5012	u16					bce_tx_quick_cons_trip;
5013	u16					bce_rx_quick_cons_trip_int;
5014	u16					bce_rx_quick_cons_trip;
5015	u16					bce_comp_prod_trip_int;
5016	u16					bce_comp_prod_trip;
5017	u16					bce_tx_ticks_int;
5018	u16					bce_tx_ticks;
5019	u16					bce_rx_ticks_int;
5020	u16					bce_rx_ticks;
5021	u16					bce_com_ticks_int;
5022	u16					bce_com_ticks;
5023	u16					bce_cmd_ticks_int;
5024	u16					bce_cmd_ticks;
5025	u32					bce_stats_ticks;
5026
5027	/* The address of the integrated PHY on the MII bus. */
5028	int					bce_phy_addr;
5029
5030	/* The device handle for the MII bus child device. */
5031	device_t			bce_miibus;
5032
5033	/* Driver maintained TX chain pointers and byte counter. */
5034	u16					rx_prod;
5035	u16					rx_cons;
5036	u32					rx_prod_bseq;	/* Counts the bytes used.  */
5037	u16					tx_prod;
5038	u16					tx_cons;
5039	u32					tx_prod_bseq;	/* Counts the bytes used.  */
5040	u16					pg_prod;
5041	u16					pg_cons;
5042
5043	int					bce_link;
5044	struct callout		bce_tick_callout;
5045	struct callout		bce_pulse_callout;
5046
5047	int watchdog_timer;			/* ticks until chip reset */
5048
5049	/* Frame size and mbuf allocation size for RX frames. */
5050	u32					max_frame_size;
5051	int					rx_bd_mbuf_alloc_size;
5052	int					rx_bd_mbuf_data_len;
5053	int					rx_bd_mbuf_align_pad;
5054	int					pg_bd_mbuf_alloc_size;
5055
5056	/* Receive mode settings (i.e promiscuous, multicast, etc.). */
5057	u32					rx_mode;
5058
5059#ifdef DEVICE_POLLING
5060	int					bce_rxcycles;				/* Counter for receive polling cycles */
5061#endif
5062
5063	/* Bus tag for the bce controller. */
5064	bus_dma_tag_t		parent_tag;
5065
5066	/* H/W maintained TX buffer descriptor chain structure. */
5067	bus_dma_tag_t		tx_bd_chain_tag;
5068	bus_dmamap_t		tx_bd_chain_map[TX_PAGES];
5069	struct tx_bd		*tx_bd_chain[TX_PAGES];
5070	bus_addr_t			tx_bd_chain_paddr[TX_PAGES];
5071
5072	/* H/W maintained RX buffer descriptor chain structure. */
5073	bus_dma_tag_t		rx_bd_chain_tag;
5074	bus_dmamap_t		rx_bd_chain_map[RX_PAGES];
5075	struct rx_bd		*rx_bd_chain[RX_PAGES];
5076	bus_addr_t			rx_bd_chain_paddr[RX_PAGES];
5077
5078	/* H/W maintained page buffer descriptor chain structure. */
5079	bus_dma_tag_t		pg_bd_chain_tag;
5080	bus_dmamap_t		pg_bd_chain_map[PG_PAGES];
5081	struct rx_bd		*pg_bd_chain[PG_PAGES];
5082	bus_addr_t			pg_bd_chain_paddr[PG_PAGES];
5083
5084	/* H/W maintained status block. */
5085	bus_dma_tag_t		status_tag;
5086	bus_dmamap_t		status_map;
5087	struct status_block	*status_block;				/* virtual address */
5088	bus_addr_t			status_block_paddr;			/* Physical address */
5089
5090	/* Driver maintained status block values. */
5091	u16					last_status_idx;
5092	u16					hw_rx_cons;
5093	u16					hw_tx_cons;
5094
5095	/* H/W maintained statistics block. */
5096	bus_dma_tag_t		stats_tag;
5097	bus_dmamap_t		stats_map;
5098	struct statistics_block *stats_block;		/* Virtual address */
5099	bus_addr_t			stats_block_paddr;		/* Physical address */
5100
5101	/* Bus tag for RX/TX mbufs. */
5102	bus_dma_tag_t		rx_mbuf_tag;
5103	bus_dma_tag_t		tx_mbuf_tag;
5104	bus_dma_tag_t		pg_mbuf_tag;
5105
5106	/* S/W maintained mbuf TX chain structure. */
5107	bus_dmamap_t		tx_mbuf_map[TOTAL_TX_BD];
5108	struct mbuf			*tx_mbuf_ptr[TOTAL_TX_BD];
5109
5110	/* S/W maintained mbuf RX chain structure. */
5111	bus_dmamap_t		rx_mbuf_map[TOTAL_RX_BD];
5112	struct mbuf			*rx_mbuf_ptr[TOTAL_RX_BD];
5113
5114	/* S/W maintained mbuf page chain structure. */
5115	bus_dmamap_t		pg_mbuf_map[TOTAL_PG_BD];
5116	struct mbuf			*pg_mbuf_ptr[TOTAL_PG_BD];
5117
5118	/* Track the number of buffer descriptors in use. */
5119	u16 free_rx_bd;
5120	u16 max_rx_bd;
5121	u16 used_tx_bd;
5122	u16 max_tx_bd;
5123	u16 free_pg_bd;
5124	u16 max_pg_bd;
5125
5126	/* Provides access to hardware statistics through sysctl. */
5127	u64 stat_IfHCInOctets;
5128	u64 stat_IfHCInBadOctets;
5129	u64 stat_IfHCOutOctets;
5130	u64 stat_IfHCOutBadOctets;
5131	u64 stat_IfHCInUcastPkts;
5132	u64 stat_IfHCInMulticastPkts;
5133	u64 stat_IfHCInBroadcastPkts;
5134	u64 stat_IfHCOutUcastPkts;
5135	u64 stat_IfHCOutMulticastPkts;
5136	u64 stat_IfHCOutBroadcastPkts;
5137
5138	u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5139	u32 stat_Dot3StatsCarrierSenseErrors;
5140	u32 stat_Dot3StatsFCSErrors;
5141	u32 stat_Dot3StatsAlignmentErrors;
5142	u32 stat_Dot3StatsSingleCollisionFrames;
5143	u32 stat_Dot3StatsMultipleCollisionFrames;
5144	u32 stat_Dot3StatsDeferredTransmissions;
5145	u32 stat_Dot3StatsExcessiveCollisions;
5146	u32 stat_Dot3StatsLateCollisions;
5147	u32 stat_EtherStatsCollisions;
5148	u32 stat_EtherStatsFragments;
5149	u32 stat_EtherStatsJabbers;
5150	u32 stat_EtherStatsUndersizePkts;
5151	u32 stat_EtherStatsOverrsizePkts;
5152	u32 stat_EtherStatsPktsRx64Octets;
5153	u32 stat_EtherStatsPktsRx65Octetsto127Octets;
5154	u32 stat_EtherStatsPktsRx128Octetsto255Octets;
5155	u32 stat_EtherStatsPktsRx256Octetsto511Octets;
5156	u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
5157	u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
5158	u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
5159	u32 stat_EtherStatsPktsTx64Octets;
5160	u32 stat_EtherStatsPktsTx65Octetsto127Octets;
5161	u32 stat_EtherStatsPktsTx128Octetsto255Octets;
5162	u32 stat_EtherStatsPktsTx256Octetsto511Octets;
5163	u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
5164	u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
5165	u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
5166	u32 stat_XonPauseFramesReceived;
5167	u32 stat_XoffPauseFramesReceived;
5168	u32 stat_OutXonSent;
5169	u32 stat_OutXoffSent;
5170	u32 stat_FlowControlDone;
5171	u32 stat_MacControlFramesReceived;
5172	u32 stat_XoffStateEntered;
5173	u32 stat_IfInFramesL2FilterDiscards;
5174	u32 stat_IfInRuleCheckerDiscards;
5175	u32 stat_IfInFTQDiscards;
5176	u32 stat_IfInMBUFDiscards;
5177	u32 stat_IfInRuleCheckerP4Hit;
5178	u32 stat_CatchupInRuleCheckerDiscards;
5179	u32 stat_CatchupInFTQDiscards;
5180	u32 stat_CatchupInMBUFDiscards;
5181	u32 stat_CatchupInRuleCheckerP4Hit;
5182
5183	/* Provides access to certain firmware statistics. */
5184	u32 com_no_buffers;
5185
5186	/* Mbuf allocation failure counter. */
5187	u32	mbuf_alloc_failed;
5188
5189	/* TX DMA mapping failure counter. */
5190	u32 tx_dma_map_failures;
5191
5192	u64 rx_intr_time;
5193
5194#ifdef BCE_DEBUG
5195	/* Track the number of enqueued mbufs. */
5196	int	debug_tx_mbuf_alloc;
5197	int debug_rx_mbuf_alloc;
5198	int debug_pg_mbuf_alloc;
5199
5200	/* Track how many and what type of interrupts are generated. */
5201	u32 interrupts_generated;
5202	u32 interrupts_handled;
5203	u32 rx_interrupts;
5204	u32 tx_interrupts;
5205
5206	/* Track interrupt time (25MHz clock). */
5207	u64 tx_intr_time;
5208
5209	u32	rx_low_watermark;			/* Lowest number of rx_bd's free. */
5210	u32 rx_empty_count;				/* Number of times the RX chain was empty. */
5211
5212	u32	pg_low_watermark;			/* Lowest number of pages free. */
5213	u32 pg_empty_count; 			/* Number of times the page chain was empty. */
5214
5215	u32 tx_hi_watermark;			/* Greatest number of tx_bd's used. */
5216	u32	tx_full_count;				/* Number of times the TX chain was full. */
5217
5218	/* Simulated mbuf allocation failure counter. */
5219	u32	debug_mbuf_sim_alloc_failed;
5220
5221	u32 l2fhdr_status_errors;
5222	u32 unexpected_attentions;
5223	u32	lost_status_block_updates;
5224
5225	u32	requested_tso_frames;		/* Number of TSO frames enqueued. */
5226#endif
5227};
5228
5229#endif /* #ifndef _BCE_H_DEFINED */
5230
5231