ar9287_attach.c revision 224634 
1/*
2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c 224634 2011-08-03 13:39:11Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v14.h"		/* XXX for tx/rx gain */
26#include "ah_eeprom_9287.h"
27
28#include "ar9002/ar9280.h"
29#include "ar9002/ar9287.h"
30#include "ar5416/ar5416reg.h"
31#include "ar5416/ar5416phy.h"
32
33#include "ar9001/ar9130_eeprom.h"
34
35#include "ar9002/ar9287_cal.h"
36#include "ar9002/ar9287_reset.h"
37#include "ar9002/ar9287_olc.h"
38
39#include "ar9002/ar9287.ini"
40
41static const HAL_PERCAL_DATA ar9287_iq_cal = {		/* single sample */
42	.calName = "IQ", .calType = IQ_MISMATCH_CAL,
43	.calNumSamples	= MIN_CAL_SAMPLES,
44	.calCountMax	= PER_MAX_LOG_COUNT,
45	.calCollect	= ar5416IQCalCollect,
46	.calPostProc	= ar5416IQCalibration
47};
48static const HAL_PERCAL_DATA ar9287_adc_gain_cal = {	/* single sample */
49	.calName = "ADC Gain", .calType = ADC_GAIN_CAL,
50	.calNumSamples	= MIN_CAL_SAMPLES,
51	.calCountMax	= PER_MIN_LOG_COUNT,
52	.calCollect	= ar5416AdcGainCalCollect,
53	.calPostProc	= ar5416AdcGainCalibration
54};
55static const HAL_PERCAL_DATA ar9287_adc_dc_cal = {	/* single sample */
56	.calName = "ADC DC", .calType = ADC_DC_CAL,
57	.calNumSamples	= MIN_CAL_SAMPLES,
58	.calCountMax	= PER_MIN_LOG_COUNT,
59	.calCollect	= ar5416AdcDcCalCollect,
60	.calPostProc	= ar5416AdcDcCalibration
61};
62static const HAL_PERCAL_DATA ar9287_adc_init_dc_cal = {
63	.calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
64	.calNumSamples	= MIN_CAL_SAMPLES,
65	.calCountMax	= INIT_LOG_COUNT,
66	.calCollect	= ar5416AdcDcCalCollect,
67	.calPostProc	= ar5416AdcDcCalibration
68};
69
70static void ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore);
71static HAL_BOOL ar9287FillCapabilityInfo(struct ath_hal *ah);
72static void ar9287WriteIni(struct ath_hal *ah,
73	const struct ieee80211_channel *chan);
74
75static void
76ar9287AniSetup(struct ath_hal *ah)
77{
78	/*
79	 * These are the parameters from the AR5416 ANI code;
80	 * they likely need quite a bit of adjustment for the
81	 * AR9280.
82	 */
83        static const struct ar5212AniParams aniparams = {
84                .maxNoiseImmunityLevel  = 4,    /* levels 0..4 */
85                .totalSizeDesired       = { -55, -55, -55, -55, -62 },
86                .coarseHigh             = { -14, -14, -14, -14, -12 },
87                .coarseLow              = { -64, -64, -64, -64, -70 },
88                .firpwr                 = { -78, -78, -78, -78, -80 },
89                .maxSpurImmunityLevel   = 2,
90                .cycPwrThr1             = { 2, 4, 6 },
91                .maxFirstepLevel        = 2,    /* levels 0..2 */
92                .firstep                = { 0, 4, 8 },
93                .ofdmTrigHigh           = 500,
94                .ofdmTrigLow            = 200,
95                .cckTrigHigh            = 200,
96                .cckTrigLow             = 100,
97                .rssiThrHigh            = 40,
98                .rssiThrLow             = 7,
99                .period                 = 100,
100        };
101	/* NB: disable ANI noise immmunity for reliable RIFS rx */
102	AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;
103
104        /* NB: ANI is not enabled yet */
105        ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
106}
107
108/*
109 * Attach for an AR9287 part.
110 */
111static struct ath_hal *
112ar9287Attach(uint16_t devid, HAL_SOFTC sc,
113	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
114	HAL_STATUS *status)
115{
116	struct ath_hal_9287 *ahp9287;
117	struct ath_hal_5212 *ahp;
118	struct ath_hal *ah;
119	uint32_t val;
120	HAL_STATUS ecode;
121	HAL_BOOL rfStatus;
122	int8_t pwr_table_offset;
123
124	HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
125	    __func__, sc, (void*) st, (void*) sh);
126
127	/* NB: memory is returned zero'd */
128	ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287));
129	if (ahp9287 == AH_NULL) {
130		HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY,
131		    "%s: cannot allocate memory for state block\n", __func__);
132		*status = HAL_ENOMEM;
133		return AH_NULL;
134	}
135	ahp = AH5212(ahp9287);
136	ah = &ahp->ah_priv.h;
137
138	ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
139
140	/* XXX override with 9280 specific state */
141	/* override 5416 methods for our needs */
142	AH5416(ah)->ah_initPLL = ar9280InitPLL;
143
144	ah->ah_setAntennaSwitch		= ar9287SetAntennaSwitch;
145	ah->ah_configPCIE		= ar9287ConfigPCIE;
146
147	AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;
148	AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;
149	AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;
150	AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;
151	/* Better performance without ADC Gain Calibration */
152	AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;
153
154	AH5416(ah)->ah_spurMitigate	= ar9280SpurMitigate;
155	AH5416(ah)->ah_writeIni		= ar9287WriteIni;
156
157	ah->ah_setTxPower		= ar9287SetTransmitPower;
158	ah->ah_setBoardValues		= ar9287SetBoardValues;
159
160	AH5416(ah)->ah_olcInit		= ar9287olcInit;
161	AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;
162	//AH5416(ah)->ah_setPowerCalTable	= ar9287SetPowerCalTable;
163	AH5416(ah)->ah_cal_initcal	= ar9287InitCalHardware;
164	AH5416(ah)->ah_cal_pacal	= ar9287PACal;
165
166	/* XXX NF calibration */
167	/* XXX Ini override? (IFS vars - since the kiwi mac clock is faster?) */
168	/* XXX what else is kiwi-specific in the radio/calibration pathway? */
169
170	AH5416(ah)->ah_rx_chainmask	= AR9287_DEFAULT_RXCHAINMASK;
171	AH5416(ah)->ah_tx_chainmask	= AR9287_DEFAULT_TXCHAINMASK;
172
173	if (eepromdata) {
174		AH_PRIVATE((ah))->ah_eepromRead = ar9130EepromRead;
175		AH_PRIVATE((ah))->ah_eepromWrite = NULL;
176		ah->ah_eepromdata = eepromdata;
177	}
178
179	if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
180		/* reset chip */
181		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
182		    __func__);
183		ecode = HAL_EIO;
184		goto bad;
185	}
186
187	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
188		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
189		    __func__);
190		ecode = HAL_EIO;
191		goto bad;
192	}
193	/* Read Revisions from Chips before taking out of reset */
194	val = OS_REG_READ(ah, AR_SREV);
195	HALDEBUG(ah, HAL_DEBUG_ATTACH,
196	    "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
197	    __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
198	    MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
199	/* NB: include chip type to differentiate from pre-Sowl versions */
200	AH_PRIVATE(ah)->ah_macVersion =
201	    (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
202	AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
203	AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
204
205	/* Don't support Kiwi < 1.2; those are pre-release chips */
206	if (! AR_SREV_KIWI_12_OR_LATER(ah)) {
207		ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n");
208		ecode = HAL_EIO;
209		goto bad;
210	}
211
212	/* setup common ini data; rf backends handle remainder */
213	HAL_INI_INIT(&ahp->ah_ini_modes, ar9287Modes_9287_1_1, 6);
214	HAL_INI_INIT(&ahp->ah_ini_common, ar9287Common_9287_1_1, 2);
215
216	/* If pcie_clock_req */
217	HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
218	    ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2);
219
220	/* XXX WoW ini values */
221
222	/* Else */
223#if 0
224	HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
225	    ar9287PciePhy_clkreq_off_L1_9287_1_1, 2);
226#endif
227
228	/* Initialise Japan arrays */
229	HAL_INI_INIT(&ahp9287->ah_ini_cckFirNormal,
230	    ar9287Common_normal_cck_fir_coeff_9287_1_1, 2);
231	HAL_INI_INIT(&ahp9287->ah_ini_cckFirJapan2484,
232	    ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2);
233
234	ar5416AttachPCIE(ah);
235
236	ecode = ath_hal_9287EepromAttach(ah);
237	if (ecode != HAL_OK)
238		goto bad;
239
240	if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */
241		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
242		ecode = HAL_EIO;
243		goto bad;
244	}
245
246	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
247
248	if (!ar5212ChipTest(ah)) {
249		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
250		    __func__);
251		ecode = HAL_ESELFTEST;
252		goto bad;
253	}
254
255	/*
256	 * Set correct Baseband to analog shift
257	 * setting to access analog chips.
258	 */
259	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
260
261	/* Read Radio Chip Rev Extract */
262	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
263	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
264        case AR_RAD2133_SREV_MAJOR:	/* Sowl: 2G/3x3 */
265	case AR_RAD5133_SREV_MAJOR:	/* Sowl: 2+5G/3x3 */
266		break;
267	default:
268		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
269			AH_PRIVATE(ah)->ah_analog5GhzRev =
270				AR_RAD5133_SREV_MAJOR;
271			break;
272		}
273#ifdef AH_DEBUG
274		HALDEBUG(ah, HAL_DEBUG_ANY,
275		    "%s: 5G Radio Chip Rev 0x%02X is not supported by "
276		    "this driver\n", __func__,
277		    AH_PRIVATE(ah)->ah_analog5GhzRev);
278		ecode = HAL_ENOTSUPP;
279		goto bad;
280#endif
281	}
282	rfStatus = ar9287RfAttach(ah, &ecode);
283	if (!rfStatus) {
284		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
285		    __func__, ecode);
286		goto bad;
287	}
288
289	/*
290	 * We only implement open-loop TX power control
291	 * for the AR9287 in this codebase.
292	 */
293	if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
294		ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control"
295		    " isn't supported.\n");
296		ecode = HAL_ENOTSUPP;
297		goto bad;
298	}
299
300        /*
301         * Check whether the power table offset isn't the default.
302         * This can occur with eeprom minor V21 or greater on Merlin.
303         */
304	(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);
305	if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB)
306		ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",
307		    AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset);
308
309	/* setup rxgain table */
310	HAL_INI_INIT(&ahp9287->ah_ini_rxgain, ar9287Modes_rx_gain_9287_1_1, 6);
311
312	/* setup txgain table */
313	HAL_INI_INIT(&ahp9287->ah_ini_txgain, ar9287Modes_tx_gain_9287_1_1, 6);
314
315	/*
316	 * Got everything we need now to setup the capabilities.
317	 */
318	if (!ar9287FillCapabilityInfo(ah)) {
319		ecode = HAL_EEREAD;
320		goto bad;
321	}
322
323	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
324	if (ecode != HAL_OK) {
325		HALDEBUG(ah, HAL_DEBUG_ANY,
326		    "%s: error getting mac address from EEPROM\n", __func__);
327		goto bad;
328        }
329	/* XXX How about the serial number ? */
330	/* Read Reg Domain */
331	AH_PRIVATE(ah)->ah_currentRD =
332	    ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
333	AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT;
334
335	/*
336	 * ah_miscMode is populated by ar5416FillCapabilityInfo()
337	 * starting from griffin. Set here to make sure that
338	 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
339	 * placed into hardware.
340	 */
341	if (ahp->ah_miscMode != 0)
342		OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
343
344	ar9287AniSetup(ah);			/* Anti Noise Immunity */
345
346	/* Setup noise floor min/max/nominal values */
347	AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
348	AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
349	AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
350	AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ;
351	AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ;
352	AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ;
353
354	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
355
356	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
357
358	return ah;
359bad:
360	if (ah != AH_NULL)
361		ah->ah_detach(ah);
362	if (status)
363		*status = ecode;
364	return AH_NULL;
365}
366
367static void
368ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore)
369{
370	if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
371		ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
372		OS_DELAY(1000);
373		OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
374		OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);	/* Yes, Kiwi uses the Kite PCIe PHY WA */
375	}
376}
377
378static void
379ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
380{
381	u_int modesIndex, freqIndex;
382	int regWrites = 0;
383
384	/* Setup the indices for the next set of register array writes */
385	/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
386	if (IEEE80211_IS_CHAN_2GHZ(chan)) {
387		freqIndex = 2;
388		if (IEEE80211_IS_CHAN_HT40(chan))
389			modesIndex = 3;
390		else if (IEEE80211_IS_CHAN_108G(chan))
391			modesIndex = 5;
392		else
393			modesIndex = 4;
394	} else {
395		freqIndex = 1;
396		if (IEEE80211_IS_CHAN_HT40(chan) ||
397		    IEEE80211_IS_CHAN_TURBO(chan))
398			modesIndex = 2;
399		else
400			modesIndex = 1;
401	}
402
403	/* Set correct Baseband to analog shift setting to access analog chips. */
404	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
405	OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
406
407	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites);
408	regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites);
409	regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites);
410	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites);
411}
412
413#define	AR_BASE_FREQ_2GHZ	2300
414#define	AR_BASE_FREQ_5GHZ	4900
415#define	AR_SPUR_FEEQ_BOUND_HT40	19
416#define	AR_SPUR_FEEQ_BOUND_HT20	10
417
418
419
420/*
421 * Fill all software cached or static hardware state information.
422 * Return failure if capabilities are to come from EEPROM and
423 * cannot be read.
424 */
425static HAL_BOOL
426ar9287FillCapabilityInfo(struct ath_hal *ah)
427{
428	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
429
430	if (!ar5416FillCapabilityInfo(ah))
431		return AH_FALSE;
432	pCap->halNumGpioPins = 10;
433	pCap->halWowSupport = AH_TRUE;
434	pCap->halWowMatchPatternExact = AH_TRUE;
435#if 0
436	pCap->halWowMatchPatternDword = AH_TRUE;
437#endif
438
439	pCap->halCSTSupport = AH_TRUE;
440	pCap->halRifsRxSupport = AH_TRUE;
441	pCap->halRifsTxSupport = AH_TRUE;
442	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
443	pCap->halExtChanDfsSupport = AH_TRUE;
444	pCap->halUseCombinedRadarRssi = AH_TRUE;
445#if 0
446	/* XXX bluetooth */
447	pCap->halBtCoexSupport = AH_TRUE;
448#endif
449	pCap->halAutoSleepSupport = AH_FALSE;	/* XXX? */
450	pCap->hal4kbSplitTransSupport = AH_FALSE;
451	/* Disable this so Block-ACK works correctly */
452	pCap->halHasRxSelfLinkedTail = AH_FALSE;
453	pCap->halPSPollBroken = AH_FALSE;
454
455	/* Hardware supports (at least) single-stream STBC TX/RX */
456	pCap->halRxStbcSupport = 1;
457	pCap->halTxStbcSupport = 1;
458
459	/* Hardware supports short-GI w/ 20MHz */
460	pCap->halHTSGI20Support = 1;
461
462	pCap->halEnhancedDfsSupport = AH_TRUE;
463
464	return AH_TRUE;
465}
466
467/*
468 * This has been disabled - having the HAL flip chainmasks on/off
469 * when attempting to implement 11n disrupts things. For now, just
470 * leave this flipped off and worry about implementing TX diversity
471 * for legacy and MCS0-7 when 11n is fully functioning.
472 */
473HAL_BOOL
474ar9287SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
475{
476	return AH_TRUE;
477}
478
479static const char*
480ar9287Probe(uint16_t vendorid, uint16_t devid)
481{
482	if (vendorid == ATHEROS_VENDOR_ID &&
483	    (devid == AR9287_DEVID_PCI || devid == AR9287_DEVID_PCIE))
484		return "Atheros 9287";
485	return AH_NULL;
486}
487AH_CHIP(AR9287, ar9287Probe, ar9287Attach);
488