1/*
2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: releng/10.2/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c 244943 2013-01-02 00:38:01Z adrian $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v14.h"		/* XXX for tx/rx gain */
26#include "ah_eeprom_9287.h"
27
28#include "ar9002/ar9280.h"
29#include "ar9002/ar9287.h"
30#include "ar5416/ar5416reg.h"
31#include "ar5416/ar5416phy.h"
32
33#include "ar9002/ar9287_cal.h"
34#include "ar9002/ar9287_reset.h"
35#include "ar9002/ar9287_olc.h"
36
37#include "ar9002/ar9287.ini"
38
39static const HAL_PERCAL_DATA ar9287_iq_cal = {		/* single sample */
40	.calName = "IQ", .calType = IQ_MISMATCH_CAL,
41	.calNumSamples	= MIN_CAL_SAMPLES,
42	.calCountMax	= PER_MAX_LOG_COUNT,
43	.calCollect	= ar5416IQCalCollect,
44	.calPostProc	= ar5416IQCalibration
45};
46static const HAL_PERCAL_DATA ar9287_adc_gain_cal = {	/* single sample */
47	.calName = "ADC Gain", .calType = ADC_GAIN_CAL,
48	.calNumSamples	= MIN_CAL_SAMPLES,
49	.calCountMax	= PER_MIN_LOG_COUNT,
50	.calCollect	= ar5416AdcGainCalCollect,
51	.calPostProc	= ar5416AdcGainCalibration
52};
53static const HAL_PERCAL_DATA ar9287_adc_dc_cal = {	/* single sample */
54	.calName = "ADC DC", .calType = ADC_DC_CAL,
55	.calNumSamples	= MIN_CAL_SAMPLES,
56	.calCountMax	= PER_MIN_LOG_COUNT,
57	.calCollect	= ar5416AdcDcCalCollect,
58	.calPostProc	= ar5416AdcDcCalibration
59};
60static const HAL_PERCAL_DATA ar9287_adc_init_dc_cal = {
61	.calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
62	.calNumSamples	= MIN_CAL_SAMPLES,
63	.calCountMax	= INIT_LOG_COUNT,
64	.calCollect	= ar5416AdcDcCalCollect,
65	.calPostProc	= ar5416AdcDcCalibration
66};
67
68static void ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
69		HAL_BOOL power_off);
70static void ar9287DisablePCIE(struct ath_hal *ah);
71static HAL_BOOL ar9287FillCapabilityInfo(struct ath_hal *ah);
72static void ar9287WriteIni(struct ath_hal *ah,
73	const struct ieee80211_channel *chan);
74
75static void
76ar9287AniSetup(struct ath_hal *ah)
77{
78	/*
79	 * These are the parameters from the AR5416 ANI code;
80	 * they likely need quite a bit of adjustment for the
81	 * AR9287.
82	 */
83        static const struct ar5212AniParams aniparams = {
84                .maxNoiseImmunityLevel  = 4,    /* levels 0..4 */
85                .totalSizeDesired       = { -55, -55, -55, -55, -62 },
86                .coarseHigh             = { -14, -14, -14, -14, -12 },
87                .coarseLow              = { -64, -64, -64, -64, -70 },
88                .firpwr                 = { -78, -78, -78, -78, -80 },
89                .maxSpurImmunityLevel   = 7,
90                .cycPwrThr1             = { 2, 4, 6, 8, 10, 12, 14, 16 },
91                .maxFirstepLevel        = 2,    /* levels 0..2 */
92                .firstep                = { 0, 4, 8 },
93                .ofdmTrigHigh           = 500,
94                .ofdmTrigLow            = 200,
95                .cckTrigHigh            = 200,
96                .cckTrigLow             = 100,
97                .rssiThrHigh            = 40,
98                .rssiThrLow             = 7,
99                .period                 = 100,
100        };
101	/* NB: disable ANI noise immmunity for reliable RIFS rx */
102	AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;
103
104        /* NB: ANI is not enabled yet */
105        ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
106}
107
108/*
109 * Attach for an AR9287 part.
110 */
111static struct ath_hal *
112ar9287Attach(uint16_t devid, HAL_SOFTC sc,
113	HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
114	HAL_STATUS *status)
115{
116	struct ath_hal_9287 *ahp9287;
117	struct ath_hal_5212 *ahp;
118	struct ath_hal *ah;
119	uint32_t val;
120	HAL_STATUS ecode;
121	HAL_BOOL rfStatus;
122	int8_t pwr_table_offset;
123
124	HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
125	    __func__, sc, (void*) st, (void*) sh);
126
127	/* NB: memory is returned zero'd */
128	ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287));
129	if (ahp9287 == AH_NULL) {
130		HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
131		    "%s: cannot allocate memory for state block\n", __func__);
132		*status = HAL_ENOMEM;
133		return AH_NULL;
134	}
135	ahp = AH5212(ahp9287);
136	ah = &ahp->ah_priv.h;
137
138	ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
139
140	if (eepromdata != AH_NULL) {
141		AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
142		AH_PRIVATE(ah)->ah_eepromWrite = NULL;
143		ah->ah_eepromdata = eepromdata;
144	}
145
146
147	/* XXX override with 9280 specific state */
148	/* override 5416 methods for our needs */
149	AH5416(ah)->ah_initPLL = ar9280InitPLL;
150
151	ah->ah_setAntennaSwitch		= ar9287SetAntennaSwitch;
152	ah->ah_configPCIE		= ar9287ConfigPCIE;
153	ah->ah_disablePCIE		= ar9287DisablePCIE;
154
155	AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;
156	AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;
157	AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;
158	AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;
159	/* Better performance without ADC Gain Calibration */
160	AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;
161
162	AH5416(ah)->ah_spurMitigate	= ar9280SpurMitigate;
163	AH5416(ah)->ah_writeIni		= ar9287WriteIni;
164
165	ah->ah_setTxPower		= ar9287SetTransmitPower;
166	ah->ah_setBoardValues		= ar9287SetBoardValues;
167
168	AH5416(ah)->ah_olcInit		= ar9287olcInit;
169	AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;
170	//AH5416(ah)->ah_setPowerCalTable	= ar9287SetPowerCalTable;
171	AH5416(ah)->ah_cal_initcal	= ar9287InitCalHardware;
172	AH5416(ah)->ah_cal_pacal	= ar9287PACal;
173
174	/* XXX NF calibration */
175	/* XXX Ini override? (IFS vars - since the kiwi mac clock is faster?) */
176	/* XXX what else is kiwi-specific in the radio/calibration pathway? */
177
178	AH5416(ah)->ah_rx_chainmask	= AR9287_DEFAULT_RXCHAINMASK;
179	AH5416(ah)->ah_tx_chainmask	= AR9287_DEFAULT_TXCHAINMASK;
180
181	if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
182		/* reset chip */
183		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
184		    __func__);
185		ecode = HAL_EIO;
186		goto bad;
187	}
188
189	if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
190		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
191		    __func__);
192		ecode = HAL_EIO;
193		goto bad;
194	}
195	/* Read Revisions from Chips before taking out of reset */
196	val = OS_REG_READ(ah, AR_SREV);
197	HALDEBUG(ah, HAL_DEBUG_ATTACH,
198	    "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
199	    __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
200	    MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
201	/* NB: include chip type to differentiate from pre-Sowl versions */
202	AH_PRIVATE(ah)->ah_macVersion =
203	    (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
204	AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
205	AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
206
207	/* Don't support Kiwi < 1.2; those are pre-release chips */
208	if (! AR_SREV_KIWI_12_OR_LATER(ah)) {
209		ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n");
210		ecode = HAL_EIO;
211		goto bad;
212	}
213
214	/* setup common ini data; rf backends handle remainder */
215	HAL_INI_INIT(&ahp->ah_ini_modes, ar9287Modes_9287_1_1, 6);
216	HAL_INI_INIT(&ahp->ah_ini_common, ar9287Common_9287_1_1, 2);
217
218	/* If pcie_clock_req */
219	HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
220	    ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2);
221
222	/* XXX WoW ini values */
223
224	/* Else */
225#if 0
226	HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
227	    ar9287PciePhy_clkreq_off_L1_9287_1_1, 2);
228#endif
229
230	/* Initialise Japan arrays */
231	HAL_INI_INIT(&ahp9287->ah_ini_cckFirNormal,
232	    ar9287Common_normal_cck_fir_coeff_9287_1_1, 2);
233	HAL_INI_INIT(&ahp9287->ah_ini_cckFirJapan2484,
234	    ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2);
235
236	ar5416AttachPCIE(ah);
237
238	ecode = ath_hal_9287EepromAttach(ah);
239	if (ecode != HAL_OK)
240		goto bad;
241
242	if (!ar5416ChipReset(ah, AH_NULL)) {	/* reset chip */
243		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
244		ecode = HAL_EIO;
245		goto bad;
246	}
247
248	AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
249
250	if (!ar5212ChipTest(ah)) {
251		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
252		    __func__);
253		ecode = HAL_ESELFTEST;
254		goto bad;
255	}
256
257	/*
258	 * Set correct Baseband to analog shift
259	 * setting to access analog chips.
260	 */
261	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
262
263	/* Read Radio Chip Rev Extract */
264	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
265	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
266        case AR_RAD2133_SREV_MAJOR:	/* Sowl: 2G/3x3 */
267	case AR_RAD5133_SREV_MAJOR:	/* Sowl: 2+5G/3x3 */
268		break;
269	default:
270		if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
271			AH_PRIVATE(ah)->ah_analog5GhzRev =
272				AR_RAD5133_SREV_MAJOR;
273			break;
274		}
275#ifdef AH_DEBUG
276		HALDEBUG(ah, HAL_DEBUG_ANY,
277		    "%s: 5G Radio Chip Rev 0x%02X is not supported by "
278		    "this driver\n", __func__,
279		    AH_PRIVATE(ah)->ah_analog5GhzRev);
280		ecode = HAL_ENOTSUPP;
281		goto bad;
282#endif
283	}
284	rfStatus = ar9287RfAttach(ah, &ecode);
285	if (!rfStatus) {
286		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
287		    __func__, ecode);
288		goto bad;
289	}
290
291	/*
292	 * We only implement open-loop TX power control
293	 * for the AR9287 in this codebase.
294	 */
295	if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
296		ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control"
297		    " isn't supported.\n");
298		ecode = HAL_ENOTSUPP;
299		goto bad;
300	}
301
302        /*
303         * Check whether the power table offset isn't the default.
304         * This can occur with eeprom minor V21 or greater on Merlin.
305         */
306	(void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);
307	if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB)
308		ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",
309		    AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset);
310
311	/* setup rxgain table */
312	HAL_INI_INIT(&ahp9287->ah_ini_rxgain, ar9287Modes_rx_gain_9287_1_1, 6);
313
314	/* setup txgain table */
315	HAL_INI_INIT(&ahp9287->ah_ini_txgain, ar9287Modes_tx_gain_9287_1_1, 6);
316
317	/*
318	 * Got everything we need now to setup the capabilities.
319	 */
320	if (!ar9287FillCapabilityInfo(ah)) {
321		ecode = HAL_EEREAD;
322		goto bad;
323	}
324
325	ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
326	if (ecode != HAL_OK) {
327		HALDEBUG(ah, HAL_DEBUG_ANY,
328		    "%s: error getting mac address from EEPROM\n", __func__);
329		goto bad;
330        }
331	/* XXX How about the serial number ? */
332	/* Read Reg Domain */
333	AH_PRIVATE(ah)->ah_currentRD =
334	    ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
335	AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT;
336
337	/*
338	 * ah_miscMode is populated by ar5416FillCapabilityInfo()
339	 * starting from griffin. Set here to make sure that
340	 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
341	 * placed into hardware.
342	 */
343	if (ahp->ah_miscMode != 0)
344		OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
345
346	ar9287AniSetup(ah);			/* Anti Noise Immunity */
347
348	/* Setup noise floor min/max/nominal values */
349	AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
350	AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
351	AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
352	AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ;
353	AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ;
354	AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ;
355
356	ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
357
358	HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
359
360	return ah;
361bad:
362	if (ah != AH_NULL)
363		ah->ah_detach(ah);
364	if (status)
365		*status = ecode;
366	return AH_NULL;
367}
368
369static void
370ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
371{
372	if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
373		ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
374		OS_DELAY(1000);
375		OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
376		/* Yes, Kiwi uses the Kite PCIe PHY WA */
377		OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
378	}
379}
380
381static void
382ar9287DisablePCIE(struct ath_hal *ah)
383{
384	/* XXX TODO */
385}
386
387static void
388ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
389{
390	u_int modesIndex, freqIndex;
391	int regWrites = 0;
392
393	/* Setup the indices for the next set of register array writes */
394	/* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
395	if (IEEE80211_IS_CHAN_2GHZ(chan)) {
396		freqIndex = 2;
397		if (IEEE80211_IS_CHAN_HT40(chan))
398			modesIndex = 3;
399		else if (IEEE80211_IS_CHAN_108G(chan))
400			modesIndex = 5;
401		else
402			modesIndex = 4;
403	} else {
404		freqIndex = 1;
405		if (IEEE80211_IS_CHAN_HT40(chan) ||
406		    IEEE80211_IS_CHAN_TURBO(chan))
407			modesIndex = 2;
408		else
409			modesIndex = 1;
410	}
411
412	/* Set correct Baseband to analog shift setting to access analog chips. */
413	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
414	OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
415
416	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites);
417	regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites);
418	regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites);
419	regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites);
420}
421
422/*
423 * Fill all software cached or static hardware state information.
424 * Return failure if capabilities are to come from EEPROM and
425 * cannot be read.
426 */
427static HAL_BOOL
428ar9287FillCapabilityInfo(struct ath_hal *ah)
429{
430	HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
431
432	if (!ar5416FillCapabilityInfo(ah))
433		return AH_FALSE;
434	pCap->halNumGpioPins = 10;
435	pCap->halWowSupport = AH_TRUE;
436	pCap->halWowMatchPatternExact = AH_TRUE;
437#if 0
438	pCap->halWowMatchPatternDword = AH_TRUE;
439#endif
440
441	pCap->halCSTSupport = AH_TRUE;
442	pCap->halRifsRxSupport = AH_TRUE;
443	pCap->halRifsTxSupport = AH_TRUE;
444	pCap->halRtsAggrLimit = 64*1024;	/* 802.11n max */
445	pCap->halExtChanDfsSupport = AH_TRUE;
446	pCap->halUseCombinedRadarRssi = AH_TRUE;
447#if 0
448	/* XXX bluetooth */
449	pCap->halBtCoexSupport = AH_TRUE;
450#endif
451	pCap->halAutoSleepSupport = AH_FALSE;	/* XXX? */
452	pCap->hal4kbSplitTransSupport = AH_FALSE;
453	/* Disable this so Block-ACK works correctly */
454	pCap->halHasRxSelfLinkedTail = AH_FALSE;
455	pCap->halPSPollBroken = AH_FALSE;
456	pCap->halSpectralScanSupport = AH_TRUE;
457
458	/* Hardware supports (at least) single-stream STBC TX/RX */
459	pCap->halRxStbcSupport = 1;
460	pCap->halTxStbcSupport = 1;
461
462	/* Hardware supports short-GI w/ 20MHz */
463	pCap->halHTSGI20Support = 1;
464
465	pCap->halEnhancedDfsSupport = AH_TRUE;
466
467	return AH_TRUE;
468}
469
470/*
471 * This has been disabled - having the HAL flip chainmasks on/off
472 * when attempting to implement 11n disrupts things. For now, just
473 * leave this flipped off and worry about implementing TX diversity
474 * for legacy and MCS0-15 when 11n is fully functioning.
475 */
476HAL_BOOL
477ar9287SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
478{
479	return AH_TRUE;
480}
481
482static const char*
483ar9287Probe(uint16_t vendorid, uint16_t devid)
484{
485	if (vendorid == ATHEROS_VENDOR_ID) {
486		if (devid == AR9287_DEVID_PCI)
487			return "Atheros 9227";
488		if (devid == AR9287_DEVID_PCIE)
489			return "Atheros 9287";
490	}
491	return AH_NULL;
492}
493AH_CHIP(AR9287, ar9287Probe, ar9287Attach);
494