ar9285phy.h revision 219481
12786Ssos/* 22786Ssos * Copyright (c) 2008-2010 Atheros Communications Inc. 32786Ssos * Copyright (c) 2010-2011 Adrian Chadd, Xenion Pty Ltd. 42786Ssos * 52786Ssos * Redistribution and use in source and binary forms, with or without 632822Syokota * modification, are permitted provided that the following conditions 72786Ssos * are met: 82786Ssos * 1. Redistributions of source code must retain the above copyright 92786Ssos * notice, this list of conditions and the following disclaimer. 102786Ssos * 2. Redistributions in binary form must reproduce the above copyright 112786Ssos * notice, this list of conditions and the following disclaimer in the 122786Ssos * documentation and/or other materials provided with the distribution. 132786Ssos * 142786Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 152786Ssos * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 162786Ssos * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1738140Syokota * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 182786Ssos * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 197420Ssos * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 202786Ssos * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 212786Ssos * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 222786Ssos * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 232786Ssos * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 242786Ssos * SUCH DAMAGE. 252786Ssos * 262786Ssos * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9285phy.h 219481 2011-03-11 11:58:54Z adrian $ 272786Ssos */ 282786Ssos#ifndef __ATH_AR9285PHY_H__ 292786Ssos#define __ATH_AR9285PHY_H__ 302786Ssos 312786Ssos#define AR9285_AN_RF2G1 0x7820 322786Ssos#define AR9285_AN_RF2G1_ENPACAL 0x00000800 332786Ssos#define AR9285_AN_RF2G1_ENPACAL_S 11 342786Ssos#define AR9285_AN_RF2G1_PDPADRV1 0x02000000 352786Ssos#define AR9285_AN_RF2G1_PDPADRV1_S 25 362786Ssos#define AR9285_AN_RF2G1_PDPADRV2 0x01000000 372786Ssos#define AR9285_AN_RF2G1_PDPADRV2_S 24 382786Ssos#define AR9285_AN_RF2G1_PDPAOUT 0x00800000 392786Ssos#define AR9285_AN_RF2G1_PDPAOUT_S 23 402786Ssos 412786Ssos#define AR9285_AN_RF2G2 0x7824 422786Ssos#define AR9285_AN_RF2G2_OFFCAL 0x00001000 432786Ssos#define AR9285_AN_RF2G2_OFFCAL_S 12 442786Ssos 452786Ssos#define AR9285_AN_RF2G3 0x7828 462786Ssos#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 472786Ssos#define AR9285_AN_RF2G3_PDVCCOMP_S 25 482786Ssos#define AR9285_AN_RF2G3_OB_0 0x00E00000 492786Ssos#define AR9285_AN_RF2G3_OB_0_S 21 502786Ssos#define AR9285_AN_RF2G3_OB_1 0x001C0000 512786Ssos#define AR9285_AN_RF2G3_OB_1_S 18 522786Ssos#define AR9285_AN_RF2G3_OB_2 0x00038000 532786Ssos#define AR9285_AN_RF2G3_OB_2_S 15 542786Ssos#define AR9285_AN_RF2G3_OB_3 0x00007000 552786Ssos#define AR9285_AN_RF2G3_OB_3_S 12 562786Ssos#define AR9285_AN_RF2G3_OB_4 0x00000E00 572786Ssos#define AR9285_AN_RF2G3_OB_4_S 9 582786Ssos 592786Ssos#define AR9285_AN_RF2G3_DB1_0 0x000001C0 602786Ssos#define AR9285_AN_RF2G3_DB1_0_S 6 612786Ssos#define AR9285_AN_RF2G3_DB1_1 0x00000038 6232822Syokota#define AR9285_AN_RF2G3_DB1_1_S 3 632786Ssos#define AR9285_AN_RF2G3_DB1_2 0x00000007 642786Ssos#define AR9285_AN_RF2G3_DB1_2_S 0 652786Ssos 662786Ssos#define AR9285_AN_RF2G4 0x782C 672786Ssos#define AR9285_AN_RF2G4_DB1_3 0xE0000000 682786Ssos#define AR9285_AN_RF2G4_DB1_3_S 29 692786Ssos#define AR9285_AN_RF2G4_DB1_4 0x1C000000 702786Ssos#define AR9285_AN_RF2G4_DB1_4_S 26 712786Ssos 722786Ssos#define AR9285_AN_RF2G4_DB2_0 0x03800000 732786Ssos#define AR9285_AN_RF2G4_DB2_0_S 23 742786Ssos#define AR9285_AN_RF2G4_DB2_1 0x00700000 752786Ssos#define AR9285_AN_RF2G4_DB2_1_S 20 762786Ssos#define AR9285_AN_RF2G4_DB2_2 0x000E0000 772786Ssos#define AR9285_AN_RF2G4_DB2_2_S 17 782786Ssos#define AR9285_AN_RF2G4_DB2_3 0x0001C000 7938140Syokota#define AR9285_AN_RF2G4_DB2_3_S 14 802786Ssos#define AR9285_AN_RF2G4_DB2_4 0x00003800 815994Ssos#define AR9285_AN_RF2G4_DB2_4_S 11 822786Ssos 832786Ssos#define AR9285_RF2G5 0x7830 842786Ssos#define AR9285_RF2G5_IC50TX 0xfffff8ff 852786Ssos#define AR9285_RF2G5_IC50TX_SET 0x00000400 862786Ssos#define AR9285_RF2G5_IC50TX_XE_SET 0x00000500 872786Ssos#define AR9285_RF2G5_IC50TX_CLEAR 0x00000700 886045Ssos#define AR9285_RF2G5_IC50TX_CLEAR_S 8 8938140Syokota 902786Ssos#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 912786Ssos#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 922786Ssos#define AR_PHY_TX_GAIN_CLC 0x0000001E 932786Ssos#define AR_PHY_TX_GAIN_CLC_S 1 9418194Ssos#define AR_PHY_TX_GAIN 0x0007F000 952786Ssos#define AR_PHY_TX_GAIN_S 12 962786Ssos 972786Ssos#define AR_PHY_CLC_TBL1 0xa35c 982786Ssos#define AR_PHY_CLC_I0 0x07ff0000 992786Ssos#define AR_PHY_CLC_I0_S 16 1002786Ssos#define AR_PHY_CLC_Q0 0x0000ffd0 1012786Ssos#define AR_PHY_CLC_Q0_S 5 1022786Ssos 1032786Ssos#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 1042786Ssos#define AR_PHY_9285_FAST_DIV_BIAS 0x00007E00 1052786Ssos#define AR_PHY_9285_FAST_DIV_BIAS_S 9 1062786Ssos#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000 1072786Ssos#define AR_PHY_9285_ANT_DIV_CTL 0x01000000 1086851Ssos#define AR_PHY_9285_ANT_DIV_CTL_S 24 1092786Ssos#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000 1106851Ssos#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25 1116851Ssos#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000 1126851Ssos#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27 113#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000 114#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29 115#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000 116#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30 117#define AR_PHY_9285_ANT_DIV_LNA1 2 118#define AR_PHY_9285_ANT_DIV_LNA2 1 119#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3 120#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0 121#define AR_PHY_9285_ANT_DIV_GAINTB_0 0 122#define AR_PHY_9285_ANT_DIV_GAINTB_1 1 123 124/* for AR_PHY_CCK_DETECT */ 125#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 126#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 127#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 128#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 129 130#endif 131