ar9130_phy.c revision 242412
1/* 2 * Copyright (c) 2011 Adrian Chadd, Xenion Pty Ltd 3 * Copyright (c) 2010 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9001/ar9130_phy.c 242412 2012-10-31 21:14:25Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ar5416/ar5416.h" 26#include "ar5416/ar5416reg.h" 27#include "ar5416/ar5416phy.h" 28#include "ar9001/ar9130_phy.h" 29 30void 31ar9130InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 32{ 33 34 uint32_t pll; 35 36 /* 37 * XXX TODO: support half/quarter rates 38 */ 39 if (chan && IEEE80211_IS_CHAN_5GHZ(chan)) 40 pll = 0x1450; 41 else 42 pll = 0x1458; 43 44 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 45 OS_DELAY(RTC_PLL_SETTLE_DELAY); 46 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 47} 48