ar5416reg.h revision 219217
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17188968Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h 219217 2011-03-03 08:30:28Z adrian $ 18185377Ssam */ 19185377Ssam#ifndef _DEV_ATH_AR5416REG_H 20185377Ssam#define _DEV_ATH_AR5416REG_H 21185377Ssam 22188968Ssam#include <dev/ath/ath_hal/ar5212/ar5212reg.h> 23185377Ssam 24185377Ssam/* 25185377Ssam * Register added starting with the AR5416 26185377Ssam */ 27185377Ssam#define AR_MIRT 0x0020 /* interrupt rate threshold */ 28185377Ssam#define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29185377Ssam#define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 30185377Ssam#define AR_GTXTO 0x0064 /* global transmit timeout */ 31185377Ssam#define AR_GTTM 0x0068 /* global transmit timeout mode */ 32185377Ssam#define AR_CST 0x006C /* carrier sense timeout */ 33185377Ssam#define AR_MAC_LED 0x1f04 /* LED control */ 34188979Ssam#define AR_WA 0x4004 /* PCIE work-arounds */ 35188979Ssam#define AR_PCIE_PM_CTRL 0x4014 36185377Ssam#define AR_AHB_MODE 0x4024 /* AHB mode for dma */ 37185377Ssam#define AR_INTR_SYNC_CAUSE_CLR 0x4028 /* clear interrupt */ 38185377Ssam#define AR_INTR_SYNC_CAUSE 0x4028 /* check pending interrupts */ 39185377Ssam#define AR_INTR_SYNC_ENABLE 0x402c /* enable interrupts */ 40185377Ssam#define AR_INTR_ASYNC_MASK 0x4030 /* asynchronous interrupt mask */ 41185377Ssam#define AR_INTR_SYNC_MASK 0x4034 /* synchronous interrupt mask */ 42185377Ssam#define AR_INTR_ASYNC_CAUSE 0x4038 /* check pending interrupts */ 43185377Ssam#define AR_INTR_ASYNC_ENABLE 0x403c /* enable interrupts */ 44185377Ssam#define AR5416_PCIE_SERDES 0x4040 45185377Ssam#define AR5416_PCIE_SERDES2 0x4044 46188976Ssam#define AR_GPIO_IN_OUT 0x4048 /* GPIO input/output register */ 47188976Ssam#define AR_GPIO_OE_OUT 0x404c /* GPIO output enable register */ 48188976Ssam#define AR_GPIO_INTR_POL 0x4050 /* GPIO interrupt polarity */ 49188976Ssam#define AR_GPIO_INPUT_EN_VAL 0x4054 /* GPIO input enable and value */ 50188976Ssam#define AR_GPIO_INPUT_MUX1 0x4058 51188976Ssam#define AR_GPIO_INPUT_MUX2 0x405c 52188976Ssam#define AR_GPIO_OUTPUT_MUX1 0x4060 53188976Ssam#define AR_GPIO_OUTPUT_MUX2 0x4064 54188976Ssam#define AR_GPIO_OUTPUT_MUX3 0x4068 55185377Ssam#define AR_EEPROM_STATUS_DATA 0x407c 56185377Ssam#define AR_OBS 0x4080 57185377Ssam#define AR_RTC_RC 0x7000 /* reset control */ 58185377Ssam#define AR_RTC_PLL_CONTROL 0x7014 59185377Ssam#define AR_RTC_RESET 0x7040 /* RTC reset register */ 60185377Ssam#define AR_RTC_STATUS 0x7044 /* system sleep status */ 61185377Ssam#define AR_RTC_SLEEP_CLK 0x7048 62185377Ssam#define AR_RTC_FORCE_WAKE 0x704c /* control MAC force wake */ 63185377Ssam#define AR_RTC_INTR_CAUSE 0x7050 /* RTC interrupt cause/clear */ 64185377Ssam#define AR_RTC_INTR_ENABLE 0x7054 /* RTC interrupt enable */ 65185377Ssam#define AR_RTC_INTR_MASK 0x7058 /* RTC interrupt mask */ 66185377Ssam/* AR9280: rf long shift registers */ 67185377Ssam#define AR_AN_RF2G1_CH0 0x7810 68185377Ssam#define AR_AN_RF5G1_CH0 0x7818 69185377Ssam#define AR_AN_RF2G1_CH1 0x7834 70185377Ssam#define AR_AN_RF5G1_CH1 0x783C 71185377Ssam#define AR_AN_TOP2 0x7894 72185377Ssam#define AR_AN_SYNTH9 0x7868 73203159Srpaulo#define AR9285_AN_RF2G1 0x7820 74203159Srpaulo#define AR9285_AN_RF2G2 0x7824 75203159Srpaulo#define AR9285_AN_RF2G3 0x7828 76203159Srpaulo#define AR9285_AN_RF2G4 0x782C 77203159Srpaulo#define AR9285_AN_RF2G6 0x7834 78203159Srpaulo#define AR9285_AN_RF2G7 0x7838 79203159Srpaulo#define AR9285_AN_RF2G8 0x783C 80203159Srpaulo#define AR9285_AN_RF2G9 0x7840 81203159Srpaulo#define AR9285_AN_RXTXBB1 0x7854 82203159Srpaulo#define AR9285_AN_TOP2 0x7868 83185377Ssam#define AR9285_AN_TOP3 0x786c 84203159Srpaulo#define AR9285_AN_TOP4 0x7870 85203159Srpaulo#define AR9285_AN_TOP4_DEFAULT 0x10142c00 86203159Srpaulo 87185377Ssam#define AR_RESET_TSF 0x8020 88185377Ssam#define AR_RXFIFO_CFG 0x8114 89185377Ssam#define AR_PHY_ERR_1 0x812c 90185377Ssam#define AR_PHY_ERR_MASK_1 0x8130 /* mask for AR_PHY_ERR_1 */ 91185377Ssam#define AR_PHY_ERR_2 0x8134 92185377Ssam#define AR_PHY_ERR_MASK_2 0x8138 /* mask for AR_PHY_ERR_2 */ 93185377Ssam#define AR_TSFOOR_THRESHOLD 0x813c 94185377Ssam#define AR_PHY_ERR_3 0x8168 95185377Ssam#define AR_PHY_ERR_MASK_3 0x816c /* mask for AR_PHY_ERR_3 */ 96185377Ssam#define AR_TXOP_X 0x81ec /* txop for legacy non-qos */ 97185377Ssam#define AR_TXOP_0_3 0x81f0 /* txop for various tid's */ 98185377Ssam#define AR_TXOP_4_7 0x81f4 99185377Ssam#define AR_TXOP_8_11 0x81f8 100185377Ssam#define AR_TXOP_12_15 0x81fc 101185377Ssam/* generic timers based on tsf - all uS */ 102185377Ssam#define AR_NEXT_TBTT 0x8200 103185377Ssam#define AR_NEXT_DBA 0x8204 104185377Ssam#define AR_NEXT_SWBA 0x8208 105185377Ssam#define AR_NEXT_CFP 0x8208 106185377Ssam#define AR_NEXT_HCF 0x820C 107185377Ssam#define AR_NEXT_TIM 0x8210 108185377Ssam#define AR_NEXT_DTIM 0x8214 109185377Ssam#define AR_NEXT_QUIET 0x8218 110185377Ssam#define AR_NEXT_NDP 0x821C 111185377Ssam#define AR5416_BEACON_PERIOD 0x8220 112185377Ssam#define AR_DBA_PERIOD 0x8224 113185377Ssam#define AR_SWBA_PERIOD 0x8228 114185377Ssam#define AR_HCF_PERIOD 0x822C 115185377Ssam#define AR_TIM_PERIOD 0x8230 116185377Ssam#define AR_DTIM_PERIOD 0x8234 117185377Ssam#define AR_QUIET_PERIOD 0x8238 118185377Ssam#define AR_NDP_PERIOD 0x823C 119185377Ssam#define AR_TIMER_MODE 0x8240 120185377Ssam#define AR_SLP32_MODE 0x8244 121185377Ssam#define AR_SLP32_WAKE 0x8248 122185377Ssam#define AR_SLP32_INC 0x824c 123185377Ssam#define AR_SLP_CNT 0x8250 /* 32kHz cycles with mac asleep */ 124185377Ssam#define AR_SLP_CYCLE_CNT 0x8254 /* absolute number of 32kHz cycles */ 125185377Ssam#define AR_SLP_MIB_CTRL 0x8258 126185377Ssam#define AR_2040_MODE 0x8318 127185377Ssam#define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ 128185377Ssam#define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ 129185377Ssam#define AR_PCU_TXBUF_CTRL 0x8340 130208711Srpaulo#define AR_PCU_MISC_MODE2 0x8344 131185377Ssam 132185377Ssam/* DMA & PCI Registers in PCI space (usable during sleep)*/ 133185377Ssam#define AR_RC_AHB 0x00000001 /* AHB reset */ 134185377Ssam#define AR_RC_APB 0x00000002 /* APB reset */ 135185377Ssam#define AR_RC_HOSTIF 0x00000100 /* host interface reset */ 136185377Ssam 137185377Ssam#define AR_MIRT_VAL 0x0000ffff /* in uS */ 138185377Ssam#define AR_MIRT_VAL_S 16 139185377Ssam 140185377Ssam#define AR_TIMT_LAST 0x0000ffff /* Last packet threshold */ 141185377Ssam#define AR_TIMT_LAST_S 0 142185377Ssam#define AR_TIMT_FIRST 0xffff0000 /* First packet threshold */ 143185377Ssam#define AR_TIMT_FIRST_S 16 144185377Ssam 145185377Ssam#define AR_RIMT_LAST 0x0000ffff /* Last packet threshold */ 146185377Ssam#define AR_RIMT_LAST_S 0 147185377Ssam#define AR_RIMT_FIRST 0xffff0000 /* First packet threshold */ 148185377Ssam#define AR_RIMT_FIRST_S 16 149185377Ssam 150185377Ssam#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 151185377Ssam#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 152185377Ssam#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 153185377Ssam 154185377Ssam#define AR_GTTM_USEC 0x00000001 // usec strobe 155185377Ssam#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle 156185377Ssam#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low 157185377Ssam#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe 158185377Ssam 159185377Ssam#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) 160185377Ssam#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) 161185377Ssam#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit 162185377Ssam 163185377Ssam/* MAC tx DMA size config */ 164185377Ssam#define AR_TXCFG_DMASZ_MASK 0x00000003 165185377Ssam#define AR_TXCFG_DMASZ_4B 0 166185377Ssam#define AR_TXCFG_DMASZ_8B 1 167185377Ssam#define AR_TXCFG_DMASZ_16B 2 168185377Ssam#define AR_TXCFG_DMASZ_32B 3 169185377Ssam#define AR_TXCFG_DMASZ_64B 4 170185377Ssam#define AR_TXCFG_DMASZ_128B 5 171185377Ssam#define AR_TXCFG_DMASZ_256B 6 172185377Ssam#define AR_TXCFG_DMASZ_512B 7 173185377Ssam#define AR_TXCFG_ATIM_TXPOLICY 0x00000800 174185377Ssam 175185377Ssam/* MAC rx DMA size config */ 176185377Ssam#define AR_RXCFG_DMASZ_MASK 0x00000007 177185377Ssam#define AR_RXCFG_DMASZ_4B 0 178185377Ssam#define AR_RXCFG_DMASZ_8B 1 179185377Ssam#define AR_RXCFG_DMASZ_16B 2 180185377Ssam#define AR_RXCFG_DMASZ_32B 3 181185377Ssam#define AR_RXCFG_DMASZ_64B 4 182185377Ssam#define AR_RXCFG_DMASZ_128B 5 183185377Ssam#define AR_RXCFG_DMASZ_256B 6 184185377Ssam#define AR_RXCFG_DMASZ_512B 7 185185377Ssam 186185377Ssam/* MAC Led registers */ 187185377Ssam#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ 188185377Ssam#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ 189185377Ssam#define AR_MAC_LED_MODE 0x00000380 /* LED mode select */ 190185377Ssam#define AR_MAC_LED_MODE_S 7 191185377Ssam#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ 192185377Ssam#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 193185377Ssam#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ 194185377Ssam#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ 195185377Ssam#define AR_MAC_LED_MODE_POWON 5 /* Power LED on (s/w control) */ 196185377Ssam#define AR_MAC_LED_MODE_NETON 6 /* Network LED on (s/w control) */ 197185377Ssam#define AR_MAC_LED_ASSOC 0x00000c00 198185377Ssam#define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ 199185377Ssam#define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ 200185377Ssam#define AR_MAC_LED_ASSOC_PEND 0x00000800 /* STA is trying to associate */ 201185377Ssam#define AR_MAC_LED_ASSOC_S 10 202185377Ssam 203188979Ssam#define AR_WA_UNTIE_RESET_EN 0x00008000 /* ena PCI reset to POR */ 204188979Ssam#define AR_WA_RESET_EN 0x00040000 /* ena AR_WA_UNTIE_RESET_EN */ 205188979Ssam#define AR_WA_ANALOG_SHIFT 0x00100000 206188979Ssam#define AR_WA_POR_SHORT 0x00200000 /* PCIE phy reset control */ 207188979Ssam 208188979Ssam#define AR_WA_DEFAULT 0x0000073f 209188979Ssam#define AR9280_WA_DEFAULT 0x0040073f 210188979Ssam#define AR9285_WA_DEFAULT 0x004a05cb 211188979Ssam 212188979Ssam#define AR_PCIE_PM_CTRL_ENA 0x00080000 213188979Ssam 214185377Ssam#define AR_AHB_EXACT_WR_EN 0x00000000 /* write exact bytes */ 215185377Ssam#define AR_AHB_BUF_WR_EN 0x00000001 /* buffer write upto cacheline*/ 216185377Ssam#define AR_AHB_EXACT_RD_EN 0x00000000 /* read exact bytes */ 217185377Ssam#define AR_AHB_CACHELINE_RD_EN 0x00000002 /* read upto end of cacheline */ 218185377Ssam#define AR_AHB_PREFETCH_RD_EN 0x00000004 /* prefetch upto page boundary*/ 219185377Ssam#define AR_AHB_PAGE_SIZE_1K 0x00000000 /* set page-size as 1k */ 220185377Ssam#define AR_AHB_PAGE_SIZE_2K 0x00000008 /* set page-size as 2k */ 221185377Ssam#define AR_AHB_PAGE_SIZE_4K 0x00000010 /* set page-size as 4k */ 222185377Ssam 223185377Ssam/* MAC PCU Registers */ 224185377Ssam#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 /* Don't replace seq num */ 225185377Ssam 226185377Ssam/* Extended PCU DIAG_SW control fields */ 227185377Ssam#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 /* dual chain channel info */ 228185377Ssam#define AR_DIAG_RX_ABORT 0x02000000 /* abort rx */ 229185377Ssam#define AR_DIAG_SATURATE_CCNT 0x04000000 /* sat. cycle cnts (no shift) */ 230185377Ssam#define AR_DIAG_OBS_PT_SEL2 0x08000000 /* observation point sel */ 231185377Ssam#define AR_DIAG_RXCLEAR_CTL_LOW 0x10000000 /* force rx_clear(ctl) low/busy */ 232185377Ssam#define AR_DIAG_RXCLEAR_EXT_LOW 0x20000000 /* force rx_clear(ext) low/busy */ 233185377Ssam 234185377Ssam#define AR_TXOP_X_VAL 0x000000FF 235185377Ssam 236185377Ssam#define AR_RESET_TSF_ONCE 0x01000000 /* reset tsf once; self-clears*/ 237185377Ssam 238185377Ssam/* Interrupts */ 239185377Ssam#define AR_ISR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 240185377Ssam#define AR_ISR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 241185377Ssam#define AR_ISR_TXINTM 0x40000000 /* Tx int after mitigation */ 242185377Ssam#define AR_ISR_RXINTM 0x80000000 /* Rx int after mitigation */ 243185377Ssam 244185377Ssam#define AR_ISR_S2_CST 0x00400000 /* Carrier sense timeout */ 245185377Ssam#define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ 246185377Ssam#define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ 247185377Ssam 248208711Srpaulo#define AR_ISR_S5 0x0098 249208711Srpaulo#define AR_ISR_S5_S 0x00d8 250208711Srpaulo#define AR_ISR_S5_TIM_TIMER 0x00000010 251208711Srpaulo 252185377Ssam#define AR_INTR_SPURIOUS 0xffffffff 253185377Ssam#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ 254185377Ssam#define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ 255185377Ssam#define AR_INTR_EEP_PROT_ACCESS 0x00000004 /* eeprom protected access */ 256185377Ssam#define AR_INTR_MAC_AWAKE 0x00020000 /* mac is awake */ 257185377Ssam#define AR_INTR_MAC_ASLEEP 0x00040000 /* mac is asleep */ 258185377Ssam 259185377Ssam/* Interrupt Mask Registers */ 260185377Ssam#define AR_IMR_TXMINTR 0x00080000 /* Maximum interrupt tx rate */ 261185377Ssam#define AR_IMR_RXMINTR 0x01000000 /* Maximum interrupt rx rate */ 262185377Ssam#define AR_IMR_TXINTM 0x40000000 /* Tx int after mitigation */ 263185377Ssam#define AR_IMR_RXINTM 0x80000000 /* Rx int after mitigation */ 264185377Ssam 265185377Ssam#define AR_IMR_S2_CST 0x00400000 /* Carrier sense timeout */ 266185377Ssam#define AR_IMR_S2_GTT 0x00800000 /* Global transmit timeout */ 267185377Ssam 268185377Ssam/* synchronous interrupt signals */ 269185377Ssam#define AR_INTR_SYNC_RTC_IRQ 0x00000001 270185377Ssam#define AR_INTR_SYNC_MAC_IRQ 0x00000002 271185377Ssam#define AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS 0x00000004 272185377Ssam#define AR_INTR_SYNC_APB_TIMEOUT 0x00000008 273185377Ssam#define AR_INTR_SYNC_PCI_MODE_CONFLICT 0x00000010 274185377Ssam#define AR_INTR_SYNC_HOST1_FATAL 0x00000020 275185377Ssam#define AR_INTR_SYNC_HOST1_PERR 0x00000040 276185377Ssam#define AR_INTR_SYNC_TRCV_FIFO_PERR 0x00000080 277185377Ssam#define AR_INTR_SYNC_RADM_CPL_EP 0x00000100 278185377Ssam#define AR_INTR_SYNC_RADM_CPL_DLLP_ABORT 0x00000200 279185377Ssam#define AR_INTR_SYNC_RADM_CPL_TLP_ABORT 0x00000400 280185377Ssam#define AR_INTR_SYNC_RADM_CPL_ECRC_ERR 0x00000800 281185377Ssam#define AR_INTR_SYNC_RADM_CPL_TIMEOUT 0x00001000 282185377Ssam#define AR_INTR_SYNC_LOCAL_TIMEOUT 0x00002000 283185377Ssam#define AR_INTR_SYNC_PM_ACCESS 0x00004000 284185377Ssam#define AR_INTR_SYNC_MAC_AWAKE 0x00008000 285185377Ssam#define AR_INTR_SYNC_MAC_ASLEEP 0x00010000 286185377Ssam#define AR_INTR_SYNC_MAC_SLEEP_ACCESS 0x00020000 287185377Ssam#define AR_INTR_SYNC_ALL 0x0003FFFF 288185377Ssam 289185377Ssam/* default synchronous interrupt signals enabled */ 290185377Ssam#define AR_INTR_SYNC_DEFAULT \ 291185377Ssam (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR | \ 292185377Ssam AR_INTR_SYNC_RADM_CPL_EP | AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | \ 293185377Ssam AR_INTR_SYNC_RADM_CPL_TLP_ABORT | AR_INTR_SYNC_RADM_CPL_ECRC_ERR | \ 294185377Ssam AR_INTR_SYNC_RADM_CPL_TIMEOUT | AR_INTR_SYNC_LOCAL_TIMEOUT | \ 295185377Ssam AR_INTR_SYNC_MAC_SLEEP_ACCESS) 296185377Ssam 297188976Ssam#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 298188976Ssam#define AR_INTR_SYNC_MASK_GPIO_S 18 299188976Ssam 300188976Ssam#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 301188976Ssam#define AR_INTR_SYNC_ENABLE_GPIO_S 18 302188976Ssam 303188976Ssam#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 /* async int mask */ 304188976Ssam#define AR_INTR_ASYNC_MASK_GPIO_S 18 305188976Ssam 306188976Ssam#define AR_INTR_ASYNC_CAUSE_GPIO 0xFFFC0000 /* GPIO interrupts */ 307188976Ssam#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_CAUSE_GPIO) 308188976Ssam 309188976Ssam#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 /* enable interrupts */ 310188976Ssam#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 311188976Ssam 312185377Ssam/* RTC registers */ 313185377Ssam#define AR_RTC_RC_M 0x00000003 314185377Ssam#define AR_RTC_RC_MAC_WARM 0x00000001 315185377Ssam#define AR_RTC_RC_MAC_COLD 0x00000002 316185377Ssam#define AR_RTC_PLL_DIV 0x0000001f 317185377Ssam#define AR_RTC_PLL_DIV_S 0 318185377Ssam#define AR_RTC_PLL_DIV2 0x00000020 319185377Ssam#define AR_RTC_PLL_REFDIV_5 0x000000c0 320185377Ssam 321185377Ssam#define AR_RTC_SOWL_PLL_DIV 0x000003ff 322185377Ssam#define AR_RTC_SOWL_PLL_DIV_S 0 323185377Ssam#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 324185377Ssam#define AR_RTC_SOWL_PLL_REFDIV_S 10 325185377Ssam#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 326185377Ssam#define AR_RTC_SOWL_PLL_CLKSEL_S 14 327185377Ssam 328185377Ssam#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ 329185377Ssam 330185377Ssam#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status */ 331185377Ssam#define AR_RTC_STATUS_M 0x0000003f /* RTC Status */ 332185377Ssam#define AR_RTC_STATUS_SHUTDOWN 0x00000001 333185377Ssam#define AR_RTC_STATUS_ON 0x00000002 334185377Ssam#define AR_RTC_STATUS_SLEEP 0x00000004 335185377Ssam#define AR_RTC_STATUS_WAKEUP 0x00000008 336185377Ssam#define AR_RTC_STATUS_COLDRESET 0x00000010 /* Not currently used */ 337185377Ssam#define AR_RTC_STATUS_PLLCHANGE 0x00000020 /* Not currently used */ 338185377Ssam 339185377Ssam#define AR_RTC_SLEEP_DERIVED_CLK 0x2 340185377Ssam 341185377Ssam#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ 342185377Ssam#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ 343185377Ssam 344185377Ssam#define AR_RTC_PLL_CLKSEL 0x00000300 345185377Ssam#define AR_RTC_PLL_CLKSEL_S 8 346185377Ssam 347185377Ssam/* AR9280: rf long shift registers */ 348185377Ssam#define AR_AN_RF2G1_CH0_OB 0x03800000 349185377Ssam#define AR_AN_RF2G1_CH0_OB_S 23 350185377Ssam#define AR_AN_RF2G1_CH0_DB 0x1C000000 351185377Ssam#define AR_AN_RF2G1_CH0_DB_S 26 352185377Ssam 353185377Ssam#define AR_AN_RF5G1_CH0_OB5 0x00070000 354185377Ssam#define AR_AN_RF5G1_CH0_OB5_S 16 355185377Ssam#define AR_AN_RF5G1_CH0_DB5 0x00380000 356185377Ssam#define AR_AN_RF5G1_CH0_DB5_S 19 357185377Ssam 358185377Ssam#define AR_AN_RF2G1_CH1_OB 0x03800000 359185377Ssam#define AR_AN_RF2G1_CH1_OB_S 23 360185377Ssam#define AR_AN_RF2G1_CH1_DB 0x1C000000 361185377Ssam#define AR_AN_RF2G1_CH1_DB_S 26 362185377Ssam 363185377Ssam#define AR_AN_RF5G1_CH1_OB5 0x00070000 364185377Ssam#define AR_AN_RF5G1_CH1_OB5_S 16 365185377Ssam#define AR_AN_RF5G1_CH1_DB5 0x00380000 366185377Ssam#define AR_AN_RF5G1_CH1_DB5_S 19 367185377Ssam 368218420Sadrian#define AR_AN_TOP1 0x7890 369218420Sadrian#define AR_AN_TOP1_DACIPMODE 0x00040000 370218420Sadrian#define AR_AN_TOP1_DACIPMODE_S 18 371218420Sadrian 372185377Ssam#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 373185377Ssam#define AR_AN_TOP2_XPABIAS_LVL_S 30 374185377Ssam#define AR_AN_TOP2_LOCALBIAS 0x00200000 375185377Ssam#define AR_AN_TOP2_LOCALBIAS_S 21 376185377Ssam#define AR_AN_TOP2_PWDCLKIND 0x00400000 377185377Ssam#define AR_AN_TOP2_PWDCLKIND_S 22 378185377Ssam 379185377Ssam#define AR_AN_SYNTH9_REFDIVA 0xf8000000 380185377Ssam#define AR_AN_SYNTH9_REFDIVA_S 27 381185377Ssam 382185377Ssam/* AR9285 Analog registers */ 383203159Srpaulo#define AR9285_AN_RF2G1_ENPACAL 0x00000800 384203159Srpaulo#define AR9285_AN_RF2G1_ENPACAL_S 11 385203159Srpaulo#define AR9285_AN_RF2G1_PDPADRV1 0x02000000 386203159Srpaulo#define AR9285_AN_RF2G1_PDPADRV1_S 25 387203159Srpaulo#define AR9285_AN_RF2G1_PDPADRV2 0x01000000 388203159Srpaulo#define AR9285_AN_RF2G1_PDPADRV2_S 24 389203159Srpaulo#define AR9285_AN_RF2G1_PDPAOUT 0x00800000 390203159Srpaulo#define AR9285_AN_RF2G1_PDPAOUT_S 23 391185377Ssam 392203159Srpaulo#define AR9285_AN_RF2G2_OFFCAL 0x00001000 393203159Srpaulo#define AR9285_AN_RF2G2_OFFCAL_S 12 394185377Ssam 395203159Srpaulo#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 396203159Srpaulo#define AR9285_AN_RF2G3_PDVCCOMP_S 25 397203159Srpaulo#define AR9285_AN_RF2G3_OB_0 0x00E00000 398203159Srpaulo#define AR9285_AN_RF2G3_OB_0_S 21 399203159Srpaulo#define AR9285_AN_RF2G3_OB_1 0x001C0000 400203159Srpaulo#define AR9285_AN_RF2G3_OB_1_S 18 401203159Srpaulo#define AR9285_AN_RF2G3_OB_2 0x00038000 402203159Srpaulo#define AR9285_AN_RF2G3_OB_2_S 15 403203159Srpaulo#define AR9285_AN_RF2G3_OB_3 0x00007000 404203159Srpaulo#define AR9285_AN_RF2G3_OB_3_S 12 405203159Srpaulo#define AR9285_AN_RF2G3_OB_4 0x00000E00 406203159Srpaulo#define AR9285_AN_RF2G3_OB_4_S 9 407185377Ssam 408203159Srpaulo#define AR9285_AN_RF2G3_DB1_0 0x000001C0 409203159Srpaulo#define AR9285_AN_RF2G3_DB1_0_S 6 410203159Srpaulo#define AR9285_AN_RF2G3_DB1_1 0x00000038 411203159Srpaulo#define AR9285_AN_RF2G3_DB1_1_S 3 412203159Srpaulo#define AR9285_AN_RF2G3_DB1_2 0x00000007 413203159Srpaulo#define AR9285_AN_RF2G3_DB1_2_S 0 414203159Srpaulo 415203159Srpaulo#define AR9285_AN_RF2G4_DB1_3 0xE0000000 416203159Srpaulo#define AR9285_AN_RF2G4_DB1_3_S 29 417203159Srpaulo#define AR9285_AN_RF2G4_DB1_4 0x1C000000 418203159Srpaulo#define AR9285_AN_RF2G4_DB1_4_S 26 419203159Srpaulo 420203159Srpaulo#define AR9285_AN_RF2G4_DB2_0 0x03800000 421203159Srpaulo#define AR9285_AN_RF2G4_DB2_0_S 23 422203159Srpaulo#define AR9285_AN_RF2G4_DB2_1 0x00700000 423203159Srpaulo#define AR9285_AN_RF2G4_DB2_1_S 20 424203159Srpaulo#define AR9285_AN_RF2G4_DB2_2 0x000E0000 425203159Srpaulo#define AR9285_AN_RF2G4_DB2_2_S 17 426203159Srpaulo#define AR9285_AN_RF2G4_DB2_3 0x0001C000 427203159Srpaulo#define AR9285_AN_RF2G4_DB2_3_S 14 428203159Srpaulo#define AR9285_AN_RF2G4_DB2_4 0x00003800 429203159Srpaulo#define AR9285_AN_RF2G4_DB2_4_S 11 430203159Srpaulo 431203159Srpaulo#define AR9285_AN_RF2G6_CCOMP 0x00007800 432203159Srpaulo#define AR9285_AN_RF2G6_CCOMP_S 11 433203159Srpaulo#define AR9285_AN_RF2G6_OFFS 0x03f00000 434203159Srpaulo#define AR9285_AN_RF2G6_OFFS_S 20 435203159Srpaulo 436203159Srpaulo#define AR9271_AN_RF2G6_OFFS 0x07f00000 437203159Srpaulo#define AR9271_AN_RF2G6_OFFS_S 20 438203159Srpaulo 439203159Srpaulo#define AR9285_AN_RF2G7_PWDDB 0x00000002 440203159Srpaulo#define AR9285_AN_RF2G7_PWDDB_S 1 441203159Srpaulo#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 442203159Srpaulo#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 443203159Srpaulo 444203159Srpaulo#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 445203159Srpaulo#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 446203159Srpaulo 447203159Srpaulo#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 448203159Srpaulo#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 449203159Srpaulo#define AR9285_AN_RXTXBB1_PDV2I 0x00000080 450203159Srpaulo#define AR9285_AN_RXTXBB1_PDV2I_S 7 451203159Srpaulo#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 452203159Srpaulo#define AR9285_AN_RXTXBB1_PDDACIF_S 8 453203159Srpaulo#define AR9285_AN_RXTXBB1_SPARE9 0x00000001 454203159Srpaulo#define AR9285_AN_RXTXBB1_SPARE9_S 0 455203159Srpaulo 456185377Ssam#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 457185377Ssam#define AR9285_AN_TOP3_XPABIAS_LVL_S 2 458203159Srpaulo#define AR9285_AN_TOP3_PWDDAC 0x00800000 459203159Srpaulo#define AR9285_AN_TOP3_PWDDAC_S 23 460185377Ssam 461185377Ssam/* Sleep control */ 462185377Ssam#define AR5416_SLEEP1_CAB_TIMEOUT 0xFFE00000 /* Cab timeout (TU) */ 463185377Ssam#define AR5416_SLEEP1_CAB_TIMEOUT_S 22 464185377Ssam 465185377Ssam#define AR5416_SLEEP2_BEACON_TIMEOUT 0xFFE00000 /* Beacon timeout (TU)*/ 466185377Ssam#define AR5416_SLEEP2_BEACON_TIMEOUT_S 22 467185377Ssam 468185377Ssam/* Sleep Registers */ 469185377Ssam#define AR_SLP32_HALFCLK_LATENCY 0x000FFFFF /* rising <-> falling edge */ 470185377Ssam#define AR_SLP32_ENA 0x00100000 471185377Ssam#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 /* tsf update in progress */ 472185377Ssam 473185377Ssam#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF /* time to wake crystal */ 474185377Ssam 475185377Ssam#define AR_SLP32_TST_INC 0x000FFFFF 476185377Ssam 477185377Ssam#define AR_SLP_MIB_CLEAR 0x00000001 /* clear pending */ 478185377Ssam#define AR_SLP_MIB_PENDING 0x00000002 /* clear counters */ 479185377Ssam 480185377Ssam#define AR_TIMER_MODE_TBTT 0x00000001 481185377Ssam#define AR_TIMER_MODE_DBA 0x00000002 482185377Ssam#define AR_TIMER_MODE_SWBA 0x00000004 483185377Ssam#define AR_TIMER_MODE_HCF 0x00000008 484185377Ssam#define AR_TIMER_MODE_TIM 0x00000010 485185377Ssam#define AR_TIMER_MODE_DTIM 0x00000020 486185377Ssam#define AR_TIMER_MODE_QUIET 0x00000040 487185377Ssam#define AR_TIMER_MODE_NDP 0x00000080 488185377Ssam#define AR_TIMER_MODE_OVERFLOW_INDEX 0x00000700 489185377Ssam#define AR_TIMER_MODE_OVERFLOW_INDEX_S 8 490185377Ssam#define AR_TIMER_MODE_THRESH 0xFFFFF000 491185377Ssam#define AR_TIMER_MODE_THRESH_S 12 492185377Ssam 493185377Ssam/* PCU Misc modes */ 494185377Ssam#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 /* force bssid to match */ 495185377Ssam#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 /* tx/rx mic keys together */ 496185377Ssam#define AR_PCU_TX_ADD_TSF 0x00000008 /* add tx_tsf + int_tsf */ 497185377Ssam#define AR_PCU_CCK_SIFS_MODE 0x00000010 /* assume 11b sifs */ 498185377Ssam#define AR_PCU_RX_ANT_UPDT 0x00000800 /* KC_RX_ANT_UPDATE */ 499185377Ssam#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 /* enforce txop / tbtt */ 500185377Ssam#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 /* count bmiss's when sleeping */ 501185377Ssam#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 /* use rx_clear to count sifs */ 502185377Ssam#define AR_PCU_FORCE_QUIET_COLL 0x00040000 /* kill xmit for channel change */ 503185377Ssam#define AR_PCU_TBTT_PROTECT 0x00200000 /* no xmit upto tbtt+20 uS */ 504185377Ssam#define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ 505185377Ssam#define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ 506185377Ssam 507208711Srpaulo#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 508219217Sadrian#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 509208711Srpaulo 510185377Ssam/* GPIO Interrupt */ 511185377Ssam#define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ 512185377Ssam#define AR_INTR_GPIO_S 20 513185377Ssam 514185377Ssam#define AR_GPIO_OUT_CTRL 0x000003FF /* 0 = out, 1 = in */ 515185377Ssam#define AR_GPIO_OUT_VAL 0x000FFC00 516185377Ssam#define AR_GPIO_OUT_VAL_S 10 517185377Ssam#define AR_GPIO_INTR_CTRL 0x3FF00000 518185377Ssam#define AR_GPIO_INTR_CTRL_S 20 519185377Ssam 520188976Ssam#define AR_GPIO_IN_VAL 0x0FFFC000 /* pre-9280 */ 521188976Ssam#define AR_GPIO_IN_VAL_S 14 522188976Ssam#define AR928X_GPIO_IN_VAL 0x000FFC00 523188976Ssam#define AR928X_GPIO_IN_VAL_S 10 524188976Ssam#define AR9285_GPIO_IN_VAL 0x00FFF000 525188976Ssam#define AR9285_GPIO_IN_VAL_S 12 526188976Ssam 527188976Ssam#define AR_GPIO_OE_OUT_DRV 0x3 /* 2 bit mask shifted by 2*bitpos */ 528188976Ssam#define AR_GPIO_OE_OUT_DRV_NO 0x0 /* tristate */ 529188976Ssam#define AR_GPIO_OE_OUT_DRV_LOW 0x1 /* drive if low */ 530188976Ssam#define AR_GPIO_OE_OUT_DRV_HI 0x2 /* drive if high */ 531188976Ssam#define AR_GPIO_OE_OUT_DRV_ALL 0x3 /* drive always */ 532188976Ssam 533188976Ssam#define AR_GPIO_INTR_POL_VAL 0x1FFF 534188976Ssam#define AR_GPIO_INTR_POL_VAL_S 0 535188976Ssam 536208711Srpaulo#define AR_GPIO_JTAG_DISABLE 0x00020000 537208711Srpaulo 538185377Ssam#define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ 539185377Ssam 540185377Ssam#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 541185377Ssam#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 542203159Srpaulo#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 543185377Ssam 544185377Ssam/* Eeprom defines */ 545185377Ssam#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 546185377Ssam#define AR_EEPROM_STATUS_DATA_VAL_S 0 547185377Ssam#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 548185377Ssam#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 549185377Ssam#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 550185377Ssam#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 551185377Ssam 552185377Ssam#define AR_SREV_REVISION_OWL_10 0x08 553185377Ssam#define AR_SREV_REVISION_OWL_20 0x09 554185377Ssam#define AR_SREV_REVISION_OWL_22 0x0a 555185377Ssam 556185377Ssam#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ 557185377Ssam#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ 558185377Ssam#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ 559185377Ssam#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ 560185377Ssam 561185377Ssam/* Test macro for owl 1.0 */ 562185377Ssam#define IS_5416V1(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_10) 563185377Ssam#define IS_5416V2(_ah) ((_ah)->ah_macRev >= AR_SREV_REVISION_OWL_20) 564185377Ssam#define IS_5416V2_2(_ah) ((_ah)->ah_macRev == AR_SREV_REVISION_OWL_22) 565185377Ssam 566185377Ssam/* Expanded Mac Silicon Rev (16 bits starting with Sowl) */ 567185377Ssam#define AR_XSREV_ID 0xFFFFFFFF /* Chip ID */ 568185377Ssam#define AR_XSREV_ID_S 0 569185377Ssam#define AR_XSREV_VERSION 0xFFFC0000 /* Chip version */ 570185377Ssam#define AR_XSREV_VERSION_S 18 571185377Ssam#define AR_XSREV_TYPE 0x0003F000 /* Chip type */ 572185377Ssam#define AR_XSREV_TYPE_S 12 573185377Ssam#define AR_XSREV_TYPE_CHAIN 0x00001000 /* Chain Mode (1:3 chains, 574185377Ssam * 0:2 chains) */ 575185377Ssam#define AR_XSREV_TYPE_HOST_MODE 0x00002000 /* Host Mode (1:PCI, 0:PCIe) */ 576185377Ssam#define AR_XSREV_REVISION 0x00000F00 577185377Ssam#define AR_XSREV_REVISION_S 8 578185377Ssam 579185377Ssam#define AR_XSREV_VERSION_OWL_PCI 0x0D 580185377Ssam#define AR_XSREV_VERSION_OWL_PCIE 0x0C 581185377Ssam#define AR_XSREV_REVISION_OWL_10 0 /* Owl 1.0 */ 582185377Ssam#define AR_XSREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ 583185377Ssam#define AR_XSREV_REVISION_OWL_22 2 /* Owl 2.2 */ 584219217Sadrian#define AR_XSREV_VERSION_HOWL 0x14 /* Howl (AR9130) */ 585185377Ssam#define AR_XSREV_VERSION_SOWL 0x40 586185377Ssam#define AR_XSREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ 587185377Ssam#define AR_XSREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ 588185377Ssam#define AR_XSREV_VERSION_MERLIN 0x80 /* Merlin Version */ 589185377Ssam#define AR_XSREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ 590185377Ssam#define AR_XSREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ 591185377Ssam#define AR_XSREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ 592185377Ssam#define AR_XSREV_VERSION_KITE 0xC0 /* Kite Version */ 593185377Ssam#define AR_XSREV_REVISION_KITE_10 0 /* Kite 1.0 */ 594203159Srpaulo#define AR_XSREV_REVISION_KITE_11 1 /* Kite 1.1 */ 595203159Srpaulo#define AR_XSREV_REVISION_KITE_12 2 /* Kite 1.2 */ 596185377Ssam 597217881Sadrian#define AR_SREV_OWL(_ah) \ 598217881Sadrian ((AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCI) || \ 599217881Sadrian (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_OWL_PCIE)) 600217881Sadrian 601185377Ssam#define AR_SREV_OWL_20_OR_LATER(_ah) \ 602219217Sadrian ((AR_SREV_OWL(_ah) && AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_20) || \ 603219217Sadrian AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 604185377Ssam#define AR_SREV_OWL_22_OR_LATER(_ah) \ 605219217Sadrian ((AR_SREV_OWL(_ah) && AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_OWL_22) || \ 606219217Sadrian AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_HOWL) 607185377Ssam 608185377Ssam#define AR_SREV_SOWL(_ah) \ 609185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_SOWL) 610185377Ssam#define AR_SREV_SOWL_10_OR_LATER(_ah) \ 611185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_SOWL) 612185377Ssam#define AR_SREV_SOWL_11(_ah) \ 613185377Ssam (AR_SREV_SOWL(_ah) && \ 614185377Ssam AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_SOWL_11) 615185377Ssam 616185377Ssam#define AR_SREV_MERLIN(_ah) \ 617185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_MERLIN) 618185377Ssam#define AR_SREV_MERLIN_10_OR_LATER(_ah) \ 619185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 620185377Ssam#define AR_SREV_MERLIN_20(_ah) \ 621185377Ssam (AR_SREV_MERLIN(_ah) && \ 622203959Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_MERLIN_20) 623185377Ssam#define AR_SREV_MERLIN_20_OR_LATER(_ah) \ 624185377Ssam (AR_SREV_MERLIN_20(_ah) || \ 625209548Srpaulo AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_MERLIN) 626185377Ssam 627185377Ssam#define AR_SREV_KITE(_ah) \ 628185377Ssam (AH_PRIVATE((_ah))->ah_macVersion == AR_XSREV_VERSION_KITE) 629185377Ssam#define AR_SREV_KITE_10_OR_LATER(_ah) \ 630185377Ssam (AH_PRIVATE((_ah))->ah_macVersion >= AR_XSREV_VERSION_KITE) 631203159Srpaulo#define AR_SREV_KITE_11(_ah) \ 632203159Srpaulo (AR_SREV_KITE(ah) && \ 633203159Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_11) 634203159Srpaulo#define AR_SREV_KITE_11_OR_LATER(_ah) \ 635203933Srpaulo (AR_SREV_KITE_11(_ah) || \ 636203159Srpaulo AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_11) 637203159Srpaulo#define AR_SREV_KITE_12(_ah) \ 638203159Srpaulo (AR_SREV_KITE(ah) && \ 639203959Srpaulo AH_PRIVATE((_ah))->ah_macRev == AR_XSREV_REVISION_KITE_12) 640203159Srpaulo#define AR_SREV_KITE_12_OR_LATER(_ah) \ 641203933Srpaulo (AR_SREV_KITE_12(_ah) || \ 642203159Srpaulo AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KITE_12) 643218061Sadrian#define AR_SREV_9285E_20(_ah) \ 644218061Sadrian (AR_SREV_KITE_12_OR_LATER(_ah) && \ 645218061Sadrian ((OS_REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 646218061Sadrian 647219217Sadrian/* Not yet implemented chips */ 648219217Sadrian#define AR_SREV_9271(_ah) 0 649219217Sadrian#define AR_SREV_9287_11_OR_LATER(_ah) 0 650219217Sadrian#define AR_SREV_9100(_ah) 0 651219217Sadrian 652185377Ssam#endif /* _DEV_ATH_AR5416REG_H */ 653