ar5416_interrupts.c revision 225921
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c 225921 2011-10-02 13:43:06Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23 24#include "ar5416/ar5416.h" 25#include "ar5416/ar5416reg.h" 26 27/* 28 * Checks to see if an interrupt is pending on our NIC 29 * 30 * Returns: TRUE if an interrupt is pending 31 * FALSE if not 32 */ 33HAL_BOOL 34ar5416IsInterruptPending(struct ath_hal *ah) 35{ 36 uint32_t isr; 37 38 if (AR_SREV_HOWL(ah)) 39 return AH_TRUE; 40 41 /* 42 * Some platforms trigger our ISR before applying power to 43 * the card, so make sure the INTPEND is really 1, not 0xffffffff. 44 */ 45 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE); 46 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0) 47 return AH_TRUE; 48 49 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 50 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT)) 51 return AH_TRUE; 52 53 return AH_FALSE; 54} 55 56/* 57 * Reads the Interrupt Status Register value from the NIC, thus deasserting 58 * the interrupt line, and returns both the masked and unmasked mapped ISR 59 * values. The value returned is mapped to abstract the hw-specific bit 60 * locations in the Interrupt Status Register. 61 * 62 * (*masked) is cleared on initial call. 63 * 64 * Returns: A hardware-abstracted bitmap of all non-masked-out 65 * interrupts pending, as well as an unmasked value 66 */ 67HAL_BOOL 68ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 69{ 70 uint32_t isr, isr0, isr1, sync_cause = 0; 71 72 /* 73 * Verify there's a mac interrupt and the RTC is on. 74 */ 75 if (AR_SREV_HOWL(ah)) { 76 *masked = 0; 77 isr = OS_REG_READ(ah, AR_ISR); 78 } else { 79 if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 80 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 81 isr = OS_REG_READ(ah, AR_ISR); 82 else 83 isr = 0; 84 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 85 sync_cause &= AR_INTR_SYNC_DEFAULT; 86 *masked = 0; 87 88 if (isr == 0 && sync_cause == 0) 89 return AH_FALSE; 90 } 91 92 if (isr != 0) { 93 struct ath_hal_5212 *ahp = AH5212(ah); 94 uint32_t mask2; 95 96 mask2 = 0; 97 if (isr & AR_ISR_BCNMISC) { 98 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); 99 if (isr2 & AR_ISR_S2_TIM) 100 mask2 |= HAL_INT_TIM; 101 if (isr2 & AR_ISR_S2_DTIM) 102 mask2 |= HAL_INT_DTIM; 103 if (isr2 & AR_ISR_S2_DTIMSYNC) 104 mask2 |= HAL_INT_DTIMSYNC; 105 if (isr2 & (AR_ISR_S2_CABEND )) 106 mask2 |= HAL_INT_CABEND; 107 if (isr2 & AR_ISR_S2_GTT) 108 mask2 |= HAL_INT_GTT; 109 if (isr2 & AR_ISR_S2_CST) 110 mask2 |= HAL_INT_CST; 111 if (isr2 & AR_ISR_S2_TSFOOR) 112 mask2 |= HAL_INT_TSFOOR; 113 } 114 115 isr = OS_REG_READ(ah, AR_ISR_RAC); 116 if (isr == 0xffffffff) { 117 *masked = 0; 118 return AH_FALSE; 119 } 120 121 *masked = isr & HAL_INT_COMMON; 122 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 123 *masked |= HAL_INT_RX; 124 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) { 125 *masked |= HAL_INT_TX; 126 isr0 = OS_REG_READ(ah, AR_ISR_S0_S); 127 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK); 128 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC); 129 isr1 = OS_REG_READ(ah, AR_ISR_S1_S); 130 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); 131 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 132 } 133 134 if (AR_SREV_MERLIN(ah) || AR_SREV_KITE(ah)) { 135 uint32_t isr5; 136 isr5 = OS_REG_READ(ah, AR_ISR_S5_S); 137 if (isr5 & AR_ISR_S5_TIM_TIMER) 138 *masked |= HAL_INT_TIM_TIMER; 139 } 140 141 /* Interrupt Mitigation on AR5416 */ 142#ifdef AH_AR5416_INTERRUPT_MITIGATION 143 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 144 *masked |= HAL_INT_RX; 145#endif 146 *masked |= mask2; 147 } 148 149 if (AR_SREV_HOWL(ah)) 150 return AH_TRUE; 151 152 if (sync_cause != 0) { 153 if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) { 154 *masked |= HAL_INT_FATAL; 155 } 156 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 157 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n", 158 __func__); 159 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 160 OS_REG_WRITE(ah, AR_RC, 0); 161 *masked |= HAL_INT_FATAL; 162 } 163 /* 164 * On fatal errors collect ISR state for debugging. 165 */ 166 if (*masked & HAL_INT_FATAL) { 167 AH_PRIVATE(ah)->ah_fatalState[0] = isr; 168 AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause; 169 HALDEBUG(ah, HAL_DEBUG_ANY, 170 "%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n", 171 __func__, isr, sync_cause); 172 } 173 174 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 175 /* NB: flush write */ 176 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 177 } 178 return AH_TRUE; 179} 180 181/* 182 * Atomically enables NIC interrupts. Interrupts are passed in 183 * via the enumerated bitmask in ints. 184 */ 185HAL_INT 186ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) 187{ 188 struct ath_hal_5212 *ahp = AH5212(ah); 189 uint32_t omask = ahp->ah_maskReg; 190 uint32_t mask, mask2; 191 192 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 193 __func__, omask, ints); 194 195 if (omask & HAL_INT_GLOBAL) { 196 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 197 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 198 (void) OS_REG_READ(ah, AR_IER); 199 200 if (! AR_SREV_HOWL(ah)) { 201 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 202 (void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE); 203 204 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 205 (void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE); 206 } 207 } 208 209 mask = ints & HAL_INT_COMMON; 210 mask2 = 0; 211 212#ifdef AH_AR5416_INTERRUPT_MITIGATION 213 /* 214 * Overwrite default mask if Interrupt mitigation 215 * is specified for AR5416 216 */ 217 if (ints & HAL_INT_RX) 218 mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM; 219#else 220 if (ints & HAL_INT_RX) 221 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 222#endif 223 if (ints & HAL_INT_TX) { 224 if (ahp->ah_txOkInterruptMask) 225 mask |= AR_IMR_TXOK; 226 if (ahp->ah_txErrInterruptMask) 227 mask |= AR_IMR_TXERR; 228 if (ahp->ah_txDescInterruptMask) 229 mask |= AR_IMR_TXDESC; 230 if (ahp->ah_txEolInterruptMask) 231 mask |= AR_IMR_TXEOL; 232 } 233 if (ints & (HAL_INT_BMISC)) { 234 mask |= AR_IMR_BCNMISC; 235 if (ints & HAL_INT_TIM) 236 mask2 |= AR_IMR_S2_TIM; 237 if (ints & HAL_INT_DTIM) 238 mask2 |= AR_IMR_S2_DTIM; 239 if (ints & HAL_INT_DTIMSYNC) 240 mask2 |= AR_IMR_S2_DTIMSYNC; 241 if (ints & HAL_INT_CABEND) 242 mask2 |= (AR_IMR_S2_CABEND ); 243 if (ints & HAL_INT_CST) 244 mask2 |= AR_IMR_S2_CST; 245 if (ints & HAL_INT_TSFOOR) 246 mask2 |= AR_IMR_S2_TSFOOR; 247 } 248 249 if (ints & (HAL_INT_GTT | HAL_INT_CST)) { 250 mask |= AR_IMR_BCNMISC; 251 if (ints & HAL_INT_GTT) 252 mask2 |= AR_IMR_S2_GTT; 253 if (ints & HAL_INT_CST) 254 mask2 |= AR_IMR_S2_CST; 255 } 256 257 /* Write the new IMR and store off our SW copy. */ 258 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 259 OS_REG_WRITE(ah, AR_IMR, mask); 260 mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 261 AR_IMR_S2_DTIM | 262 AR_IMR_S2_DTIMSYNC | 263 AR_IMR_S2_CABEND | 264 AR_IMR_S2_CABTO | 265 AR_IMR_S2_TSFOOR | 266 AR_IMR_S2_GTT | 267 AR_IMR_S2_CST); 268 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2); 269 270 ahp->ah_maskReg = ints; 271 272 /* Re-enable interrupts if they were enabled before. */ 273 if (ints & HAL_INT_GLOBAL) { 274 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 275 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 276 277 if (! AR_SREV_HOWL(ah)) { 278 mask = AR_INTR_MAC_IRQ; 279 if (ints & HAL_INT_GPIO) 280 mask |= SM(AH5416(ah)->ah_gpioMask, 281 AR_INTR_ASYNC_MASK_GPIO); 282 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask); 283 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask); 284 285 mask = AR_INTR_SYNC_DEFAULT; 286 if (ints & HAL_INT_GPIO) 287 mask |= SM(AH5416(ah)->ah_gpioMask, 288 AR_INTR_SYNC_MASK_GPIO); 289 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask); 290 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask); 291 } 292 } 293 294 return omask; 295} 296