ar5416_interrupts.c revision 220966
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c 220966 2011-04-23 06:37:09Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23 24#include "ar5416/ar5416.h" 25#include "ar5416/ar5416reg.h" 26 27/* 28 * Checks to see if an interrupt is pending on our NIC 29 * 30 * Returns: TRUE if an interrupt is pending 31 * FALSE if not 32 */ 33HAL_BOOL 34ar5416IsInterruptPending(struct ath_hal *ah) 35{ 36 uint32_t isr; 37 /* 38 * Some platforms trigger our ISR before applying power to 39 * the card, so make sure the INTPEND is really 1, not 0xffffffff. 40 */ 41 isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE); 42 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_MAC_IRQ) != 0) 43 return AH_TRUE; 44 45 isr = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 46 if (isr != AR_INTR_SPURIOUS && (isr & AR_INTR_SYNC_DEFAULT)) 47 return AH_TRUE; 48 49 return AH_FALSE; 50} 51 52/* 53 * Reads the Interrupt Status Register value from the NIC, thus deasserting 54 * the interrupt line, and returns both the masked and unmasked mapped ISR 55 * values. The value returned is mapped to abstract the hw-specific bit 56 * locations in the Interrupt Status Register. 57 * 58 * (*masked) is cleared on initial call. 59 * 60 * Returns: A hardware-abstracted bitmap of all non-masked-out 61 * interrupts pending, as well as an unmasked value 62 */ 63HAL_BOOL 64ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 65{ 66 uint32_t isr, isr0, isr1, sync_cause; 67 68 /* 69 * Verify there's a mac interrupt and the RTC is on. 70 */ 71 if ((OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) && 72 (OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) == AR_RTC_STATUS_ON) 73 isr = OS_REG_READ(ah, AR_ISR); 74 else 75 isr = 0; 76 sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 77 sync_cause &= AR_INTR_SYNC_DEFAULT; 78 *masked = 0; 79 80 if (isr == 0 && sync_cause == 0) 81 return AH_FALSE; 82 83 if (isr != 0) { 84 struct ath_hal_5212 *ahp = AH5212(ah); 85 uint32_t mask2; 86 87 mask2 = 0; 88 if (isr & AR_ISR_BCNMISC) { 89 uint32_t isr2 = OS_REG_READ(ah, AR_ISR_S2); 90 if (isr2 & AR_ISR_S2_TIM) 91 mask2 |= HAL_INT_TIM; 92 if (isr2 & AR_ISR_S2_DTIM) 93 mask2 |= HAL_INT_DTIM; 94 if (isr2 & AR_ISR_S2_DTIMSYNC) 95 mask2 |= HAL_INT_DTIMSYNC; 96 if (isr2 & (AR_ISR_S2_CABEND )) 97 mask2 |= HAL_INT_CABEND; 98 if (isr2 & AR_ISR_S2_GTT) 99 mask2 |= HAL_INT_GTT; 100 if (isr2 & AR_ISR_S2_CST) 101 mask2 |= HAL_INT_CST; 102 if (isr2 & AR_ISR_S2_TSFOOR) 103 mask2 |= HAL_INT_TSFOOR; 104 } 105 106 isr = OS_REG_READ(ah, AR_ISR_RAC); 107 if (isr == 0xffffffff) { 108 *masked = 0; 109 return AH_FALSE; 110 } 111 112 *masked = isr & HAL_INT_COMMON; 113 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 114 *masked |= HAL_INT_RX; 115 if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) { 116 *masked |= HAL_INT_TX; 117 isr0 = OS_REG_READ(ah, AR_ISR_S0_S); 118 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK); 119 ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC); 120 isr1 = OS_REG_READ(ah, AR_ISR_S1_S); 121 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); 122 ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 123 } 124 125 if (AR_SREV_MERLIN(ah) || AR_SREV_KITE(ah)) { 126 uint32_t isr5; 127 isr5 = OS_REG_READ(ah, AR_ISR_S5_S); 128 if (isr5 & AR_ISR_S5_TIM_TIMER) 129 *masked |= HAL_INT_TIM_TIMER; 130 } 131 132 /* Interrupt Mitigation on AR5416 */ 133#ifdef AH_AR5416_INTERRUPT_MITIGATION 134 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) 135 *masked |= HAL_INT_RX; 136 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) 137 *masked |= HAL_INT_TX; 138#endif 139 *masked |= mask2; 140 } 141 if (sync_cause != 0) { 142 if (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) { 143 *masked |= HAL_INT_FATAL; 144 } 145 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 146 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RADM CPL timeout\n", 147 __func__); 148 OS_REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 149 OS_REG_WRITE(ah, AR_RC, 0); 150 *masked |= HAL_INT_FATAL; 151 } 152 /* 153 * On fatal errors collect ISR state for debugging. 154 */ 155 if (*masked & HAL_INT_FATAL) { 156 AH_PRIVATE(ah)->ah_fatalState[0] = isr; 157 AH_PRIVATE(ah)->ah_fatalState[1] = sync_cause; 158 HALDEBUG(ah, HAL_DEBUG_ANY, 159 "%s: fatal error, ISR_RAC 0x%x SYNC_CAUSE 0x%x\n", 160 __func__, isr, sync_cause); 161 } 162 163 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 164 /* NB: flush write */ 165 (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); 166 } 167 return AH_TRUE; 168} 169 170/* 171 * Atomically enables NIC interrupts. Interrupts are passed in 172 * via the enumerated bitmask in ints. 173 */ 174HAL_INT 175ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) 176{ 177 struct ath_hal_5212 *ahp = AH5212(ah); 178 uint32_t omask = ahp->ah_maskReg; 179 uint32_t mask, mask2; 180 181 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 182 __func__, omask, ints); 183 184 if (omask & HAL_INT_GLOBAL) { 185 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 186 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 187 (void) OS_REG_READ(ah, AR_IER); 188 189 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); 190 (void) OS_REG_READ(ah, AR_INTR_ASYNC_ENABLE); 191 192 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 193 (void) OS_REG_READ(ah, AR_INTR_SYNC_ENABLE); 194 } 195 196 mask = ints & HAL_INT_COMMON; 197 mask2 = 0; 198 199#ifdef AH_AR5416_INTERRUPT_MITIGATION 200 /* 201 * Overwrite default mask if Interrupt mitigation 202 * is specified for AR5416 203 */ 204 mask = ints & HAL_INT_COMMON; 205 if (ints & HAL_INT_TX) 206 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; 207 if (ints & HAL_INT_RX) 208 mask |= AR_IMR_RXERR | AR_IMR_RXMINTR | AR_IMR_RXINTM; 209 if (ints & HAL_INT_TX) { 210 if (ahp->ah_txErrInterruptMask) 211 mask |= AR_IMR_TXERR; 212 if (ahp->ah_txEolInterruptMask) 213 mask |= AR_IMR_TXEOL; 214 } 215#else 216 if (ints & HAL_INT_TX) { 217 if (ahp->ah_txOkInterruptMask) 218 mask |= AR_IMR_TXOK; 219 if (ahp->ah_txErrInterruptMask) 220 mask |= AR_IMR_TXERR; 221 if (ahp->ah_txDescInterruptMask) 222 mask |= AR_IMR_TXDESC; 223 if (ahp->ah_txEolInterruptMask) 224 mask |= AR_IMR_TXEOL; 225 } 226 if (ints & HAL_INT_RX) 227 mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 228#endif 229 if (ints & (HAL_INT_BMISC)) { 230 mask |= AR_IMR_BCNMISC; 231 if (ints & HAL_INT_TIM) 232 mask2 |= AR_IMR_S2_TIM; 233 if (ints & HAL_INT_DTIM) 234 mask2 |= AR_IMR_S2_DTIM; 235 if (ints & HAL_INT_DTIMSYNC) 236 mask2 |= AR_IMR_S2_DTIMSYNC; 237 if (ints & HAL_INT_CABEND) 238 mask2 |= (AR_IMR_S2_CABEND ); 239 if (ints & HAL_INT_CST) 240 mask2 |= AR_IMR_S2_CST; 241 if (ints & HAL_INT_TSFOOR) 242 mask2 |= AR_IMR_S2_TSFOOR; 243 } 244 245 if (ints & (HAL_INT_GTT | HAL_INT_CST)) { 246 mask |= AR_IMR_BCNMISC; 247 if (ints & HAL_INT_GTT) 248 mask2 |= AR_IMR_S2_GTT; 249 if (ints & HAL_INT_CST) 250 mask2 |= AR_IMR_S2_CST; 251 } 252 253 /* Write the new IMR and store off our SW copy. */ 254 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 255 OS_REG_WRITE(ah, AR_IMR, mask); 256 mask = OS_REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 257 AR_IMR_S2_DTIM | 258 AR_IMR_S2_DTIMSYNC | 259 AR_IMR_S2_CABEND | 260 AR_IMR_S2_CABTO | 261 AR_IMR_S2_TSFOOR | 262 AR_IMR_S2_GTT | 263 AR_IMR_S2_CST); 264 OS_REG_WRITE(ah, AR_IMR_S2, mask | mask2); 265 266 ahp->ah_maskReg = ints; 267 268 /* Re-enable interrupts if they were enabled before. */ 269 if (ints & HAL_INT_GLOBAL) { 270 HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 271 OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 272 273 mask = AR_INTR_MAC_IRQ; 274 if (ints & HAL_INT_GPIO) 275 mask |= SM(AH5416(ah)->ah_gpioMask, 276 AR_INTR_ASYNC_MASK_GPIO); 277 OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, mask); 278 OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, mask); 279 280 mask = AR_INTR_SYNC_DEFAULT; 281 if (ints & HAL_INT_GPIO) 282 mask |= SM(AH5416(ah)->ah_gpioMask, 283 AR_INTR_SYNC_MASK_GPIO); 284 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, mask); 285 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, mask); 286 } 287 288 return omask; 289} 290