ar5212_interrupts.c revision 185380
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17185380Ssam * $Id: ar5212_interrupts.c,v 1.6 2008/11/27 22:30:00 sam Exp $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#ifdef AH_SUPPORT_AR5212 22185377Ssam 23185377Ssam#include "ah.h" 24185377Ssam#include "ah_internal.h" 25185377Ssam 26185377Ssam#include "ar5212/ar5212.h" 27185377Ssam#include "ar5212/ar5212reg.h" 28185377Ssam#include "ar5212/ar5212phy.h" 29185377Ssam 30185377Ssam 31185377Ssam/* 32185377Ssam * Checks to see if an interrupt is pending on our NIC 33185377Ssam * 34185377Ssam * Returns: TRUE if an interrupt is pending 35185377Ssam * FALSE if not 36185377Ssam */ 37185377SsamHAL_BOOL 38185377Ssamar5212IsInterruptPending(struct ath_hal *ah) 39185377Ssam{ 40185377Ssam /* 41185377Ssam * Some platforms trigger our ISR before applying power to 42185377Ssam * the card, so make sure the INTPEND is really 1, not 0xffffffff. 43185377Ssam */ 44185377Ssam return (OS_REG_READ(ah, AR_INTPEND) == AR_INTPEND_TRUE); 45185377Ssam} 46185377Ssam 47185377Ssam/* 48185377Ssam * Reads the Interrupt Status Register value from the NIC, thus deasserting 49185377Ssam * the interrupt line, and returns both the masked and unmasked mapped ISR 50185377Ssam * values. The value returned is mapped to abstract the hw-specific bit 51185377Ssam * locations in the Interrupt Status Register. 52185377Ssam * 53185377Ssam * Returns: A hardware-abstracted bitmap of all non-masked-out 54185377Ssam * interrupts pending, as well as an unmasked value 55185377Ssam */ 56185377SsamHAL_BOOL 57185377Ssamar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) 58185377Ssam{ 59185377Ssam uint32_t isr, isr0, isr1; 60185377Ssam uint32_t mask2=0; 61185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 62185377Ssam 63185377Ssam isr = OS_REG_READ(ah, AR_ISR); 64185377Ssam if (isr & AR_ISR_BCNMISC) { 65185377Ssam uint32_t isr2; 66185377Ssam isr2 = OS_REG_READ(ah, AR_ISR_S2); 67185377Ssam if (isr2 & AR_ISR_S2_TIM) 68185377Ssam mask2 |= HAL_INT_TIM; 69185377Ssam if (isr2 & AR_ISR_S2_DTIM) 70185377Ssam mask2 |= HAL_INT_DTIM; 71185377Ssam if (isr2 & AR_ISR_S2_DTIMSYNC) 72185377Ssam mask2 |= HAL_INT_DTIMSYNC; 73185377Ssam if (isr2 & (AR_ISR_S2_CABEND )) 74185377Ssam mask2 |= HAL_INT_CABEND; 75185377Ssam } 76185377Ssam isr = OS_REG_READ(ah, AR_ISR_RAC); 77185377Ssam if (isr == 0xffffffff) { 78185377Ssam *masked = 0; 79185377Ssam return AH_FALSE;; 80185377Ssam } 81185377Ssam 82185377Ssam *masked = isr & HAL_INT_COMMON; 83185377Ssam 84185377Ssam if (isr & AR_ISR_HIUERR) 85185377Ssam *masked |= HAL_INT_FATAL; 86185377Ssam if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) 87185377Ssam *masked |= HAL_INT_RX; 88185377Ssam if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) { 89185377Ssam *masked |= HAL_INT_TX; 90185377Ssam isr0 = OS_REG_READ(ah, AR_ISR_S0_S); 91185377Ssam ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXOK); 92185377Ssam ahp->ah_intrTxqs |= MS(isr0, AR_ISR_S0_QCU_TXDESC); 93185377Ssam isr1 = OS_REG_READ(ah, AR_ISR_S1_S); 94185377Ssam ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXERR); 95185377Ssam ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); 96185377Ssam } 97185377Ssam 98185377Ssam /* 99185380Ssam * Receive overrun is usually non-fatal on Oahu/Spirit. 100185380Ssam * BUT on some parts rx could fail and the chip must be reset. 101185380Ssam * So we force a hardware reset in all cases. 102185377Ssam */ 103185377Ssam if ((isr & AR_ISR_RXORN) && AH_PRIVATE(ah)->ah_rxornIsFatal) { 104185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 105185377Ssam "%s: receive FIFO overrun interrupt\n", __func__); 106185377Ssam *masked |= HAL_INT_FATAL; 107185377Ssam } 108185377Ssam *masked |= mask2; 109185377Ssam 110185377Ssam /* 111185377Ssam * On fatal errors collect ISR state for debugging. 112185377Ssam */ 113185377Ssam if (*masked & HAL_INT_FATAL) { 114185377Ssam AH_PRIVATE(ah)->ah_fatalState[0] = isr; 115185377Ssam AH_PRIVATE(ah)->ah_fatalState[1] = OS_REG_READ(ah, AR_ISR_S0_S); 116185377Ssam AH_PRIVATE(ah)->ah_fatalState[2] = OS_REG_READ(ah, AR_ISR_S1_S); 117185377Ssam AH_PRIVATE(ah)->ah_fatalState[3] = OS_REG_READ(ah, AR_ISR_S2_S); 118185377Ssam AH_PRIVATE(ah)->ah_fatalState[4] = OS_REG_READ(ah, AR_ISR_S3_S); 119185377Ssam AH_PRIVATE(ah)->ah_fatalState[5] = OS_REG_READ(ah, AR_ISR_S4_S); 120185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 121185377Ssam "%s: fatal error, ISR_RAC=0x%x ISR_S2_S=0x%x\n", 122185377Ssam __func__, isr, AH_PRIVATE(ah)->ah_fatalState[3]); 123185377Ssam } 124185377Ssam return AH_TRUE; 125185377Ssam} 126185377Ssam 127185377SsamHAL_INT 128185377Ssamar5212GetInterrupts(struct ath_hal *ah) 129185377Ssam{ 130185377Ssam return AH5212(ah)->ah_maskReg; 131185377Ssam} 132185377Ssam 133185377Ssam/* 134185377Ssam * Atomically enables NIC interrupts. Interrupts are passed in 135185377Ssam * via the enumerated bitmask in ints. 136185377Ssam */ 137185377SsamHAL_INT 138185377Ssamar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints) 139185377Ssam{ 140185377Ssam struct ath_hal_5212 *ahp = AH5212(ah); 141185377Ssam uint32_t omask = ahp->ah_maskReg; 142185377Ssam uint32_t mask,mask2; 143185377Ssam 144185377Ssam HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: 0x%x => 0x%x\n", 145185377Ssam __func__, omask, ints); 146185377Ssam 147185377Ssam if (omask & HAL_INT_GLOBAL) { 148185377Ssam HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: disable IER\n", __func__); 149185377Ssam OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 150185377Ssam (void) OS_REG_READ(ah, AR_IER); /* flush write to HW */ 151185377Ssam } 152185377Ssam 153185377Ssam mask = ints & HAL_INT_COMMON; 154185377Ssam mask2 = 0; 155185377Ssam if (ints & HAL_INT_TX) { 156185377Ssam if (ahp->ah_txOkInterruptMask) 157185377Ssam mask |= AR_IMR_TXOK; 158185377Ssam if (ahp->ah_txErrInterruptMask) 159185377Ssam mask |= AR_IMR_TXERR; 160185377Ssam if (ahp->ah_txDescInterruptMask) 161185377Ssam mask |= AR_IMR_TXDESC; 162185377Ssam if (ahp->ah_txEolInterruptMask) 163185377Ssam mask |= AR_IMR_TXEOL; 164185377Ssam } 165185377Ssam if (ints & HAL_INT_RX) 166185377Ssam mask |= AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXDESC; 167185377Ssam if (ints & (HAL_INT_BMISC)) { 168185377Ssam mask |= AR_IMR_BCNMISC; 169185377Ssam if (ints & HAL_INT_TIM) 170185377Ssam mask2 |= AR_IMR_S2_TIM; 171185377Ssam if (ints & HAL_INT_DTIM) 172185377Ssam mask2 |= AR_IMR_S2_DTIM; 173185377Ssam if (ints & HAL_INT_DTIMSYNC) 174185377Ssam mask2 |= AR_IMR_S2_DTIMSYNC; 175185377Ssam if (ints & HAL_INT_CABEND) 176185377Ssam mask2 |= (AR_IMR_S2_CABEND ); 177185377Ssam } 178185377Ssam if (ints & HAL_INT_FATAL) { 179185377Ssam /* 180185377Ssam * NB: ar5212Reset sets MCABT+SSERR+DPERR in AR_IMR_S2 181185377Ssam * so enabling HIUERR enables delivery. 182185377Ssam */ 183185377Ssam mask |= AR_IMR_HIUERR; 184185377Ssam } 185185377Ssam 186185377Ssam /* Write the new IMR and store off our SW copy. */ 187185377Ssam HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, mask); 188185377Ssam OS_REG_WRITE(ah, AR_IMR, mask); 189185377Ssam OS_REG_WRITE(ah, AR_IMR_S2, 190185377Ssam (OS_REG_READ(ah, AR_IMR_S2) & 191185377Ssam ~(AR_IMR_S2_TIM | 192185377Ssam AR_IMR_S2_DTIM | 193185377Ssam AR_IMR_S2_DTIMSYNC | 194185377Ssam AR_IMR_S2_CABEND | 195185377Ssam AR_IMR_S2_CABTO | 196185377Ssam AR_IMR_S2_TSFOOR ) ) 197185377Ssam | mask2); 198185377Ssam ahp->ah_maskReg = ints; 199185377Ssam 200185377Ssam /* Re-enable interrupts if they were enabled before. */ 201185377Ssam if (ints & HAL_INT_GLOBAL) { 202185377Ssam HALDEBUG(ah, HAL_DEBUG_INTERRUPT, "%s: enable IER\n", __func__); 203185377Ssam OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 204185377Ssam } 205185377Ssam 206185377Ssam 207185377Ssam return omask; 208185377Ssam} 209185377Ssam#endif /* AH_SUPPORT_AR5212 */ 210