ar5212_gpio.c revision 256281
181400Sru/* 281400Sru * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 381400Sru * Copyright (c) 2002-2008 Atheros Communications, Inc. 481400Sru * 581400Sru * Permission to use, copy, modify, and/or distribute this software for any 681400Sru * purpose with or without fee is hereby granted, provided that the above 781400Sru * copyright notice and this permission notice appear in all copies. 881400Sru * 981400Sru * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1081400Sru * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1181400Sru * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1281400Sru * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1381400Sru * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1481400Sru * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1581400Sru * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1681400Sru * 1781400Sru * $FreeBSD: stable/10/sys/dev/ath/ath_hal/ar5212/ar5212_gpio.c 188974 2009-02-24 00:12:16Z sam $ 1881400Sru */ 1981400Sru#include "opt_ah.h" 2081400Sru 2181400Sru#include "ah.h" 2281400Sru#include "ah_internal.h" 2381400Sru#include "ah_devid.h" 2481400Sru#ifdef AH_DEBUG 2581400Sru#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 2681400Sru#endif 2781400Sru 28206622Suqs#include "ar5212/ar5212.h" 2981400Sru#include "ar5212/ar5212reg.h" 3081400Sru#include "ar5212/ar5212phy.h" 3181400Sru 3281400Sru#define AR_NUM_GPIO 6 /* 6 GPIO pins */ 3381400Sru#define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */ 3488509Sdavidc 3581400Sru/* 3681400Sru * Configure GPIO Output lines 3781400Sru */ 3881400SruHAL_BOOL 3981400Sruar5212GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type) 4081400Sru{ 4181400Sru HALASSERT(gpio < AR_NUM_GPIO); 4281400Sru 4381400Sru /* 4481400Sru * NB: AR_GPIOCR_CR_A(pin) is all 1's so there's no need 4581400Sru * to clear the field before or'ing in the new value. 4681400Sru */ 4781400Sru OS_REG_WRITE(ah, AR_GPIOCR, 4891470Sdavidc OS_REG_READ(ah, AR_GPIOCR) | AR_GPIOCR_CR_A(gpio)); 4991470Sdavidc 5091470Sdavidc return AH_TRUE; 5191470Sdavidc} 5291470Sdavidc 5381400Sru/* 5481400Sru * Configure GPIO Input lines 5581400Sru */ 5681400SruHAL_BOOL 5781400Sruar5212GpioCfgInput(struct ath_hal *ah, uint32_t gpio) 5881400Sru{ 5981400Sru HALASSERT(gpio < AR_NUM_GPIO); 6081400Sru 61122309Sjkoshy OS_REG_WRITE(ah, AR_GPIOCR, 62122309Sjkoshy (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_CR_A(gpio)) 6381400Sru | AR_GPIOCR_CR_N(gpio)); 64147647Shmp 6581400Sru return AH_TRUE; 66} 67 68/* 69 * Once configured for I/O - set output lines 70 */ 71HAL_BOOL 72ar5212GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val) 73{ 74 uint32_t reg; 75 76 HALASSERT(gpio < AR_NUM_GPIO); 77 78 reg = OS_REG_READ(ah, AR_GPIODO); 79 reg &= ~(1 << gpio); 80 reg |= (val&1) << gpio; 81 82 OS_REG_WRITE(ah, AR_GPIODO, reg); 83 return AH_TRUE; 84} 85 86/* 87 * Once configured for I/O - get input lines 88 */ 89uint32_t 90ar5212GpioGet(struct ath_hal *ah, uint32_t gpio) 91{ 92 if (gpio < AR_NUM_GPIO) { 93 uint32_t val = OS_REG_READ(ah, AR_GPIODI); 94 val = ((val & AR_GPIOD_MASK) >> gpio) & 0x1; 95 return val; 96 } else { 97 return 0xffffffff; 98 } 99} 100 101/* 102 * Set the GPIO Interrupt 103 */ 104void 105ar5212GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel) 106{ 107 uint32_t val; 108 109 /* XXX bounds check gpio */ 110 val = OS_REG_READ(ah, AR_GPIOCR); 111 val &= ~(AR_GPIOCR_CR_A(gpio) | 112 AR_GPIOCR_INT_MASK | AR_GPIOCR_INT_ENA | AR_GPIOCR_INT_SEL); 113 val |= AR_GPIOCR_CR_N(gpio) | AR_GPIOCR_INT(gpio) | AR_GPIOCR_INT_ENA; 114 if (ilevel) 115 val |= AR_GPIOCR_INT_SELH; /* interrupt on pin high */ 116 else 117 val |= AR_GPIOCR_INT_SELL; /* interrupt on pin low */ 118 119 /* Don't need to change anything for low level interrupt. */ 120 OS_REG_WRITE(ah, AR_GPIOCR, val); 121 122 /* Change the interrupt mask. */ 123 (void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO); 124} 125