ar5212.h revision 256281
1249259Sdim/* 2249259Sdim * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3249259Sdim * Copyright (c) 2002-2008 Atheros Communications, Inc. 4249259Sdim * 5249259Sdim * Permission to use, copy, modify, and/or distribute this software for any 6249259Sdim * purpose with or without fee is hereby granted, provided that the above 7249259Sdim * copyright notice and this permission notice appear in all copies. 8249259Sdim * 9249259Sdim * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10249259Sdim * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11249259Sdim * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12249259Sdim * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13249259Sdim * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14249259Sdim * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15249259Sdim * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16249259Sdim * 17249259Sdim * $FreeBSD: stable/10/sys/dev/ath/ath_hal/ar5212/ar5212.h 256139 2013-10-08 11:28:59Z adrian $ 18249259Sdim */ 19249259Sdim#ifndef _ATH_AR5212_H_ 20249259Sdim#define _ATH_AR5212_H_ 21249259Sdim 22249259Sdim#include "ah_eeprom.h" 23249259Sdim 24249259Sdim#define AR5212_MAGIC 0x19541014 25249259Sdim 26249259Sdim/* DCU Transmit Filter macros */ 27249259Sdim#define CALC_MMR(dcu, idx) \ 28249259Sdim ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) 29249259Sdim#define TXBLK_FROM_MMR(mmr) \ 30249259Sdim (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) 31249259Sdim#define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) 32249259Sdim#define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) 33249259Sdim 34249259Sdim/* MAC register values */ 35249259Sdim 36249259Sdim#define INIT_INTERRUPT_MASK \ 37249259Sdim ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ 38249259Sdim AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ 39249259Sdim AR_IMR_HIUERR ) 40249259Sdim#define INIT_BEACON_CONTROL \ 41249259Sdim ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 42249259Sdim (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) 43249259Sdim 44249259Sdim#define INIT_CONFIG_STATUS 0x00000000 45249259Sdim#define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 46249259Sdim#define INIT_IQCAL_LOG_COUNT_MAX 0xF 47249259Sdim#define INIT_BCON_CNTRL_REG 0x00000000 48249259Sdim 49249259Sdim#define INIT_USEC 40 50249259Sdim#define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ 51249259Sdim#define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ 52249259Sdim 53249259Sdim#define RX_NON_FULL_RATE_LATENCY 63 54249259Sdim#define TX_HALF_RATE_LATENCY 108 55249259Sdim#define TX_QUARTER_RATE_LATENCY 216 56249259Sdim 57249259Sdim#define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 58249259Sdim#define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 59249259Sdim#define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 60249259Sdim#define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 61249259Sdim#define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 62249259Sdim#define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 63249259Sdim 64249259Sdim#define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ 65249259Sdim 66249259Sdim/* Tx frame start to tx data start delay */ 67249259Sdim#define TX_FRAME_D_START_HALF_RATE 0xc 68249259Sdim#define TX_FRAME_D_START_QUARTER_RATE 0xd 69249259Sdim 70249259Sdim/* 71249259Sdim * Various fifo fill before Tx start, in 64-byte units 72249259Sdim * i.e. put the frame in the air while still DMAing 73249259Sdim */ 74249259Sdim#define MIN_TX_FIFO_THRESHOLD 0x1 75249259Sdim#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 76249259Sdim#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 77249259Sdim 78249259Sdim#define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ 79249259Sdim 80249259Sdim/* 81249259Sdim * Gain support. 82249259Sdim */ 83249259Sdim#define NUM_CORNER_FIX_BITS 4 84249259Sdim#define NUM_CORNER_FIX_BITS_5112 7 85249259Sdim#define DYN_ADJ_UP_MARGIN 15 86249259Sdim#define DYN_ADJ_LO_MARGIN 20 87249259Sdim#define PHY_PROBE_CCK_CORRECTION 5 88249259Sdim#define CCK_OFDM_GAIN_DELTA 15 89249259Sdim 90249259Sdimenum GAIN_PARAMS { 91249259Sdim GP_TXCLIP, 92249259Sdim GP_PD90, 93249259Sdim GP_PD84, 94249259Sdim GP_GSEL, 95249259Sdim}; 96249259Sdim 97249259Sdimenum GAIN_PARAMS_5112 { 98249259Sdim GP_MIXGAIN_OVR, 99249259Sdim GP_PWD_138, 100249259Sdim GP_PWD_137, 101249259Sdim GP_PWD_136, 102249259Sdim GP_PWD_132, 103249259Sdim GP_PWD_131, 104249259Sdim GP_PWD_130, 105249259Sdim}; 106249259Sdim 107249259Sdimtypedef struct _gainOptStep { 108249259Sdim int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; 109249259Sdim int32_t stepGain; 110249259Sdim int8_t stepName[16]; 111249259Sdim} GAIN_OPTIMIZATION_STEP; 112249259Sdim 113249259Sdimtypedef struct { 114249259Sdim uint32_t numStepsInLadder; 115249259Sdim uint32_t defaultStepNum; 116249259Sdim GAIN_OPTIMIZATION_STEP optStep[10]; 117249259Sdim} GAIN_OPTIMIZATION_LADDER; 118249259Sdim 119249259Sdimtypedef struct { 120249259Sdim uint32_t currStepNum; 121249259Sdim uint32_t currGain; 122249259Sdim uint32_t targetGain; 123249259Sdim uint32_t loTrig; 124249259Sdim uint32_t hiTrig; 125249259Sdim uint32_t active; 126249259Sdim const GAIN_OPTIMIZATION_STEP *currStep; 127249259Sdim} GAIN_VALUES; 128249259Sdim 129249259Sdim/* RF HAL structures */ 130249259Sdimtypedef struct RfHalFuncs { 131249259Sdim void *priv; /* private state */ 132249259Sdim 133249259Sdim void (*rfDetach)(struct ath_hal *ah); 134249259Sdim void (*writeRegs)(struct ath_hal *, 135249259Sdim u_int modeIndex, u_int freqIndex, int regWrites); 136249259Sdim uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); 137249259Sdim HAL_BOOL (*setChannel)(struct ath_hal *, 138249259Sdim const struct ieee80211_channel *); 139249259Sdim HAL_BOOL (*setRfRegs)(struct ath_hal *, 140249259Sdim const struct ieee80211_channel *, uint16_t modesIndex, 141249259Sdim uint16_t *rfXpdGain); 142249259Sdim HAL_BOOL (*setPowerTable)(struct ath_hal *ah, 143249259Sdim int16_t *minPower, int16_t *maxPower, 144249259Sdim const struct ieee80211_channel *, uint16_t *rfXpdGain); 145249259Sdim HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, 146249259Sdim const struct ieee80211_channel *, 147249259Sdim int16_t *maxPow, int16_t *minPow); 148249259Sdim int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); 149249259Sdim} RF_HAL_FUNCS; 150249259Sdim 151249259Sdimstruct ar5212AniParams { 152249259Sdim int maxNoiseImmunityLevel; /* [0..4] */ 153249259Sdim int totalSizeDesired[5]; 154249259Sdim int coarseHigh[5]; 155249259Sdim int coarseLow[5]; 156249259Sdim int firpwr[5]; 157249259Sdim 158249259Sdim int maxSpurImmunityLevel; /* [0..7] */ 159249259Sdim int cycPwrThr1[8]; 160249259Sdim 161249259Sdim int maxFirstepLevel; /* [0..2] */ 162249259Sdim int firstep[3]; 163249259Sdim 164249259Sdim uint32_t ofdmTrigHigh; 165249259Sdim uint32_t ofdmTrigLow; 166249259Sdim uint32_t cckTrigHigh; 167249259Sdim uint32_t cckTrigLow; 168249259Sdim int32_t rssiThrLow; 169249259Sdim uint32_t rssiThrHigh; 170249259Sdim 171249259Sdim int period; /* update listen period */ 172249259Sdim 173249259Sdim /* NB: intentionally ordered so data exported to user space is first */ 174249259Sdim uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ 175249259Sdim uint32_t cckPhyErrBase; /* Base value for cck err counters */ 176249259Sdim}; 177249259Sdim 178249259Sdim/* 179249259Sdim * Per-channel ANI state private to the driver. 180249259Sdim */ 181249259Sdimstruct ar5212AniState { 182249259Sdim uint8_t noiseImmunityLevel; 183249259Sdim uint8_t spurImmunityLevel; 184249259Sdim uint8_t firstepLevel; 185249259Sdim uint8_t ofdmWeakSigDetectOff; 186249259Sdim uint8_t cckWeakSigThreshold; 187249259Sdim uint32_t listenTime; 188249259Sdim 189249259Sdim /* NB: intentionally ordered so data exported to user space is first */ 190249259Sdim uint32_t txFrameCount; /* Last txFrameCount */ 191249259Sdim uint32_t rxFrameCount; /* Last rx Frame count */ 192249259Sdim uint32_t cycleCount; /* Last cycleCount 193249259Sdim (to detect wrap-around) */ 194249259Sdim uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 195249259Sdim uint32_t cckPhyErrCount; /* CCK err count since last reset */ 196249259Sdim 197249259Sdim const struct ar5212AniParams *params; 198249259Sdim}; 199249259Sdim 200249259Sdim#define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ 201249259Sdim#define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/ 202249259Sdim 203249259Sdimstruct ar5212Stats { 204249259Sdim uint32_t ast_ani_niup; /* ANI increased noise immunity */ 205249259Sdim uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 206249259Sdim uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 207249259Sdim uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 208249259Sdim uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 209249259Sdim uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 210249259Sdim uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 211249259Sdim uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 212249259Sdim uint32_t ast_ani_stepup; /* ANI increased first step level */ 213249259Sdim uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 214249259Sdim uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 215249259Sdim uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 216249259Sdim uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 217249259Sdim uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 218249259Sdim uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 219249259Sdim HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 220249259Sdim HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 221249259Sdim}; 222249259Sdim 223249259Sdim/* 224249259Sdim * NF Cal history buffer 225249259Sdim */ 226249259Sdim#define AR5212_CCA_MAX_GOOD_VALUE -95 227249259Sdim#define AR5212_CCA_MAX_HIGH_VALUE -62 228249259Sdim#define AR5212_CCA_MIN_BAD_VALUE -125 229249259Sdim 230249259Sdim#define AR512_NF_CAL_HIST_MAX 5 231249259Sdim 232249259Sdimstruct ar5212NfCalHist { 233249259Sdim int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; 234249259Sdim int16_t privNF; 235249259Sdim uint8_t currIndex; 236249259Sdim uint8_t first_run; 237249259Sdim uint8_t invalidNFcount; 238249259Sdim}; 239249259Sdim 240249259Sdimstruct ath_hal_5212 { 241249259Sdim struct ath_hal_private ah_priv; /* base class */ 242249259Sdim 243249259Sdim /* 244249259Sdim * Per-chip common Initialization data. 245249259Sdim * NB: RF backends have their own ini data. 246249259Sdim */ 247249259Sdim HAL_INI_ARRAY ah_ini_modes; 248249259Sdim HAL_INI_ARRAY ah_ini_common; 249249259Sdim 250249259Sdim GAIN_VALUES ah_gainValues; 251249259Sdim 252249259Sdim uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 253249259Sdim uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 254249259Sdim uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; 255249259Sdim uint16_t ah_assocId; 256249259Sdim 257249259Sdim /* 258249259Sdim * Runtime state. 259249259Sdim */ 260249259Sdim uint32_t ah_maskReg; /* copy of AR_IMR */ 261249259Sdim struct ar5212Stats ah_stats; /* various statistics */ 262249259Sdim RF_HAL_FUNCS *ah_rfHal; 263249259Sdim uint32_t ah_txDescMask; /* mask for TXDESC */ 264249259Sdim uint32_t ah_txOkInterruptMask; 265249259Sdim uint32_t ah_txErrInterruptMask; 266249259Sdim uint32_t ah_txDescInterruptMask; 267249259Sdim uint32_t ah_txEolInterruptMask; 268249259Sdim uint32_t ah_txUrnInterruptMask; 269249259Sdim HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 270249259Sdim uint32_t ah_intrTxqs; /* tx q interrupt state */ 271249259Sdim /* decomp mask array */ 272249259Sdim uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 273249259Sdim HAL_POWER_MODE ah_powerMode; 274249259Sdim HAL_ANT_SETTING ah_antControl; /* antenna setting */ 275249259Sdim HAL_BOOL ah_diversity; /* fast diversity setting */ 276249259Sdim enum { 277249259Sdim IQ_CAL_INACTIVE, 278249259Sdim IQ_CAL_RUNNING, 279249259Sdim IQ_CAL_DONE 280249259Sdim } ah_bIQCalibration; /* IQ calibrate state */ 281249259Sdim HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ 282249259Sdim uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ 283249259Sdim uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 284249259Sdim uint32_t ah_miscMode; /* MISC_MODE settings */ 285249259Sdim uint32_t ah_rssiThr; /* RSSI_THR settings */ 286249259Sdim HAL_BOOL ah_cwCalRequire; /* for ap51 */ 287249259Sdim HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ 288249259Sdim HAL_BOOL ah_phyPowerOn; /* PHY power state */ 289249259Sdim HAL_BOOL ah_isHb63; /* cached HB63 check */ 290249259Sdim uint32_t ah_macTPC; /* tpc register */ 291249259Sdim uint32_t ah_beaconInterval; /* XXX */ 292249259Sdim enum { 293249259Sdim AUTO_32KHZ, /* use it if 32kHz crystal present */ 294249259Sdim USE_32KHZ, /* do it regardless */ 295249259Sdim DONT_USE_32KHZ, /* don't use it regardless */ 296249259Sdim } ah_enable32kHzClock; /* whether to sleep at 32kHz */ 297249259Sdim uint32_t ah_ofdmTxPower; 298249259Sdim int16_t ah_txPowerIndexOffset; 299249259Sdim /* 300249259Sdim * Noise floor cal histogram support. 301249259Sdim */ 302249259Sdim struct ar5212NfCalHist ah_nfCalHist; 303249259Sdim 304249259Sdim u_int ah_slottime; /* user-specified slot time */ 305249259Sdim u_int ah_acktimeout; /* user-specified ack timeout */ 306249259Sdim u_int ah_ctstimeout; /* user-specified cts timeout */ 307249259Sdim u_int ah_sifstime; /* user-specified sifs time */ 308249259Sdim /* 309249259Sdim * RF Silent handling; setup according to the EEPROM. 310249259Sdim */ 311249259Sdim uint32_t ah_gpioSelect; /* GPIO pin to use */ 312249259Sdim uint32_t ah_polarity; /* polarity to disable RF */ 313249259Sdim uint32_t ah_gpioBit; /* after init, prev value */ 314249259Sdim /* 315249259Sdim * ANI support. 316249259Sdim */ 317249259Sdim uint32_t ah_procPhyErr; /* Process Phy errs */ 318249259Sdim HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ 319249259Sdim struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ 320249259Sdim struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ 321249259Sdim struct ar5212AniState *ah_curani; /* cached last reference */ 322249259Sdim struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */ 323249259Sdim HAL_CHANNEL_SURVEY ah_chansurvey; /* channel survey */ 324249259Sdim 325249259Sdim /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */ 326249259Sdim HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param); 327249259Sdim 328249259Sdim /* 329249259Sdim * Transmit power state. Note these are maintained 330249259Sdim * here so they can be retrieved by diagnostic tools. 331249259Sdim */ 332249259Sdim uint16_t *ah_pcdacTable; 333249259Sdim u_int ah_pcdacTableSize; 334249259Sdim uint16_t ah_ratesArray[37]; 335249259Sdim 336249259Sdim uint8_t ah_txTrigLev; /* current Tx trigger level */ 337249259Sdim uint8_t ah_maxTxTrigLev; /* max tx trigger level */ 338249259Sdim 339249259Sdim /* 340249259Sdim * Channel Tx, Rx, Rx Clear State 341249259Sdim */ 342249259Sdim uint32_t ah_cycleCount; 343249259Sdim uint32_t ah_ctlBusy; 344249259Sdim uint32_t ah_rxBusy; 345249259Sdim uint32_t ah_txBusy; 346249259Sdim uint32_t ah_rx_chainmask; 347249259Sdim uint32_t ah_tx_chainmask; 348249259Sdim}; 349249259Sdim#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 350249259Sdim 351249259Sdim/* 352249259Sdim * IS_XXXX macros test the MAC version 353249259Sdim * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) 354249259Sdim * 355249259Sdim * Some single chip radios have equivalent radio/RF (e.g. 5112) 356249259Sdim * for those use IS_RADXXX_ANY macros. 357249259Sdim */ 358249259Sdim#define IS_2317(ah) \ 359249259Sdim ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ 360249259Sdim (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) 361249259Sdim#define IS_2316(ah) \ 362249259Sdim (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) 363249259Sdim#define IS_2413(ah) \ 364249259Sdim (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) 365249259Sdim#define IS_5424(ah) \ 366249259Sdim (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ 367249259Sdim (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ 368249259Sdim AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) 369249259Sdim#define IS_5413(ah) \ 370249259Sdim (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) 371249259Sdim#define IS_2425(ah) \ 372249259Sdim (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) 373249259Sdim#define IS_2417(ah) \ 374249259Sdim ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) 375249259Sdim#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) 376249259Sdim 377249259Sdim#define AH_RADIO_MAJOR(ah) \ 378249259Sdim (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) 379249259Sdim#define AH_RADIO_MINOR(ah) \ 380249259Sdim (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) 381249259Sdim#define IS_RAD5111(ah) \ 382249259Sdim (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ 383249259Sdim AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) 384249259Sdim#define IS_RAD5112(ah) \ 385249259Sdim (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ 386249259Sdim AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) 387249259Sdim/* NB: does not include 5413 as Atheros' IS_5112 macro does */ 388249259Sdim#define IS_RAD5112_ANY(ah) \ 389249259Sdim (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ 390249259Sdim AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) 391249259Sdim#define IS_RAD5112_REV1(ah) \ 392249259Sdim (IS_RAD5112(ah) && \ 393249259Sdim AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) 394249259Sdim#define IS_RADX112_REV2(ah) \ 395249259Sdim (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ 396249259Sdim AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ 397249259Sdim AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ 398249259Sdim AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) 399249259Sdim 400249259Sdim#define ar5212RfDetach(ah) do { \ 401249259Sdim if (AH5212(ah)->ah_rfHal != AH_NULL) \ 402249259Sdim AH5212(ah)->ah_rfHal->rfDetach(ah); \ 403249259Sdim} while (0) 404249259Sdim#define ar5212GetRfBank(ah, b) \ 405249259Sdim AH5212(ah)->ah_rfHal->getRfBank(ah, b) 406249259Sdim 407249259Sdim/* 408249259Sdim * Hack macros for Nala/San: 11b is handled 409249259Sdim * using 11g; flip the channel flags to accomplish this. 410249259Sdim */ 411249259Sdim#define SAVE_CCK(_ah, _chan, _flag) do { \ 412249259Sdim if ((IS_2425(_ah) || IS_2417(_ah)) && \ 413249259Sdim (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \ 414249259Sdim (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \ 415249259Sdim (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \ 416249259Sdim (_flag) = AH_TRUE; \ 417249259Sdim } else \ 418249259Sdim (_flag) = AH_FALSE; \ 419249259Sdim} while (0) 420249259Sdim#define RESTORE_CCK(_ah, _chan, _flag) do { \ 421249259Sdim if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \ 422249259Sdim (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \ 423249259Sdim (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \ 424249259Sdim } \ 425249259Sdim} while (0) 426249259Sdim 427249259Sdimstruct ath_hal; 428249259Sdim 429249259Sdimextern uint32_t ar5212GetRadioRev(struct ath_hal *ah); 430249259Sdimextern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, 431249259Sdim HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 432249259Sdimextern void ar5212Detach(struct ath_hal *ah); 433249259Sdimextern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); 434249259Sdimextern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, 435249259Sdim uint16_t flags, uint16_t *low, uint16_t *high); 436249259Sdimextern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); 437249259Sdim 438249259Sdimextern void ar5212SetBeaconTimers(struct ath_hal *ah, 439249259Sdim const HAL_BEACON_TIMERS *); 440249259Sdimextern void ar5212BeaconInit(struct ath_hal *ah, 441249259Sdim uint32_t next_beacon, uint32_t beacon_period); 442249259Sdimextern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); 443249259Sdimextern void ar5212SetStaBeaconTimers(struct ath_hal *ah, 444249259Sdim const HAL_BEACON_STATE *); 445249259Sdimextern uint64_t ar5212GetNextTBTT(struct ath_hal *); 446249259Sdim 447249259Sdimextern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); 448249259Sdimextern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); 449249259Sdimextern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); 450249259Sdimextern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); 451249259Sdim 452249259Sdimextern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); 453249259Sdimextern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); 454249259Sdimextern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 455249259Sdimextern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, 456249259Sdim uint16_t entry, const uint8_t *mac); 457249259Sdimextern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 458249259Sdim const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 459249259Sdim 460249259Sdimextern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); 461249259Sdimextern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); 462249259Sdimextern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); 463249259Sdimextern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); 464249259Sdimextern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); 465249259Sdimextern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); 466249259Sdimextern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, 467249259Sdim uint16_t regDomain, HAL_STATUS *stats); 468249259Sdimextern u_int ar5212GetWirelessModes(struct ath_hal *ah); 469249259Sdimextern void ar5212EnableRfKill(struct ath_hal *); 470249259Sdimextern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio, 471249259Sdim HAL_GPIO_MUX_TYPE); 472249259Sdimextern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); 473249259Sdimextern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 474249259Sdimextern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); 475249259Sdimextern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 476249259Sdimextern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 477249259Sdimextern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, 478249259Sdim uint16_t assocId); 479249259Sdimextern uint32_t ar5212GetTsf32(struct ath_hal *ah); 480249259Sdimextern uint64_t ar5212GetTsf64(struct ath_hal *ah); 481249259Sdimextern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64); 482249259Sdimextern void ar5212ResetTsf(struct ath_hal *ah); 483249259Sdimextern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); 484249259Sdimextern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); 485249259Sdimextern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); 486249259Sdimextern void ar5212EnableMibCounters(struct ath_hal *); 487249259Sdimextern void ar5212DisableMibCounters(struct ath_hal *); 488249259Sdimextern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); 489249259Sdimextern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); 490249259Sdimextern uint32_t ar5212GetCurRssi(struct ath_hal *ah); 491249259Sdimextern u_int ar5212GetDefAntenna(struct ath_hal *ah); 492249259Sdimextern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); 493249259Sdimextern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); 494249259Sdimextern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 495249259Sdimextern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); 496249259Sdimextern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); 497249259Sdimextern u_int ar5212GetSifsTime(struct ath_hal *); 498249259Sdimextern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); 499249259Sdimextern u_int ar5212GetSlotTime(struct ath_hal *); 500249259Sdimextern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); 501249259Sdimextern u_int ar5212GetAckTimeout(struct ath_hal *); 502249259Sdimextern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); 503249259Sdimextern u_int ar5212GetAckCTSRate(struct ath_hal *); 504249259Sdimextern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); 505249259Sdimextern u_int ar5212GetCTSTimeout(struct ath_hal *); 506249259Sdimextern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); 507249259Sdimvoid ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); 508249259Sdimextern void ar5212SetPCUConfig(struct ath_hal *); 509249259Sdimextern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); 510249259Sdimextern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); 511249259Sdimextern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); 512249259Sdimextern int16_t ar5212GetNfAdjust(struct ath_hal *, 513249259Sdim const HAL_CHANNEL_INTERNAL *); 514249259Sdimextern void ar5212SetCompRegs(struct ath_hal *ah); 515249259Sdimextern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 516249259Sdim uint32_t, uint32_t *); 517249259Sdimextern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 518249259Sdim uint32_t, uint32_t, HAL_STATUS *); 519249259Sdimextern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, 520249259Sdim const void *args, uint32_t argsize, 521249259Sdim void **result, uint32_t *resultsize); 522249259Sdimextern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period, 523249259Sdim uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag); 524249259Sdimextern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *, 525249259Sdim HAL_SURVEY_SAMPLE *); 526249259Sdimextern void ar5212SetChainMasks(struct ath_hal *, uint32_t, uint32_t); 527249259Sdim 528249259Sdimextern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 529249259Sdim int setChip); 530249259Sdimextern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); 531249259Sdimextern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); 532249259Sdim 533249259Sdimextern uint32_t ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE); 534249259Sdimextern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE); 535249259Sdimextern void ar5212EnableReceive(struct ath_hal *ah); 536249259Sdimextern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); 537249259Sdimextern void ar5212StartPcuReceive(struct ath_hal *ah); 538249259Sdimextern void ar5212StopPcuReceive(struct ath_hal *ah); 539249259Sdimextern void ar5212SetMulticastFilter(struct ath_hal *ah, 540249259Sdim uint32_t filter0, uint32_t filter1); 541249259Sdimextern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); 542249259Sdimextern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); 543249259Sdimextern uint32_t ar5212GetRxFilter(struct ath_hal *ah); 544249259Sdimextern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); 545249259Sdimextern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, 546249259Sdim struct ath_desc *, uint32_t size, u_int flags); 547249259Sdimextern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 548249259Sdim uint32_t, struct ath_desc *, uint64_t, 549249259Sdim struct ath_rx_status *); 550249259Sdim 551249259Sdimextern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 552249259Sdim struct ieee80211_channel *chan, HAL_BOOL bChannelChange, 553249259Sdim HAL_STATUS *status); 554249259Sdimextern HAL_BOOL ar5212SetChannel(struct ath_hal *, 555249259Sdim const struct ieee80211_channel *); 556249259Sdimextern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); 557249259Sdimextern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); 558249259Sdimextern HAL_BOOL ar5212Disable(struct ath_hal *ah); 559249259Sdimextern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, 560249259Sdim const struct ieee80211_channel *); 561249259Sdimextern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, 562249259Sdim struct ieee80211_channel *chan, HAL_BOOL *isIQdone); 563249259Sdimextern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, 564249259Sdim struct ieee80211_channel *chan, u_int chainMask, 565249259Sdim HAL_BOOL longCal, HAL_BOOL *isCalDone); 566249259Sdimextern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, 567249259Sdim const struct ieee80211_channel *); 568249259Sdimextern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); 569249259Sdimextern void ar5212InitNfCalHistBuffer(struct ath_hal *); 570249259Sdimextern int16_t ar5212GetNfHistMid(const int16_t calData[]); 571249259Sdimextern void ar5212SetSpurMitigation(struct ath_hal *, 572249259Sdim const struct ieee80211_channel *); 573249259Sdimextern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, 574249259Sdim HAL_ANT_SETTING settings, const struct ieee80211_channel *); 575249259Sdimextern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 576249259Sdimextern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, 577249259Sdim struct ieee80211_channel *chan); 578249259Sdimextern void ar5212InitializeGainValues(struct ath_hal *); 579249259Sdimextern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); 580249259Sdimextern void ar5212RequestRfgain(struct ath_hal *); 581249259Sdim 582249259Sdimextern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, 583249259Sdim HAL_BOOL IncTrigLevel); 584249259Sdimextern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, 585249259Sdim const HAL_TXQ_INFO *qInfo); 586249259Sdimextern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, 587249259Sdim HAL_TXQ_INFO *qInfo); 588249259Sdimextern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 589249259Sdim const HAL_TXQ_INFO *qInfo); 590249259Sdimextern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); 591249259Sdimextern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); 592249259Sdimextern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); 593249259Sdimextern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); 594249259Sdimextern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); 595249259Sdimextern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); 596249259Sdimextern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); 597249259Sdimextern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 598249259Sdim u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 599249259Sdim u_int txRate0, u_int txTries0, 600249259Sdim u_int keyIx, u_int antMode, u_int flags, 601249259Sdim u_int rtsctsRate, u_int rtsctsDuration, 602249259Sdim u_int compicvLen, u_int compivLen, u_int comp); 603249259Sdimextern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, 604249259Sdim u_int txRate1, u_int txRetries1, 605249259Sdim u_int txRate2, u_int txRetries2, 606249259Sdim u_int txRate3, u_int txRetries3); 607249259Sdimextern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 608249259Sdim HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 609249259Sdim u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 610249259Sdim const struct ath_desc *ds0); 611249259Sdimextern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, 612249259Sdim struct ath_desc *, struct ath_tx_status *); 613249259Sdimextern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 614249259Sdimextern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 615249259Sdimextern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah, 616249259Sdim const struct ath_desc *ds0, int *rates, int *tries); 617249259Sdimextern void ar5212SetTxDescLink(struct ath_hal *ah, void *ds, 618249259Sdim uint32_t link); 619249259Sdimextern void ar5212GetTxDescLink(struct ath_hal *ah, void *ds, 620249259Sdim uint32_t *link); 621249259Sdimextern void ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds, 622249259Sdim uint32_t **linkptr); 623249259Sdim 624249259Sdimextern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); 625249259Sdim 626249259Sdimextern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, 627249259Sdim const struct ar5212AniParams *, HAL_BOOL ena); 628249259Sdimextern void ar5212AniDetach(struct ath_hal *); 629249259Sdimextern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); 630249259Sdimextern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *); 631249259Sdimextern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 632249259Sdimextern HAL_BOOL ar5212AniSetParams(struct ath_hal *, 633249259Sdim const struct ar5212AniParams *, const struct ar5212AniParams *); 634249259Sdimstruct ath_rx_status; 635249259Sdimextern void ar5212AniPhyErrReport(struct ath_hal *ah, 636249259Sdim const struct ath_rx_status *rs); 637249259Sdimextern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 638249259Sdimextern void ar5212RxMonitor(struct ath_hal *, const HAL_NODE_STATS *, 639249259Sdim const struct ieee80211_channel *); 640249259Sdimextern void ar5212AniPoll(struct ath_hal *, const struct ieee80211_channel *); 641249259Sdimextern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *, 642249259Sdim HAL_OPMODE, int); 643249259Sdim 644249259Sdimextern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah); 645249259Sdimextern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i); 646249259Sdimextern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 647249259Sdimextern HAL_BOOL ar5212GetDfsDefaultThresh(struct ath_hal *ah, 648249259Sdim HAL_PHYERR_PARAM *pe); 649249259Sdimextern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 650249259Sdimextern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah, 651249259Sdim struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf, 652249259Sdim HAL_DFS_EVENT *event); 653249259Sdimextern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah); 654249259Sdimextern uint32_t ar5212Get11nExtBusy(struct ath_hal *ah); 655249259Sdim 656249259Sdim#endif /* _ATH_AR5212_H_ */ 657249259Sdim