ar5212.h revision 185521
1240517Sbapt/* 2234949Sbapt * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3234949Sbapt * Copyright (c) 2002-2008 Atheros Communications, Inc. 4234949Sbapt * 5234949Sbapt * Permission to use, copy, modify, and/or distribute this software for any 6234949Sbapt * purpose with or without fee is hereby granted, provided that the above 7234949Sbapt * copyright notice and this permission notice appear in all copies. 8234949Sbapt * 9234949Sbapt * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10234949Sbapt * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11234949Sbapt * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12234949Sbapt * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13234949Sbapt * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14240517Sbapt * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15240517Sbapt * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16240517Sbapt * 17240517Sbapt * $Id: ar5212.h,v 1.16 2008/11/22 07:42:00 sam Exp $ 18234949Sbapt */ 19234949Sbapt#ifndef _ATH_AR5212_H_ 20234949Sbapt#define _ATH_AR5212_H_ 21234949Sbapt 22234949Sbapt#include "ah_eeprom.h" 23234949Sbapt 24234949Sbapt#define AR5212_MAGIC 0x19541014 25234949Sbapt 26234949Sbapt/* DCU Transmit Filter macros */ 27234949Sbapt#define CALC_MMR(dcu, idx) \ 28234949Sbapt ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) ) 29234949Sbapt#define TXBLK_FROM_MMR(mmr) \ 30234949Sbapt (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3)) 31234949Sbapt#define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx))) 32234949Sbapt#define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f)) 33234949Sbapt 34234949Sbapt/* MAC register values */ 35234949Sbapt 36234949Sbapt#define INIT_INTERRUPT_MASK \ 37234949Sbapt ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \ 38234949Sbapt AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \ 39234949Sbapt AR_IMR_HIUERR ) 40234949Sbapt#define INIT_BEACON_CONTROL \ 41234949Sbapt ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \ 42234949Sbapt (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD) 43234949Sbapt 44234949Sbapt#define INIT_CONFIG_STATUS 0x00000000 45234949Sbapt#define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 46234949Sbapt#define INIT_IQCAL_LOG_COUNT_MAX 0xF 47234949Sbapt#define INIT_BCON_CNTRL_REG 0x00000000 48234949Sbapt 49234949Sbapt#define INIT_USEC 40 50234949Sbapt#define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */ 51234949Sbapt#define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */ 52234949Sbapt 53234949Sbapt#define RX_NON_FULL_RATE_LATENCY 63 54234949Sbapt#define TX_HALF_RATE_LATENCY 108 55234949Sbapt#define TX_QUARTER_RATE_LATENCY 216 56234949Sbapt 57234949Sbapt#define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */ 58234949Sbapt#define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */ 59234949Sbapt#define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */ 60234949Sbapt#define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */ 61234949Sbapt#define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */ 62234949Sbapt#define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */ 63234949Sbapt 64234949Sbapt#define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */ 65234949Sbapt 66234949Sbapt/* Tx frame start to tx data start delay */ 67234949Sbapt#define TX_FRAME_D_START_HALF_RATE 0xc 68234949Sbapt#define TX_FRAME_D_START_QUARTER_RATE 0xd 69234949Sbapt 70234949Sbapt/* 71234949Sbapt * Various fifo fill before Tx start, in 64-byte units 72234949Sbapt * i.e. put the frame in the air while still DMAing 73234949Sbapt */ 74234949Sbapt#define MIN_TX_FIFO_THRESHOLD 0x1 75234949Sbapt#define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1) 76234949Sbapt#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 77234949Sbapt 78234949Sbapt#define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */ 79234949Sbapt 80234949Sbapt/* 81234949Sbapt * Gain support. 82234949Sbapt */ 83234949Sbapt#define NUM_CORNER_FIX_BITS 4 84234949Sbapt#define NUM_CORNER_FIX_BITS_5112 7 85234949Sbapt#define DYN_ADJ_UP_MARGIN 15 86234949Sbapt#define DYN_ADJ_LO_MARGIN 20 87234949Sbapt#define PHY_PROBE_CCK_CORRECTION 5 88234949Sbapt#define CCK_OFDM_GAIN_DELTA 15 89234949Sbapt 90234949Sbaptenum GAIN_PARAMS { 91234949Sbapt GP_TXCLIP, 92234949Sbapt GP_PD90, 93234949Sbapt GP_PD84, 94234949Sbapt GP_GSEL, 95234949Sbapt}; 96234949Sbapt 97234949Sbaptenum GAIN_PARAMS_5112 { 98234949Sbapt GP_MIXGAIN_OVR, 99234949Sbapt GP_PWD_138, 100234949Sbapt GP_PWD_137, 101234949Sbapt GP_PWD_136, 102234949Sbapt GP_PWD_132, 103234949Sbapt GP_PWD_131, 104234949Sbapt GP_PWD_130, 105234949Sbapt}; 106234949Sbapt 107234949Sbapttypedef struct _gainOptStep { 108234949Sbapt int16_t paramVal[NUM_CORNER_FIX_BITS_5112]; 109234949Sbapt int32_t stepGain; 110234949Sbapt int8_t stepName[16]; 111234949Sbapt} GAIN_OPTIMIZATION_STEP; 112234949Sbapt 113234949Sbapttypedef struct { 114234949Sbapt uint32_t numStepsInLadder; 115234949Sbapt uint32_t defaultStepNum; 116234949Sbapt GAIN_OPTIMIZATION_STEP optStep[10]; 117234949Sbapt} GAIN_OPTIMIZATION_LADDER; 118234949Sbapt 119234949Sbapttypedef struct { 120234949Sbapt uint32_t currStepNum; 121234949Sbapt uint32_t currGain; 122234949Sbapt uint32_t targetGain; 123234949Sbapt uint32_t loTrig; 124234949Sbapt uint32_t hiTrig; 125234949Sbapt uint32_t gainFCorrection; 126234949Sbapt uint32_t active; 127234949Sbapt const GAIN_OPTIMIZATION_STEP *currStep; 128234949Sbapt} GAIN_VALUES; 129234949Sbapt 130234949Sbapt/* RF HAL structures */ 131234949Sbapttypedef struct RfHalFuncs { 132234949Sbapt void *priv; /* private state */ 133234949Sbapt 134234949Sbapt void (*rfDetach)(struct ath_hal *ah); 135234949Sbapt void (*writeRegs)(struct ath_hal *, 136234949Sbapt u_int modeIndex, u_int freqIndex, int regWrites); 137234949Sbapt uint32_t *(*getRfBank)(struct ath_hal *ah, int bank); 138234949Sbapt HAL_BOOL (*setChannel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 139240517Sbapt HAL_BOOL (*setRfRegs)(struct ath_hal *, 140234949Sbapt HAL_CHANNEL_INTERNAL *, uint16_t modesIndex, 141234949Sbapt uint16_t *rfXpdGain); 142234949Sbapt HAL_BOOL (*setPowerTable)(struct ath_hal *ah, 143240517Sbapt int16_t *minPower, int16_t *maxPower, 144234949Sbapt HAL_CHANNEL_INTERNAL *, uint16_t *rfXpdGain); 145234949Sbapt HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah, HAL_CHANNEL *, 146234949Sbapt int16_t *maxPow, int16_t *minPow); 147234949Sbapt int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*); 148234949Sbapt} RF_HAL_FUNCS; 149234949Sbapt 150234949Sbaptstruct ar5212AniParams { 151234949Sbapt int maxNoiseImmunityLevel; /* [0..4] */ 152234949Sbapt int totalSizeDesired[5]; 153234949Sbapt int coarseHigh[5]; 154234949Sbapt int coarseLow[5]; 155234949Sbapt int firpwr[5]; 156234949Sbapt 157234949Sbapt int maxSpurImmunityLevel; /* [0..7] */ 158234949Sbapt int cycPwrThr1[8]; 159234949Sbapt 160234949Sbapt int maxFirstepLevel; /* [0..2] */ 161234949Sbapt int firstep[3]; 162234949Sbapt 163234949Sbapt uint32_t ofdmTrigHigh; 164234949Sbapt uint32_t ofdmTrigLow; 165234949Sbapt uint32_t cckTrigHigh; 166234949Sbapt uint32_t cckTrigLow; 167234949Sbapt int32_t rssiThrLow; 168234949Sbapt uint32_t rssiThrHigh; 169234949Sbapt 170234949Sbapt int period; /* update listen period */ 171234949Sbapt 172234949Sbapt /* NB: intentionally ordered so data exported to user space is first */ 173234949Sbapt uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */ 174234949Sbapt uint32_t cckPhyErrBase; /* Base value for cck err counters */ 175234949Sbapt}; 176234949Sbapt 177234949Sbapt/* 178234949Sbapt * Per-channel ANI state private to the driver. 179234949Sbapt */ 180234949Sbaptstruct ar5212AniState { 181234949Sbapt uint8_t noiseImmunityLevel; 182234949Sbapt uint8_t spurImmunityLevel; 183234949Sbapt uint8_t firstepLevel; 184234949Sbapt uint8_t ofdmWeakSigDetectOff; 185234949Sbapt uint8_t cckWeakSigThreshold; 186234949Sbapt uint32_t listenTime; 187234949Sbapt 188234949Sbapt /* NB: intentionally ordered so data exported to user space is first */ 189234949Sbapt HAL_CHANNEL c; 190234949Sbapt HAL_BOOL isSetup; /* has state to do a restore */ 191234949Sbapt uint32_t txFrameCount; /* Last txFrameCount */ 192234949Sbapt uint32_t rxFrameCount; /* Last rx Frame count */ 193234949Sbapt uint32_t cycleCount; /* Last cycleCount 194234949Sbapt (to detect wrap-around) */ 195234949Sbapt uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */ 196234949Sbapt uint32_t cckPhyErrCount; /* CCK err count since last reset */ 197234949Sbapt 198234949Sbapt const struct ar5212AniParams *params; 199234949Sbapt}; 200234949Sbapt 201234949Sbapt#define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */ 202234949Sbapt#define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/ 203234949Sbapt 204234949Sbaptstruct ar5212Stats { 205234949Sbapt uint32_t ast_ani_niup; /* ANI increased noise immunity */ 206234949Sbapt uint32_t ast_ani_nidown; /* ANI decreased noise immunity */ 207234949Sbapt uint32_t ast_ani_spurup; /* ANI increased spur immunity */ 208234949Sbapt uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 209234949Sbapt uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 210234949Sbapt uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 211234949Sbapt uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 212234949Sbapt uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 213234949Sbapt uint32_t ast_ani_stepup; /* ANI increased first step level */ 214234949Sbapt uint32_t ast_ani_stepdown;/* ANI decreased first step level */ 215234949Sbapt uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 216234949Sbapt uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 217234949Sbapt uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 218234949Sbapt uint32_t ast_ani_lzero; /* ANI listen time forced to zero */ 219234949Sbapt uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 220234949Sbapt HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 221234949Sbapt HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 222234949Sbapt}; 223234949Sbapt 224234949Sbapt/* 225234949Sbapt * NF Cal history buffer 226234949Sbapt */ 227234949Sbapt#define AR5212_CCA_MAX_GOOD_VALUE -95 228234949Sbapt#define AR5212_CCA_MAX_HIGH_VALUE -62 229234949Sbapt#define AR5212_CCA_MIN_BAD_VALUE -125 230234949Sbapt 231234949Sbapt#define AR512_NF_CAL_HIST_MAX 5 232234949Sbapt 233234949Sbaptstruct ar5212NfCalHist { 234234949Sbapt int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX]; 235234949Sbapt int16_t privNF; 236234949Sbapt uint8_t currIndex; 237234949Sbapt uint8_t first_run; 238234949Sbapt uint8_t invalidNFcount; 239234949Sbapt}; 240234949Sbapt 241234949Sbaptstruct ath_hal_5212 { 242234949Sbapt struct ath_hal_private ah_priv; /* base class */ 243234949Sbapt 244234949Sbapt /* 245234949Sbapt * Per-chip common Initialization data. 246234949Sbapt * NB: RF backends have their own ini data. 247234949Sbapt */ 248234949Sbapt HAL_INI_ARRAY ah_ini_modes; 249234949Sbapt HAL_INI_ARRAY ah_ini_common; 250240517Sbapt 251234949Sbapt GAIN_VALUES ah_gainValues; 252234949Sbapt 253234949Sbapt uint8_t ah_macaddr[IEEE80211_ADDR_LEN]; 254234949Sbapt uint8_t ah_bssid[IEEE80211_ADDR_LEN]; 255234949Sbapt uint8_t ah_bssidmask[IEEE80211_ADDR_LEN]; 256234949Sbapt 257234949Sbapt /* 258234949Sbapt * Runtime state. 259234949Sbapt */ 260234949Sbapt uint32_t ah_maskReg; /* copy of AR_IMR */ 261234949Sbapt struct ar5212Stats ah_stats; /* various statistics */ 262234949Sbapt RF_HAL_FUNCS *ah_rfHal; 263234949Sbapt uint32_t ah_txDescMask; /* mask for TXDESC */ 264234949Sbapt uint32_t ah_txOkInterruptMask; 265234949Sbapt uint32_t ah_txErrInterruptMask; 266234949Sbapt uint32_t ah_txDescInterruptMask; 267234949Sbapt uint32_t ah_txEolInterruptMask; 268234949Sbapt uint32_t ah_txUrnInterruptMask; 269234949Sbapt HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 270234949Sbapt uint32_t ah_intrTxqs; /* tx q interrupt state */ 271234949Sbapt /* decomp mask array */ 272234949Sbapt uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; 273234949Sbapt HAL_POWER_MODE ah_powerMode; 274234949Sbapt HAL_ANT_SETTING ah_antControl; /* antenna setting */ 275234949Sbapt HAL_BOOL ah_diversity; /* fast diversity setting */ 276234949Sbapt enum { 277234949Sbapt IQ_CAL_INACTIVE, 278234949Sbapt IQ_CAL_RUNNING, 279234949Sbapt IQ_CAL_DONE 280234949Sbapt } ah_bIQCalibration; /* IQ calibrate state */ 281234949Sbapt HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */ 282234949Sbapt uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */ 283234949Sbapt uint32_t ah_staId1Defaults; /* STA_ID1 default settings */ 284234949Sbapt uint32_t ah_miscMode; /* MISC_MODE settings */ 285234949Sbapt uint32_t ah_rssiThr; /* RSSI_THR settings */ 286234949Sbapt HAL_BOOL ah_cwCalRequire; /* for ap51 */ 287234949Sbapt HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */ 288234949Sbapt HAL_BOOL ah_phyPowerOn; /* PHY power state */ 289234949Sbapt HAL_BOOL ah_isHb63; /* cached HB63 check */ 290234949Sbapt uint32_t ah_macTPC; /* tpc register */ 291234949Sbapt uint32_t ah_beaconInterval; /* XXX */ 292234949Sbapt enum { 293234949Sbapt AUTO_32KHZ, /* use it if 32kHz crystal present */ 294234949Sbapt USE_32KHZ, /* do it regardless */ 295234949Sbapt DONT_USE_32KHZ, /* don't use it regardless */ 296234949Sbapt } ah_enable32kHzClock; /* whether to sleep at 32kHz */ 297234949Sbapt uint32_t ah_ofdmTxPower; 298234949Sbapt int16_t ah_txPowerIndexOffset; 299234949Sbapt /* 300234949Sbapt * Noise floor cal histogram support. 301234949Sbapt */ 302234949Sbapt struct ar5212NfCalHist ah_nfCalHist; 303234949Sbapt 304234949Sbapt u_int ah_slottime; /* user-specified slot time */ 305234949Sbapt u_int ah_acktimeout; /* user-specified ack timeout */ 306234949Sbapt u_int ah_ctstimeout; /* user-specified cts timeout */ 307234949Sbapt u_int ah_sifstime; /* user-specified sifs time */ 308234949Sbapt /* 309234949Sbapt * RF Silent handling; setup according to the EEPROM. 310234949Sbapt */ 311234949Sbapt uint32_t ah_gpioSelect; /* GPIO pin to use */ 312234949Sbapt uint32_t ah_polarity; /* polarity to disable RF */ 313234949Sbapt uint32_t ah_gpioBit; /* after init, prev value */ 314234949Sbapt /* 315234949Sbapt * ANI support. 316234949Sbapt */ 317234949Sbapt uint32_t ah_procPhyErr; /* Process Phy errs */ 318234949Sbapt HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */ 319234949Sbapt struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */ 320234949Sbapt struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */ 321234949Sbapt struct ar5212AniState *ah_curani; /* cached last reference */ 322234949Sbapt struct ar5212AniState ah_ani[64]; /* per-channel state */ 323234949Sbapt 324234949Sbapt /* 325234949Sbapt * Transmit power state. Note these are maintained 326234949Sbapt * here so they can be retrieved by diagnostic tools. 327234949Sbapt */ 328234949Sbapt uint16_t *ah_pcdacTable; 329234949Sbapt u_int ah_pcdacTableSize; 330234949Sbapt uint16_t ah_ratesArray[16]; 331234949Sbapt}; 332234949Sbapt#define AH5212(_ah) ((struct ath_hal_5212 *)(_ah)) 333234949Sbapt 334234949Sbapt/* 335234949Sbapt * IS_XXXX macros test the MAC version 336234949Sbapt * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G) 337234949Sbapt * 338234949Sbapt * Some single chip radios have equivalent radio/RF (e.g. 5112) 339234949Sbapt * for those use IS_RADXXX_ANY macros. 340234949Sbapt */ 341234949Sbapt#define IS_2317(ah) \ 342234949Sbapt ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \ 343234949Sbapt (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2)) 344234949Sbapt#define IS_2316(ah) \ 345234949Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415) 346234949Sbapt#define IS_2413(ah) \ 347234949Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah)) 348234949Sbapt#define IS_5424(ah) \ 349234949Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \ 350234949Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \ 351240517Sbapt AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS)) 352240517Sbapt#define IS_5413(ah) \ 353240517Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah)) 354240517Sbapt#define IS_2425(ah) \ 355240517Sbapt (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) 356234949Sbapt#define IS_2417(ah) \ 357234949Sbapt ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417) 358240517Sbapt#define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE) 359234949Sbapt 360234949Sbapt#define IS_PCIE(ah) (IS_5424(ah) || IS_2425(ah)) 361240517Sbapt 362240517Sbapt#define AH_RADIO_MAJOR(ah) \ 363240517Sbapt (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) 364234949Sbapt#define AH_RADIO_MINOR(ah) \ 365234949Sbapt (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR) 366240517Sbapt#define IS_RAD5111(ah) \ 367234949Sbapt (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \ 368234949Sbapt AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR) 369234949Sbapt#define IS_RAD5112(ah) \ 370234949Sbapt (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \ 371234949Sbapt AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR) 372234949Sbapt/* NB: does not include 5413 as Atheros' IS_5112 macro does */ 373234949Sbapt#define IS_RAD5112_ANY(ah) \ 374234949Sbapt (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \ 375234949Sbapt AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR) 376234949Sbapt#define IS_RAD5112_REV1(ah) \ 377234949Sbapt (IS_RAD5112(ah) && \ 378234949Sbapt AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR)) 379234949Sbapt#define IS_RADX112_REV2(ah) \ 380234949Sbapt (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \ 381234949Sbapt AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \ 382234949Sbapt AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \ 383234949Sbapt AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1) 384234949Sbapt 385234949Sbapt#define ar5212RfDetach(ah) do { \ 386234949Sbapt if (AH5212(ah)->ah_rfHal != AH_NULL) \ 387234949Sbapt AH5212(ah)->ah_rfHal->rfDetach(ah); \ 388234949Sbapt} while (0) 389234949Sbapt#define ar5212GetRfBank(ah, b) \ 390234949Sbapt AH5212(ah)->ah_rfHal->getRfBank(ah, b) 391234949Sbapt 392234949Sbapt/* 393234949Sbapt * Hack macros for Nala/San: 11b is handled 394234949Sbapt * using 11g; flip the channel flags to accomplish this. 395234949Sbapt */ 396234949Sbapt#define SAVE_CCK(_ah, _chan, _flag) do { \ 397234949Sbapt if ((IS_2425(_ah) || IS_2417(_ah)) && \ 398234949Sbapt (((_chan)->channelFlags) & CHANNEL_CCK)) { \ 399234949Sbapt (_chan)->channelFlags &= ~CHANNEL_CCK; \ 400234949Sbapt (_chan)->channelFlags |= CHANNEL_OFDM; \ 401234949Sbapt (_flag) = AH_TRUE; \ 402234949Sbapt } \ 403234949Sbapt} while (0) 404234949Sbapt#define RESTORE_CCK(_ah, _chan, _flag) do { \ 405234949Sbapt if ((IS_2425(_ah) || IS_2417(_ah)) && (_flag) == AH_TRUE) {\ 406234949Sbapt (_chan)->channelFlags &= ~CHANNEL_OFDM; \ 407234949Sbapt (_chan)->channelFlags |= CHANNEL_CCK; \ 408234949Sbapt } \ 409234949Sbapt} while (0) 410234949Sbapt 411234949Sbaptstruct ath_hal; 412234949Sbapt 413234949Sbaptextern uint32_t ar5212GetRadioRev(struct ath_hal *ah); 414234949Sbaptextern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC, 415234949Sbapt HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status); 416234949Sbaptextern void ar5212Detach(struct ath_hal *ah); 417234949Sbaptextern HAL_BOOL ar5212ChipTest(struct ath_hal *ah); 418234949Sbaptextern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah, 419234949Sbapt uint16_t flags, uint16_t *low, uint16_t *high); 420234949Sbaptextern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah); 421234949Sbapt 422234949Sbaptextern void ar5212SetBeaconTimers(struct ath_hal *ah, 423234949Sbapt const HAL_BEACON_TIMERS *); 424234949Sbaptextern void ar5212BeaconInit(struct ath_hal *ah, 425234949Sbapt uint32_t next_beacon, uint32_t beacon_period); 426234949Sbaptextern void ar5212ResetStaBeaconTimers(struct ath_hal *ah); 427234949Sbaptextern void ar5212SetStaBeaconTimers(struct ath_hal *ah, 428234949Sbapt const HAL_BEACON_STATE *); 429234949Sbapt 430234949Sbaptextern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah); 431234949Sbaptextern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); 432234949Sbaptextern HAL_INT ar5212GetInterrupts(struct ath_hal *ah); 433234949Sbaptextern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints); 434234949Sbapt 435234949Sbaptextern uint32_t ar5212GetKeyCacheSize(struct ath_hal *); 436234949Sbaptextern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry); 437234949Sbaptextern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry); 438234949Sbaptextern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *, 439234949Sbapt uint16_t entry, const uint8_t *mac); 440240517Sbaptextern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, 441234949Sbapt const HAL_KEYVAL *k, const uint8_t *mac, int xorKey); 442234949Sbapt 443234949Sbaptextern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac); 444234949Sbaptextern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *); 445234949Sbaptextern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac); 446234949Sbaptextern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *); 447234949Sbaptextern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data); 448234949Sbaptextern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data); 449234949Sbaptextern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah, 450234949Sbapt uint16_t regDomain, HAL_STATUS *stats); 451234949Sbaptextern u_int ar5212GetWirelessModes(struct ath_hal *ah); 452234949Sbaptextern void ar5212EnableRfKill(struct ath_hal *); 453234949Sbaptextern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio); 454234949Sbaptextern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio); 455extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val); 456extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio); 457extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel); 458extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state); 459extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, 460 uint16_t assocId); 461extern uint32_t ar5212GetTsf32(struct ath_hal *ah); 462extern uint64_t ar5212GetTsf64(struct ath_hal *ah); 463extern void ar5212ResetTsf(struct ath_hal *ah); 464extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet); 465extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah); 466extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah); 467extern void ar5212EnableMibCounters(struct ath_hal *); 468extern void ar5212DisableMibCounters(struct ath_hal *); 469extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats); 470extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah); 471extern uint32_t ar5212GetCurRssi(struct ath_hal *ah); 472extern u_int ar5212GetDefAntenna(struct ath_hal *ah); 473extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna); 474extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *); 475extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING); 476extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah); 477extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int); 478extern u_int ar5212GetSifsTime(struct ath_hal *); 479extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int); 480extern u_int ar5212GetSlotTime(struct ath_hal *); 481extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int); 482extern u_int ar5212GetAckTimeout(struct ath_hal *); 483extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int); 484extern u_int ar5212GetAckCTSRate(struct ath_hal *); 485extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int); 486extern u_int ar5212GetCTSTimeout(struct ath_hal *); 487extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int); 488void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int); 489extern void ar5212SetPCUConfig(struct ath_hal *); 490extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode); 491extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode); 492extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode); 493extern int16_t ar5212GetNfAdjust(struct ath_hal *, 494 const HAL_CHANNEL_INTERNAL *); 495extern void ar5212SetCompRegs(struct ath_hal *ah); 496extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 497 uint32_t, uint32_t *); 498extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, 499 uint32_t, uint32_t, HAL_STATUS *); 500extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request, 501 const void *args, uint32_t argsize, 502 void **result, uint32_t *resultsize); 503 504extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, 505 int setChip); 506extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah); 507extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah); 508 509extern uint32_t ar5212GetRxDP(struct ath_hal *ath); 510extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp); 511extern void ar5212EnableReceive(struct ath_hal *ah); 512extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah); 513extern void ar5212StartPcuReceive(struct ath_hal *ah); 514extern void ar5212StopPcuReceive(struct ath_hal *ah); 515extern void ar5212SetMulticastFilter(struct ath_hal *ah, 516 uint32_t filter0, uint32_t filter1); 517extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix); 518extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix); 519extern uint32_t ar5212GetRxFilter(struct ath_hal *ah); 520extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits); 521extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *, 522 struct ath_desc *, uint32_t size, u_int flags); 523extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *, 524 uint32_t, struct ath_desc *, uint64_t, 525 struct ath_rx_status *); 526 527extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode, 528 HAL_CHANNEL *chan, HAL_BOOL bChannelChange, HAL_STATUS *status); 529extern HAL_BOOL ar5212SetChannel(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 530extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode); 531extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah); 532extern HAL_BOOL ar5212Disable(struct ath_hal *ah); 533extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah, HAL_CHANNEL *); 534extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah, HAL_CHANNEL *chan, 535 HAL_BOOL *isIQdone); 536extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah, HAL_CHANNEL *chan, 537 u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone); 538extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah, HAL_CHANNEL *chan); 539extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah); 540extern void ar5212InitNfCalHistBuffer(struct ath_hal *); 541extern int16_t ar5212GetNfHistMid(const int16_t calData[]); 542extern void ar5212SetSpurMitigation(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 543extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah, 544 HAL_ANT_SETTING settings, const HAL_CHANNEL_INTERNAL *ichan); 545extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit); 546extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah, 547 HAL_CHANNEL *chans, uint32_t nchans); 548extern void ar5212InitializeGainValues(struct ath_hal *); 549extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah); 550extern void ar5212RequestRfgain(struct ath_hal *); 551 552extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *, 553 HAL_BOOL IncTrigLevel); 554extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q, 555 const HAL_TXQ_INFO *qInfo); 556extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q, 557 HAL_TXQ_INFO *qInfo); 558extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type, 559 const HAL_TXQ_INFO *qInfo); 560extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q); 561extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q); 562extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q); 563extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp); 564extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q); 565extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q); 566extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q); 567extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds, 568 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower, 569 u_int txRate0, u_int txTries0, 570 u_int keyIx, u_int antMode, u_int flags, 571 u_int rtsctsRate, u_int rtsctsDuration, 572 u_int compicvLen, u_int compivLen, u_int comp); 573extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *, 574 u_int txRate1, u_int txRetries1, 575 u_int txRate2, u_int txRetries2, 576 u_int txRate3, u_int txRetries3); 577extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds, 578 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, 579 const struct ath_desc *ds0); 580extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah, 581 struct ath_desc *, struct ath_tx_status *); 582extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *); 583extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *); 584 585extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode); 586 587extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *, 588 const struct ar5212AniParams *, HAL_BOOL ena); 589extern void ar5212AniDetach(struct ath_hal *); 590extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *); 591extern struct ar5212Stats *ar5212AniGetCurrentStats(struct ath_hal *); 592extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param); 593extern HAL_BOOL ar5212AniSetParams(struct ath_hal *, 594 const struct ar5212AniParams *, const struct ar5212AniParams *); 595struct ath_rx_status; 596extern void ar5212AniPhyErrReport(struct ath_hal *ah, 597 const struct ath_rx_status *rs); 598extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *); 599extern void ar5212AniPoll(struct ath_hal *, const HAL_NODE_STATS *, 600 HAL_CHANNEL *); 601extern void ar5212AniReset(struct ath_hal *, HAL_CHANNEL_INTERNAL *, 602 HAL_OPMODE, int); 603#endif /* _ATH_AR5212_H_ */ 604