1193323Sed/* 2193323Sed * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3193323Sed * Copyright (c) 2002-2004 Atheros Communications, Inc. 4193323Sed * 5193323Sed * Permission to use, copy, modify, and/or distribute this software for any 6193323Sed * purpose with or without fee is hereby granted, provided that the above 7193323Sed * copyright notice and this permission notice appear in all copies. 8193323Sed * 9193323Sed * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10193323Sed * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11193323Sed * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12193323Sed * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13204961Srdivacky * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14198090Srdivacky * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15193323Sed * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16206274Srdivacky * 17263508Sdim * $FreeBSD: releng/10.2/sys/dev/ath/ath_hal/ar5210/ar5210reg.h 243317 2012-11-19 23:42:46Z adrian $ 18234353Sdim */ 19221345Sdim#ifndef _DEV_ATH_AR5210REG_H 20249423Sdim#define _DEV_ATH_AR5210REG_H 21249423Sdim 22249423Sdim/* 23249423Sdim * Register defintions for the Atheros AR5210/5110 MAC/Basedband 24198090Srdivacky * Processor for IEEE 802.11a 5-GHz Wireless LANs. 25193323Sed */ 26249423Sdim 27249423Sdim#ifndef PCI_VENDOR_ATHEROS 28249423Sdim#define PCI_VENDOR_ATHEROS 0x168c 29249423Sdim#endif 30249423Sdim#define PCI_PRODUCT_ATHEROS_AR5210 0x0007 31249423Sdim#define PCI_PRODUCT_ATHEROS_AR5210_OLD 0x0004 32204961Srdivacky 33198090Srdivacky/* DMA Registers */ 34198090Srdivacky#define AR_TXDP0 0x0000 /* TX queue pointer 0 register */ 35204961Srdivacky#define AR_TXDP1 0x0004 /* TX queue pointer 1 register */ 36207618Srdivacky#define AR_CR 0x0008 /* Command register */ 37198090Srdivacky#define AR_RXDP 0x000c /* RX queue descriptor ptr register */ 38263508Sdim#define AR_CFG 0x0014 /* Configuration and status register */ 39198090Srdivacky#define AR_ISR 0x001c /* Interrupt status register */ 40202878Srdivacky#define AR_IMR 0x0020 /* Interrupt mask register */ 41263508Sdim#define AR_IER 0x0024 /* Interrupt global enable register */ 42249423Sdim#define AR_BCR 0x0028 /* Beacon control register */ 43193323Sed#define AR_BSR 0x002c /* Beacon status register */ 44249423Sdim#define AR_TXCFG 0x0030 /* TX configuration register */ 45249423Sdim#define AR_RXCFG 0x0034 /* RX configuration register */ 46249423Sdim#define AR_MIBC 0x0040 /* MIB control register */ 47249423Sdim#define AR_TOPS 0x0044 /* Timeout prescale register */ 48249423Sdim#define AR_RXNOFRM 0x0048 /* RX no frame timeout register */ 49249423Sdim#define AR_TXNOFRM 0x004c /* TX no frame timeout register */ 50193323Sed#define AR_RPGTO 0x0050 /* RX frame gap timeout register */ 51193323Sed#define AR_RFCNT 0x0054 /* RX frame count limit register */ 52263508Sdim#define AR_MISC 0x0058 /* Misc control and status register */ 53263508Sdim#define AR_RC 0x4000 /* Reset control */ 54263508Sdim#define AR_SCR 0x4004 /* Sleep control */ 55207618Srdivacky#define AR_INTPEND 0x4008 /* Interrupt pending */ 56263508Sdim#define AR_SFR 0x400c /* Force sleep */ 57263508Sdim#define AR_PCICFG 0x4010 /* PCI configuration */ 58263508Sdim#define AR_GPIOCR 0x4014 /* GPIO configuration */ 59263508Sdim#define AR_GPIODO 0x4018 /* GPIO data output */ 60208599Srdivacky#define AR_GPIODI 0x401c /* GPIO data input */ 61263508Sdim#define AR_SREV 0x4020 /* Silicon revision */ 62263508Sdim/* EEPROM Access Registers */ 63263508Sdim#define AR_EP_AIR_BASE 0x6000 /* EEPROM access initiation regs base */ 64263508Sdim#define AR_EP_AIR(n) (AR_EP_AIR_BASE + (n)*4) 65249423Sdim#define AR_EP_RDATA 0x6800 /* EEPROM read data register */ 66263508Sdim#define AR_EP_STA 0x6c00 /* EEPROM access status register */ 67263508Sdim/* PCU Registers */ 68263508Sdim#define AR_STA_ID0 0x8000 /* Lower 32bits of MAC address */ 69263508Sdim#define AR_STA_ID1 0x8004 /* Upper 16bits of MAC address */ 70263508Sdim#define AR_BSS_ID0 0x8008 /* Lower 32bits of BSSID */ 71263508Sdim#define AR_BSS_ID1 0x800c /* Upper 16bits of BSSID */ 72263508Sdim#define AR_SLOT_TIME 0x8010 /* Length of a back-off */ 73263508Sdim#define AR_TIME_OUT 0x8014 /* Timeout to wait for ACK and CTS */ 74263508Sdim#define AR_RSSI_THR 0x8018 /* Beacon RSSI warning threshold */ 75263508Sdim#define AR_RETRY_LMT 0x801c /* Short and long frame retry limit */ 76243830Sdim#define AR_USEC 0x8020 /* Transmit latency */ 77263508Sdim#define AR_BEACON 0x8024 /* Beacon control */ 78263508Sdim#define AR_CFP_PERIOD 0x8028 /* CFP period */ 79263508Sdim#define AR_TIMER0 0x802c /* Next beacon time */ 80263508Sdim#define AR_TIMER1 0x8030 /* Next DMA beacon alert time */ 81263508Sdim#define AR_TIMER2 0x8034 /* Next software beacon alert time */ 82243830Sdim#define AR_TIMER3 0x8038 /* Next ATIM window time */ 83243830Sdim#define AR_IFS0 0x8040 /* Protocol timers */ 84263508Sdim#define AR_IFS1 0x8044 /* Protocol time and control */ 85263508Sdim#define AR_CFP_DUR 0x8048 /* Maximum CFP duration */ 86263508Sdim#define AR_RX_FILTER 0x804c /* Receive filter */ 87263508Sdim#define AR_MCAST_FIL0 0x8050 /* Lower 32bits of mcast filter mask */ 88263508Sdim#define AR_MCAST_FIL1 0x8054 /* Upper 16bits of mcast filter mask */ 89263508Sdim#define AR_TX_MASK0 0x8058 /* Lower 32bits of TX mask */ 90263508Sdim#define AR_TX_MASK1 0x805c /* Upper 16bits of TX mask */ 91234353Sdim#define AR_CLR_TMASK 0x8060 /* Clear TX mask */ 92263508Sdim#define AR_TRIG_LEV 0x8064 /* Minimum FIFO fill level before TX */ 93263508Sdim#define AR_DIAG_SW 0x8068 /* PCU control */ 94263508Sdim#define AR_TSF_L32 0x806c /* Lower 32bits of local clock */ 95263508Sdim#define AR_TSF_U32 0x8070 /* Upper 32bits of local clock */ 96263508Sdim#define AR_LAST_TSTP 0x8080 /* Lower 32bits of last beacon tstamp */ 97263508Sdim#define AR_RETRY_CNT 0x8084 /* Current short or long retry cnt */ 98263508Sdim#define AR_BACKOFF 0x8088 /* Back-off status */ 99243830Sdim#define AR_NAV 0x808c /* Current NAV value */ 100263508Sdim#define AR_RTS_OK 0x8090 /* RTS success counter */ 101263508Sdim#define AR_RTS_FAIL 0x8094 /* RTS failure counter */ 102263508Sdim#define AR_ACK_FAIL 0x8098 /* ACK failure counter */ 103263508Sdim#define AR_FCS_FAIL 0x809c /* FCS failure counter */ 104263508Sdim#define AR_BEACON_CNT 0x80a0 /* Valid beacon counter */ 105263508Sdim#define AR_KEYTABLE_0 0x9000 /* Encryption key table */ 106263508Sdim#define AR_KEYTABLE(n) (AR_KEYTABLE_0 + ((n)*32)) 107249423Sdim 108263508Sdim#define AR_CR_TXE0 0x00000001 /* TX queue 0 enable */ 109263508Sdim#define AR_CR_TXE1 0x00000002 /* TX queue 1 enable */ 110263508Sdim#define AR_CR_RXE 0x00000004 /* RX enable */ 111263508Sdim#define AR_CR_TXD0 0x00000008 /* TX queue 0 disable */ 112251662Sdim#define AR_CR_TXD1 0x00000010 /* TX queue 1 disable */ 113263508Sdim#define AR_CR_RXD 0x00000020 /* RX disable */ 114263508Sdim#define AR_CR_SWI 0x00000040 /* software interrupt */ 115207618Srdivacky#define AR_CR_BITS \ 116193323Sed "\20\1TXE0\2TXE1\3RXE\4TXD0\5TXD1\6RXD\7SWI" 117193323Sed 118249423Sdim#define AR_CFG_SWTD 0x00000001 /* BE for TX desc */ 119249423Sdim#define AR_CFG_SWTB 0x00000002 /* BE for TX data */ 120193323Sed#define AR_CFG_SWRD 0x00000004 /* BE for RX desc */ 121193323Sed#define AR_CFG_SWRB 0x00000008 /* BE for RX data */ 122193323Sed#define AR_CFG_SWRG 0x00000010 /* BE for registers */ 123193323Sed#define AR_CFG_EEBS 0x00000200 /* EEPROM busy */ 124263508Sdim#define AR_CFG_TXCNT 0x00007800 /* number of TX desc in Q */ 125263508Sdim#define AR_CFG_TXCNT_S 11 126263508Sdim#define AR_CFG_TXFSTAT 0x00008000 /* TX DMA status */ 127263508Sdim#define AR_CFG_TXFSTRT 0x00010000 /* re-enable TX DMA */ 128263508Sdim#define AR_CFG_BITS \ 129263508Sdim "\20\1SWTD\2SWTB\3SWRD\4SWRB\5SWRG\14EEBS\17TXFSTAT\20TXFSTRT" 130263508Sdim 131226633Sdim#define AR_ISR_RXOK_INT 0x00000001 /* RX frame OK */ 132221345Sdim#define AR_ISR_RXDESC_INT 0x00000002 /* RX intr request */ 133221345Sdim#define AR_ISR_RXERR_INT 0x00000004 /* RX error */ 134221345Sdim#define AR_ISR_RXNOFRM_INT 0x00000008 /* no frame received */ 135221345Sdim#define AR_ISR_RXEOL_INT 0x00000010 /* RX desc empty */ 136221345Sdim#define AR_ISR_RXORN_INT 0x00000020 /* RX fifo overrun */ 137221345Sdim#define AR_ISR_TXOK_INT 0x00000040 /* TX frame OK */ 138221345Sdim#define AR_ISR_TXDESC_INT 0x00000080 /* TX intr request */ 139221345Sdim#define AR_ISR_TXERR_INT 0x00000100 /* TX error */ 140221345Sdim#define AR_ISR_TXNOFRM_INT 0x00000200 /* no frame transmitted */ 141221345Sdim#define AR_ISR_TXEOL_INT 0x00000400 /* TX desc empty */ 142249423Sdim#define AR_ISR_TXURN_INT 0x00000800 /* TX fifo underrun */ 143221345Sdim#define AR_ISR_MIB_INT 0x00001000 /* MIB interrupt */ 144221345Sdim#define AR_ISR_SWI_INT 0x00002000 /* software interrupt */ 145249423Sdim#define AR_ISR_RXPHY_INT 0x00004000 /* PHY RX error */ 146221345Sdim#define AR_ISR_RXKCM_INT 0x00008000 /* Key cache miss */ 147221345Sdim#define AR_ISR_SWBA_INT 0x00010000 /* software beacon alert */ 148221345Sdim#define AR_ISR_BRSSI_INT 0x00020000 /* beacon threshold */ 149221345Sdim#define AR_ISR_BMISS_INT 0x00040000 /* beacon missed */ 150221345Sdim#define AR_ISR_MCABT_INT 0x00100000 /* master cycle abort */ 151249423Sdim#define AR_ISR_SSERR_INT 0x00200000 /* SERR on PCI */ 152221345Sdim#define AR_ISR_DPERR_INT 0x00400000 /* Parity error on PCI */ 153221345Sdim#define AR_ISR_GPIO_INT 0x01000000 /* GPIO interrupt */ 154249423Sdim#define AR_ISR_BITS \ 155221345Sdim "\20\1RXOK\2RXDESC\3RXERR\4RXNOFM\5RXEOL\6RXORN\7TXOK\10TXDESC"\ 156221345Sdim "\11TXERR\12TXNOFRM\13TXEOL\14TXURN\15MIB\16SWI\17RXPHY\20RXKCM"\ 157221345Sdim "\21SWBA\22BRSSI\23BMISS\24MCABT\25SSERR\26DPERR\27GPIO" 158221345Sdim 159221345Sdim#define AR_IMR_RXOK_INT 0x00000001 /* RX frame OK */ 160221345Sdim#define AR_IMR_RXDESC_INT 0x00000002 /* RX intr request */ 161263508Sdim#define AR_IMR_RXERR_INT 0x00000004 /* RX error */ 162249423Sdim#define AR_IMR_RXNOFRM_INT 0x00000008 /* no frame received */ 163263508Sdim#define AR_IMR_RXEOL_INT 0x00000010 /* RX desc empty */ 164263508Sdim#define AR_IMR_RXORN_INT 0x00000020 /* RX fifo overrun */ 165249423Sdim#define AR_IMR_TXOK_INT 0x00000040 /* TX frame OK */ 166263508Sdim#define AR_IMR_TXDESC_INT 0x00000080 /* TX intr request */ 167221345Sdim#define AR_IMR_TXERR_INT 0x00000100 /* TX error */ 168263508Sdim#define AR_IMR_TXNOFRM_INT 0x00000200 /* no frame transmitted */ 169221345Sdim#define AR_IMR_TXEOL_INT 0x00000400 /* TX desc empty */ 170263508Sdim#define AR_IMR_TXURN_INT 0x00000800 /* TX fifo underrun */ 171221345Sdim#define AR_IMR_MIB_INT 0x00001000 /* MIB interrupt */ 172212904Sdim#define AR_IMR_SWI_INT 0x00002000 /* software interrupt */ 173221345Sdim#define AR_IMR_RXPHY_INT 0x00004000 /* PHY RX error */ 174221345Sdim#define AR_IMR_RXKCM_INT 0x00008000 /* Key cache miss */ 175193323Sed#define AR_IMR_SWBA_INT 0x00010000 /* software beacon alert */ 176206274Srdivacky#define AR_IMR_BRSSI_INT 0x00020000 /* beacon threshold */ 177193323Sed#define AR_IMR_BMISS_INT 0x00040000 /* beacon missed */ 178263508Sdim#define AR_IMR_MCABT_INT 0x00100000 /* master cycle abort */ 179263508Sdim#define AR_IMR_SSERR_INT 0x00200000 /* SERR on PCI */ 180263508Sdim#define AR_IMR_DPERR_INT 0x00400000 /* Parity error on PCI */ 181263508Sdim#define AR_IMR_GPIO_INT 0x01000000 /* GPIO interrupt */ 182263508Sdim#define AR_IMR_BITS AR_ISR_BITS 183263508Sdim 184263508Sdim#define AR_IER_DISABLE 0x00000000 /* pseudo-flag */ 185263508Sdim#define AR_IER_ENABLE 0x00000001 /* global interrupt enable */ 186206274Srdivacky#define AR_IER_BITS "\20\1ENABLE" 187208599Srdivacky 188212904Sdim#define AR_BCR_BCMD 0x00000001 /* ad hoc beacon mode */ 189249423Sdim#define AR_BCR_BDMAE 0x00000002 /* beacon DMA enable */ 190249423Sdim#define AR_BCR_TQ1FV 0x00000004 /* use TXQ1 for non-beacon */ 191263508Sdim#define AR_BCR_TQ1V 0x00000008 /* TXQ1 valid for beacon */ 192249423Sdim#define AR_BCR_BCGET 0x00000010 /* force a beacon fetch */ 193249423Sdim#define AR_BCR_BITS "\20\1BCMD\2BDMAE\3TQ1FV\4TQ1V\5BCGET" 194263508Sdim 195249423Sdim#define AR_BSR_BDLYSW 0x00000001 /* software beacon delay */ 196212904Sdim#define AR_BSR_BDLYDMA 0x00000002 /* DMA beacon delay */ 197223017Sdim#define AR_BSR_TXQ1F 0x00000004 /* TXQ1 fetch */ 198206274Srdivacky#define AR_BSR_ATIMDLY 0x00000008 /* ATIM delay */ 199249423Sdim#define AR_BSR_SNPBCMD 0x00000100 /* snapshot of BCMD */ 200251662Sdim#define AR_BSR_SNPBDMAE 0x00000200 /* snapshot of BDMAE */ 201249423Sdim#define AR_BSR_SNPTQ1FV 0x00000400 /* snapshot of TQ1FV */ 202208599Srdivacky#define AR_BSR_SNPTQ1V 0x00000800 /* snapshot of TQ1V */ 203234353Sdim#define AR_BSR_SNAPPEDBCRVALID 0x00001000 /* snapshot of BCR are valid */ 204263508Sdim#define AR_BSR_SWBA_CNT 0x00ff0000 /* software beacon alert cnt */ 205263508Sdim#define AR_BSR_BITS \ 206251662Sdim "\20\1BDLYSW\2BDLYDMA\3TXQ1F\4ATIMDLY\11SNPBCMD\12SNPBDMAE"\ 207243830Sdim "\13SNPTQ1FV\14SNPTQ1V\15SNAPPEDBCRVALID" 208263508Sdim 209263508Sdim#define AR_TXCFG_SDMAMR 0x00000007 /* DMA burst size 2^(2+x) */ 210263508Sdim#define AR_TXCFG_TXFSTP 0x00000008 /* Stop TX DMA on filtered */ 211263508Sdim#define AR_TXCFG_TXFULL 0x00000070 /* TX DMA desc Q full thresh */ 212243830Sdim#define AR_TXCFG_TXCONT_EN 0x00000080 /* Enable continuous TX mode */ 213249423Sdim#define AR_TXCFG_BITS "\20\3TXFSTP\7TXCONT_EN" 214249423Sdim 215249423Sdim#define AR_RXCFG_SDMAMW 0x00000007 /* DMA burst size 2^(2+x) */ 216263508Sdim#define AR_RXCFG_ZLFDMA 0x00000010 /* enable zero length DMA */ 217249423Sdim 218263508Sdim/* DMA sizes used for both AR_TXCFG_SDMAMR and AR_RXCFG_SDMAMW */ 219263508Sdim#define AR_DMASIZE_4B 0 /* DMA size 4 bytes */ 220263508Sdim#define AR_DMASIZE_8B 1 /* DMA size 8 bytes */ 221263508Sdim#define AR_DMASIZE_16B 2 /* DMA size 16 bytes */ 222263508Sdim#define AR_DMASIZE_32B 3 /* DMA size 32 bytes */ 223263508Sdim#define AR_DMASIZE_64B 4 /* DMA size 64 bytes */ 224263508Sdim#define AR_DMASIZE_128B 5 /* DMA size 128 bytes */ 225263508Sdim#define AR_DMASIZE_256B 6 /* DMA size 256 bytes */ 226263508Sdim#define AR_DMASIZE_512B 7 /* DMA size 512 bytes */ 227210299Sed 228210299Sed#define AR_MIBC_COW 0x00000001 /* counter overflow warning */ 229249423Sdim#define AR_MIBC_FMC 0x00000002 /* freeze MIB counters */ 230207618Srdivacky#define AR_MIBC_CMC 0x00000004 /* clear MIB counters */ 231193323Sed#define AR_MIBC_MCS 0x00000008 /* MIB counter strobe */ 232193323Sed 233249423Sdim#define AR_RFCNT_RFCL 0x0000000f /* RX frame count limit */ 234249423Sdim 235249423Sdim#define AR_MISC_LED_DECAY 0x001c0000 /* LED decay rate */ 236234353Sdim#define AR_MISC_LED_BLINK 0x00e00000 /* LED blink rate */ 237234353Sdim 238234353Sdim#define AR_RC_RPCU 0x00000001 /* PCU Warm Reset */ 239234353Sdim#define AR_RC_RDMA 0x00000002 /* DMA Warm Reset */ 240234353Sdim#define AR_RC_RMAC 0x00000004 /* MAC Warm Reset */ 241234353Sdim#define AR_RC_RPHY 0x00000008 /* PHY Warm Reset */ 242234353Sdim#define AR_RC_RPCI 0x00000010 /* PCI Core Warm Reset */ 243234353Sdim#define AR_RC_BITS "\20\1RPCU\2RDMA\3RMAC\4RPHY\5RPCI" 244234353Sdim 245249423Sdim#define AR_SCR_SLDUR 0x0000ffff /* sleep duration */ 246249423Sdim#define AR_SCR_SLE 0x00030000 /* sleep enable */ 247234353Sdim#define AR_SCR_SLE_S 16 248234353Sdim/* 249249423Sdim * The previous values for the following three defines were: 250249423Sdim * 251249423Sdim * AR_SCR_SLE_WAKE 0x00000000 252205218Srdivacky * AR_SCR_SLE_SLP 0x00010000 253205218Srdivacky * AR_SCR_SLE_ALLOW 0x00020000 254205218Srdivacky * 255249423Sdim * However, these have been pre-shifted with AR_SCR_SLE_S. The 256205218Srdivacky * OS_REG_READ() macro would attempt to shift them again, effectively 257205218Srdivacky * shifting out any of the set bits completely. 258249423Sdim */ 259249423Sdim#define AR_SCR_SLE_WAKE 0 /* force wake */ 260249423Sdim#define AR_SCR_SLE_SLP 1 /* force sleep */ 261249423Sdim#define AR_SCR_SLE_ALLOW 2 /* allow to control sleep */ 262249423Sdim#define AR_SCR_BITS "\20\20SLE_SLP\21SLE_ALLOW" 263249423Sdim 264249423Sdim#define AR_INTPEND_IP 0x00000001 /* interrupt pending */ 265249423Sdim#define AR_INTPEND_BITS "\20\1IP" 266249423Sdim 267249423Sdim#define AR_SFR_SF 0x00000001 /* force sleep immediately */ 268263508Sdim 269263508Sdim#define AR_PCICFG_EEPROMSEL 0x00000001 /* EEPROM access enable */ 270263508Sdim#define AR_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable */ 271249423Sdim#define AR_PCICFG_LED_PEND 0x00000020 /* LED for assoc pending */ 272263508Sdim#define AR_PCICFG_LED_ACT 0x00000040 /* LED for assoc active */ 273263508Sdim#define AR_PCICFG_SL_INTEN 0x00000800 /* Enable sleep intr */ 274263508Sdim#define AR_PCICFG_LED_BCTL 0x00001000 /* LED blink for local act */ 275263508Sdim#define AR_PCICFG_SL_INPEN 0x00002800 /* sleep even intr pending */ 276263508Sdim#define AR_PCICFG_SPWR_DN 0x00010000 /* sleep indication */ 277263508Sdim#define AR_PCICFG_BITS \ 278249423Sdim "\20\1EEPROMSEL\3CLKRUNEN\5LED_PEND\6LED_ACT\13SL_INTEN"\ 279249423Sdim "\14LED_BCTL\20SPWR_DN" 280249423Sdim 281249423Sdim#define AR_GPIOCR_IN(n) (0<<((n)*2)) /* input-only */ 282249423Sdim#define AR_GPIOCR_OUT0(n) (1<<((n)*2)) /* output-only if GPIODO = 0 */ 283193323Sed#define AR_GPIOCR_OUT1(n) (2<<((n)*2)) /* output-only if GPIODO = 1 */ 284249423Sdim#define AR_GPIOCR_OUT(n) (3<<((n)*2)) /* always output */ 285193323Sed#define AR_GPIOCR_ALL(n) (3<<((n)*2)) /* all bits for pin */ 286193323Sed#define AR_GPIOCR_INT_SEL(n) ((n)<<12) /* GPIO interrupt pin select */ 287193323Sed#define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ 288193323Sed#define AR_GPIOCR_INT_SELL 0x00000000 /* Interrupt if pin is low */ 289263508Sdim#define AR_GPIOCR_INT_SELH 0x00010000 /* Interrupt if pin is high */ 290193323Sed 291193323Sed#define AR_SREV_CRETE 4 /* Crete 1st version */ 292263508Sdim#define AR_SREV_CRETE_MS 5 /* Crete FCS version */ 293193323Sed#define AR_SREV_CRETE_23 8 /* Crete version 2.3 */ 294193323Sed 295193323Sed#define AR_EP_STA_RDERR 0x00000001 /* read error */ 296193323Sed#define AR_EP_STA_RDCMPLT 0x00000002 /* read complete */ 297193323Sed#define AR_EP_STA_WRERR 0x00000004 /* write error */ 298193323Sed#define AR_EP_STA_WRCMPLT 0x00000008 /* write complete */ 299234353Sdim#define AR_EP_STA_BITS \ 300234353Sdim "\20\1RDERR\2RDCMPLT\3WRERR\4WRCMPLT" 301234353Sdim 302234353Sdim#define AR_STA_ID1_AP 0x00010000 /* Access Point Operation */ 303234353Sdim#define AR_STA_ID1_ADHOC 0x00020000 /* ad hoc Operation */ 304234353Sdim#define AR_STA_ID1_PWR_SV 0x00040000 /* power save report enable */ 305234353Sdim#define AR_STA_ID1_NO_KEYSRCH 0x00080000 /* key table search disable */ 306263508Sdim#define AR_STA_ID1_NO_PSPOLL 0x00100000 /* auto PS-POLL disable */ 307234353Sdim#define AR_STA_ID1_PCF 0x00200000 /* PCF observation enable */ 308234353Sdim#define AR_STA_ID1_DESC_ANTENNA 0x00400000 /* use antenna in TX desc */ 309234353Sdim#define AR_STA_ID1_DEFAULT_ANTENNA 0x00800000 /* toggle default antenna */ 310234353Sdim#define AR_STA_ID1_ACKCTS_6MB 0x01000000 /* use 6Mbps for ACK/CTS */ 311234353Sdim#define AR_STA_ID1_BITS \ 312234353Sdim "\20\20AP\21ADHOC\22PWR_SV\23NO_KEYSRCH\24NO_PSPOLL\25PCF"\ 313234353Sdim "\26DESC_ANTENNA\27DEFAULT_ANTENNA\30ACKCTS_6MB" 314234353Sdim 315234353Sdim#define AR_BSS_ID1_AID 0xffff0000 /* association ID */ 316234353Sdim#define AR_BSS_ID1_AID_S 16 317234353Sdim 318234353Sdim#define AR_TIME_OUT_ACK 0x00001fff /* ACK timeout */ 319234353Sdim#define AR_TIME_OUT_ACK_S 0 320234353Sdim#define AR_TIME_OUT_CTS 0x1fff0000 /* CTS timeout */ 321234353Sdim#define AR_TIME_OUT_CTS_S 16 322234353Sdim 323234353Sdim#define AR_RSSI_THR_BM_THR 0x00000700 /* missed beacon threshold */ 324234353Sdim#define AR_RSSI_THR_BM_THR_S 8 325234353Sdim 326263508Sdim#define AR_RETRY_LMT_SH_RETRY 0x0000000f /* short frame retry limit */ 327263508Sdim#define AR_RETRY_LMT_SH_RETRY_S 0 328263508Sdim#define AR_RETRY_LMT_LG_RETRY 0x000000f0 /* long frame retry limit */ 329263508Sdim#define AR_RETRY_LMT_LG_RETRY_S 4 330263508Sdim#define AR_RETRY_LMT_SSH_RETRY 0x00003f00 /* short station retry limit */ 331263508Sdim#define AR_RETRY_LMT_SSH_RETRY_S 8 332263508Sdim#define AR_RETRY_LMT_SLG_RETRY 0x000fc000 /* long station retry limit */ 333234353Sdim#define AR_RETRY_LMT_SLG_RETRY_S 14 334263508Sdim#define AR_RETRY_LMT_CW_MIN 0x3ff00000 /* minimum contention window */ 335263508Sdim#define AR_RETRY_LMT_CW_MIN_S 20 336263508Sdim 337234353Sdim#define AR_USEC_1 0x0000007f /* number of clk in 1us */ 338234353Sdim#define AR_USEC_1_S 0 339234353Sdim#define AR_USEC_32 0x00003f80 /* number of 32MHz clk in 1us */ 340234353Sdim#define AR_USEC_32_S 7 341234353Sdim#define AR_USEC_TX_LATENCY 0x000fc000 /* transmit latency in us */ 342234353Sdim#define AR_USEC_TX_LATENCY_S 14 343234353Sdim#define AR_USEC_RX_LATENCY 0x03f00000 /* receive latency in us */ 344234353Sdim#define AR_USEC_RX_LATENCY_S 20 345234353Sdim 346234353Sdim#define AR_BEACON_PERIOD 0x0000ffff /* beacon period in TU/ms */ 347234353Sdim#define AR_BEACON_PERIOD_S 0 348234353Sdim#define AR_BEACON_TIM 0x007f0000 /* byte offset */ 349234353Sdim#define AR_BEACON_TIM_S 16 350234353Sdim#define AR_BEACON_EN 0x00800000 /* beacon transmission enable */ 351234353Sdim#define AR_BEACON_RESET_TSF 0x01000000 /* TSF reset oneshot */ 352234353Sdim#define AR_BEACON_BITS "\20\27ENABLE\30RESET_TSF" 353234353Sdim 354234353Sdim#define AR_IFS0_SIFS 0x000007ff /* SIFS in core clock cycles */ 355234353Sdim#define AR_IFS0_SIFS_S 0 356234353Sdim#define AR_IFS0_DIFS 0x007ff800 /* DIFS in core clock cycles */ 357234353Sdim#define AR_IFS0_DIFS_S 11 358234353Sdim 359234353Sdim#define AR_IFS1_PIFS 0x00000fff /* Programmable IFS */ 360263508Sdim#define AR_IFS1_PIFS_S 0 361263508Sdim#define AR_IFS1_EIFS 0x03fff000 /* EIFS in core clock cycles */ 362263508Sdim#define AR_IFS1_EIFS_S 12 363263508Sdim#define AR_IFS1_CS_EN 0x04000000 /* carrier sense enable */ 364263508Sdim 365263508Sdim#define AR_RX_FILTER_UNICAST 0x00000001 /* unicast frame enable */ 366263508Sdim#define AR_RX_FILTER_MULTICAST 0x00000002 /* multicast frame enable */ 367263508Sdim#define AR_RX_FILTER_BROADCAST 0x00000004 /* broadcast frame enable */ 368263508Sdim#define AR_RX_FILTER_CONTROL 0x00000008 /* control frame enable */ 369263508Sdim#define AR_RX_FILTER_BEACON 0x00000010 /* beacon frame enable */ 370263508Sdim#define AR_RX_FILTER_PROMISCUOUS 0x00000020 /* promiscuous receive enable */ 371263508Sdim#define AR_RX_FILTER_BITS \ 372263508Sdim "\20\1UCAST\2MCAST\3BCAST\4CONTROL\5BEACON\6PROMISC" 373249423Sdim 374249423Sdim#define AR_DIAG_SW_DIS_WEP_ACK 0x00000001 /* disable ACK if no key found*/ 375249423Sdim#define AR_DIAG_SW_DIS_ACK 0x00000002 /* disable ACK generation */ 376263508Sdim#define AR_DIAG_SW_DIS_CTS 0x00000004 /* disable CTS generation */ 377263508Sdim#define AR_DIAG_SW_DIS_ENC 0x00000008 /* encryption disable */ 378210299Sed#define AR_DIAG_SW_DIS_DEC 0x00000010 /* decryption disable */ 379206274Srdivacky#define AR_DIAG_SW_DIS_TX 0x00000020 /* TX disable */ 380212904Sdim#define AR_DIAG_SW_DIS_RX 0x00000040 /* RX disable */ 381243830Sdim#define AR_DIAG_SW_LOOP_BACK 0x00000080 /* TX data loopback enable */ 382243830Sdim#define AR_DIAG_SW_CORR_FCS 0x00000100 /* corrupt FCS enable */ 383243830Sdim#define AR_DIAG_SW_CHAN_INFO 0x00000200 /* channel information enable */ 384263508Sdim#define AR_DIAG_SW_EN_SCRAM_SEED 0x00000400 /* use fixed scrambler seed */ 385243830Sdim#define AR_DIAG_SW_SCVRAM_SEED 0x0003f800 /* fixed scrambler seed */ 386263508Sdim#define AR_DIAG_SW_DIS_SEQ_INC 0x00040000 /* seq increment disable */ 387263508Sdim#define AR_DIAG_SW_FRAME_NV0 0x00080000 /* accept frame vers != 0 */ 388243830Sdim#define AR_DIAG_SW_DIS_CRYPTO (AR_DIAG_SW_DIS_ENC | AR_DIAG_SW_DIS_DEC) 389243830Sdim#define AR_DIAG_SW_BITS \ 390243830Sdim "\20\1DIS_WEP_ACK\2DIS_ACK\3DIS_CTS\4DIS_ENC\5DIS_DEC\6DIS_TX"\ 391243830Sdim "\7DIS_RX\10LOOP_BACK\11CORR_FCS\12CHAN_INFO\13EN_SCRAM_SEED"\ 392243830Sdim "\22DIS_SEQ_INC\24FRAME_NV0" 393243830Sdim 394243830Sdim#define AR_RETRY_CNT_SSH 0x0000003f /* current short retry count */ 395243830Sdim#define AR_RETRY_CNT_SLG 0x00000fc0 /* current long retry count */ 396263508Sdim 397263508Sdim#define AR_BACKOFF_CW 0x000003ff /* current contention window */ 398263508Sdim#define AR_BACKOFF_CNT 0x03ff0000 /* backoff count */ 399263508Sdim 400243830Sdim#define AR_KEYTABLE_KEY0(n) (AR_KEYTABLE(n) + 0) /* key bit 0-31 */ 401243830Sdim#define AR_KEYTABLE_KEY1(n) (AR_KEYTABLE(n) + 4) /* key bit 32-47 */ 402243830Sdim#define AR_KEYTABLE_KEY2(n) (AR_KEYTABLE(n) + 8) /* key bit 48-79 */ 403243830Sdim#define AR_KEYTABLE_KEY3(n) (AR_KEYTABLE(n) + 12) /* key bit 80-95 */ 404243830Sdim#define AR_KEYTABLE_KEY4(n) (AR_KEYTABLE(n) + 16) /* key bit 96-127 */ 405263508Sdim#define AR_KEYTABLE_TYPE(n) (AR_KEYTABLE(n) + 20) /* key type */ 406243830Sdim#define AR_KEYTABLE_TYPE_40 0x00000000 /* 40 bit key */ 407269000Semaste#define AR_KEYTABLE_TYPE_104 0x00000001 /* 104 bit key */ 408243830Sdim#define AR_KEYTABLE_TYPE_128 0x00000003 /* 128 bit key */ 409269000Semaste#define AR_KEYTABLE_MAC0(n) (AR_KEYTABLE(n) + 24) /* MAC address 1-32 */ 410269000Semaste#define AR_KEYTABLE_MAC1(n) (AR_KEYTABLE(n) + 28) /* MAC address 33-47 */ 411269000Semaste#define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ 412269000Semaste 413269000Semaste#endif /* _DEV_ATH_AR5210REG_H */ 414269000Semaste