ah_desc.h revision 250346
1189251Ssam/* 2189251Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3189251Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4189251Ssam * 5189251Ssam * Permission to use, copy, modify, and/or distribute this software for any 6189251Ssam * purpose with or without fee is hereby granted, provided that the above 7189251Ssam * copyright notice and this permission notice appear in all copies. 8189251Ssam * 9189251Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10189251Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11189251Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12189251Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13189251Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14189251Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15189251Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16189251Ssam * 17189251Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ah_desc.h 250346 2013-05-08 01:11:25Z adrian $ 18189251Ssam */ 19189251Ssam 20189251Ssam#ifndef _DEV_ATH_DESC_H 21189251Ssam#define _DEV_ATH_DESC_H 22189251Ssam 23189251Ssam#include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */ 24189251Ssam 25189251Ssam/* 26189251Ssam * For now, define this for the structure definitions. 27189251Ssam * Because of how the HAL / driver module currently builds, 28189251Ssam * it's not very feasible to build the module without 29189251Ssam * this defined. The rest of the code (eg in the driver 30189251Ssam * body) can work fine with these fields being uninitialised; 31189251Ssam * they'll be initialised to 0 anyway. 32189251Ssam */ 33189251Ssam 34189251Ssam#ifndef AH_SUPPORT_AR5416 35189251Ssam#define AH_SUPPORT_AR5416 1 36189251Ssam#endif 37189251Ssam 38189251Ssam/* 39189251Ssam * Transmit descriptor status. This structure is filled 40189251Ssam * in only after the tx descriptor process method finds a 41189251Ssam * ``done'' descriptor; at which point it returns something 42189251Ssam * other than HAL_EINPROGRESS. 43189251Ssam * 44189251Ssam * Note that ts_antenna may not be valid for all h/w. It 45189251Ssam * should be used only if non-zero. 46189251Ssam */ 47189251Ssamstruct ath_tx_status { 48189251Ssam uint16_t ts_seqnum; /* h/w assigned sequence number */ 49189251Ssam uint16_t ts_tstamp; /* h/w assigned timestamp */ 50189251Ssam uint8_t ts_status; /* frame status, 0 => xmit ok */ 51189251Ssam uint8_t ts_rate; /* h/w transmit rate index */ 52189251Ssam int8_t ts_rssi; /* tx ack RSSI */ 53189251Ssam uint8_t ts_shortretry; /* # short retries */ 54189251Ssam uint8_t ts_longretry; /* # long retries */ 55189251Ssam uint8_t ts_virtcol; /* virtual collision count */ 56189251Ssam uint8_t ts_antenna; /* antenna information */ 57189251Ssam uint8_t ts_finaltsi; /* final transmit series index */ 58189251Ssam#ifdef AH_SUPPORT_AR5416 59189251Ssam /* 802.11n status */ 60189251Ssam uint8_t ts_flags; /* misc flags */ 61189251Ssam uint8_t ts_queue_id; /* AR9300: TX queue id */ 62189251Ssam uint8_t ts_desc_id; /* AR9300: TX descriptor id */ 63189251Ssam uint8_t ts_tid; /* TID */ 64189251Ssam/* #define ts_rssi ts_rssi_combined */ 65189251Ssam uint32_t ts_ba_low; /* blockack bitmap low */ 66189251Ssam uint32_t ts_ba_high; /* blockack bitmap high */ 67189251Ssam uint32_t ts_evm0; /* evm bytes */ 68189251Ssam uint32_t ts_evm1; 69189251Ssam uint32_t ts_evm2; 70189251Ssam int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */ 71189251Ssam int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */ 72189251Ssam uint8_t ts_pad[2]; 73189251Ssam#endif /* AH_SUPPORT_AR5416 */ 74189251Ssam}; 75189251Ssam 76189251Ssam/* bits found in ts_status */ 77189251Ssam#define HAL_TXERR_XRETRY 0x01 /* excessive retries */ 78189251Ssam#define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ 79189251Ssam#define HAL_TXERR_FIFO 0x04 /* fifo underrun */ 80189251Ssam#define HAL_TXERR_XTXOP 0x08 /* txop exceeded */ 81189251Ssam#define HAL_TXERR_TIMER_EXPIRED 0x10 /* Tx timer expired */ 82189251Ssam 83189251Ssam/* bits found in ts_flags */ 84189251Ssam#define HAL_TX_BA 0x01 /* Block Ack seen */ 85189251Ssam#define HAL_TX_AGGR 0x02 /* Aggregate */ 86189251Ssam#define HAL_TX_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */ 87189251Ssam#define HAL_TX_DATA_UNDERRUN 0x20 /* Tx buffer underrun */ 88189251Ssam#define HAL_TX_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */ 89189251Ssam 90189251Ssam/* 91189251Ssam * Receive descriptor status. This structure is filled 92189251Ssam * in only after the rx descriptor process method finds a 93189251Ssam * ``done'' descriptor; at which point it returns something 94189251Ssam * other than HAL_EINPROGRESS. 95189251Ssam * 96189251Ssam * If rx_status is zero, then the frame was received ok; 97189251Ssam * otherwise the error information is indicated and rs_phyerr 98189251Ssam * contains a phy error code if HAL_RXERR_PHY is set. In general 99189251Ssam * the frame contents is undefined when an error occurred thought 100189251Ssam * for some errors (e.g. a decryption error), it may be meaningful. 101189251Ssam * 102189251Ssam * Note that the receive timestamp is expanded using the TSF to 103189251Ssam * at least 15 bits (regardless of what the h/w provides directly). 104189251Ssam * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to 105189251Ssam * find out if the hardware is capable. 106189251Ssam * 107189251Ssam * rx_rssi is in units of dbm above the noise floor. This value 108189251Ssam * is measured during the preamble and PLCP; i.e. with the initial 109189251Ssam * 4us of detection. The noise floor is typically a consistent 110189251Ssam * -96dBm absolute power in a 20MHz channel. 111189251Ssam */ 112189251Ssamstruct ath_rx_status { 113189251Ssam uint16_t rs_datalen; /* rx frame length */ 114189251Ssam uint8_t rs_status; /* rx status, 0 => recv ok */ 115189251Ssam uint8_t rs_phyerr; /* phy error code */ 116189251Ssam int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */ 117189251Ssam uint8_t rs_keyix; /* key cache index */ 118189251Ssam uint8_t rs_rate; /* h/w receive rate index */ 119189251Ssam uint8_t rs_more; /* more descriptors follow */ 120189251Ssam uint32_t rs_tstamp; /* h/w assigned timestamp */ 121189251Ssam uint32_t rs_antenna; /* antenna information */ 122189251Ssam#ifdef AH_SUPPORT_AR5416 123189251Ssam /* 802.11n status */ 124189251Ssam int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */ 125189251Ssam int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */ 126189251Ssam uint8_t rs_isaggr; /* is part of the aggregate */ 127189251Ssam uint8_t rs_moreaggr; /* more frames in aggr to follow */ 128189251Ssam uint16_t rs_flags; /* misc flags */ 129189251Ssam uint8_t rs_num_delims; /* number of delims in aggr */ 130189251Ssam uint8_t rs_spare0; /* padding */ 131189251Ssam uint32_t rs_evm0; /* evm bytes */ 132189251Ssam uint32_t rs_evm1; 133189251Ssam uint32_t rs_evm2; 134189251Ssam uint32_t rs_evm3; /* needed for ar9300 and later */ 135189251Ssam uint32_t rs_evm4; /* needed for ar9300 and later */ 136189251Ssam#endif /* AH_SUPPORT_AR5416 */ 137189251Ssam}; 138189251Ssam 139189251Ssam/* bits found in rs_status */ 140189251Ssam#define HAL_RXERR_CRC 0x01 /* CRC error on frame */ 141189251Ssam#define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ 142189251Ssam#define HAL_RXERR_FIFO 0x04 /* fifo overrun */ 143189251Ssam#define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ 144189251Ssam#define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ 145189251Ssam#define HAL_RXERR_INCOMP 0x20 /* Rx Desc processing is incomplete */ 146189251Ssam#define HAL_RXERR_KEYMISS 0x40 /* Key not found in keycache */ 147189251Ssam 148189251Ssam/* bits found in rs_flags */ 149189251Ssam#define HAL_RX_MORE 0x0001 /* more descriptors follow */ 150189251Ssam#define HAL_RX_MORE_AGGR 0x0002 /* more frames in aggr */ 151189251Ssam#define HAL_RX_GI 0x0004 /* full gi */ 152189251Ssam#define HAL_RX_2040 0x0008 /* 40 Mhz */ 153189251Ssam#define HAL_RX_DELIM_CRC_PRE 0x0010 /* crc error in delimiter pre */ 154189251Ssam#define HAL_RX_DELIM_CRC_POST 0x0020 /* crc error in delim after */ 155189251Ssam#define HAL_RX_DECRYPT_BUSY 0x0040 /* decrypt was too slow */ 156189251Ssam#define HAL_RX_HI_RX_CHAIN 0x0080 /* SM power save: hi Rx chain control */ 157189251Ssam#define HAL_RX_IS_APSD 0x0100 /* Is ASPD trigger frame */ 158189251Ssam#define HAL_RX_STBC 0x0200 /* Is an STBC frame */ 159189251Ssam 160189251Ssamenum { 161189251Ssam HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 162189251Ssam HAL_PHYERR_TIMING = 1, /* Timing error */ 163189251Ssam HAL_PHYERR_PARITY = 2, /* Illegal parity */ 164189251Ssam HAL_PHYERR_RATE = 3, /* Illegal rate */ 165189251Ssam HAL_PHYERR_LENGTH = 4, /* Illegal length */ 166189251Ssam HAL_PHYERR_RADAR = 5, /* Radar detect */ 167189251Ssam HAL_PHYERR_SERVICE = 6, /* Illegal service */ 168189251Ssam HAL_PHYERR_TOR = 7, /* Transmit override receive */ 169189251Ssam /* NB: these are specific to the 5212 and later */ 170189251Ssam HAL_PHYERR_OFDM_TIMING = 17, /* */ 171189251Ssam HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ 172189251Ssam HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ 173189251Ssam HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ 174189251Ssam HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ 175189251Ssam HAL_PHYERR_OFDM_SERVICE = 22, /* */ 176189251Ssam HAL_PHYERR_OFDM_RESTART = 23, /* */ 177189251Ssam HAL_PHYERR_FALSE_RADAR_EXT = 24, /* */ 178189251Ssam HAL_PHYERR_CCK_TIMING = 25, /* */ 179189251Ssam HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ 180189251Ssam HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ 181189251Ssam HAL_PHYERR_CCK_SERVICE = 30, /* */ 182189251Ssam HAL_PHYERR_CCK_RESTART = 31, /* */ 183189251Ssam HAL_PHYERR_CCK_LENGTH_ILLEGAL = 32, /* */ 184189251Ssam HAL_PHYERR_CCK_POWER_DROP = 33, /* */ 185189251Ssam /* AR5416 and later */ 186189251Ssam HAL_PHYERR_HT_CRC_ERROR = 34, /* */ 187189251Ssam HAL_PHYERR_HT_LENGTH_ILLEGAL = 35, /* */ 188189251Ssam HAL_PHYERR_HT_RATE_ILLEGAL = 36, /* */ 189189251Ssam 190189251Ssam HAL_PHYERR_SPECTRAL = 38, 191189251Ssam}; 192189251Ssam 193189251Ssam/* value found in rs_keyix to mark invalid entries */ 194189251Ssam#define HAL_RXKEYIX_INVALID ((uint8_t) -1) 195189251Ssam/* value used to specify no encryption key for xmit */ 196189251Ssam#define HAL_TXKEYIX_INVALID ((u_int) -1) 197189251Ssam 198189251Ssam/* XXX rs_antenna definitions */ 199189251Ssam 200189251Ssam/* 201189251Ssam * Definitions for the software frame/packet descriptors used by 202189251Ssam * the Atheros HAL. This definition obscures hardware-specific 203189251Ssam * details from the driver. Drivers are expected to fillin the 204189251Ssam * portions of a descriptor that are not opaque then use HAL calls 205189251Ssam * to complete the work. Status for completed frames is returned 206189251Ssam * in a device-independent format. 207189251Ssam */ 208189251Ssam#ifdef AH_SUPPORT_AR5416 209189251Ssam#define HAL_DESC_HW_SIZE 20 210189251Ssam#else 211189251Ssam#define HAL_DESC_HW_SIZE 4 212189251Ssam#endif /* AH_SUPPORT_AR5416 */ 213189251Ssam 214189251Ssamstruct ath_desc { 215189251Ssam /* 216189251Ssam * The following definitions are passed directly 217189251Ssam * the hardware and managed by the HAL. Drivers 218189251Ssam * should not touch those elements marked opaque. 219189251Ssam */ 220189251Ssam uint32_t ds_link; /* phys address of next descriptor */ 221189251Ssam uint32_t ds_data; /* phys address of data buffer */ 222189251Ssam uint32_t ds_ctl0; /* opaque DMA control 0 */ 223189251Ssam uint32_t ds_ctl1; /* opaque DMA control 1 */ 224189251Ssam uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */ 225189251Ssam}; 226189251Ssam 227189251Ssamstruct ath_desc_txedma { 228189251Ssam uint32_t ds_info; 229189251Ssam uint32_t ds_link; 230189251Ssam uint32_t ds_hw[21]; /* includes buf/len */ 231189251Ssam}; 232189251Ssam 233189251Ssamstruct ath_desc_status { 234189251Ssam union { 235189251Ssam struct ath_tx_status tx;/* xmit status */ 236189251Ssam struct ath_rx_status rx;/* recv status */ 237189251Ssam } ds_us; 238189251Ssam}; 239189251Ssam 240189251Ssam#define ds_txstat ds_us.tx 241189251Ssam#define ds_rxstat ds_us.rx 242189251Ssam 243189251Ssam/* flags passed to tx descriptor setup methods */ 244189251Ssam/* This is a uint16_t field in ath_buf, just be warned! */ 245189251Ssam#define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ 246189251Ssam#define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ 247189251Ssam#define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ 248189251Ssam#define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ 249189251Ssam#define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ 250189251Ssam#define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ 251189251Ssam/* NB: this only affects frame, not any RTS/CTS */ 252189251Ssam#define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */ 253189251Ssam#define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */ 254189251Ssam#define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */ 255189251Ssam#define HAL_TXDESC_VMF 0x0200 /* virtual more frag */ 256189251Ssam#define HAL_TXDESC_LOWRXCHAIN 0x0400 /* switch to low RX chain */ 257189251Ssam#define HAL_TXDESC_LDPC 0x1000 258189251Ssam 259189251Ssam/* flags passed to rx descriptor setup methods */ 260189251Ssam#define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ 261189251Ssam#endif /* _DEV_ATH_DESC_H */ 262189251Ssam