ah.h revision 247774
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 247774 2013-03-04 07:40:49Z adrian $ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38#define AH_MAX_CHAINS 3 39#define AH_MIMO_MAX_EVM_PILOTS 6 40 41/* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48#ifndef __ahdecl 49#define __ahdecl 50#endif 51 52/* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76 HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77} HAL_STATUS; 78 79typedef enum { 80 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81 AH_TRUE = 1, 82} HAL_BOOL; 83 84typedef enum { 85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99 HAL_CAP_TXPOW = 15, /* global tx power limit */ 100 HAL_CAP_TPC = 16, /* per-packet tx power control */ 101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105 /* 21 was HAL_CAP_XR */ 106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107 /* 23 was HAL_CAP_CHAN_HALFRATE */ 108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113 HAL_CAP_PCIE_PS = 29, 114 HAL_CAP_HT = 30, /* hardware can support HT */ 115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120 121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122 HAL_CAP_RIFS_RX = 39, 123 HAL_CAP_RIFS_TX = 40, 124 HAL_CAP_FORCE_PPM = 41, 125 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 126 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 127 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 128 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 129 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 130 131 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 132 automatically after waking up to receive TIM */ 133 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 134 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 135 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 136 HAL_CAP_BB_RIFS_HANG = 52, 137 HAL_CAP_RIFS_RX_ENABLED = 53, 138 HAL_CAP_BB_DFS_HANG = 54, 139 140 HAL_CAP_RX_STBC = 58, 141 HAL_CAP_TX_STBC = 59, 142 143 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 144 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 145 146 HAL_CAP_DS = 67, /* 2 stream */ 147 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 148 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 149 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 150 151 HAL_CAP_TS = 72, /* 3 stream */ 152 153 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 154 HAL_CAP_NUM_TXMAPS = 76, /* Number of buffers in a transmit descriptor */ 155 HAL_CAP_TXDESCLEN = 77, /* Length of transmit descriptor */ 156 HAL_CAP_TXSTATUSLEN = 78, /* Length of transmit status descriptor */ 157 HAL_CAP_RXSTATUSLEN = 79, /* Length of transmit status descriptor */ 158 HAL_CAP_RXFIFODEPTH = 80, /* Receive hardware FIFO depth */ 159 HAL_CAP_RXBUFSIZE = 81, /* Receive Buffer Length */ 160 HAL_CAP_NUM_MR_RETRIES = 82, /* limit on multirate retries */ 161 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 162 HAL_CAP_SPECTRAL_SCAN = 90, /* Hardware supports spectral scan */ 163 164 HAL_CAP_BB_PANIC_WATCHDOG = 92, 165 166 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 167 168 HAL_CAP_LDPC = 99, 169 170 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 171 172 HAL_CAP_PHYRESTART_CLR_WAR = 106, /* in some cases, clear phy restart to fix bb hang */ 173 HAL_CAP_ENTERPRISE_MODE = 107, /* Enterprise mode features */ 174 HAL_CAP_LDPCWAR = 108, 175 HAL_CAP_CHANNEL_SWITCH_TIME_USEC = 109, /* Channel change time, usec */ 176 HAL_CAP_ENABLE_APM = 110, /* APM enabled */ 177 HAL_CAP_PCIE_LCR_EXTSYNC_EN = 111, 178 HAL_CAP_PCIE_LCR_OFFSET = 112, 179 180 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 181 HAL_CAP_MCI = 118, 182 HAL_CAP_SMARTANTENNA = 119, 183 HAL_CAP_TRAFFIC_FAST_RECOVER = 120, 184 HAL_CAP_TX_DIVERSITY = 121, 185 HAL_CAP_CRDC = 122, 186 187 /* The following are private to the FreeBSD HAL (224 onward) */ 188 189 HAL_CAP_INTMIT = 229, /* interference mitigation */ 190 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 191 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 192 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 193 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 194 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 195 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 196 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 197 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 198 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 199 HAL_CAP_ENFORCE_TXOP = 246, /* Enforce TXOP if supported */ 200} HAL_CAPABILITY_TYPE; 201 202/* 203 * "States" for setting the LED. These correspond to 204 * the possible 802.11 operational states and there may 205 * be a many-to-one mapping between these states and the 206 * actual hardware state for the LED's (i.e. the hardware 207 * may have fewer states). 208 */ 209typedef enum { 210 HAL_LED_INIT = 0, 211 HAL_LED_SCAN = 1, 212 HAL_LED_AUTH = 2, 213 HAL_LED_ASSOC = 3, 214 HAL_LED_RUN = 4 215} HAL_LED_STATE; 216 217/* 218 * Transmit queue types/numbers. These are used to tag 219 * each transmit queue in the hardware and to identify a set 220 * of transmit queues for operations such as start/stop dma. 221 */ 222typedef enum { 223 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 224 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 225 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 226 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 227 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 228 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 229 HAL_TX_QUEUE_CFEND = 6, 230 HAL_TX_QUEUE_PAPRD = 7, 231} HAL_TX_QUEUE; 232 233#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 234 235/* 236 * Receive queue types. These are used to tag 237 * each transmit queue in the hardware and to identify a set 238 * of transmit queues for operations such as start/stop dma. 239 */ 240typedef enum { 241 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 242 HAL_RX_QUEUE_LP = 1, /* low priority recv queue */ 243} HAL_RX_QUEUE; 244 245#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 246 247#define HAL_TXFIFO_DEPTH 8 /* transmit fifo depth */ 248 249/* 250 * Transmit queue subtype. These map directly to 251 * WME Access Categories (except for UPSD). Refer 252 * to Table 5 of the WME spec. 253 */ 254typedef enum { 255 HAL_WME_AC_BK = 0, /* background access category */ 256 HAL_WME_AC_BE = 1, /* best effort access category*/ 257 HAL_WME_AC_VI = 2, /* video access category */ 258 HAL_WME_AC_VO = 3, /* voice access category */ 259 HAL_WME_UPSD = 4, /* uplink power save */ 260} HAL_TX_QUEUE_SUBTYPE; 261 262/* 263 * Transmit queue flags that control various 264 * operational parameters. 265 */ 266typedef enum { 267 /* 268 * Per queue interrupt enables. When set the associated 269 * interrupt may be delivered for packets sent through 270 * the queue. Without these enabled no interrupts will 271 * be delivered for transmits through the queue. 272 */ 273 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 274 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 275 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 276 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 277 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 278 /* 279 * Enable hardware compression for packets sent through 280 * the queue. The compression buffer must be setup and 281 * packets must have a key entry marked in the tx descriptor. 282 */ 283 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 284 /* 285 * Disable queue when veol is hit or ready time expires. 286 * By default the queue is disabled only on reaching the 287 * physical end of queue (i.e. a null link ptr in the 288 * descriptor chain). 289 */ 290 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 291 /* 292 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 293 * event. Frames will be transmitted only when this timer 294 * fires, e.g to transmit a beacon in ap or adhoc modes. 295 */ 296 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 297 /* 298 * Each transmit queue has a counter that is incremented 299 * each time the queue is enabled and decremented when 300 * the list of frames to transmit is traversed (or when 301 * the ready time for the queue expires). This counter 302 * must be non-zero for frames to be scheduled for 303 * transmission. The following controls disable bumping 304 * this counter under certain conditions. Typically this 305 * is used to gate frames based on the contents of another 306 * queue (e.g. CAB traffic may only follow a beacon frame). 307 * These are meaningful only when frames are scheduled 308 * with a non-ASAP policy (e.g. DBA-gated). 309 */ 310 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 311 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 312 313 /* 314 * Fragment burst backoff policy. Normally the no backoff 315 * is done after a successful transmission, the next fragment 316 * is sent at SIFS. If this flag is set backoff is done 317 * after each fragment, regardless whether it was ack'd or 318 * not, after the backoff count reaches zero a normal channel 319 * access procedure is done before the next transmit (i.e. 320 * wait AIFS instead of SIFS). 321 */ 322 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 323 /* 324 * Disable post-tx backoff following each frame. 325 */ 326 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 327 /* 328 * DCU arbiter lockout control. This controls how 329 * lower priority tx queues are handled with respect to 330 * to a specific queue when multiple queues have frames 331 * to send. No lockout means lower priority queues arbitrate 332 * concurrently with this queue. Intra-frame lockout 333 * means lower priority queues are locked out until the 334 * current frame transmits (e.g. including backoffs and bursting). 335 * Global lockout means nothing lower can arbitrary so 336 * long as there is traffic activity on this queue (frames, 337 * backoff, etc). 338 */ 339 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 340 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 341 342 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 343 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 344} HAL_TX_QUEUE_FLAGS; 345 346typedef struct { 347 uint32_t tqi_ver; /* hal TXQ version */ 348 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 349 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 350 uint32_t tqi_priority; /* (not used) */ 351 uint32_t tqi_aifs; /* aifs */ 352 uint32_t tqi_cwmin; /* cwMin */ 353 uint32_t tqi_cwmax; /* cwMax */ 354 uint16_t tqi_shretry; /* rts retry limit */ 355 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 356 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 357 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 358 uint32_t tqi_burstTime; /* max burst duration (us) */ 359 uint32_t tqi_readyTime; /* frame schedule time (us) */ 360 uint32_t tqi_compBuf; /* comp buffer phys addr */ 361} HAL_TXQ_INFO; 362 363#define HAL_TQI_NONVAL 0xffff 364 365/* token to use for aifs, cwmin, cwmax */ 366#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 367 368/* compression definitions */ 369#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 370#define HAL_COMP_BUF_ALIGN_SIZE 512 371 372/* 373 * Transmit packet types. This belongs in ah_desc.h, but 374 * is here so we can give a proper type to various parameters 375 * (and not require everyone include the file). 376 * 377 * NB: These values are intentionally assigned for 378 * direct use when setting up h/w descriptors. 379 */ 380typedef enum { 381 HAL_PKT_TYPE_NORMAL = 0, 382 HAL_PKT_TYPE_ATIM = 1, 383 HAL_PKT_TYPE_PSPOLL = 2, 384 HAL_PKT_TYPE_BEACON = 3, 385 HAL_PKT_TYPE_PROBE_RESP = 4, 386 HAL_PKT_TYPE_CHIRP = 5, 387 HAL_PKT_TYPE_GRP_POLL = 6, 388 HAL_PKT_TYPE_AMPDU = 7, 389} HAL_PKT_TYPE; 390 391/* Rx Filter Frame Types */ 392typedef enum { 393 /* 394 * These bits correspond to AR_RX_FILTER for all chips. 395 * Not all bits are supported by all chips. 396 */ 397 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 398 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 399 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 400 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 401 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 402 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 403 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 404 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 405 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 406 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 407 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 408 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 409 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 410 /* Allow all mcast/bcast frames */ 411 412 /* 413 * Magic RX filter flags that aren't targetting hardware bits 414 * but instead the HAL sets individual bits - eg PHYERR will result 415 * in OFDM/CCK timing error frames being received. 416 */ 417 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 418} HAL_RX_FILTER; 419 420typedef enum { 421 HAL_PM_AWAKE = 0, 422 HAL_PM_FULL_SLEEP = 1, 423 HAL_PM_NETWORK_SLEEP = 2, 424 HAL_PM_UNDEFINED = 3 425} HAL_POWER_MODE; 426 427/* 428 * Enterprise mode flags 429 */ 430#define AH_ENT_DUAL_BAND_DISABLE 0x00000001 431#define AH_ENT_CHAIN2_DISABLE 0x00000002 432#define AH_ENT_5MHZ_DISABLE 0x00000004 433#define AH_ENT_10MHZ_DISABLE 0x00000008 434#define AH_ENT_49GHZ_DISABLE 0x00000010 435#define AH_ENT_LOOPBACK_DISABLE 0x00000020 436#define AH_ENT_TPC_PERF_DISABLE 0x00000040 437#define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080 438#define AH_ENT_SPECTRAL_PRECISION 0x00000300 439#define AH_ENT_SPECTRAL_PRECISION_S 8 440#define AH_ENT_RTSCTS_DELIM_WAR 0x00010000 441 442#define AH_FIRST_DESC_NDELIMS 60 443 444/* 445 * NOTE WELL: 446 * These are mapped to take advantage of the common locations for many of 447 * the bits on all of the currently supported MAC chips. This is to make 448 * the ISR as efficient as possible, while still abstracting HW differences. 449 * When new hardware breaks this commonality this enumerated type, as well 450 * as the HAL functions using it, must be modified. All values are directly 451 * mapped unless commented otherwise. 452 */ 453typedef enum { 454 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 455 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */ 456 HAL_INT_RXERR = 0x00000004, 457 HAL_INT_RXHP = 0x00000001, /* EDMA */ 458 HAL_INT_RXLP = 0x00000002, /* EDMA */ 459 HAL_INT_RXNOFRM = 0x00000008, 460 HAL_INT_RXEOL = 0x00000010, 461 HAL_INT_RXORN = 0x00000020, 462 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 463 HAL_INT_TXDESC = 0x00000080, 464 HAL_INT_TIM_TIMER= 0x00000100, 465 HAL_INT_MCI = 0x00000200, 466 HAL_INT_BBPANIC = 0x00000400, 467 HAL_INT_TXURN = 0x00000800, 468 HAL_INT_MIB = 0x00001000, 469 HAL_INT_RXPHY = 0x00004000, 470 HAL_INT_RXKCM = 0x00008000, 471 HAL_INT_SWBA = 0x00010000, 472 HAL_INT_BRSSI = 0x00020000, 473 HAL_INT_BMISS = 0x00040000, 474 HAL_INT_BNR = 0x00100000, 475 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 476 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 477 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 478 HAL_INT_GPIO = 0x01000000, 479 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 480 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 481 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 482 /* Atheros ref driver has a generic timer interrupt now..*/ 483 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */ 484 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 485 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 486 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 487#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 488 HAL_INT_BMISC = HAL_INT_TIM 489 | HAL_INT_DTIM 490 | HAL_INT_DTIMSYNC 491 | HAL_INT_CABEND 492 | HAL_INT_TBTT, 493 494 /* Interrupt bits that map directly to ISR/IMR bits */ 495 HAL_INT_COMMON = HAL_INT_RXNOFRM 496 | HAL_INT_RXDESC 497 | HAL_INT_RXEOL 498 | HAL_INT_RXORN 499 | HAL_INT_TXDESC 500 | HAL_INT_TXURN 501 | HAL_INT_MIB 502 | HAL_INT_RXPHY 503 | HAL_INT_RXKCM 504 | HAL_INT_SWBA 505 | HAL_INT_BMISS 506 | HAL_INT_BRSSI 507 | HAL_INT_BNR 508 | HAL_INT_GPIO, 509} HAL_INT; 510 511/* 512 * MSI vector assignments 513 */ 514typedef enum { 515 HAL_MSIVEC_MISC = 0, 516 HAL_MSIVEC_TX = 1, 517 HAL_MSIVEC_RXLP = 2, 518 HAL_MSIVEC_RXHP = 3, 519} HAL_MSIVEC; 520 521typedef enum { 522 HAL_INT_LINE = 0, 523 HAL_INT_MSI = 1, 524} HAL_INT_TYPE; 525 526/* For interrupt mitigation registers */ 527typedef enum { 528 HAL_INT_RX_FIRSTPKT=0, 529 HAL_INT_RX_LASTPKT, 530 HAL_INT_TX_FIRSTPKT, 531 HAL_INT_TX_LASTPKT, 532 HAL_INT_THRESHOLD 533} HAL_INT_MITIGATION; 534 535/* XXX this is duplicate information! */ 536typedef struct { 537 u_int32_t cyclecnt_diff; /* delta cycle count */ 538 u_int32_t rxclr_cnt; /* rx clear count */ 539 u_int32_t txframecnt_diff; /* delta tx frame count */ 540 u_int32_t rxframecnt_diff; /* delta rx frame count */ 541 u_int32_t listen_time; /* listen time in msec - time for which ch is free */ 542 u_int32_t ofdmphyerr_cnt; /* OFDM err count since last reset */ 543 u_int32_t cckphyerr_cnt; /* CCK err count since last reset */ 544 u_int32_t ofdmphyerrcnt_diff; /* delta OFDM Phy Error Count */ 545 HAL_BOOL valid; /* if the stats are valid*/ 546} HAL_ANISTATS; 547 548typedef struct { 549 u_int8_t txctl_offset; 550 u_int8_t txctl_numwords; 551 u_int8_t txstatus_offset; 552 u_int8_t txstatus_numwords; 553 554 u_int8_t rxctl_offset; 555 u_int8_t rxctl_numwords; 556 u_int8_t rxstatus_offset; 557 u_int8_t rxstatus_numwords; 558 559 u_int8_t macRevision; 560} HAL_DESC_INFO; 561 562typedef enum { 563 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 564 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 565 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 566 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 567 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 568 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 569 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6 570} HAL_GPIO_MUX_TYPE; 571 572typedef enum { 573 HAL_GPIO_INTR_LOW = 0, 574 HAL_GPIO_INTR_HIGH = 1, 575 HAL_GPIO_INTR_DISABLE = 2 576} HAL_GPIO_INTR_TYPE; 577 578typedef struct halCounters { 579 u_int32_t tx_frame_count; 580 u_int32_t rx_frame_count; 581 u_int32_t rx_clear_count; 582 u_int32_t cycle_count; 583 u_int8_t is_rx_active; // true (1) or false (0) 584 u_int8_t is_tx_active; // true (1) or false (0) 585} HAL_COUNTERS; 586 587typedef enum { 588 HAL_RFGAIN_INACTIVE = 0, 589 HAL_RFGAIN_READ_REQUESTED = 1, 590 HAL_RFGAIN_NEED_CHANGE = 2 591} HAL_RFGAIN; 592 593typedef uint16_t HAL_CTRY_CODE; /* country code */ 594typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 595 596#define HAL_ANTENNA_MIN_MODE 0 597#define HAL_ANTENNA_FIXED_A 1 598#define HAL_ANTENNA_FIXED_B 2 599#define HAL_ANTENNA_MAX_MODE 3 600 601typedef struct { 602 uint32_t ackrcv_bad; 603 uint32_t rts_bad; 604 uint32_t rts_good; 605 uint32_t fcs_bad; 606 uint32_t beacons; 607} HAL_MIB_STATS; 608 609/* 610 * These bits represent what's in ah_currentRDext. 611 */ 612typedef enum { 613 REG_EXT_FCC_MIDBAND = 0, 614 REG_EXT_JAPAN_MIDBAND = 1, 615 REG_EXT_FCC_DFS_HT40 = 2, 616 REG_EXT_JAPAN_NONDFS_HT40 = 3, 617 REG_EXT_JAPAN_DFS_HT40 = 4 618} REG_EXT_BITMAP; 619 620enum { 621 HAL_MODE_11A = 0x001, /* 11a channels */ 622 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 623 HAL_MODE_11B = 0x004, /* 11b channels */ 624 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 625#ifdef notdef 626 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 627#else 628 HAL_MODE_11G = 0x008, /* XXX historical */ 629#endif 630 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 631 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 632 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 633 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 634 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 635 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 636 HAL_MODE_11NG_HT20 = 0x008000, 637 HAL_MODE_11NA_HT20 = 0x010000, 638 HAL_MODE_11NG_HT40PLUS = 0x020000, 639 HAL_MODE_11NG_HT40MINUS = 0x040000, 640 HAL_MODE_11NA_HT40PLUS = 0x080000, 641 HAL_MODE_11NA_HT40MINUS = 0x100000, 642 HAL_MODE_ALL = 0xffffff 643}; 644 645typedef struct { 646 int rateCount; /* NB: for proper padding */ 647 uint8_t rateCodeToIndex[256]; /* back mapping */ 648 struct { 649 uint8_t valid; /* valid for rate control use */ 650 uint8_t phy; /* CCK/OFDM/XR */ 651 uint32_t rateKbps; /* transfer rate in kbs */ 652 uint8_t rateCode; /* rate for h/w descriptors */ 653 uint8_t shortPreamble; /* mask for enabling short 654 * preamble in CCK rate code */ 655 uint8_t dot11Rate; /* value for supported rates 656 * info element of MLME */ 657 uint8_t controlRate; /* index of next lower basic 658 * rate; used for dur. calcs */ 659 uint16_t lpAckDuration; /* long preamble ACK duration */ 660 uint16_t spAckDuration; /* short preamble ACK duration*/ 661 } info[64]; 662} HAL_RATE_TABLE; 663 664typedef struct { 665 u_int rs_count; /* number of valid entries */ 666 uint8_t rs_rates[64]; /* rates */ 667} HAL_RATE_SET; 668 669/* 670 * 802.11n specific structures and enums 671 */ 672typedef enum { 673 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 674 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 675} HAL_CHAIN_TYPE; 676 677typedef struct { 678 u_int Tries; 679 u_int Rate; /* hardware rate code */ 680 u_int RateIndex; /* rate series table index */ 681 u_int PktDuration; 682 u_int ChSel; 683 u_int RateFlags; 684#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 685#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 686#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 687#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ 688 u_int tx_power_cap; /* in 1/2 dBm units XXX TODO */ 689} HAL_11N_RATE_SERIES; 690 691typedef enum { 692 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 693 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 694} HAL_HT_MACMODE; 695 696typedef enum { 697 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 698 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 699} HAL_HT_PHYMODE; 700 701typedef enum { 702 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 703 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 704} HAL_HT_EXTPROTSPACING; 705 706 707typedef enum { 708 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 709 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 710} HAL_HT_RXCLEAR; 711 712typedef enum { 713 HAL_FREQ_BAND_5GHZ = 0, 714 HAL_FREQ_BAND_2GHZ = 1, 715} HAL_FREQ_BAND; 716 717/* 718 * Antenna switch control. By default antenna selection 719 * enables multiple (2) antenna use. To force use of the 720 * A or B antenna only specify a fixed setting. Fixing 721 * the antenna will also disable any diversity support. 722 */ 723typedef enum { 724 HAL_ANT_VARIABLE = 0, /* variable by programming */ 725 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 726 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 727} HAL_ANT_SETTING; 728 729typedef enum { 730 HAL_M_STA = 1, /* infrastructure station */ 731 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 732 HAL_M_HOSTAP = 6, /* Software Access Point */ 733 HAL_M_MONITOR = 8 /* Monitor mode */ 734} HAL_OPMODE; 735 736typedef struct { 737 uint8_t kv_type; /* one of HAL_CIPHER */ 738 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 739 uint16_t kv_len; /* length in bits */ 740 uint8_t kv_val[16]; /* enough for 128-bit keys */ 741 uint8_t kv_mic[8]; /* TKIP MIC key */ 742 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 743} HAL_KEYVAL; 744 745/* 746 * This is the TX descriptor field which marks the key padding requirement. 747 * The naming is unfortunately unclear. 748 */ 749#define AH_KEYTYPE_MASK 0x0F 750typedef enum { 751 HAL_KEY_TYPE_CLEAR, 752 HAL_KEY_TYPE_WEP, 753 HAL_KEY_TYPE_AES, 754 HAL_KEY_TYPE_TKIP, 755} HAL_KEY_TYPE; 756 757typedef enum { 758 HAL_CIPHER_WEP = 0, 759 HAL_CIPHER_AES_OCB = 1, 760 HAL_CIPHER_AES_CCM = 2, 761 HAL_CIPHER_CKIP = 3, 762 HAL_CIPHER_TKIP = 4, 763 HAL_CIPHER_CLR = 5, /* no encryption */ 764 765 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 766} HAL_CIPHER; 767 768enum { 769 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 770 HAL_SLOT_TIME_9 = 9, 771 HAL_SLOT_TIME_20 = 20, 772}; 773 774/* 775 * Per-station beacon timer state. Note that the specified 776 * beacon interval (given in TU's) can also include flags 777 * to force a TSF reset and to enable the beacon xmit logic. 778 * If bs_cfpmaxduration is non-zero the hardware is setup to 779 * coexist with a PCF-capable AP. 780 */ 781typedef struct { 782 uint32_t bs_nexttbtt; /* next beacon in TU */ 783 uint32_t bs_nextdtim; /* next DTIM in TU */ 784 uint32_t bs_intval; /* beacon interval+flags */ 785/* 786 * HAL_BEACON_PERIOD, HAL_BEACON_ENA and HAL_BEACON_RESET_TSF 787 * are all 1:1 correspondances with the pre-11n chip AR_BEACON 788 * register. 789 */ 790#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 791#define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */ 792#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 793#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 794#define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */ 795 uint32_t bs_dtimperiod; 796 uint16_t bs_cfpperiod; /* CFP period in TU */ 797 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 798 uint32_t bs_cfpnext; /* next CFP in TU */ 799 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 800 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 801 uint32_t bs_sleepduration; /* max sleep duration */ 802 uint32_t bs_tsfoor_threshold; /* TSF out of range threshold */ 803} HAL_BEACON_STATE; 804 805/* 806 * Like HAL_BEACON_STATE but for non-station mode setup. 807 * NB: see above flag definitions for bt_intval. 808 */ 809typedef struct { 810 uint32_t bt_intval; /* beacon interval+flags */ 811 uint32_t bt_nexttbtt; /* next beacon in TU */ 812 uint32_t bt_nextatim; /* next ATIM in TU */ 813 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 814 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 815 uint32_t bt_flags; /* timer enables */ 816#define HAL_BEACON_TBTT_EN 0x00000001 817#define HAL_BEACON_DBA_EN 0x00000002 818#define HAL_BEACON_SWBA_EN 0x00000004 819} HAL_BEACON_TIMERS; 820 821/* 822 * Per-node statistics maintained by the driver for use in 823 * optimizing signal quality and other operational aspects. 824 */ 825typedef struct { 826 uint32_t ns_avgbrssi; /* average beacon rssi */ 827 uint32_t ns_avgrssi; /* average data rssi */ 828 uint32_t ns_avgtxrssi; /* average tx rssi */ 829} HAL_NODE_STATS; 830 831#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 832 833 834struct ath_desc; 835struct ath_tx_status; 836struct ath_rx_status; 837struct ieee80211_channel; 838 839/* 840 * This is a channel survey sample entry. 841 * 842 * The AR5212 ANI routines fill these samples. The ANI code then uses it 843 * when calculating listen time; it is also exported via a diagnostic 844 * API. 845 */ 846typedef struct { 847 uint32_t seq_num; 848 uint32_t tx_busy; 849 uint32_t rx_busy; 850 uint32_t chan_busy; 851 uint32_t ext_chan_busy; 852 uint32_t cycle_count; 853 /* XXX TODO */ 854 uint32_t ofdm_phyerr_count; 855 uint32_t cck_phyerr_count; 856} HAL_SURVEY_SAMPLE; 857 858/* 859 * This provides 3.2 seconds of sample space given an 860 * ANI time of 1/10th of a second. This may not be enough! 861 */ 862#define CHANNEL_SURVEY_SAMPLE_COUNT 32 863 864typedef struct { 865 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 866 uint32_t cur_sample; /* current sample in sequence */ 867 uint32_t cur_seq; /* current sequence number */ 868} HAL_CHANNEL_SURVEY; 869 870/* 871 * ANI commands. 872 * 873 * These are used both internally and externally via the diagnostic 874 * API. 875 * 876 * Note that this is NOT the ANI commands being used via the INTMIT 877 * capability - that has a different mapping for some reason. 878 */ 879typedef enum { 880 HAL_ANI_PRESENT = 0, /* is ANI support present */ 881 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 882 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 883 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 884 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 885 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 886 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 887 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 888 HAL_ANI_MRC_CCK = 8, 889} HAL_ANI_CMD; 890 891#define HAL_ANI_ALL 0xffffffff 892 893/* 894 * This is the layout of the ANI INTMIT capability. 895 * 896 * Notice that the command values differ to HAL_ANI_CMD. 897 */ 898typedef enum { 899 HAL_CAP_INTMIT_PRESENT = 0, 900 HAL_CAP_INTMIT_ENABLE = 1, 901 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 902 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 903 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 904 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 905 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 906} HAL_CAP_INTMIT_CMD; 907 908typedef struct { 909 int32_t pe_firpwr; /* FIR pwr out threshold */ 910 int32_t pe_rrssi; /* Radar rssi thresh */ 911 int32_t pe_height; /* Pulse height thresh */ 912 int32_t pe_prssi; /* Pulse rssi thresh */ 913 int32_t pe_inband; /* Inband thresh */ 914 915 /* The following params are only for AR5413 and later */ 916 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 917 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 918 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 919 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 920 int32_t pe_blockradar; /* 921 * Enable to block radar check if pkt detect is done via OFDM 922 * weak signal detect or pkt is detected immediately after tx 923 * to rx transition 924 */ 925 int32_t pe_enmaxrssi; /* 926 * Enable to use the max rssi instead of the last rssi during 927 * fine gain changes for radar detection 928 */ 929 int32_t pe_extchannel; /* Enable DFS on ext channel */ 930 int32_t pe_enabled; /* Whether radar detection is enabled */ 931 int32_t pe_enrelpwr; 932 int32_t pe_en_relstep_check; 933} HAL_PHYERR_PARAM; 934 935#define HAL_PHYERR_PARAM_NOVAL 65535 936 937typedef struct { 938 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 939 u_int16_t ss_period; /* Spectral scan period */ 940 u_int16_t ss_count; /* # of reports to return from ss_active */ 941 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 942 u_int8_t radar_bin_thresh_sel; /* strong signal radar FFT threshold configuration */ 943 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 944 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 945 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 946 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 947 int ss_enabled; 948 int ss_active; 949} HAL_SPECTRAL_PARAM; 950#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 951#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 952 953/* 954 * DFS operating mode flags. 955 */ 956typedef enum { 957 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 958 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 959 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 960 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 961} HAL_DFS_DOMAIN; 962 963 964/* 965 * MFP decryption options for initializing the MAC. 966 */ 967typedef enum { 968 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */ 969 HAL_MFP_PASSTHRU, /* Don't decrypt MFP frames at all. Passthrough */ 970 HAL_MFP_HW_CRYPTO /* hardware decryption enabled. Merlin can do it. */ 971} HAL_MFP_OPT_T; 972 973/* LNA config supported */ 974typedef enum { 975 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0, 976 HAL_ANT_DIV_COMB_LNA2 = 1, 977 HAL_ANT_DIV_COMB_LNA1 = 2, 978 HAL_ANT_DIV_COMB_LNA1_PLUS_LNA2 = 3, 979} HAL_ANT_DIV_COMB_LNA_CONF; 980 981typedef struct { 982 u_int8_t main_lna_conf; 983 u_int8_t alt_lna_conf; 984 u_int8_t fast_div_bias; 985 u_int8_t main_gaintb; 986 u_int8_t alt_gaintb; 987 u_int8_t antdiv_configgroup; 988 int8_t lna1_lna2_delta; 989} HAL_ANT_COMB_CONFIG; 990 991#define DEFAULT_ANTDIV_CONFIG_GROUP 0x00 992#define HAL_ANTDIV_CONFIG_GROUP_1 0x01 993#define HAL_ANTDIV_CONFIG_GROUP_2 0x02 994#define HAL_ANTDIV_CONFIG_GROUP_3 0x03 995 996/* 997 * Flag for setting QUIET period 998 */ 999typedef enum { 1000 HAL_QUIET_DISABLE = 0x0, 1001 HAL_QUIET_ENABLE = 0x1, 1002 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 1003 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 1004} HAL_QUIET_FLAG; 1005 1006#define HAL_DFS_EVENT_PRICH 0x0000001 1007#define HAL_DFS_EVENT_EXTCH 0x0000002 1008#define HAL_DFS_EVENT_EXTEARLY 0x0000004 1009#define HAL_DFS_EVENT_ISDC 0x0000008 1010 1011struct hal_dfs_event { 1012 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 1013 uint32_t re_ts; /* Original 15 bit recv timestamp */ 1014 uint8_t re_rssi; /* rssi of radar event */ 1015 uint8_t re_dur; /* duration of radar pulse */ 1016 uint32_t re_flags; /* Flags (see above) */ 1017}; 1018typedef struct hal_dfs_event HAL_DFS_EVENT; 1019 1020/* 1021 * Generic Timer domain 1022 */ 1023typedef enum { 1024 HAL_GEN_TIMER_TSF = 0, 1025 HAL_GEN_TIMER_TSF2, 1026 HAL_GEN_TIMER_TSF_ANY 1027} HAL_GEN_TIMER_DOMAIN; 1028 1029typedef enum { 1030 HAL_RESET_NONE = 0x0, 1031 HAL_RESET_BBPANIC = 0x1, 1032} HAL_RESET_TYPE; 1033 1034/* 1035 * BT Co-existence definitions 1036 */ 1037typedef enum { 1038 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 1039 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 1040 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 1041 HAL_MAX_BT_MODULES 1042} HAL_BT_MODULE; 1043 1044typedef struct { 1045 HAL_BT_MODULE bt_module; 1046 u_int8_t bt_coex_config; 1047 u_int8_t bt_gpio_bt_active; 1048 u_int8_t bt_gpio_bt_priority; 1049 u_int8_t bt_gpio_wlan_active; 1050 u_int8_t bt_active_polarity; 1051 HAL_BOOL bt_single_ant; 1052 u_int8_t bt_dutyCycle; 1053 u_int8_t bt_isolation; 1054 u_int8_t bt_period; 1055} HAL_BT_COEX_INFO; 1056 1057typedef enum { 1058 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 1059 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 1060 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 1061 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 1062} HAL_BT_COEX_MODE; 1063 1064typedef enum { 1065 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 1066 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 1067 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 1068 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 1069 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 1070 HAL_BT_COEX_CFG_MCI /* MCI */ 1071} HAL_BT_COEX_CFG; 1072 1073typedef enum { 1074 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 1075 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 1076 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 1077} HAL_BT_COEX_SET_PARAMETER; 1078 1079#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 1080#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 1081/* Check Rx Diversity is allowed */ 1082#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 1083/* Check Diversity is on or off */ 1084#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 1085 1086#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 1087/* main: LNA1, alt: LNA2 */ 1088#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 1089#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 1090#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 1091#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 1092#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 1093 1094#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 1095 1096#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 1097 1098#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 1099 1100#define HAL_BT_COEX_LOW_ACK_POWER 0x0 1101#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 1102 1103typedef enum { 1104 HAL_BT_COEX_NO_STOMP = 0, 1105 HAL_BT_COEX_STOMP_ALL, 1106 HAL_BT_COEX_STOMP_LOW, 1107 HAL_BT_COEX_STOMP_NONE, 1108 HAL_BT_COEX_STOMP_ALL_FORCE, 1109 HAL_BT_COEX_STOMP_LOW_FORCE, 1110} HAL_BT_COEX_STOMP_TYPE; 1111 1112typedef struct { 1113 /* extend rx_clear after tx/rx to protect the burst (in usec). */ 1114 u_int8_t bt_time_extend; 1115 1116 /* 1117 * extend rx_clear as long as txsm is 1118 * transmitting or waiting for ack. 1119 */ 1120 HAL_BOOL bt_txstate_extend; 1121 1122 /* 1123 * extend rx_clear so that when tx_frame 1124 * is asserted, rx_clear will drop. 1125 */ 1126 HAL_BOOL bt_txframe_extend; 1127 1128 /* 1129 * coexistence mode 1130 */ 1131 HAL_BT_COEX_MODE bt_mode; 1132 1133 /* 1134 * treat BT high priority traffic as 1135 * a quiet collision 1136 */ 1137 HAL_BOOL bt_quiet_collision; 1138 1139 /* 1140 * invert rx_clear as WLAN_ACTIVE 1141 */ 1142 HAL_BOOL bt_rxclear_polarity; 1143 1144 /* 1145 * slotted mode only. indicate the time in usec 1146 * from the rising edge of BT_ACTIVE to the time 1147 * BT_PRIORITY can be sampled to indicate priority. 1148 */ 1149 u_int8_t bt_priority_time; 1150 1151 /* 1152 * slotted mode only. indicate the time in usec 1153 * from the rising edge of BT_ACTIVE to the time 1154 * BT_PRIORITY can be sampled to indicate tx/rx and 1155 * BT_FREQ is sampled. 1156 */ 1157 u_int8_t bt_first_slot_time; 1158 1159 /* 1160 * slotted mode only. rx_clear and bt_ant decision 1161 * will be held the entire time that BT_ACTIVE is asserted, 1162 * otherwise the decision is made before every slot boundry. 1163 */ 1164 HAL_BOOL bt_hold_rxclear; 1165} HAL_BT_COEX_CONFIG; 1166 1167struct hal_bb_panic_info { 1168 u_int32_t status; 1169 u_int32_t tsf; 1170 u_int32_t phy_panic_wd_ctl1; 1171 u_int32_t phy_panic_wd_ctl2; 1172 u_int32_t phy_gen_ctrl; 1173 u_int32_t rxc_pcnt; 1174 u_int32_t rxf_pcnt; 1175 u_int32_t txf_pcnt; 1176 u_int32_t cycles; 1177 u_int32_t wd; 1178 u_int32_t det; 1179 u_int32_t rdar; 1180 u_int32_t r_odfm; 1181 u_int32_t r_cck; 1182 u_int32_t t_odfm; 1183 u_int32_t t_cck; 1184 u_int32_t agc; 1185 u_int32_t src; 1186}; 1187 1188/* Serialize Register Access Mode */ 1189typedef enum { 1190 SER_REG_MODE_OFF = 0, 1191 SER_REG_MODE_ON = 1, 1192 SER_REG_MODE_AUTO = 2, 1193} SER_REG_MODE; 1194 1195typedef struct 1196{ 1197 int ah_debug; /* only used if AH_DEBUG is defined */ 1198 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 1199 1200 /* NB: these are deprecated; they exist for now for compatibility */ 1201 int ah_dma_beacon_response_time;/* in TU's */ 1202 int ah_sw_beacon_response_time; /* in TU's */ 1203 int ah_additional_swba_backoff; /* in TU's */ 1204 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 1205 int ah_serialise_reg_war; /* force serialisation of register IO */ 1206 1207 /* XXX these don't belong here, they're just for the ar9300 HAL port effort */ 1208 int ath_hal_desc_tpc; /* Per-packet TPC */ 1209 int ath_hal_sta_update_tx_pwr_enable; /* GreenTX */ 1210 int ath_hal_sta_update_tx_pwr_enable_S1; /* GreenTX */ 1211 int ath_hal_sta_update_tx_pwr_enable_S2; /* GreenTX */ 1212 int ath_hal_sta_update_tx_pwr_enable_S3; /* GreenTX */ 1213 1214 /* I'm not sure what the default values for these should be */ 1215 int ath_hal_pll_pwr_save; 1216 int ath_hal_pcie_power_save_enable; 1217 int ath_hal_intr_mitigation_rx; 1218 int ath_hal_intr_mitigation_tx; 1219 1220 int ath_hal_pcie_clock_req; 1221#define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0) 1222#define AR_PCIE_PLL_PWRSAVE_ON_D3 (1<<1) 1223#define AR_PCIE_PLL_PWRSAVE_ON_D0 (1<<2) 1224 1225 int ath_hal_pcie_waen; 1226 int ath_hal_pcie_ser_des_write; 1227 1228 /* these are important for correct AR9300 behaviour */ 1229 int ath_hal_ht_enable; /* needs to be enabled for AR9300 HT */ 1230 int ath_hal_diversity_control; 1231 int ath_hal_antenna_switch_swap; 1232 int ath_hal_ext_lna_ctl_gpio; 1233 int ath_hal_spur_mode; 1234 int ath_hal_6mb_ack; /* should set this to 1 for 11a/11na? */ 1235 int ath_hal_enable_msi; /* enable MSI interrupts (needed?) */ 1236 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */ 1237 1238 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */ 1239 int ath_hal_mfp_support; 1240 1241 int ath_hal_enable_ani; /* should set this.. */ 1242 int ath_hal_cwm_ignore_ext_cca; 1243 int ath_hal_show_bb_panic; 1244 int ath_hal_ant_ctrl_comm2g_switch_enable; 1245 int ath_hal_ext_atten_margin_cfg; 1246 int ath_hal_war70c; 1247} HAL_OPS_CONFIG; 1248 1249/* 1250 * Hardware Access Layer (HAL) API. 1251 * 1252 * Clients of the HAL call ath_hal_attach to obtain a reference to an 1253 * ath_hal structure for use with the device. Hardware-related operations 1254 * that follow must call back into the HAL through interface, supplying 1255 * the reference as the first parameter. Note that before using the 1256 * reference returned by ath_hal_attach the caller should verify the 1257 * ABI version number. 1258 */ 1259struct ath_hal { 1260 uint32_t ah_magic; /* consistency check magic number */ 1261 uint16_t ah_devid; /* PCI device ID */ 1262 uint16_t ah_subvendorid; /* PCI subvendor ID */ 1263 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 1264 HAL_BUS_TAG ah_st; /* params for register r+w */ 1265 HAL_BUS_HANDLE ah_sh; 1266 HAL_CTRY_CODE ah_countryCode; 1267 1268 uint32_t ah_macVersion; /* MAC version id */ 1269 uint16_t ah_macRev; /* MAC revision */ 1270 uint16_t ah_phyRev; /* PHY revision */ 1271 /* NB: when only one radio is present the rev is in 5Ghz */ 1272 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1273 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1274 1275 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1276 1277 uint32_t ah_intrstate[8]; /* last int state */ 1278 uint32_t ah_syncstate; /* last sync intr state */ 1279 1280 HAL_OPS_CONFIG ah_config; 1281 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1282 u_int mode); 1283 void __ahdecl(*ah_detach)(struct ath_hal*); 1284 1285 /* Reset functions */ 1286 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1287 struct ieee80211_channel *, 1288 HAL_BOOL bChannelChange, HAL_STATUS *status); 1289 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1290 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1291 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1292 HAL_BOOL power_off); 1293 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1294 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1295 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1296 struct ieee80211_channel *, HAL_BOOL *); 1297 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1298 struct ieee80211_channel *, u_int chainMask, 1299 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1300 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1301 const struct ieee80211_channel *); 1302 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1303 const struct ieee80211_channel *, uint16_t *); 1304 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1305 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1306 const struct ieee80211_channel *); 1307 1308 /* Transmit functions */ 1309 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1310 HAL_BOOL incTrigLevel); 1311 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1312 const HAL_TXQ_INFO *qInfo); 1313 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1314 const HAL_TXQ_INFO *qInfo); 1315 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1316 HAL_TXQ_INFO *qInfo); 1317 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1318 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1319 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1320 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1321 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1322 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1323 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1324 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1325 u_int pktLen, u_int hdrLen, 1326 HAL_PKT_TYPE type, u_int txPower, 1327 u_int txRate0, u_int txTries0, 1328 u_int keyIx, u_int antMode, u_int flags, 1329 u_int rtsctsRate, u_int rtsctsDuration, 1330 u_int compicvLen, u_int compivLen, 1331 u_int comp); 1332 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1333 u_int txRate1, u_int txTries1, 1334 u_int txRate2, u_int txTries2, 1335 u_int txRate3, u_int txTries3); 1336 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1337 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList, 1338 u_int descId, u_int qcuId, HAL_BOOL firstSeg, 1339 HAL_BOOL lastSeg, const struct ath_desc *); 1340 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1341 struct ath_desc *, struct ath_tx_status *); 1342 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1343 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1344 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1345 const struct ath_desc *ds, int *rates, int *tries); 1346 void __ahdecl(*ah_setTxDescLink)(struct ath_hal *ah, void *ds, 1347 uint32_t link); 1348 void __ahdecl(*ah_getTxDescLink)(struct ath_hal *ah, void *ds, 1349 uint32_t *link); 1350 void __ahdecl(*ah_getTxDescLinkPtr)(struct ath_hal *ah, void *ds, 1351 uint32_t **linkptr); 1352 void __ahdecl(*ah_setupTxStatusRing)(struct ath_hal *, 1353 void *ts_start, uint32_t ts_paddr_start, 1354 uint16_t size); 1355 void __ahdecl(*ah_getTxRawTxDesc)(struct ath_hal *, u_int32_t *); 1356 1357 /* Receive Functions */ 1358 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*, HAL_RX_QUEUE); 1359 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp, HAL_RX_QUEUE); 1360 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1361 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1362 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1363 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1364 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1365 uint32_t filter0, uint32_t filter1); 1366 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1367 uint32_t index); 1368 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1369 uint32_t index); 1370 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1371 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1372 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1373 uint32_t size, u_int flags); 1374 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1375 struct ath_desc *, uint32_t phyAddr, 1376 struct ath_desc *next, uint64_t tsf, 1377 struct ath_rx_status *); 1378 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1379 const HAL_NODE_STATS *, 1380 const struct ieee80211_channel *); 1381 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1382 const struct ieee80211_channel *); 1383 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1384 const HAL_NODE_STATS *); 1385 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 1386 struct ath_rx_status *, 1387 unsigned long, int); 1388 1389 /* Misc Functions */ 1390 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1391 HAL_CAPABILITY_TYPE, uint32_t capability, 1392 uint32_t *result); 1393 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1394 HAL_CAPABILITY_TYPE, uint32_t capability, 1395 uint32_t setting, HAL_STATUS *); 1396 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1397 const void *args, uint32_t argsize, 1398 void **result, uint32_t *resultsize); 1399 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1400 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1401 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1402 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1403 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1404 uint16_t, HAL_STATUS *); 1405 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1406 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1407 const uint8_t *bssid, uint16_t assocId); 1408 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1409 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1410 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1411 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1412 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1413 uint32_t gpio, uint32_t val); 1414 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1415 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1416 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1417 void __ahdecl(*ah_setTsf64)(struct ath_hal *, uint64_t); 1418 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1419 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1420 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1421 HAL_MIB_STATS*); 1422 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1423 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1424 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1425 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1426 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1427 HAL_ANT_SETTING); 1428 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1429 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1430 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1431 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1432 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1433 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1434 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1435 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1436 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1437 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1438 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1439 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1440 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1441 uint32_t duration, uint32_t nextStart, 1442 HAL_QUIET_FLAG flag); 1443 void __ahdecl(*ah_setChainMasks)(struct ath_hal *, 1444 uint32_t, uint32_t); 1445 1446 /* DFS functions */ 1447 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1448 HAL_PHYERR_PARAM *pe); 1449 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1450 HAL_PHYERR_PARAM *pe); 1451 HAL_BOOL __ahdecl(*ah_getDfsDefaultThresh)(struct ath_hal *ah, 1452 HAL_PHYERR_PARAM *pe); 1453 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1454 struct ath_rx_status *rxs, uint64_t fulltsf, 1455 const char *buf, HAL_DFS_EVENT *event); 1456 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1457 1458 /* Spectral Scan functions */ 1459 void __ahdecl(*ah_spectralConfigure)(struct ath_hal *ah, 1460 HAL_SPECTRAL_PARAM *sp); 1461 void __ahdecl(*ah_spectralGetConfig)(struct ath_hal *ah, 1462 HAL_SPECTRAL_PARAM *sp); 1463 void __ahdecl(*ah_spectralStart)(struct ath_hal *); 1464 void __ahdecl(*ah_spectralStop)(struct ath_hal *); 1465 HAL_BOOL __ahdecl(*ah_spectralIsEnabled)(struct ath_hal *); 1466 HAL_BOOL __ahdecl(*ah_spectralIsActive)(struct ath_hal *); 1467 /* XXX getNfPri() and getNfExt() */ 1468 1469 /* Key Cache Functions */ 1470 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1471 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1472 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1473 uint16_t); 1474 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1475 uint16_t, const HAL_KEYVAL *, 1476 const uint8_t *, int); 1477 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1478 uint16_t, const uint8_t *); 1479 1480 /* Power Management Functions */ 1481 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1482 HAL_POWER_MODE mode, int setChip); 1483 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1484 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1485 const struct ieee80211_channel *); 1486 1487 /* Beacon Management Functions */ 1488 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1489 const HAL_BEACON_TIMERS *); 1490 /* NB: deprecated, use ah_setBeaconTimers instead */ 1491 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1492 uint32_t nexttbtt, uint32_t intval); 1493 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1494 const HAL_BEACON_STATE *); 1495 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1496 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1497 1498 /* 802.11n Functions */ 1499 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1500 struct ath_desc *, 1501 HAL_DMA_ADDR *bufAddrList, 1502 uint32_t *segLenList, 1503 u_int, u_int, HAL_PKT_TYPE, 1504 u_int, HAL_CIPHER, uint8_t, HAL_BOOL, 1505 HAL_BOOL, HAL_BOOL); 1506 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1507 struct ath_desc *, u_int, u_int, u_int, 1508 u_int, u_int, u_int, u_int, u_int); 1509 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1510 struct ath_desc *, const struct ath_desc *); 1511 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1512 struct ath_desc *, u_int, u_int, 1513 HAL_11N_RATE_SERIES [], u_int, u_int); 1514 1515 /* 1516 * The next 4 (set11ntxdesc -> set11naggrlast) are specific 1517 * to the EDMA HAL. Descriptors are chained together by 1518 * using filltxdesc (not ChainTxDesc) and then setting the 1519 * aggregate flags appropriately using first/middle/last. 1520 */ 1521 void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *, 1522 void *, u_int, HAL_PKT_TYPE, u_int, u_int, 1523 u_int); 1524 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1525 struct ath_desc *, u_int, u_int); 1526 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1527 struct ath_desc *, u_int); 1528 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1529 struct ath_desc *); 1530 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1531 struct ath_desc *); 1532 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1533 struct ath_desc *, u_int); 1534 void __ahdecl(*ah_set11nVirtMoreFrag)(struct ath_hal *, 1535 struct ath_desc *, u_int); 1536 1537 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1538 HAL_SURVEY_SAMPLE *); 1539 1540 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1541 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1542 HAL_HT_MACMODE); 1543 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1544 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1545 HAL_HT_RXCLEAR); 1546 1547 /* Interrupt functions */ 1548 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1549 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1550 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1551 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1552 1553 /* Bluetooth Coexistence functions */ 1554 void __ahdecl(*ah_btCoexSetInfo)(struct ath_hal *, 1555 HAL_BT_COEX_INFO *); 1556 void __ahdecl(*ah_btCoexSetConfig)(struct ath_hal *, 1557 HAL_BT_COEX_CONFIG *); 1558 void __ahdecl(*ah_btCoexSetQcuThresh)(struct ath_hal *, 1559 int); 1560 void __ahdecl(*ah_btCoexSetWeights)(struct ath_hal *, 1561 uint32_t); 1562 void __ahdecl(*ah_btCoexSetBmissThresh)(struct ath_hal *, 1563 uint32_t); 1564 void __ahdecl(*ah_btcoexSetParameter)(struct ath_hal *, 1565 uint32_t, uint32_t); 1566 void __ahdecl(*ah_btCoexDisable)(struct ath_hal *); 1567 int __ahdecl(*ah_btCoexEnable)(struct ath_hal *); 1568}; 1569 1570/* 1571 * Check the PCI vendor ID and device ID against Atheros' values 1572 * and return a printable description for any Atheros hardware. 1573 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1574 */ 1575extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1576 1577/* 1578 * Attach the HAL for use with the specified device. The device is 1579 * defined by the PCI device ID. The caller provides an opaque pointer 1580 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1581 * HAL state block for later use. Hardware register accesses are done 1582 * using the specified bus tag and handle. On successful return a 1583 * reference to a state block is returned that must be supplied in all 1584 * subsequent HAL calls. Storage associated with this reference is 1585 * dynamically allocated and must be freed by calling the ah_detach 1586 * method when the client is done. If the attach operation fails a 1587 * null (AH_NULL) reference will be returned and a status code will 1588 * be returned if the status parameter is non-zero. 1589 */ 1590extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1591 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1592 1593extern const char *ath_hal_mac_name(struct ath_hal *); 1594extern const char *ath_hal_rf_name(struct ath_hal *); 1595 1596/* 1597 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1598 * request a set of channels for a particular country code and/or 1599 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1600 * this list is constructed according to the contents of the EEPROM. 1601 * ath_hal_getchannels acts similarly but does not alter the operating 1602 * state; this can be used to collect information for a particular 1603 * regulatory configuration. Finally ath_hal_set_channels installs a 1604 * channel list constructed outside the driver. The HAL will adopt the 1605 * channel list and setup internal state according to the specified 1606 * regulatory configuration (e.g. conformance test limits). 1607 * 1608 * For all interfaces the channel list is returned in the supplied array. 1609 * maxchans defines the maximum size of this array. nchans contains the 1610 * actual number of channels returned. If a problem occurred then a 1611 * status code != HAL_OK is returned. 1612 */ 1613struct ieee80211_channel; 1614 1615/* 1616 * Return a list of channels according to the specified regulatory. 1617 */ 1618extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1619 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1620 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1621 HAL_BOOL enableExtendedChannels); 1622 1623/* 1624 * Return a list of channels and install it as the current operating 1625 * regulatory list. 1626 */ 1627extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1628 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1629 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1630 HAL_BOOL enableExtendedChannels); 1631 1632/* 1633 * Install the list of channels as the current operating regulatory 1634 * and setup related state according to the country code and sku. 1635 */ 1636extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1637 struct ieee80211_channel *chans, int nchans, 1638 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1639 1640/* 1641 * Fetch the ctl/ext noise floor values reported by a MIMO 1642 * radio. Returns 1 for valid results, 0 for invalid channel. 1643 */ 1644extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1645 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1646 int16_t *nf_ext); 1647 1648/* 1649 * Calibrate noise floor data following a channel scan or similar. 1650 * This must be called prior retrieving noise floor data. 1651 */ 1652extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1653 1654/* 1655 * Return bit mask of wireless modes supported by the hardware. 1656 */ 1657extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1658 1659/* 1660 * Get the HAL wireless mode for the given channel. 1661 */ 1662extern int ath_hal_get_curmode(struct ath_hal *ah, 1663 const struct ieee80211_channel *chan); 1664 1665/* 1666 * Calculate the packet TX time for a legacy or 11n frame 1667 */ 1668extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1669 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1670 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1671 1672/* 1673 * Calculate the duration of an 11n frame. 1674 */ 1675extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1676 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1677 1678/* 1679 * Calculate the transmit duration of a legacy frame. 1680 */ 1681extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1682 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1683 uint16_t rateix, HAL_BOOL shortPreamble); 1684 1685/* 1686 * Adjust the TSF. 1687 */ 1688extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1689 1690/* 1691 * Enable or disable CCA. 1692 */ 1693void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1694 1695/* 1696 * Get CCA setting. 1697 */ 1698int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1699 1700/* 1701 * Read EEPROM data from ah_eepromdata 1702 */ 1703HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1704 u_int off, uint16_t *data); 1705 1706/* 1707 * For now, simply pass through MFP frames. 1708 */ 1709static inline u_int32_t 1710ath_hal_get_mfp_qos(struct ath_hal *ah) 1711{ 1712 //return AH_PRIVATE(ah)->ah_mfp_qos; 1713 return HAL_MFP_QOSDATA; 1714} 1715 1716#endif /* _ATH_AH_H_ */ 1717