ah.h revision 237957
1217044Snwhitehorn/* 2217044Snwhitehorn * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3217044Snwhitehorn * Copyright (c) 2002-2008 Atheros Communications, Inc. 4217044Snwhitehorn * 5217044Snwhitehorn * Permission to use, copy, modify, and/or distribute this software for any 6217044Snwhitehorn * purpose with or without fee is hereby granted, provided that the above 7217044Snwhitehorn * copyright notice and this permission notice appear in all copies. 8217044Snwhitehorn * 9217044Snwhitehorn * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10217044Snwhitehorn * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11217044Snwhitehorn * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12217044Snwhitehorn * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13217044Snwhitehorn * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14217044Snwhitehorn * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15217044Snwhitehorn * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16217044Snwhitehorn * 17217044Snwhitehorn * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 237957 2012-07-02 06:07:46Z adrian $ 18217044Snwhitehorn */ 19217044Snwhitehorn 20217044Snwhitehorn#ifndef _ATH_AH_H_ 21217044Snwhitehorn#define _ATH_AH_H_ 22217044Snwhitehorn/* 23217044Snwhitehorn * Atheros Hardware Access Layer 24217044Snwhitehorn * 25217044Snwhitehorn * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26217044Snwhitehorn * structure for use with the device. Hardware-related operations that 27217044Snwhitehorn * follow must call back into the HAL through interface, supplying the 28217044Snwhitehorn * reference as the first parameter. 29217044Snwhitehorn */ 30217044Snwhitehorn 31217044Snwhitehorn#include "ah_osdep.h" 32217044Snwhitehorn 33217044Snwhitehorn/* 34217044Snwhitehorn * The maximum number of TX/RX chains supported. 35217044Snwhitehorn * This is intended to be used by various statistics gathering operations 36217044Snwhitehorn * (NF, RSSI, EVM). 37217044Snwhitehorn */ 38217044Snwhitehorn#define AH_MIMO_MAX_CHAINS 3 39217044Snwhitehorn#define AH_MIMO_MAX_EVM_PILOTS 6 40217044Snwhitehorn 41217044Snwhitehorn/* 42217044Snwhitehorn * __ahdecl is analogous to _cdecl; it defines the calling 43217044Snwhitehorn * convention used within the HAL. For most systems this 44217044Snwhitehorn * can just default to be empty and the compiler will (should) 45217044Snwhitehorn * use _cdecl. For systems where _cdecl is not compatible this 46217044Snwhitehorn * must be defined. See linux/ah_osdep.h for an example. 47217044Snwhitehorn */ 48217044Snwhitehorn#ifndef __ahdecl 49217044Snwhitehorn#define __ahdecl 50217044Snwhitehorn#endif 51217044Snwhitehorn 52217044Snwhitehorn/* 53217044Snwhitehorn * Status codes that may be returned by the HAL. Note that 54217044Snwhitehorn * interfaces that return a status code set it only when an 55217044Snwhitehorn * error occurs--i.e. you cannot check it for success. 56217044Snwhitehorn */ 57217044Snwhitehorntypedef enum { 58217044Snwhitehorn HAL_OK = 0, /* No error */ 59217044Snwhitehorn HAL_ENXIO = 1, /* No hardware present */ 60217044Snwhitehorn HAL_ENOMEM = 2, /* Memory allocation failed */ 61217044Snwhitehorn HAL_EIO = 3, /* Hardware didn't respond as expected */ 62217044Snwhitehorn HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63217044Snwhitehorn HAL_EEVERSION = 5, /* EEPROM version invalid */ 64217044Snwhitehorn HAL_EELOCKED = 6, /* EEPROM unreadable */ 65217044Snwhitehorn HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66217044Snwhitehorn HAL_EEREAD = 8, /* EEPROM read problem */ 67217044Snwhitehorn HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68217044Snwhitehorn HAL_EESIZE = 10, /* EEPROM size not supported */ 69217044Snwhitehorn HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70217044Snwhitehorn HAL_EINVAL = 12, /* Invalid parameter to function */ 71224106Snwhitehorn HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72224857Snwhitehorn HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73224106Snwhitehorn HAL_EINPROGRESS = 15, /* Operation incomplete */ 74224857Snwhitehorn HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75224857Snwhitehorn HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76224857Snwhitehorn HAL_INV_PMODE = 18, /* Couldn't bring out of sleep state */ 77224857Snwhitehorn} HAL_STATUS; 78224106Snwhitehorn 79217044Snwhitehorntypedef enum { 80217044Snwhitehorn AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 81 AH_TRUE = 1, 82} HAL_BOOL; 83 84typedef enum { 85 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 86 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 87 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 88 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 89 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 90 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 91 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 92 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 93 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 94 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 95 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 96 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 97 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 98 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 99 HAL_CAP_TXPOW = 15, /* global tx power limit */ 100 HAL_CAP_TPC = 16, /* per-packet tx power control */ 101 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 102 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 103 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 104 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 105 /* 21 was HAL_CAP_XR */ 106 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 107 /* 23 was HAL_CAP_CHAN_HALFRATE */ 108 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 109 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 110 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 111 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 112 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 113 HAL_CAP_PCIE_PS = 29, 114 HAL_CAP_HT = 30, /* hardware can support HT */ 115 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 116 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 117 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 118 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 119 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 120 121 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 122 123 HAL_CAP_RIFS_RX = 39, 124 HAL_CAP_RIFS_TX = 40, 125 HAL_CAP_FORCE_PPM = 41, 126 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 127 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 128 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 129 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 130 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 131 132 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 133 automatically after waking up to receive TIM */ 134 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 135 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 136 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 137 HAL_CAP_BB_RIFS_HANG = 52, 138 HAL_CAP_RIFS_RX_ENABLED = 53, 139 HAL_CAP_BB_DFS_HANG = 54, 140 141 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 142 HAL_CAP_DYNAMIC_SMPS = 61, /* Dynamic MIMO Power Save hardware support */ 143 144 HAL_CAP_DS = 67, /* 2 stream */ 145 HAL_CAP_BB_RX_CLEAR_STUCK_HANG = 68, 146 HAL_CAP_MAC_HANG = 69, /* can MAC hang */ 147 HAL_CAP_MFP = 70, /* Management Frame Protection in hardware */ 148 149 HAL_CAP_TS = 72, /* 3 stream */ 150 151 HAL_CAP_ENHANCED_DMA_SUPPORT = 75, /* DMA FIFO support */ 152 153 HAL_CAP_RXBUFSIZE = 81, 154 HAL_CAP_NUM_MR_RETRIES = 82, 155 HAL_CAP_OL_PWRCTRL = 84, /* Open loop TX power control */ 156 157 HAL_CAP_BB_PANIC_WATCHDOG = 92, 158 159 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 160 161 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 162 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 163 164 /* The following are private to the FreeBSD HAL (224 onward) */ 165 166 HAL_CAP_INTMIT = 229, /* interference mitigation */ 167 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 168 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 169 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 170 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 171 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 172 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 173 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 174 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 175 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 176} HAL_CAPABILITY_TYPE; 177 178/* 179 * "States" for setting the LED. These correspond to 180 * the possible 802.11 operational states and there may 181 * be a many-to-one mapping between these states and the 182 * actual hardware state for the LED's (i.e. the hardware 183 * may have fewer states). 184 */ 185typedef enum { 186 HAL_LED_INIT = 0, 187 HAL_LED_SCAN = 1, 188 HAL_LED_AUTH = 2, 189 HAL_LED_ASSOC = 3, 190 HAL_LED_RUN = 4 191} HAL_LED_STATE; 192 193/* 194 * Transmit queue types/numbers. These are used to tag 195 * each transmit queue in the hardware and to identify a set 196 * of transmit queues for operations such as start/stop dma. 197 */ 198typedef enum { 199 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 200 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 201 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 202 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 203 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 204 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 205 HAL_TX_QUEUE_CFEND = 6, 206 HAL_TX_QUEUE_PAPRD = 7, 207} HAL_TX_QUEUE; 208 209#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 210 211typedef enum { 212 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */ 213 HAL_RX_QUEUE_LP = 0, /* low priority recv queue */ 214} HAL_RX_QUEUE; 215 216#define HAL_NUM_RX_QUEUES 2 /* max possible # of queues */ 217 218/* 219 * Transmit queue subtype. These map directly to 220 * WME Access Categories (except for UPSD). Refer 221 * to Table 5 of the WME spec. 222 */ 223typedef enum { 224 HAL_WME_AC_BK = 0, /* background access category */ 225 HAL_WME_AC_BE = 1, /* best effort access category*/ 226 HAL_WME_AC_VI = 2, /* video access category */ 227 HAL_WME_AC_VO = 3, /* voice access category */ 228 HAL_WME_UPSD = 4, /* uplink power save */ 229} HAL_TX_QUEUE_SUBTYPE; 230 231/* 232 * Transmit queue flags that control various 233 * operational parameters. 234 */ 235typedef enum { 236 /* 237 * Per queue interrupt enables. When set the associated 238 * interrupt may be delivered for packets sent through 239 * the queue. Without these enabled no interrupts will 240 * be delivered for transmits through the queue. 241 */ 242 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 243 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 244 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 245 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 246 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 247 /* 248 * Enable hardware compression for packets sent through 249 * the queue. The compression buffer must be setup and 250 * packets must have a key entry marked in the tx descriptor. 251 */ 252 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 253 /* 254 * Disable queue when veol is hit or ready time expires. 255 * By default the queue is disabled only on reaching the 256 * physical end of queue (i.e. a null link ptr in the 257 * descriptor chain). 258 */ 259 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 260 /* 261 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 262 * event. Frames will be transmitted only when this timer 263 * fires, e.g to transmit a beacon in ap or adhoc modes. 264 */ 265 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 266 /* 267 * Each transmit queue has a counter that is incremented 268 * each time the queue is enabled and decremented when 269 * the list of frames to transmit is traversed (or when 270 * the ready time for the queue expires). This counter 271 * must be non-zero for frames to be scheduled for 272 * transmission. The following controls disable bumping 273 * this counter under certain conditions. Typically this 274 * is used to gate frames based on the contents of another 275 * queue (e.g. CAB traffic may only follow a beacon frame). 276 * These are meaningful only when frames are scheduled 277 * with a non-ASAP policy (e.g. DBA-gated). 278 */ 279 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 280 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 281 282 /* 283 * Fragment burst backoff policy. Normally the no backoff 284 * is done after a successful transmission, the next fragment 285 * is sent at SIFS. If this flag is set backoff is done 286 * after each fragment, regardless whether it was ack'd or 287 * not, after the backoff count reaches zero a normal channel 288 * access procedure is done before the next transmit (i.e. 289 * wait AIFS instead of SIFS). 290 */ 291 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 292 /* 293 * Disable post-tx backoff following each frame. 294 */ 295 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 296 /* 297 * DCU arbiter lockout control. This controls how 298 * lower priority tx queues are handled with respect to 299 * to a specific queue when multiple queues have frames 300 * to send. No lockout means lower priority queues arbitrate 301 * concurrently with this queue. Intra-frame lockout 302 * means lower priority queues are locked out until the 303 * current frame transmits (e.g. including backoffs and bursting). 304 * Global lockout means nothing lower can arbitrary so 305 * long as there is traffic activity on this queue (frames, 306 * backoff, etc). 307 */ 308 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 309 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 310 311 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 312 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 313} HAL_TX_QUEUE_FLAGS; 314 315typedef struct { 316 uint32_t tqi_ver; /* hal TXQ version */ 317 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 318 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 319 uint32_t tqi_priority; /* (not used) */ 320 uint32_t tqi_aifs; /* aifs */ 321 uint32_t tqi_cwmin; /* cwMin */ 322 uint32_t tqi_cwmax; /* cwMax */ 323 uint16_t tqi_shretry; /* rts retry limit */ 324 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 325 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 326 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 327 uint32_t tqi_burstTime; /* max burst duration (us) */ 328 uint32_t tqi_readyTime; /* frame schedule time (us) */ 329 uint32_t tqi_compBuf; /* comp buffer phys addr */ 330} HAL_TXQ_INFO; 331 332#define HAL_TQI_NONVAL 0xffff 333 334/* token to use for aifs, cwmin, cwmax */ 335#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 336 337/* compression definitions */ 338#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 339#define HAL_COMP_BUF_ALIGN_SIZE 512 340 341/* 342 * Transmit packet types. This belongs in ah_desc.h, but 343 * is here so we can give a proper type to various parameters 344 * (and not require everyone include the file). 345 * 346 * NB: These values are intentionally assigned for 347 * direct use when setting up h/w descriptors. 348 */ 349typedef enum { 350 HAL_PKT_TYPE_NORMAL = 0, 351 HAL_PKT_TYPE_ATIM = 1, 352 HAL_PKT_TYPE_PSPOLL = 2, 353 HAL_PKT_TYPE_BEACON = 3, 354 HAL_PKT_TYPE_PROBE_RESP = 4, 355 HAL_PKT_TYPE_CHIRP = 5, 356 HAL_PKT_TYPE_GRP_POLL = 6, 357 HAL_PKT_TYPE_AMPDU = 7, 358} HAL_PKT_TYPE; 359 360/* Rx Filter Frame Types */ 361typedef enum { 362 /* 363 * These bits correspond to AR_RX_FILTER for all chips. 364 * Not all bits are supported by all chips. 365 */ 366 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 367 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 368 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 369 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 370 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 371 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 372 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 373 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 374 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 375 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 376 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 377 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 378 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 379 /* Allow all mcast/bcast frames */ 380 381 /* 382 * Magic RX filter flags that aren't targetting hardware bits 383 * but instead the HAL sets individual bits - eg PHYERR will result 384 * in OFDM/CCK timing error frames being received. 385 */ 386 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 387} HAL_RX_FILTER; 388 389typedef enum { 390 HAL_PM_AWAKE = 0, 391 HAL_PM_FULL_SLEEP = 1, 392 HAL_PM_NETWORK_SLEEP = 2, 393 HAL_PM_UNDEFINED = 3 394} HAL_POWER_MODE; 395 396/* 397 * NOTE WELL: 398 * These are mapped to take advantage of the common locations for many of 399 * the bits on all of the currently supported MAC chips. This is to make 400 * the ISR as efficient as possible, while still abstracting HW differences. 401 * When new hardware breaks this commonality this enumerated type, as well 402 * as the HAL functions using it, must be modified. All values are directly 403 * mapped unless commented otherwise. 404 */ 405typedef enum { 406 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 407 HAL_INT_RXDESC = 0x00000002, 408 HAL_INT_RXNOFRM = 0x00000008, 409 HAL_INT_RXEOL = 0x00000010, 410 HAL_INT_RXORN = 0x00000020, 411 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 412 HAL_INT_TXDESC = 0x00000080, 413 HAL_INT_TIM_TIMER= 0x00000100, 414 HAL_INT_TXURN = 0x00000800, 415 HAL_INT_MIB = 0x00001000, 416 HAL_INT_RXPHY = 0x00004000, 417 HAL_INT_RXKCM = 0x00008000, 418 HAL_INT_SWBA = 0x00010000, 419 HAL_INT_BMISS = 0x00040000, 420 HAL_INT_BNR = 0x00100000, 421 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 422 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 423 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 424 HAL_INT_GPIO = 0x01000000, 425 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 426 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 427 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 428 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 429 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 430 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 431#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 432 HAL_INT_BMISC = HAL_INT_TIM 433 | HAL_INT_DTIM 434 | HAL_INT_DTIMSYNC 435 | HAL_INT_CABEND 436 | HAL_INT_TBTT, 437 438 /* Interrupt bits that map directly to ISR/IMR bits */ 439 HAL_INT_COMMON = HAL_INT_RXNOFRM 440 | HAL_INT_RXDESC 441 | HAL_INT_RXEOL 442 | HAL_INT_RXORN 443 | HAL_INT_TXDESC 444 | HAL_INT_TXURN 445 | HAL_INT_MIB 446 | HAL_INT_RXPHY 447 | HAL_INT_RXKCM 448 | HAL_INT_SWBA 449 | HAL_INT_BMISS 450 | HAL_INT_BNR 451 | HAL_INT_GPIO, 452} HAL_INT; 453 454/* 455 * MSI vector assignments 456 */ 457typedef enum { 458 HAL_MSIVEC_MISC = 0, 459 HAL_MSIVEC_TX = 1, 460 HAL_MSIVEC_RXLP = 2, 461 HAL_MSIVEC_RXHP = 3, 462} HAL_MSIVEC; 463 464typedef enum { 465 HAL_INT_LINE = 0, 466 HAL_INT_MSI = 1, 467} HAL_INT_TYPE; 468 469/* For interrupt mitigation registers */ 470typedef enum { 471 HAL_INT_RX_FIRSTPKT=0, 472 HAL_INT_RX_LASTPKT, 473 HAL_INT_TX_FIRSTPKT, 474 HAL_INT_TX_LASTPKT, 475 HAL_INT_THRESHOLD 476} HAL_INT_MITIGATION; 477 478typedef enum { 479 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0, 480 HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED = 1, 481 HAL_GPIO_OUTPUT_MUX_PCIE_POWER_LED = 2, 482 HAL_GPIO_OUTPUT_MUX_MAC_NETWORK_LED = 3, 483 HAL_GPIO_OUTPUT_MUX_MAC_POWER_LED = 4, 484 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE = 5, 485 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME = 6 486} HAL_GPIO_MUX_TYPE; 487 488typedef enum { 489 HAL_GPIO_INTR_LOW = 0, 490 HAL_GPIO_INTR_HIGH = 1, 491 HAL_GPIO_INTR_DISABLE = 2 492} HAL_GPIO_INTR_TYPE; 493 494typedef enum { 495 HAL_RFGAIN_INACTIVE = 0, 496 HAL_RFGAIN_READ_REQUESTED = 1, 497 HAL_RFGAIN_NEED_CHANGE = 2 498} HAL_RFGAIN; 499 500typedef uint16_t HAL_CTRY_CODE; /* country code */ 501typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 502 503#define HAL_ANTENNA_MIN_MODE 0 504#define HAL_ANTENNA_FIXED_A 1 505#define HAL_ANTENNA_FIXED_B 2 506#define HAL_ANTENNA_MAX_MODE 3 507 508typedef struct { 509 uint32_t ackrcv_bad; 510 uint32_t rts_bad; 511 uint32_t rts_good; 512 uint32_t fcs_bad; 513 uint32_t beacons; 514} HAL_MIB_STATS; 515 516enum { 517 HAL_MODE_11A = 0x001, /* 11a channels */ 518 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 519 HAL_MODE_11B = 0x004, /* 11b channels */ 520 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 521#ifdef notdef 522 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 523#else 524 HAL_MODE_11G = 0x008, /* XXX historical */ 525#endif 526 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 527 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 528 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 529 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 530 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 531 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 532 HAL_MODE_11NG_HT20 = 0x008000, 533 HAL_MODE_11NA_HT20 = 0x010000, 534 HAL_MODE_11NG_HT40PLUS = 0x020000, 535 HAL_MODE_11NG_HT40MINUS = 0x040000, 536 HAL_MODE_11NA_HT40PLUS = 0x080000, 537 HAL_MODE_11NA_HT40MINUS = 0x100000, 538 HAL_MODE_ALL = 0xffffff 539}; 540 541typedef struct { 542 int rateCount; /* NB: for proper padding */ 543 uint8_t rateCodeToIndex[144]; /* back mapping */ 544 struct { 545 uint8_t valid; /* valid for rate control use */ 546 uint8_t phy; /* CCK/OFDM/XR */ 547 uint32_t rateKbps; /* transfer rate in kbs */ 548 uint8_t rateCode; /* rate for h/w descriptors */ 549 uint8_t shortPreamble; /* mask for enabling short 550 * preamble in CCK rate code */ 551 uint8_t dot11Rate; /* value for supported rates 552 * info element of MLME */ 553 uint8_t controlRate; /* index of next lower basic 554 * rate; used for dur. calcs */ 555 uint16_t lpAckDuration; /* long preamble ACK duration */ 556 uint16_t spAckDuration; /* short preamble ACK duration*/ 557 } info[32]; 558} HAL_RATE_TABLE; 559 560typedef struct { 561 u_int rs_count; /* number of valid entries */ 562 uint8_t rs_rates[32]; /* rates */ 563} HAL_RATE_SET; 564 565/* 566 * 802.11n specific structures and enums 567 */ 568typedef enum { 569 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 570 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 571} HAL_CHAIN_TYPE; 572 573typedef struct { 574 u_int Tries; 575 u_int Rate; 576 u_int PktDuration; 577 u_int ChSel; 578 u_int RateFlags; 579#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 580#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 581#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 582} HAL_11N_RATE_SERIES; 583 584typedef enum { 585 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 586 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 587} HAL_HT_MACMODE; 588 589typedef enum { 590 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 591 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 592} HAL_HT_PHYMODE; 593 594typedef enum { 595 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 596 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 597} HAL_HT_EXTPROTSPACING; 598 599 600typedef enum { 601 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 602 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 603} HAL_HT_RXCLEAR; 604 605/* 606 * Antenna switch control. By default antenna selection 607 * enables multiple (2) antenna use. To force use of the 608 * A or B antenna only specify a fixed setting. Fixing 609 * the antenna will also disable any diversity support. 610 */ 611typedef enum { 612 HAL_ANT_VARIABLE = 0, /* variable by programming */ 613 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 614 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 615} HAL_ANT_SETTING; 616 617typedef enum { 618 HAL_M_STA = 1, /* infrastructure station */ 619 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 620 HAL_M_HOSTAP = 6, /* Software Access Point */ 621 HAL_M_MONITOR = 8 /* Monitor mode */ 622} HAL_OPMODE; 623 624typedef struct { 625 uint8_t kv_type; /* one of HAL_CIPHER */ 626 uint8_t kv_apsd; /* Mask for APSD enabled ACs */ 627 uint16_t kv_len; /* length in bits */ 628 uint8_t kv_val[16]; /* enough for 128-bit keys */ 629 uint8_t kv_mic[8]; /* TKIP MIC key */ 630 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 631} HAL_KEYVAL; 632 633typedef enum { 634 HAL_CIPHER_WEP = 0, 635 HAL_CIPHER_AES_OCB = 1, 636 HAL_CIPHER_AES_CCM = 2, 637 HAL_CIPHER_CKIP = 3, 638 HAL_CIPHER_TKIP = 4, 639 HAL_CIPHER_CLR = 5, /* no encryption */ 640 641 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 642} HAL_CIPHER; 643 644enum { 645 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 646 HAL_SLOT_TIME_9 = 9, 647 HAL_SLOT_TIME_20 = 20, 648}; 649 650/* 651 * Per-station beacon timer state. Note that the specified 652 * beacon interval (given in TU's) can also include flags 653 * to force a TSF reset and to enable the beacon xmit logic. 654 * If bs_cfpmaxduration is non-zero the hardware is setup to 655 * coexist with a PCF-capable AP. 656 */ 657typedef struct { 658 uint32_t bs_nexttbtt; /* next beacon in TU */ 659 uint32_t bs_nextdtim; /* next DTIM in TU */ 660 uint32_t bs_intval; /* beacon interval+flags */ 661#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 662#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 663#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 664 uint32_t bs_dtimperiod; 665 uint16_t bs_cfpperiod; /* CFP period in TU */ 666 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 667 uint32_t bs_cfpnext; /* next CFP in TU */ 668 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 669 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 670 uint32_t bs_sleepduration; /* max sleep duration */ 671} HAL_BEACON_STATE; 672 673/* 674 * Like HAL_BEACON_STATE but for non-station mode setup. 675 * NB: see above flag definitions for bt_intval. 676 */ 677typedef struct { 678 uint32_t bt_intval; /* beacon interval+flags */ 679 uint32_t bt_nexttbtt; /* next beacon in TU */ 680 uint32_t bt_nextatim; /* next ATIM in TU */ 681 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 682 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 683 uint32_t bt_flags; /* timer enables */ 684#define HAL_BEACON_TBTT_EN 0x00000001 685#define HAL_BEACON_DBA_EN 0x00000002 686#define HAL_BEACON_SWBA_EN 0x00000004 687} HAL_BEACON_TIMERS; 688 689/* 690 * Per-node statistics maintained by the driver for use in 691 * optimizing signal quality and other operational aspects. 692 */ 693typedef struct { 694 uint32_t ns_avgbrssi; /* average beacon rssi */ 695 uint32_t ns_avgrssi; /* average data rssi */ 696 uint32_t ns_avgtxrssi; /* average tx rssi */ 697} HAL_NODE_STATS; 698 699#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 700 701struct ath_desc; 702struct ath_tx_status; 703struct ath_rx_status; 704struct ieee80211_channel; 705 706/* 707 * This is a channel survey sample entry. 708 * 709 * The AR5212 ANI routines fill these samples. The ANI code then uses it 710 * when calculating listen time; it is also exported via a diagnostic 711 * API. 712 */ 713typedef struct { 714 uint32_t seq_num; 715 uint32_t tx_busy; 716 uint32_t rx_busy; 717 uint32_t chan_busy; 718 uint32_t ext_chan_busy; 719 uint32_t cycle_count; 720 /* XXX TODO */ 721 uint32_t ofdm_phyerr_count; 722 uint32_t cck_phyerr_count; 723} HAL_SURVEY_SAMPLE; 724 725/* 726 * This provides 3.2 seconds of sample space given an 727 * ANI time of 1/10th of a second. This may not be enough! 728 */ 729#define CHANNEL_SURVEY_SAMPLE_COUNT 32 730 731typedef struct { 732 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 733 uint32_t cur_sample; /* current sample in sequence */ 734 uint32_t cur_seq; /* current sequence number */ 735} HAL_CHANNEL_SURVEY; 736 737/* 738 * ANI commands. 739 * 740 * These are used both internally and externally via the diagnostic 741 * API. 742 * 743 * Note that this is NOT the ANI commands being used via the INTMIT 744 * capability - that has a different mapping for some reason. 745 */ 746typedef enum { 747 HAL_ANI_PRESENT = 0, /* is ANI support present */ 748 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 749 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 750 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 751 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 752 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 753 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 754 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 755 HAL_ANI_MRC_CCK = 8, 756} HAL_ANI_CMD; 757 758/* 759 * This is the layout of the ANI INTMIT capability. 760 * 761 * Notice that the command values differ to HAL_ANI_CMD. 762 */ 763typedef enum { 764 HAL_CAP_INTMIT_PRESENT = 0, 765 HAL_CAP_INTMIT_ENABLE = 1, 766 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 767 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 768 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 769 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 770 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 771} HAL_CAP_INTMIT_CMD; 772 773/* DFS defines */ 774typedef struct { 775 int32_t pe_firpwr; /* FIR pwr out threshold */ 776 int32_t pe_rrssi; /* Radar rssi thresh */ 777 int32_t pe_height; /* Pulse height thresh */ 778 int32_t pe_prssi; /* Pulse rssi thresh */ 779 int32_t pe_inband; /* Inband thresh */ 780 781 /* The following params are only for AR5413 and later */ 782 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 783 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 784 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 785 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 786 int32_t pe_blockradar; /* 787 * Enable to block radar check if pkt detect is done via OFDM 788 * weak signal detect or pkt is detected immediately after tx 789 * to rx transition 790 */ 791 int32_t pe_enmaxrssi; /* 792 * Enable to use the max rssi instead of the last rssi during 793 * fine gain changes for radar detection 794 */ 795 int32_t pe_extchannel; /* Enable DFS on ext channel */ 796 int32_t pe_enabled; /* Whether radar detection is enabled */ 797 int32_t pe_enrelpwr; 798 int32_t pe_en_relstep_check; 799} HAL_PHYERR_PARAM; 800 801#define HAL_PHYERR_PARAM_NOVAL 65535 802 803/* 804 * DFS operating mode flags. 805 */ 806typedef enum { 807 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 808 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 809 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 810 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 811} HAL_DFS_DOMAIN; 812 813/* 814 * Flag for setting QUIET period 815 */ 816typedef enum { 817 HAL_QUIET_DISABLE = 0x0, 818 HAL_QUIET_ENABLE = 0x1, 819 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 820 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 821} HAL_QUIET_FLAG; 822 823#define HAL_DFS_EVENT_PRICH 0x0000001 824#define HAL_DFS_EVENT_EXTCH 0x0000002 825#define HAL_DFS_EVENT_EXTEARLY 0x0000004 826#define HAL_DFS_EVENT_ISDC 0x0000008 827 828struct hal_dfs_event { 829 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 830 uint32_t re_ts; /* Original 15 bit recv timestamp */ 831 uint8_t re_rssi; /* rssi of radar event */ 832 uint8_t re_dur; /* duration of radar pulse */ 833 uint32_t re_flags; /* Flags (see above) */ 834}; 835typedef struct hal_dfs_event HAL_DFS_EVENT; 836 837/* 838 * BT Co-existence definitions 839 */ 840typedef enum { 841 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */ 842 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */ 843 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */ 844 HAL_MAX_BT_MODULES 845} HAL_BT_MODULE; 846 847typedef struct { 848 HAL_BT_MODULE bt_module; 849 u_int8_t bt_coex_config; 850 u_int8_t bt_gpio_bt_active; 851 u_int8_t bt_gpio_bt_priority; 852 u_int8_t bt_gpio_wlan_active; 853 u_int8_t bt_active_polarity; 854 HAL_BOOL bt_single_ant; 855 u_int8_t bt_dutyCycle; 856 u_int8_t bt_isolation; 857 u_int8_t bt_period; 858} HAL_BT_COEX_INFO; 859 860typedef enum { 861 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */ 862 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */ 863 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */ 864 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */ 865} HAL_BT_COEX_MODE; 866 867typedef enum { 868 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */ 869 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */ 870 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */ 871 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */ 872 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */ 873 HAL_BT_COEX_CFG_MCI /* MCI */ 874} HAL_BT_COEX_CFG; 875 876typedef enum { 877 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */ 878 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */ 879 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */ 880} HAL_BT_COEX_SET_PARAMETER; 881 882#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 883#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 884/* Check Rx Diversity is allowed */ 885#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 886/* Check Diversity is on or off */ 887#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 888 889#define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b 890/* main: LNA1, alt: LNA2 */ 891#define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09 892#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04 893#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09 894#define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02 895#define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06 896 897#define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30 898 899#define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666 900 901#define HAL_BT_COEX_HELIUS_CHAINMASK 0x02 902 903#define HAL_BT_COEX_LOW_ACK_POWER 0x0 904#define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f 905 906typedef enum { 907 HAL_BT_COEX_NO_STOMP = 0, 908 HAL_BT_COEX_STOMP_ALL, 909 HAL_BT_COEX_STOMP_LOW, 910 HAL_BT_COEX_STOMP_NONE, 911 HAL_BT_COEX_STOMP_ALL_FORCE, 912 HAL_BT_COEX_STOMP_LOW_FORCE, 913} HAL_BT_COEX_STOMP_TYPE; 914 915typedef struct { 916 /* extend rx_clear after tx/rx to protect the burst (in usec). */ 917 u_int8_t bt_time_extend; 918 919 /* 920 * extend rx_clear as long as txsm is 921 * transmitting or waiting for ack. 922 */ 923 HAL_BOOL bt_txstate_extend; 924 925 /* 926 * extend rx_clear so that when tx_frame 927 * is asserted, rx_clear will drop. 928 */ 929 HAL_BOOL bt_txframe_extend; 930 931 /* 932 * coexistence mode 933 */ 934 HAL_BT_COEX_MODE bt_mode; 935 936 /* 937 * treat BT high priority traffic as 938 * a quiet collision 939 */ 940 HAL_BOOL bt_quiet_collision; 941 942 /* 943 * invert rx_clear as WLAN_ACTIVE 944 */ 945 HAL_BOOL bt_rxclear_polarity; 946 947 /* 948 * slotted mode only. indicate the time in usec 949 * from the rising edge of BT_ACTIVE to the time 950 * BT_PRIORITY can be sampled to indicate priority. 951 */ 952 u_int8_t bt_priority_time; 953 954 /* 955 * slotted mode only. indicate the time in usec 956 * from the rising edge of BT_ACTIVE to the time 957 * BT_PRIORITY can be sampled to indicate tx/rx and 958 * BT_FREQ is sampled. 959 */ 960 u_int8_t bt_first_slot_time; 961 962 /* 963 * slotted mode only. rx_clear and bt_ant decision 964 * will be held the entire time that BT_ACTIVE is asserted, 965 * otherwise the decision is made before every slot boundry. 966 */ 967 HAL_BOOL bt_hold_rxclear; 968} HAL_BT_COEX_CONFIG; 969 970typedef struct 971{ 972 int ah_debug; /* only used if AH_DEBUG is defined */ 973 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 974 975 /* NB: these are deprecated; they exist for now for compatibility */ 976 int ah_dma_beacon_response_time;/* in TU's */ 977 int ah_sw_beacon_response_time; /* in TU's */ 978 int ah_additional_swba_backoff; /* in TU's */ 979 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 980 int ah_serialise_reg_war; /* force serialisation of register IO */ 981} HAL_OPS_CONFIG; 982 983/* 984 * Hardware Access Layer (HAL) API. 985 * 986 * Clients of the HAL call ath_hal_attach to obtain a reference to an 987 * ath_hal structure for use with the device. Hardware-related operations 988 * that follow must call back into the HAL through interface, supplying 989 * the reference as the first parameter. Note that before using the 990 * reference returned by ath_hal_attach the caller should verify the 991 * ABI version number. 992 */ 993struct ath_hal { 994 uint32_t ah_magic; /* consistency check magic number */ 995 uint16_t ah_devid; /* PCI device ID */ 996 uint16_t ah_subvendorid; /* PCI subvendor ID */ 997 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 998 HAL_BUS_TAG ah_st; /* params for register r+w */ 999 HAL_BUS_HANDLE ah_sh; 1000 HAL_CTRY_CODE ah_countryCode; 1001 1002 uint32_t ah_macVersion; /* MAC version id */ 1003 uint16_t ah_macRev; /* MAC revision */ 1004 uint16_t ah_phyRev; /* PHY revision */ 1005 /* NB: when only one radio is present the rev is in 5Ghz */ 1006 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 1007 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 1008 1009 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 1010 1011 uint32_t ah_intrstate[8]; /* last int state */ 1012 uint32_t ah_syncstate; /* last sync intr state */ 1013 1014 HAL_OPS_CONFIG ah_config; 1015 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 1016 u_int mode); 1017 void __ahdecl(*ah_detach)(struct ath_hal*); 1018 1019 /* Reset functions */ 1020 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 1021 struct ieee80211_channel *, 1022 HAL_BOOL bChannelChange, HAL_STATUS *status); 1023 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 1024 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 1025 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 1026 HAL_BOOL power_off); 1027 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 1028 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 1029 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 1030 struct ieee80211_channel *, HAL_BOOL *); 1031 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 1032 struct ieee80211_channel *, u_int chainMask, 1033 HAL_BOOL longCal, HAL_BOOL *isCalDone); 1034 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 1035 const struct ieee80211_channel *); 1036 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 1037 const struct ieee80211_channel *, uint16_t *); 1038 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 1039 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 1040 const struct ieee80211_channel *); 1041 1042 /* Transmit functions */ 1043 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 1044 HAL_BOOL incTrigLevel); 1045 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 1046 const HAL_TXQ_INFO *qInfo); 1047 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 1048 const HAL_TXQ_INFO *qInfo); 1049 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 1050 HAL_TXQ_INFO *qInfo); 1051 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 1052 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 1053 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 1054 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 1055 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 1056 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 1057 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 1058 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 1059 u_int pktLen, u_int hdrLen, 1060 HAL_PKT_TYPE type, u_int txPower, 1061 u_int txRate0, u_int txTries0, 1062 u_int keyIx, u_int antMode, u_int flags, 1063 u_int rtsctsRate, u_int rtsctsDuration, 1064 u_int compicvLen, u_int compivLen, 1065 u_int comp); 1066 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 1067 u_int txRate1, u_int txTries1, 1068 u_int txRate2, u_int txTries2, 1069 u_int txRate3, u_int txTries3); 1070 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 1071 u_int segLen, HAL_BOOL firstSeg, 1072 HAL_BOOL lastSeg, const struct ath_desc *); 1073 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 1074 struct ath_desc *, struct ath_tx_status *); 1075 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 1076 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 1077 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 1078 const struct ath_desc *ds, int *rates, int *tries); 1079 1080 /* Receive Functions */ 1081 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 1082 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 1083 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 1084 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 1085 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 1086 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 1087 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 1088 uint32_t filter0, uint32_t filter1); 1089 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 1090 uint32_t index); 1091 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 1092 uint32_t index); 1093 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 1094 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 1095 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 1096 uint32_t size, u_int flags); 1097 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 1098 struct ath_desc *, uint32_t phyAddr, 1099 struct ath_desc *next, uint64_t tsf, 1100 struct ath_rx_status *); 1101 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 1102 const HAL_NODE_STATS *, 1103 const struct ieee80211_channel *); 1104 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 1105 const struct ieee80211_channel *); 1106 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 1107 const HAL_NODE_STATS *); 1108 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 1109 struct ath_rx_status *, 1110 unsigned long, int); 1111 1112 /* Misc Functions */ 1113 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 1114 HAL_CAPABILITY_TYPE, uint32_t capability, 1115 uint32_t *result); 1116 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 1117 HAL_CAPABILITY_TYPE, uint32_t capability, 1118 uint32_t setting, HAL_STATUS *); 1119 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 1120 const void *args, uint32_t argsize, 1121 void **result, uint32_t *resultsize); 1122 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 1123 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 1124 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 1125 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 1126 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 1127 uint16_t, HAL_STATUS *); 1128 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 1129 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 1130 const uint8_t *bssid, uint16_t assocId); 1131 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 1132 uint32_t gpio, HAL_GPIO_MUX_TYPE); 1133 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 1134 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 1135 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 1136 uint32_t gpio, uint32_t val); 1137 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 1138 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 1139 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 1140 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 1141 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 1142 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 1143 HAL_MIB_STATS*); 1144 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 1145 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 1146 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 1147 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 1148 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 1149 HAL_ANT_SETTING); 1150 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 1151 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 1152 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 1153 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 1154 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 1155 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 1156 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 1157 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 1158 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 1159 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 1160 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 1161 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 1162 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 1163 uint32_t duration, uint32_t nextStart, 1164 HAL_QUIET_FLAG flag); 1165 1166 /* DFS functions */ 1167 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 1168 HAL_PHYERR_PARAM *pe); 1169 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 1170 HAL_PHYERR_PARAM *pe); 1171 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 1172 struct ath_rx_status *rxs, uint64_t fulltsf, 1173 const char *buf, HAL_DFS_EVENT *event); 1174 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 1175 1176 /* Key Cache Functions */ 1177 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 1178 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 1179 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 1180 uint16_t); 1181 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 1182 uint16_t, const HAL_KEYVAL *, 1183 const uint8_t *, int); 1184 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 1185 uint16_t, const uint8_t *); 1186 1187 /* Power Management Functions */ 1188 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 1189 HAL_POWER_MODE mode, int setChip); 1190 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1191 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1192 const struct ieee80211_channel *); 1193 1194 /* Beacon Management Functions */ 1195 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1196 const HAL_BEACON_TIMERS *); 1197 /* NB: deprecated, use ah_setBeaconTimers instead */ 1198 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1199 uint32_t nexttbtt, uint32_t intval); 1200 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1201 const HAL_BEACON_STATE *); 1202 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1203 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1204 1205 /* 802.11n Functions */ 1206 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1207 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, 1208 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, 1209 HAL_BOOL, HAL_BOOL); 1210 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1211 struct ath_desc *, u_int, u_int, u_int, 1212 u_int, u_int, u_int, u_int, u_int); 1213 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1214 struct ath_desc *, const struct ath_desc *); 1215 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1216 struct ath_desc *, u_int, u_int, 1217 HAL_11N_RATE_SERIES [], u_int, u_int); 1218 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1219 struct ath_desc *, u_int, u_int); 1220 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1221 struct ath_desc *, u_int); 1222 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1223 struct ath_desc *); 1224 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1225 struct ath_desc *); 1226 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1227 struct ath_desc *, u_int); 1228 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1229 HAL_SURVEY_SAMPLE *); 1230 1231 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1232 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1233 HAL_HT_MACMODE); 1234 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1235 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1236 HAL_HT_RXCLEAR); 1237 1238 /* Interrupt functions */ 1239 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1240 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1241 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1242 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1243}; 1244 1245/* 1246 * Check the PCI vendor ID and device ID against Atheros' values 1247 * and return a printable description for any Atheros hardware. 1248 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1249 */ 1250extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1251 1252/* 1253 * Attach the HAL for use with the specified device. The device is 1254 * defined by the PCI device ID. The caller provides an opaque pointer 1255 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1256 * HAL state block for later use. Hardware register accesses are done 1257 * using the specified bus tag and handle. On successful return a 1258 * reference to a state block is returned that must be supplied in all 1259 * subsequent HAL calls. Storage associated with this reference is 1260 * dynamically allocated and must be freed by calling the ah_detach 1261 * method when the client is done. If the attach operation fails a 1262 * null (AH_NULL) reference will be returned and a status code will 1263 * be returned if the status parameter is non-zero. 1264 */ 1265extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1266 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1267 1268extern const char *ath_hal_mac_name(struct ath_hal *); 1269extern const char *ath_hal_rf_name(struct ath_hal *); 1270 1271/* 1272 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1273 * request a set of channels for a particular country code and/or 1274 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1275 * this list is constructed according to the contents of the EEPROM. 1276 * ath_hal_getchannels acts similarly but does not alter the operating 1277 * state; this can be used to collect information for a particular 1278 * regulatory configuration. Finally ath_hal_set_channels installs a 1279 * channel list constructed outside the driver. The HAL will adopt the 1280 * channel list and setup internal state according to the specified 1281 * regulatory configuration (e.g. conformance test limits). 1282 * 1283 * For all interfaces the channel list is returned in the supplied array. 1284 * maxchans defines the maximum size of this array. nchans contains the 1285 * actual number of channels returned. If a problem occurred then a 1286 * status code != HAL_OK is returned. 1287 */ 1288struct ieee80211_channel; 1289 1290/* 1291 * Return a list of channels according to the specified regulatory. 1292 */ 1293extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1294 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1295 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1296 HAL_BOOL enableExtendedChannels); 1297 1298/* 1299 * Return a list of channels and install it as the current operating 1300 * regulatory list. 1301 */ 1302extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1303 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1304 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1305 HAL_BOOL enableExtendedChannels); 1306 1307/* 1308 * Install the list of channels as the current operating regulatory 1309 * and setup related state according to the country code and sku. 1310 */ 1311extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1312 struct ieee80211_channel *chans, int nchans, 1313 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1314 1315/* 1316 * Fetch the ctl/ext noise floor values reported by a MIMO 1317 * radio. Returns 1 for valid results, 0 for invalid channel. 1318 */ 1319extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1320 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1321 int16_t *nf_ext); 1322 1323/* 1324 * Calibrate noise floor data following a channel scan or similar. 1325 * This must be called prior retrieving noise floor data. 1326 */ 1327extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1328 1329/* 1330 * Return bit mask of wireless modes supported by the hardware. 1331 */ 1332extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1333 1334/* 1335 * Calculate the packet TX time for a legacy or 11n frame 1336 */ 1337extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1338 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1339 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1340 1341/* 1342 * Calculate the duration of an 11n frame. 1343 */ 1344extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1345 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1346 1347/* 1348 * Calculate the transmit duration of a legacy frame. 1349 */ 1350extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1351 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1352 uint16_t rateix, HAL_BOOL shortPreamble); 1353 1354/* 1355 * Adjust the TSF. 1356 */ 1357extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1358 1359/* 1360 * Enable or disable CCA. 1361 */ 1362void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1363 1364/* 1365 * Get CCA setting. 1366 */ 1367int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1368 1369/* 1370 * Read EEPROM data from ah_eepromdata 1371 */ 1372HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1373 u_int off, uint16_t *data); 1374 1375#endif /* _ATH_AH_H_ */ 1376