ah.h revision 235972
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 235972 2012-05-25 05:01:27Z adrian $ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * The maximum number of TX/RX chains supported. 35 * This is intended to be used by various statistics gathering operations 36 * (NF, RSSI, EVM). 37 */ 38#define AH_MIMO_MAX_CHAINS 3 39#define AH_MIMO_MAX_EVM_PILOTS 6 40 41/* 42 * __ahdecl is analogous to _cdecl; it defines the calling 43 * convention used within the HAL. For most systems this 44 * can just default to be empty and the compiler will (should) 45 * use _cdecl. For systems where _cdecl is not compatible this 46 * must be defined. See linux/ah_osdep.h for an example. 47 */ 48#ifndef __ahdecl 49#define __ahdecl 50#endif 51 52/* 53 * Status codes that may be returned by the HAL. Note that 54 * interfaces that return a status code set it only when an 55 * error occurs--i.e. you cannot check it for success. 56 */ 57typedef enum { 58 HAL_OK = 0, /* No error */ 59 HAL_ENXIO = 1, /* No hardware present */ 60 HAL_ENOMEM = 2, /* Memory allocation failed */ 61 HAL_EIO = 3, /* Hardware didn't respond as expected */ 62 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 63 HAL_EEVERSION = 5, /* EEPROM version invalid */ 64 HAL_EELOCKED = 6, /* EEPROM unreadable */ 65 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 66 HAL_EEREAD = 8, /* EEPROM read problem */ 67 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 68 HAL_EESIZE = 10, /* EEPROM size not supported */ 69 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 70 HAL_EINVAL = 12, /* Invalid parameter to function */ 71 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 72 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 73 HAL_EINPROGRESS = 15, /* Operation incomplete */ 74 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 75 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 76} HAL_STATUS; 77 78typedef enum { 79 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 80 AH_TRUE = 1, 81} HAL_BOOL; 82 83typedef enum { 84 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 85 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 86 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 87 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 88 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 89 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 90 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 91 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 92 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 93 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 94 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 95 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 96 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 97 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 98 HAL_CAP_TXPOW = 15, /* global tx power limit */ 99 HAL_CAP_TPC = 16, /* per-packet tx power control */ 100 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 101 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 102 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 103 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 104 /* 21 was HAL_CAP_XR */ 105 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 106 /* 23 was HAL_CAP_CHAN_HALFRATE */ 107 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 108 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 109 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 110 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 111 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 112 113 HAL_CAP_HT = 30, /* hardware can support HT */ 114 HAL_CAP_GTXTO = 31, /* hardware supports global tx timeout */ 115 HAL_CAP_FAST_CC = 32, /* hardware supports fast channel change */ 116 HAL_CAP_TX_CHAINMASK = 33, /* mask of TX chains supported */ 117 HAL_CAP_RX_CHAINMASK = 34, /* mask of RX chains supported */ 118 HAL_CAP_NUM_GPIO_PINS = 36, /* number of GPIO pins */ 119 120 HAL_CAP_CST = 38, /* hardware supports carrier sense timeout */ 121 122 HAL_CAP_RTS_AGGR_LIMIT = 42, /* aggregation limit with RTS */ 123 HAL_CAP_4ADDR_AGGR = 43, /* hardware is capable of 4addr aggregation */ 124 HAL_CAP_DFS_DMN = 44, /* current DFS domain */ 125 HAL_CAP_EXT_CHAN_DFS = 45, /* DFS support for extension channel */ 126 HAL_CAP_COMBINED_RADAR_RSSI = 46, /* Is combined RSSI for radar accurate */ 127 128 HAL_CAP_AUTO_SLEEP = 48, /* hardware can go to network sleep 129 automatically after waking up to receive TIM */ 130 HAL_CAP_MBSSID_AGGR_SUPPORT = 49, /* Support for mBSSID Aggregation */ 131 HAL_CAP_SPLIT_4KB_TRANS = 50, /* hardware supports descriptors straddling a 4k page boundary */ 132 HAL_CAP_REG_FLAG = 51, /* Regulatory domain flags */ 133 134 HAL_CAP_BT_COEX = 60, /* hardware is capable of bluetooth coexistence */ 135 136 HAL_CAP_HT20_SGI = 96, /* hardware supports HT20 short GI */ 137 138 HAL_CAP_RXTSTAMP_PREC = 100, /* rx desc tstamp precision (bits) */ 139 HAL_CAP_ENHANCED_DFS_SUPPORT = 117, /* hardware supports enhanced DFS */ 140 141 /* The following are private to the FreeBSD HAL (224 onward) */ 142 143 HAL_CAP_INTMIT = 229, /* interference mitigation */ 144 HAL_CAP_RXORN_FATAL = 230, /* HAL_INT_RXORN treated as fatal */ 145 HAL_CAP_BB_HANG = 235, /* can baseband hang */ 146 HAL_CAP_MAC_HANG = 236, /* can MAC hang */ 147 HAL_CAP_INTRMASK = 237, /* bitmask of supported interrupts */ 148 HAL_CAP_BSSIDMATCH = 238, /* hardware has disable bssid match */ 149 HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */ 150 HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */ 151 HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */ 152 HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */ 153 HAL_CAP_SERIALISE_WAR = 245, /* serialise register access on PCI */ 154} HAL_CAPABILITY_TYPE; 155 156/* 157 * "States" for setting the LED. These correspond to 158 * the possible 802.11 operational states and there may 159 * be a many-to-one mapping between these states and the 160 * actual hardware state for the LED's (i.e. the hardware 161 * may have fewer states). 162 */ 163typedef enum { 164 HAL_LED_INIT = 0, 165 HAL_LED_SCAN = 1, 166 HAL_LED_AUTH = 2, 167 HAL_LED_ASSOC = 3, 168 HAL_LED_RUN = 4 169} HAL_LED_STATE; 170 171/* 172 * Transmit queue types/numbers. These are used to tag 173 * each transmit queue in the hardware and to identify a set 174 * of transmit queues for operations such as start/stop dma. 175 */ 176typedef enum { 177 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 178 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 179 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 180 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 181 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 182 HAL_TX_QUEUE_PSPOLL = 5, /* power save poll xmit q */ 183} HAL_TX_QUEUE; 184 185#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 186 187/* 188 * Transmit queue subtype. These map directly to 189 * WME Access Categories (except for UPSD). Refer 190 * to Table 5 of the WME spec. 191 */ 192typedef enum { 193 HAL_WME_AC_BK = 0, /* background access category */ 194 HAL_WME_AC_BE = 1, /* best effort access category*/ 195 HAL_WME_AC_VI = 2, /* video access category */ 196 HAL_WME_AC_VO = 3, /* voice access category */ 197 HAL_WME_UPSD = 4, /* uplink power save */ 198} HAL_TX_QUEUE_SUBTYPE; 199 200/* 201 * Transmit queue flags that control various 202 * operational parameters. 203 */ 204typedef enum { 205 /* 206 * Per queue interrupt enables. When set the associated 207 * interrupt may be delivered for packets sent through 208 * the queue. Without these enabled no interrupts will 209 * be delivered for transmits through the queue. 210 */ 211 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 212 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 213 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 214 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 215 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 216 /* 217 * Enable hardware compression for packets sent through 218 * the queue. The compression buffer must be setup and 219 * packets must have a key entry marked in the tx descriptor. 220 */ 221 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 222 /* 223 * Disable queue when veol is hit or ready time expires. 224 * By default the queue is disabled only on reaching the 225 * physical end of queue (i.e. a null link ptr in the 226 * descriptor chain). 227 */ 228 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 229 /* 230 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 231 * event. Frames will be transmitted only when this timer 232 * fires, e.g to transmit a beacon in ap or adhoc modes. 233 */ 234 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 235 /* 236 * Each transmit queue has a counter that is incremented 237 * each time the queue is enabled and decremented when 238 * the list of frames to transmit is traversed (or when 239 * the ready time for the queue expires). This counter 240 * must be non-zero for frames to be scheduled for 241 * transmission. The following controls disable bumping 242 * this counter under certain conditions. Typically this 243 * is used to gate frames based on the contents of another 244 * queue (e.g. CAB traffic may only follow a beacon frame). 245 * These are meaningful only when frames are scheduled 246 * with a non-ASAP policy (e.g. DBA-gated). 247 */ 248 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 249 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 250 251 /* 252 * Fragment burst backoff policy. Normally the no backoff 253 * is done after a successful transmission, the next fragment 254 * is sent at SIFS. If this flag is set backoff is done 255 * after each fragment, regardless whether it was ack'd or 256 * not, after the backoff count reaches zero a normal channel 257 * access procedure is done before the next transmit (i.e. 258 * wait AIFS instead of SIFS). 259 */ 260 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 261 /* 262 * Disable post-tx backoff following each frame. 263 */ 264 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 265 /* 266 * DCU arbiter lockout control. This controls how 267 * lower priority tx queues are handled with respect to 268 * to a specific queue when multiple queues have frames 269 * to send. No lockout means lower priority queues arbitrate 270 * concurrently with this queue. Intra-frame lockout 271 * means lower priority queues are locked out until the 272 * current frame transmits (e.g. including backoffs and bursting). 273 * Global lockout means nothing lower can arbitrary so 274 * long as there is traffic activity on this queue (frames, 275 * backoff, etc). 276 */ 277 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 278 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 279 280 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 281 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 282} HAL_TX_QUEUE_FLAGS; 283 284typedef struct { 285 uint32_t tqi_ver; /* hal TXQ version */ 286 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 287 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 288 uint32_t tqi_priority; /* (not used) */ 289 uint32_t tqi_aifs; /* aifs */ 290 uint32_t tqi_cwmin; /* cwMin */ 291 uint32_t tqi_cwmax; /* cwMax */ 292 uint16_t tqi_shretry; /* rts retry limit */ 293 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 294 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 295 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 296 uint32_t tqi_burstTime; /* max burst duration (us) */ 297 uint32_t tqi_readyTime; /* frame schedule time (us) */ 298 uint32_t tqi_compBuf; /* comp buffer phys addr */ 299} HAL_TXQ_INFO; 300 301#define HAL_TQI_NONVAL 0xffff 302 303/* token to use for aifs, cwmin, cwmax */ 304#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 305 306/* compression definitions */ 307#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 308#define HAL_COMP_BUF_ALIGN_SIZE 512 309 310/* 311 * Transmit packet types. This belongs in ah_desc.h, but 312 * is here so we can give a proper type to various parameters 313 * (and not require everyone include the file). 314 * 315 * NB: These values are intentionally assigned for 316 * direct use when setting up h/w descriptors. 317 */ 318typedef enum { 319 HAL_PKT_TYPE_NORMAL = 0, 320 HAL_PKT_TYPE_ATIM = 1, 321 HAL_PKT_TYPE_PSPOLL = 2, 322 HAL_PKT_TYPE_BEACON = 3, 323 HAL_PKT_TYPE_PROBE_RESP = 4, 324 HAL_PKT_TYPE_CHIRP = 5, 325 HAL_PKT_TYPE_GRP_POLL = 6, 326 HAL_PKT_TYPE_AMPDU = 7, 327} HAL_PKT_TYPE; 328 329/* Rx Filter Frame Types */ 330typedef enum { 331 /* 332 * These bits correspond to AR_RX_FILTER for all chips. 333 * Not all bits are supported by all chips. 334 */ 335 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 336 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 337 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 338 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 339 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 340 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 341 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 342 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 343 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 344 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */ 345 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */ 346 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */ 347 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 348 /* Allow all mcast/bcast frames */ 349 350 /* 351 * Magic RX filter flags that aren't targetting hardware bits 352 * but instead the HAL sets individual bits - eg PHYERR will result 353 * in OFDM/CCK timing error frames being received. 354 */ 355 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */ 356} HAL_RX_FILTER; 357 358typedef enum { 359 HAL_PM_AWAKE = 0, 360 HAL_PM_FULL_SLEEP = 1, 361 HAL_PM_NETWORK_SLEEP = 2, 362 HAL_PM_UNDEFINED = 3 363} HAL_POWER_MODE; 364 365/* 366 * NOTE WELL: 367 * These are mapped to take advantage of the common locations for many of 368 * the bits on all of the currently supported MAC chips. This is to make 369 * the ISR as efficient as possible, while still abstracting HW differences. 370 * When new hardware breaks this commonality this enumerated type, as well 371 * as the HAL functions using it, must be modified. All values are directly 372 * mapped unless commented otherwise. 373 */ 374typedef enum { 375 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 376 HAL_INT_RXDESC = 0x00000002, 377 HAL_INT_RXNOFRM = 0x00000008, 378 HAL_INT_RXEOL = 0x00000010, 379 HAL_INT_RXORN = 0x00000020, 380 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 381 HAL_INT_TXDESC = 0x00000080, 382 HAL_INT_TIM_TIMER= 0x00000100, 383 HAL_INT_TXURN = 0x00000800, 384 HAL_INT_MIB = 0x00001000, 385 HAL_INT_RXPHY = 0x00004000, 386 HAL_INT_RXKCM = 0x00008000, 387 HAL_INT_SWBA = 0x00010000, 388 HAL_INT_BMISS = 0x00040000, 389 HAL_INT_BNR = 0x00100000, 390 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 391 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 392 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 393 HAL_INT_GPIO = 0x01000000, 394 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 395 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 396 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 397 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 398 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 399 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 400#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 401 HAL_INT_BMISC = HAL_INT_TIM 402 | HAL_INT_DTIM 403 | HAL_INT_DTIMSYNC 404 | HAL_INT_CABEND 405 | HAL_INT_TBTT, 406 407 /* Interrupt bits that map directly to ISR/IMR bits */ 408 HAL_INT_COMMON = HAL_INT_RXNOFRM 409 | HAL_INT_RXDESC 410 | HAL_INT_RXEOL 411 | HAL_INT_RXORN 412 | HAL_INT_TXDESC 413 | HAL_INT_TXURN 414 | HAL_INT_MIB 415 | HAL_INT_RXPHY 416 | HAL_INT_RXKCM 417 | HAL_INT_SWBA 418 | HAL_INT_BMISS 419 | HAL_INT_BNR 420 | HAL_INT_GPIO, 421} HAL_INT; 422 423typedef enum { 424 HAL_GPIO_MUX_OUTPUT = 0, 425 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 426 HAL_GPIO_MUX_PCIE_POWER_LED = 2, 427 HAL_GPIO_MUX_TX_FRAME = 3, 428 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 429 HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 430 HAL_GPIO_MUX_MAC_POWER_LED = 6 431} HAL_GPIO_MUX_TYPE; 432 433typedef enum { 434 HAL_GPIO_INTR_LOW = 0, 435 HAL_GPIO_INTR_HIGH = 1, 436 HAL_GPIO_INTR_DISABLE = 2 437} HAL_GPIO_INTR_TYPE; 438 439typedef enum { 440 HAL_RFGAIN_INACTIVE = 0, 441 HAL_RFGAIN_READ_REQUESTED = 1, 442 HAL_RFGAIN_NEED_CHANGE = 2 443} HAL_RFGAIN; 444 445typedef uint16_t HAL_CTRY_CODE; /* country code */ 446typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 447 448#define HAL_ANTENNA_MIN_MODE 0 449#define HAL_ANTENNA_FIXED_A 1 450#define HAL_ANTENNA_FIXED_B 2 451#define HAL_ANTENNA_MAX_MODE 3 452 453typedef struct { 454 uint32_t ackrcv_bad; 455 uint32_t rts_bad; 456 uint32_t rts_good; 457 uint32_t fcs_bad; 458 uint32_t beacons; 459} HAL_MIB_STATS; 460 461enum { 462 HAL_MODE_11A = 0x001, /* 11a channels */ 463 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 464 HAL_MODE_11B = 0x004, /* 11b channels */ 465 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 466#ifdef notdef 467 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 468#else 469 HAL_MODE_11G = 0x008, /* XXX historical */ 470#endif 471 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 472 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 473 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 474 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 475 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 476 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 477 HAL_MODE_11NG_HT20 = 0x008000, 478 HAL_MODE_11NA_HT20 = 0x010000, 479 HAL_MODE_11NG_HT40PLUS = 0x020000, 480 HAL_MODE_11NG_HT40MINUS = 0x040000, 481 HAL_MODE_11NA_HT40PLUS = 0x080000, 482 HAL_MODE_11NA_HT40MINUS = 0x100000, 483 HAL_MODE_ALL = 0xffffff 484}; 485 486typedef struct { 487 int rateCount; /* NB: for proper padding */ 488 uint8_t rateCodeToIndex[144]; /* back mapping */ 489 struct { 490 uint8_t valid; /* valid for rate control use */ 491 uint8_t phy; /* CCK/OFDM/XR */ 492 uint32_t rateKbps; /* transfer rate in kbs */ 493 uint8_t rateCode; /* rate for h/w descriptors */ 494 uint8_t shortPreamble; /* mask for enabling short 495 * preamble in CCK rate code */ 496 uint8_t dot11Rate; /* value for supported rates 497 * info element of MLME */ 498 uint8_t controlRate; /* index of next lower basic 499 * rate; used for dur. calcs */ 500 uint16_t lpAckDuration; /* long preamble ACK duration */ 501 uint16_t spAckDuration; /* short preamble ACK duration*/ 502 } info[32]; 503} HAL_RATE_TABLE; 504 505typedef struct { 506 u_int rs_count; /* number of valid entries */ 507 uint8_t rs_rates[32]; /* rates */ 508} HAL_RATE_SET; 509 510/* 511 * 802.11n specific structures and enums 512 */ 513typedef enum { 514 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 515 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 516} HAL_CHAIN_TYPE; 517 518typedef struct { 519 u_int Tries; 520 u_int Rate; 521 u_int PktDuration; 522 u_int ChSel; 523 u_int RateFlags; 524#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 525#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 526#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 527} HAL_11N_RATE_SERIES; 528 529typedef enum { 530 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 531 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 532} HAL_HT_MACMODE; 533 534typedef enum { 535 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 536 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 537} HAL_HT_PHYMODE; 538 539typedef enum { 540 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 541 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 542} HAL_HT_EXTPROTSPACING; 543 544 545typedef enum { 546 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 547 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 548} HAL_HT_RXCLEAR; 549 550/* 551 * Antenna switch control. By default antenna selection 552 * enables multiple (2) antenna use. To force use of the 553 * A or B antenna only specify a fixed setting. Fixing 554 * the antenna will also disable any diversity support. 555 */ 556typedef enum { 557 HAL_ANT_VARIABLE = 0, /* variable by programming */ 558 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 559 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 560} HAL_ANT_SETTING; 561 562typedef enum { 563 HAL_M_STA = 1, /* infrastructure station */ 564 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 565 HAL_M_HOSTAP = 6, /* Software Access Point */ 566 HAL_M_MONITOR = 8 /* Monitor mode */ 567} HAL_OPMODE; 568 569typedef struct { 570 uint8_t kv_type; /* one of HAL_CIPHER */ 571 uint8_t kv_pad; 572 uint16_t kv_len; /* length in bits */ 573 uint8_t kv_val[16]; /* enough for 128-bit keys */ 574 uint8_t kv_mic[8]; /* TKIP MIC key */ 575 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 576} HAL_KEYVAL; 577 578typedef enum { 579 HAL_CIPHER_WEP = 0, 580 HAL_CIPHER_AES_OCB = 1, 581 HAL_CIPHER_AES_CCM = 2, 582 HAL_CIPHER_CKIP = 3, 583 HAL_CIPHER_TKIP = 4, 584 HAL_CIPHER_CLR = 5, /* no encryption */ 585 586 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 587} HAL_CIPHER; 588 589enum { 590 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 591 HAL_SLOT_TIME_9 = 9, 592 HAL_SLOT_TIME_20 = 20, 593}; 594 595/* 596 * Per-station beacon timer state. Note that the specified 597 * beacon interval (given in TU's) can also include flags 598 * to force a TSF reset and to enable the beacon xmit logic. 599 * If bs_cfpmaxduration is non-zero the hardware is setup to 600 * coexist with a PCF-capable AP. 601 */ 602typedef struct { 603 uint32_t bs_nexttbtt; /* next beacon in TU */ 604 uint32_t bs_nextdtim; /* next DTIM in TU */ 605 uint32_t bs_intval; /* beacon interval+flags */ 606#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 607#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 608#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 609 uint32_t bs_dtimperiod; 610 uint16_t bs_cfpperiod; /* CFP period in TU */ 611 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 612 uint32_t bs_cfpnext; /* next CFP in TU */ 613 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 614 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 615 uint32_t bs_sleepduration; /* max sleep duration */ 616} HAL_BEACON_STATE; 617 618/* 619 * Like HAL_BEACON_STATE but for non-station mode setup. 620 * NB: see above flag definitions for bt_intval. 621 */ 622typedef struct { 623 uint32_t bt_intval; /* beacon interval+flags */ 624 uint32_t bt_nexttbtt; /* next beacon in TU */ 625 uint32_t bt_nextatim; /* next ATIM in TU */ 626 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 627 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 628 uint32_t bt_flags; /* timer enables */ 629#define HAL_BEACON_TBTT_EN 0x00000001 630#define HAL_BEACON_DBA_EN 0x00000002 631#define HAL_BEACON_SWBA_EN 0x00000004 632} HAL_BEACON_TIMERS; 633 634/* 635 * Per-node statistics maintained by the driver for use in 636 * optimizing signal quality and other operational aspects. 637 */ 638typedef struct { 639 uint32_t ns_avgbrssi; /* average beacon rssi */ 640 uint32_t ns_avgrssi; /* average data rssi */ 641 uint32_t ns_avgtxrssi; /* average tx rssi */ 642} HAL_NODE_STATS; 643 644#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 645 646struct ath_desc; 647struct ath_tx_status; 648struct ath_rx_status; 649struct ieee80211_channel; 650 651/* 652 * This is a channel survey sample entry. 653 * 654 * The AR5212 ANI routines fill these samples. The ANI code then uses it 655 * when calculating listen time; it is also exported via a diagnostic 656 * API. 657 */ 658typedef struct { 659 uint32_t seq_num; 660 uint32_t tx_busy; 661 uint32_t rx_busy; 662 uint32_t chan_busy; 663 uint32_t ext_chan_busy; 664 uint32_t cycle_count; 665 /* XXX TODO */ 666 uint32_t ofdm_phyerr_count; 667 uint32_t cck_phyerr_count; 668} HAL_SURVEY_SAMPLE; 669 670/* 671 * This provides 3.2 seconds of sample space given an 672 * ANI time of 1/10th of a second. This may not be enough! 673 */ 674#define CHANNEL_SURVEY_SAMPLE_COUNT 32 675 676typedef struct { 677 HAL_SURVEY_SAMPLE samples[CHANNEL_SURVEY_SAMPLE_COUNT]; 678 uint32_t cur_sample; /* current sample in sequence */ 679 uint32_t cur_seq; /* current sequence number */ 680} HAL_CHANNEL_SURVEY; 681 682/* 683 * ANI commands. 684 * 685 * These are used both internally and externally via the diagnostic 686 * API. 687 * 688 * Note that this is NOT the ANI commands being used via the INTMIT 689 * capability - that has a different mapping for some reason. 690 */ 691typedef enum { 692 HAL_ANI_PRESENT = 0, /* is ANI support present */ 693 HAL_ANI_NOISE_IMMUNITY_LEVEL = 1, /* set level */ 694 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 2, /* enable/disable */ 695 HAL_ANI_CCK_WEAK_SIGNAL_THR = 3, /* enable/disable */ 696 HAL_ANI_FIRSTEP_LEVEL = 4, /* set level */ 697 HAL_ANI_SPUR_IMMUNITY_LEVEL = 5, /* set level */ 698 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */ 699 HAL_ANI_PHYERR_RESET = 7, /* reset phy error stats */ 700} HAL_ANI_CMD; 701 702/* 703 * This is the layout of the ANI INTMIT capability. 704 * 705 * Notice that the command values differ to HAL_ANI_CMD. 706 */ 707typedef enum { 708 HAL_CAP_INTMIT_PRESENT = 0, 709 HAL_CAP_INTMIT_ENABLE = 1, 710 HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL = 2, 711 HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL = 3, 712 HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR = 4, 713 HAL_CAP_INTMIT_FIRSTEP_LEVEL = 5, 714 HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL = 6 715} HAL_CAP_INTMIT_CMD; 716 717typedef struct { 718 int32_t pe_firpwr; /* FIR pwr out threshold */ 719 int32_t pe_rrssi; /* Radar rssi thresh */ 720 int32_t pe_height; /* Pulse height thresh */ 721 int32_t pe_prssi; /* Pulse rssi thresh */ 722 int32_t pe_inband; /* Inband thresh */ 723 724 /* The following params are only for AR5413 and later */ 725 u_int32_t pe_relpwr; /* Relative power threshold in 0.5dB steps */ 726 u_int32_t pe_relstep; /* Pulse Relative step threshold in 0.5dB steps */ 727 u_int32_t pe_maxlen; /* Max length of radar sign in 0.8us units */ 728 int32_t pe_usefir128; /* Use the average in-band power measured over 128 cycles */ 729 int32_t pe_blockradar; /* 730 * Enable to block radar check if pkt detect is done via OFDM 731 * weak signal detect or pkt is detected immediately after tx 732 * to rx transition 733 */ 734 int32_t pe_enmaxrssi; /* 735 * Enable to use the max rssi instead of the last rssi during 736 * fine gain changes for radar detection 737 */ 738 int32_t pe_extchannel; /* Enable DFS on ext channel */ 739 int32_t pe_enabled; /* Whether radar detection is enabled */ 740 int32_t pe_enrelpwr; 741 int32_t pe_en_relstep_check; 742} HAL_PHYERR_PARAM; 743 744#define HAL_PHYERR_PARAM_NOVAL 65535 745 746/* 747 * DFS operating mode flags. 748 */ 749typedef enum { 750 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */ 751 HAL_DFS_FCC_DOMAIN = 1, /* FCC3 dfs domain */ 752 HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ 753 HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ 754} HAL_DFS_DOMAIN; 755 756/* 757 * Flag for setting QUIET period 758 */ 759typedef enum { 760 HAL_QUIET_DISABLE = 0x0, 761 HAL_QUIET_ENABLE = 0x1, 762 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */ 763 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */ 764} HAL_QUIET_FLAG; 765 766#define HAL_DFS_EVENT_PRICH 0x0000001 767#define HAL_DFS_EVENT_EXTCH 0x0000002 768#define HAL_DFS_EVENT_EXTEARLY 0x0000004 769#define HAL_DFS_EVENT_ISDC 0x0000008 770 771struct hal_dfs_event { 772 uint64_t re_full_ts; /* 64-bit full timestamp from interrupt time */ 773 uint32_t re_ts; /* Original 15 bit recv timestamp */ 774 uint8_t re_rssi; /* rssi of radar event */ 775 uint8_t re_dur; /* duration of radar pulse */ 776 uint32_t re_flags; /* Flags (see above) */ 777}; 778typedef struct hal_dfs_event HAL_DFS_EVENT; 779 780typedef struct 781{ 782 int ah_debug; /* only used if AH_DEBUG is defined */ 783 int ah_ar5416_biasadj; /* enable AR2133 radio specific bias fiddling */ 784 785 /* NB: these are deprecated; they exist for now for compatibility */ 786 int ah_dma_beacon_response_time;/* in TU's */ 787 int ah_sw_beacon_response_time; /* in TU's */ 788 int ah_additional_swba_backoff; /* in TU's */ 789 int ah_force_full_reset; /* force full chip reset rather then warm reset */ 790 int ah_serialise_reg_war; /* force serialisation of register IO */ 791} HAL_OPS_CONFIG; 792 793/* 794 * Hardware Access Layer (HAL) API. 795 * 796 * Clients of the HAL call ath_hal_attach to obtain a reference to an 797 * ath_hal structure for use with the device. Hardware-related operations 798 * that follow must call back into the HAL through interface, supplying 799 * the reference as the first parameter. Note that before using the 800 * reference returned by ath_hal_attach the caller should verify the 801 * ABI version number. 802 */ 803struct ath_hal { 804 uint32_t ah_magic; /* consistency check magic number */ 805 uint16_t ah_devid; /* PCI device ID */ 806 uint16_t ah_subvendorid; /* PCI subvendor ID */ 807 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 808 HAL_BUS_TAG ah_st; /* params for register r+w */ 809 HAL_BUS_HANDLE ah_sh; 810 HAL_CTRY_CODE ah_countryCode; 811 812 uint32_t ah_macVersion; /* MAC version id */ 813 uint16_t ah_macRev; /* MAC revision */ 814 uint16_t ah_phyRev; /* PHY revision */ 815 /* NB: when only one radio is present the rev is in 5Ghz */ 816 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 817 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 818 819 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 820 821 uint32_t ah_intrstate[8]; /* last int state */ 822 uint32_t ah_syncstate; /* last sync intr state */ 823 824 HAL_OPS_CONFIG ah_config; 825 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 826 u_int mode); 827 void __ahdecl(*ah_detach)(struct ath_hal*); 828 829 /* Reset functions */ 830 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 831 struct ieee80211_channel *, 832 HAL_BOOL bChannelChange, HAL_STATUS *status); 833 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 834 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 835 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore, 836 HAL_BOOL power_off); 837 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 838 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 839 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 840 struct ieee80211_channel *, HAL_BOOL *); 841 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 842 struct ieee80211_channel *, u_int chainMask, 843 HAL_BOOL longCal, HAL_BOOL *isCalDone); 844 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 845 const struct ieee80211_channel *); 846 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 847 const struct ieee80211_channel *, uint16_t *); 848 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 849 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 850 const struct ieee80211_channel *); 851 852 /* Transmit functions */ 853 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 854 HAL_BOOL incTrigLevel); 855 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 856 const HAL_TXQ_INFO *qInfo); 857 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 858 const HAL_TXQ_INFO *qInfo); 859 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 860 HAL_TXQ_INFO *qInfo); 861 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 862 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 863 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 864 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 865 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 866 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 867 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 868 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 869 u_int pktLen, u_int hdrLen, 870 HAL_PKT_TYPE type, u_int txPower, 871 u_int txRate0, u_int txTries0, 872 u_int keyIx, u_int antMode, u_int flags, 873 u_int rtsctsRate, u_int rtsctsDuration, 874 u_int compicvLen, u_int compivLen, 875 u_int comp); 876 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 877 u_int txRate1, u_int txTries1, 878 u_int txRate2, u_int txTries2, 879 u_int txRate3, u_int txTries3); 880 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 881 u_int segLen, HAL_BOOL firstSeg, 882 HAL_BOOL lastSeg, const struct ath_desc *); 883 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 884 struct ath_desc *, struct ath_tx_status *); 885 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 886 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 887 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 888 const struct ath_desc *ds, int *rates, int *tries); 889 890 /* Receive Functions */ 891 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 892 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 893 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 894 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 895 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 896 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 897 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 898 uint32_t filter0, uint32_t filter1); 899 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 900 uint32_t index); 901 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 902 uint32_t index); 903 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 904 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 905 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 906 uint32_t size, u_int flags); 907 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 908 struct ath_desc *, uint32_t phyAddr, 909 struct ath_desc *next, uint64_t tsf, 910 struct ath_rx_status *); 911 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 912 const HAL_NODE_STATS *, 913 const struct ieee80211_channel *); 914 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 915 const struct ieee80211_channel *); 916 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 917 const HAL_NODE_STATS *); 918 void __ahdecl(*ah_rxAntCombDiversity)(struct ath_hal *, 919 struct ath_rx_status *, 920 unsigned long, int); 921 922 /* Misc Functions */ 923 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 924 HAL_CAPABILITY_TYPE, uint32_t capability, 925 uint32_t *result); 926 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 927 HAL_CAPABILITY_TYPE, uint32_t capability, 928 uint32_t setting, HAL_STATUS *); 929 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 930 const void *args, uint32_t argsize, 931 void **result, uint32_t *resultsize); 932 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 933 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 934 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 935 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 936 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 937 uint16_t, HAL_STATUS *); 938 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 939 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 940 const uint8_t *bssid, uint16_t assocId); 941 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 942 uint32_t gpio, HAL_GPIO_MUX_TYPE); 943 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 944 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 945 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 946 uint32_t gpio, uint32_t val); 947 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 948 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 949 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 950 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 951 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 952 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 953 HAL_MIB_STATS*); 954 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 955 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 956 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 957 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 958 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 959 HAL_ANT_SETTING); 960 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 961 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 962 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 963 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 964 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 965 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 966 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 967 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 968 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 969 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 970 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 971 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 972 HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period, 973 uint32_t duration, uint32_t nextStart, 974 HAL_QUIET_FLAG flag); 975 976 /* DFS functions */ 977 void __ahdecl(*ah_enableDfs)(struct ath_hal *ah, 978 HAL_PHYERR_PARAM *pe); 979 void __ahdecl(*ah_getDfsThresh)(struct ath_hal *ah, 980 HAL_PHYERR_PARAM *pe); 981 HAL_BOOL __ahdecl(*ah_procRadarEvent)(struct ath_hal *ah, 982 struct ath_rx_status *rxs, uint64_t fulltsf, 983 const char *buf, HAL_DFS_EVENT *event); 984 HAL_BOOL __ahdecl(*ah_isFastClockEnabled)(struct ath_hal *ah); 985 986 /* Key Cache Functions */ 987 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 988 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 989 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 990 uint16_t); 991 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 992 uint16_t, const HAL_KEYVAL *, 993 const uint8_t *, int); 994 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 995 uint16_t, const uint8_t *); 996 997 /* Power Management Functions */ 998 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 999 HAL_POWER_MODE mode, int setChip); 1000 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 1001 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 1002 const struct ieee80211_channel *); 1003 1004 /* Beacon Management Functions */ 1005 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 1006 const HAL_BEACON_TIMERS *); 1007 /* NB: deprecated, use ah_setBeaconTimers instead */ 1008 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 1009 uint32_t nexttbtt, uint32_t intval); 1010 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 1011 const HAL_BEACON_STATE *); 1012 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 1013 uint64_t __ahdecl(*ah_getNextTBTT)(struct ath_hal *); 1014 1015 /* 802.11n Functions */ 1016 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 1017 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, 1018 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, 1019 HAL_BOOL, HAL_BOOL); 1020 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 1021 struct ath_desc *, u_int, u_int, u_int, 1022 u_int, u_int, u_int, u_int, u_int); 1023 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 1024 struct ath_desc *, const struct ath_desc *); 1025 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 1026 struct ath_desc *, u_int, u_int, 1027 HAL_11N_RATE_SERIES [], u_int, u_int); 1028 void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *, 1029 struct ath_desc *, u_int, u_int); 1030 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 1031 struct ath_desc *, u_int); 1032 void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *, 1033 struct ath_desc *); 1034 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 1035 struct ath_desc *); 1036 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 1037 struct ath_desc *, u_int); 1038 HAL_BOOL __ahdecl(*ah_getMibCycleCounts) (struct ath_hal *, 1039 HAL_SURVEY_SAMPLE *); 1040 1041 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 1042 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 1043 HAL_HT_MACMODE); 1044 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 1045 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 1046 HAL_HT_RXCLEAR); 1047 1048 /* Interrupt functions */ 1049 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 1050 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 1051 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 1052 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 1053}; 1054 1055/* 1056 * Check the PCI vendor ID and device ID against Atheros' values 1057 * and return a printable description for any Atheros hardware. 1058 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1059 */ 1060extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 1061 1062/* 1063 * Attach the HAL for use with the specified device. The device is 1064 * defined by the PCI device ID. The caller provides an opaque pointer 1065 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1066 * HAL state block for later use. Hardware register accesses are done 1067 * using the specified bus tag and handle. On successful return a 1068 * reference to a state block is returned that must be supplied in all 1069 * subsequent HAL calls. Storage associated with this reference is 1070 * dynamically allocated and must be freed by calling the ah_detach 1071 * method when the client is done. If the attach operation fails a 1072 * null (AH_NULL) reference will be returned and a status code will 1073 * be returned if the status parameter is non-zero. 1074 */ 1075extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 1076 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 1077 1078extern const char *ath_hal_mac_name(struct ath_hal *); 1079extern const char *ath_hal_rf_name(struct ath_hal *); 1080 1081/* 1082 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 1083 * request a set of channels for a particular country code and/or 1084 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 1085 * this list is constructed according to the contents of the EEPROM. 1086 * ath_hal_getchannels acts similarly but does not alter the operating 1087 * state; this can be used to collect information for a particular 1088 * regulatory configuration. Finally ath_hal_set_channels installs a 1089 * channel list constructed outside the driver. The HAL will adopt the 1090 * channel list and setup internal state according to the specified 1091 * regulatory configuration (e.g. conformance test limits). 1092 * 1093 * For all interfaces the channel list is returned in the supplied array. 1094 * maxchans defines the maximum size of this array. nchans contains the 1095 * actual number of channels returned. If a problem occurred then a 1096 * status code != HAL_OK is returned. 1097 */ 1098struct ieee80211_channel; 1099 1100/* 1101 * Return a list of channels according to the specified regulatory. 1102 */ 1103extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 1104 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1105 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 1106 HAL_BOOL enableExtendedChannels); 1107 1108/* 1109 * Return a list of channels and install it as the current operating 1110 * regulatory list. 1111 */ 1112extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 1113 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 1114 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 1115 HAL_BOOL enableExtendedChannels); 1116 1117/* 1118 * Install the list of channels as the current operating regulatory 1119 * and setup related state according to the country code and sku. 1120 */ 1121extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 1122 struct ieee80211_channel *chans, int nchans, 1123 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 1124 1125/* 1126 * Fetch the ctl/ext noise floor values reported by a MIMO 1127 * radio. Returns 1 for valid results, 0 for invalid channel. 1128 */ 1129extern int __ahdecl ath_hal_get_mimo_chan_noise(struct ath_hal *ah, 1130 const struct ieee80211_channel *chan, int16_t *nf_ctl, 1131 int16_t *nf_ext); 1132 1133/* 1134 * Calibrate noise floor data following a channel scan or similar. 1135 * This must be called prior retrieving noise floor data. 1136 */ 1137extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 1138 1139/* 1140 * Return bit mask of wireless modes supported by the hardware. 1141 */ 1142extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 1143 1144/* 1145 * Calculate the packet TX time for a legacy or 11n frame 1146 */ 1147extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 1148 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1149 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 1150 1151/* 1152 * Calculate the duration of an 11n frame. 1153 */ 1154extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 1155 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 1156 1157/* 1158 * Calculate the transmit duration of a legacy frame. 1159 */ 1160extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 1161 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1162 uint16_t rateix, HAL_BOOL shortPreamble); 1163 1164/* 1165 * Adjust the TSF. 1166 */ 1167extern void __ahdecl ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta); 1168 1169/* 1170 * Enable or disable CCA. 1171 */ 1172void __ahdecl ath_hal_setcca(struct ath_hal *ah, int ena); 1173 1174/* 1175 * Get CCA setting. 1176 */ 1177int __ahdecl ath_hal_getcca(struct ath_hal *ah); 1178 1179/* 1180 * Read EEPROM data from ah_eepromdata 1181 */ 1182HAL_BOOL __ahdecl ath_hal_EepromDataRead(struct ath_hal *ah, 1183 u_int off, uint16_t *data); 1184 1185#endif /* _ATH_AH_H_ */ 1186