ah.h revision 218150
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 218150 2011-02-01 03:51:35Z adrian $ 18 */ 19 20#ifndef _ATH_AH_H_ 21#define _ATH_AH_H_ 22/* 23 * Atheros Hardware Access Layer 24 * 25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal 26 * structure for use with the device. Hardware-related operations that 27 * follow must call back into the HAL through interface, supplying the 28 * reference as the first parameter. 29 */ 30 31#include "ah_osdep.h" 32 33/* 34 * __ahdecl is analogous to _cdecl; it defines the calling 35 * convention used within the HAL. For most systems this 36 * can just default to be empty and the compiler will (should) 37 * use _cdecl. For systems where _cdecl is not compatible this 38 * must be defined. See linux/ah_osdep.h for an example. 39 */ 40#ifndef __ahdecl 41#define __ahdecl 42#endif 43 44/* 45 * Status codes that may be returned by the HAL. Note that 46 * interfaces that return a status code set it only when an 47 * error occurs--i.e. you cannot check it for success. 48 */ 49typedef enum { 50 HAL_OK = 0, /* No error */ 51 HAL_ENXIO = 1, /* No hardware present */ 52 HAL_ENOMEM = 2, /* Memory allocation failed */ 53 HAL_EIO = 3, /* Hardware didn't respond as expected */ 54 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 55 HAL_EEVERSION = 5, /* EEPROM version invalid */ 56 HAL_EELOCKED = 6, /* EEPROM unreadable */ 57 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 58 HAL_EEREAD = 8, /* EEPROM read problem */ 59 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 60 HAL_EESIZE = 10, /* EEPROM size not supported */ 61 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 62 HAL_EINVAL = 12, /* Invalid parameter to function */ 63 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 64 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 65 HAL_EINPROGRESS = 15, /* Operation incomplete */ 66 HAL_EEBADREG = 16, /* EEPROM invalid regulatory contents */ 67 HAL_EEBADCC = 17, /* EEPROM invalid country code */ 68} HAL_STATUS; 69 70typedef enum { 71 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 72 AH_TRUE = 1, 73} HAL_BOOL; 74 75typedef enum { 76 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 77 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 78 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 79 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 80 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 81 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 82 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 83 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 84 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 85 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ 86 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 87 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 88 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 89 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 90 HAL_CAP_TXPOW = 15, /* global tx power limit */ 91 HAL_CAP_TPC = 16, /* per-packet tx power control */ 92 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 93 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 94 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 95 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 96 /* 21 was HAL_CAP_XR */ 97 HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ 98 /* 23 was HAL_CAP_CHAN_HALFRATE */ 99 /* 24 was HAL_CAP_CHAN_QUARTERRATE */ 100 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 101 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 102 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 103 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 104 HAL_CAP_INTMIT = 29, /* interference mitigation */ 105 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */ 106 HAL_CAP_HT = 31, /* hardware can support HT */ 107 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */ 108 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */ 109 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */ 110 HAL_CAP_BB_HANG = 35, /* can baseband hang */ 111 HAL_CAP_MAC_HANG = 36, /* can MAC hang */ 112 HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */ 113 HAL_CAP_BSSIDMATCH = 38, /* hardware has disable bssid match */ 114 HAL_CAP_STREAMS = 39, /* how many 802.11n spatial streams are available */ 115} HAL_CAPABILITY_TYPE; 116 117/* 118 * "States" for setting the LED. These correspond to 119 * the possible 802.11 operational states and there may 120 * be a many-to-one mapping between these states and the 121 * actual hardware state for the LED's (i.e. the hardware 122 * may have fewer states). 123 */ 124typedef enum { 125 HAL_LED_INIT = 0, 126 HAL_LED_SCAN = 1, 127 HAL_LED_AUTH = 2, 128 HAL_LED_ASSOC = 3, 129 HAL_LED_RUN = 4 130} HAL_LED_STATE; 131 132/* 133 * Transmit queue types/numbers. These are used to tag 134 * each transmit queue in the hardware and to identify a set 135 * of transmit queues for operations such as start/stop dma. 136 */ 137typedef enum { 138 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 139 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 140 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 141 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 142 HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ 143} HAL_TX_QUEUE; 144 145#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ 146 147/* 148 * Transmit queue subtype. These map directly to 149 * WME Access Categories (except for UPSD). Refer 150 * to Table 5 of the WME spec. 151 */ 152typedef enum { 153 HAL_WME_AC_BK = 0, /* background access category */ 154 HAL_WME_AC_BE = 1, /* best effort access category*/ 155 HAL_WME_AC_VI = 2, /* video access category */ 156 HAL_WME_AC_VO = 3, /* voice access category */ 157 HAL_WME_UPSD = 4, /* uplink power save */ 158} HAL_TX_QUEUE_SUBTYPE; 159 160/* 161 * Transmit queue flags that control various 162 * operational parameters. 163 */ 164typedef enum { 165 /* 166 * Per queue interrupt enables. When set the associated 167 * interrupt may be delivered for packets sent through 168 * the queue. Without these enabled no interrupts will 169 * be delivered for transmits through the queue. 170 */ 171 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 172 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 173 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 174 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 175 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 176 /* 177 * Enable hardware compression for packets sent through 178 * the queue. The compression buffer must be setup and 179 * packets must have a key entry marked in the tx descriptor. 180 */ 181 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 182 /* 183 * Disable queue when veol is hit or ready time expires. 184 * By default the queue is disabled only on reaching the 185 * physical end of queue (i.e. a null link ptr in the 186 * descriptor chain). 187 */ 188 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 189 /* 190 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 191 * event. Frames will be transmitted only when this timer 192 * fires, e.g to transmit a beacon in ap or adhoc modes. 193 */ 194 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 195 /* 196 * Each transmit queue has a counter that is incremented 197 * each time the queue is enabled and decremented when 198 * the list of frames to transmit is traversed (or when 199 * the ready time for the queue expires). This counter 200 * must be non-zero for frames to be scheduled for 201 * transmission. The following controls disable bumping 202 * this counter under certain conditions. Typically this 203 * is used to gate frames based on the contents of another 204 * queue (e.g. CAB traffic may only follow a beacon frame). 205 * These are meaningful only when frames are scheduled 206 * with a non-ASAP policy (e.g. DBA-gated). 207 */ 208 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 209 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 210 211 /* 212 * Fragment burst backoff policy. Normally the no backoff 213 * is done after a successful transmission, the next fragment 214 * is sent at SIFS. If this flag is set backoff is done 215 * after each fragment, regardless whether it was ack'd or 216 * not, after the backoff count reaches zero a normal channel 217 * access procedure is done before the next transmit (i.e. 218 * wait AIFS instead of SIFS). 219 */ 220 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 221 /* 222 * Disable post-tx backoff following each frame. 223 */ 224 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 225 /* 226 * DCU arbiter lockout control. This controls how 227 * lower priority tx queues are handled with respect to 228 * to a specific queue when multiple queues have frames 229 * to send. No lockout means lower priority queues arbitrate 230 * concurrently with this queue. Intra-frame lockout 231 * means lower priority queues are locked out until the 232 * current frame transmits (e.g. including backoffs and bursting). 233 * Global lockout means nothing lower can arbitrary so 234 * long as there is traffic activity on this queue (frames, 235 * backoff, etc). 236 */ 237 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 238 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 239 240 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 241 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ 242} HAL_TX_QUEUE_FLAGS; 243 244typedef struct { 245 uint32_t tqi_ver; /* hal TXQ version */ 246 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 247 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 248 uint32_t tqi_priority; /* (not used) */ 249 uint32_t tqi_aifs; /* aifs */ 250 uint32_t tqi_cwmin; /* cwMin */ 251 uint32_t tqi_cwmax; /* cwMax */ 252 uint16_t tqi_shretry; /* rts retry limit */ 253 uint16_t tqi_lgretry; /* long retry limit (not used)*/ 254 uint32_t tqi_cbrPeriod; /* CBR period (us) */ 255 uint32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ 256 uint32_t tqi_burstTime; /* max burst duration (us) */ 257 uint32_t tqi_readyTime; /* frame schedule time (us) */ 258 uint32_t tqi_compBuf; /* comp buffer phys addr */ 259} HAL_TXQ_INFO; 260 261#define HAL_TQI_NONVAL 0xffff 262 263/* token to use for aifs, cwmin, cwmax */ 264#define HAL_TXQ_USEDEFAULT ((uint32_t) -1) 265 266/* compression definitions */ 267#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ 268#define HAL_COMP_BUF_ALIGN_SIZE 512 269 270/* 271 * Transmit packet types. This belongs in ah_desc.h, but 272 * is here so we can give a proper type to various parameters 273 * (and not require everyone include the file). 274 * 275 * NB: These values are intentionally assigned for 276 * direct use when setting up h/w descriptors. 277 */ 278typedef enum { 279 HAL_PKT_TYPE_NORMAL = 0, 280 HAL_PKT_TYPE_ATIM = 1, 281 HAL_PKT_TYPE_PSPOLL = 2, 282 HAL_PKT_TYPE_BEACON = 3, 283 HAL_PKT_TYPE_PROBE_RESP = 4, 284 HAL_PKT_TYPE_CHIRP = 5, 285 HAL_PKT_TYPE_GRP_POLL = 6, 286 HAL_PKT_TYPE_AMPDU = 7, 287} HAL_PKT_TYPE; 288 289/* Rx Filter Frame Types */ 290typedef enum { 291 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 292 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 293 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 294 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 295 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 296 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 297 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 298 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 299 HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors */ 300 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */ 301 HAL_RX_FILTER_BSSID = 0x00000800, /* Disable BSSID match */ 302} HAL_RX_FILTER; 303 304typedef enum { 305 HAL_PM_AWAKE = 0, 306 HAL_PM_FULL_SLEEP = 1, 307 HAL_PM_NETWORK_SLEEP = 2, 308 HAL_PM_UNDEFINED = 3 309} HAL_POWER_MODE; 310 311/* 312 * NOTE WELL: 313 * These are mapped to take advantage of the common locations for many of 314 * the bits on all of the currently supported MAC chips. This is to make 315 * the ISR as efficient as possible, while still abstracting HW differences. 316 * When new hardware breaks this commonality this enumerated type, as well 317 * as the HAL functions using it, must be modified. All values are directly 318 * mapped unless commented otherwise. 319 */ 320typedef enum { 321 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 322 HAL_INT_RXDESC = 0x00000002, 323 HAL_INT_RXNOFRM = 0x00000008, 324 HAL_INT_RXEOL = 0x00000010, 325 HAL_INT_RXORN = 0x00000020, 326 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 327 HAL_INT_TXDESC = 0x00000080, 328 HAL_INT_TIM_TIMER= 0x00000100, 329 HAL_INT_TXURN = 0x00000800, 330 HAL_INT_MIB = 0x00001000, 331 HAL_INT_RXPHY = 0x00004000, 332 HAL_INT_RXKCM = 0x00008000, 333 HAL_INT_SWBA = 0x00010000, 334 HAL_INT_BMISS = 0x00040000, 335 HAL_INT_BNR = 0x00100000, 336 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 337 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 338 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ 339 HAL_INT_GPIO = 0x01000000, 340 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 341 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */ 342 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */ 343 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 344 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 345 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 346#define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */ 347 HAL_INT_BMISC = HAL_INT_TIM 348 | HAL_INT_DTIM 349 | HAL_INT_DTIMSYNC 350 | HAL_INT_CABEND 351 | HAL_INT_TBTT, 352 353 /* Interrupt bits that map directly to ISR/IMR bits */ 354 HAL_INT_COMMON = HAL_INT_RXNOFRM 355 | HAL_INT_RXDESC 356 | HAL_INT_RXEOL 357 | HAL_INT_RXORN 358 | HAL_INT_TXDESC 359 | HAL_INT_TXURN 360 | HAL_INT_MIB 361 | HAL_INT_RXPHY 362 | HAL_INT_RXKCM 363 | HAL_INT_SWBA 364 | HAL_INT_BMISS 365 | HAL_INT_BNR 366 | HAL_INT_GPIO, 367} HAL_INT; 368 369typedef enum { 370 HAL_GPIO_MUX_OUTPUT = 0, 371 HAL_GPIO_MUX_PCIE_ATTENTION_LED = 1, 372 HAL_GPIO_MUX_PCIE_POWER_LED = 2, 373 HAL_GPIO_MUX_TX_FRAME = 3, 374 HAL_GPIO_MUX_RX_CLEAR_EXTERNAL = 4, 375 HAL_GPIO_MUX_MAC_NETWORK_LED = 5, 376 HAL_GPIO_MUX_MAC_POWER_LED = 6 377} HAL_GPIO_MUX_TYPE; 378 379typedef enum { 380 HAL_GPIO_INTR_LOW = 0, 381 HAL_GPIO_INTR_HIGH = 1, 382 HAL_GPIO_INTR_DISABLE = 2 383} HAL_GPIO_INTR_TYPE; 384 385typedef enum { 386 HAL_RFGAIN_INACTIVE = 0, 387 HAL_RFGAIN_READ_REQUESTED = 1, 388 HAL_RFGAIN_NEED_CHANGE = 2 389} HAL_RFGAIN; 390 391typedef uint16_t HAL_CTRY_CODE; /* country code */ 392typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 393 394#define HAL_ANTENNA_MIN_MODE 0 395#define HAL_ANTENNA_FIXED_A 1 396#define HAL_ANTENNA_FIXED_B 2 397#define HAL_ANTENNA_MAX_MODE 3 398 399typedef struct { 400 uint32_t ackrcv_bad; 401 uint32_t rts_bad; 402 uint32_t rts_good; 403 uint32_t fcs_bad; 404 uint32_t beacons; 405} HAL_MIB_STATS; 406 407enum { 408 HAL_MODE_11A = 0x001, /* 11a channels */ 409 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 410 HAL_MODE_11B = 0x004, /* 11b channels */ 411 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 412#ifdef notdef 413 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ 414#else 415 HAL_MODE_11G = 0x008, /* XXX historical */ 416#endif 417 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 418 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 419 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */ 420 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */ 421 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */ 422 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */ 423 HAL_MODE_11NG_HT20 = 0x008000, 424 HAL_MODE_11NA_HT20 = 0x010000, 425 HAL_MODE_11NG_HT40PLUS = 0x020000, 426 HAL_MODE_11NG_HT40MINUS = 0x040000, 427 HAL_MODE_11NA_HT40PLUS = 0x080000, 428 HAL_MODE_11NA_HT40MINUS = 0x100000, 429 HAL_MODE_ALL = 0xffffff 430}; 431 432typedef struct { 433 int rateCount; /* NB: for proper padding */ 434 uint8_t rateCodeToIndex[144]; /* back mapping */ 435 struct { 436 uint8_t valid; /* valid for rate control use */ 437 uint8_t phy; /* CCK/OFDM/XR */ 438 uint32_t rateKbps; /* transfer rate in kbs */ 439 uint8_t rateCode; /* rate for h/w descriptors */ 440 uint8_t shortPreamble; /* mask for enabling short 441 * preamble in CCK rate code */ 442 uint8_t dot11Rate; /* value for supported rates 443 * info element of MLME */ 444 uint8_t controlRate; /* index of next lower basic 445 * rate; used for dur. calcs */ 446 uint16_t lpAckDuration; /* long preamble ACK duration */ 447 uint16_t spAckDuration; /* short preamble ACK duration*/ 448 } info[32]; 449} HAL_RATE_TABLE; 450 451typedef struct { 452 u_int rs_count; /* number of valid entries */ 453 uint8_t rs_rates[32]; /* rates */ 454} HAL_RATE_SET; 455 456/* 457 * 802.11n specific structures and enums 458 */ 459typedef enum { 460 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 461 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 462} HAL_CHAIN_TYPE; 463 464typedef struct { 465 u_int Tries; 466 u_int Rate; 467 u_int PktDuration; 468 u_int ChSel; 469 u_int RateFlags; 470#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 471#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 472#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 473} HAL_11N_RATE_SERIES; 474 475typedef enum { 476 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 477 HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ 478} HAL_HT_MACMODE; 479 480typedef enum { 481 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 482 HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ 483} HAL_HT_PHYMODE; 484 485typedef enum { 486 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 487 HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ 488} HAL_HT_EXTPROTSPACING; 489 490 491typedef enum { 492 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ 493 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ 494} HAL_HT_RXCLEAR; 495 496/* 497 * Antenna switch control. By default antenna selection 498 * enables multiple (2) antenna use. To force use of the 499 * A or B antenna only specify a fixed setting. Fixing 500 * the antenna will also disable any diversity support. 501 */ 502typedef enum { 503 HAL_ANT_VARIABLE = 0, /* variable by programming */ 504 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 505 HAL_ANT_FIXED_B = 2, /* fixed antenna B */ 506} HAL_ANT_SETTING; 507 508typedef enum { 509 HAL_M_STA = 1, /* infrastructure station */ 510 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 511 HAL_M_HOSTAP = 6, /* Software Access Point */ 512 HAL_M_MONITOR = 8 /* Monitor mode */ 513} HAL_OPMODE; 514 515typedef struct { 516 uint8_t kv_type; /* one of HAL_CIPHER */ 517 uint8_t kv_pad; 518 uint16_t kv_len; /* length in bits */ 519 uint8_t kv_val[16]; /* enough for 128-bit keys */ 520 uint8_t kv_mic[8]; /* TKIP MIC key */ 521 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 522} HAL_KEYVAL; 523 524typedef enum { 525 HAL_CIPHER_WEP = 0, 526 HAL_CIPHER_AES_OCB = 1, 527 HAL_CIPHER_AES_CCM = 2, 528 HAL_CIPHER_CKIP = 3, 529 HAL_CIPHER_TKIP = 4, 530 HAL_CIPHER_CLR = 5, /* no encryption */ 531 532 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 533} HAL_CIPHER; 534 535enum { 536 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 537 HAL_SLOT_TIME_9 = 9, 538 HAL_SLOT_TIME_20 = 20, 539}; 540 541/* 542 * Per-station beacon timer state. Note that the specified 543 * beacon interval (given in TU's) can also include flags 544 * to force a TSF reset and to enable the beacon xmit logic. 545 * If bs_cfpmaxduration is non-zero the hardware is setup to 546 * coexist with a PCF-capable AP. 547 */ 548typedef struct { 549 uint32_t bs_nexttbtt; /* next beacon in TU */ 550 uint32_t bs_nextdtim; /* next DTIM in TU */ 551 uint32_t bs_intval; /* beacon interval+flags */ 552#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 553#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 554#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 555 uint32_t bs_dtimperiod; 556 uint16_t bs_cfpperiod; /* CFP period in TU */ 557 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 558 uint32_t bs_cfpnext; /* next CFP in TU */ 559 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 560 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 561 uint32_t bs_sleepduration; /* max sleep duration */ 562} HAL_BEACON_STATE; 563 564/* 565 * Like HAL_BEACON_STATE but for non-station mode setup. 566 * NB: see above flag definitions for bt_intval. 567 */ 568typedef struct { 569 uint32_t bt_intval; /* beacon interval+flags */ 570 uint32_t bt_nexttbtt; /* next beacon in TU */ 571 uint32_t bt_nextatim; /* next ATIM in TU */ 572 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 573 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 574 uint32_t bt_flags; /* timer enables */ 575#define HAL_BEACON_TBTT_EN 0x00000001 576#define HAL_BEACON_DBA_EN 0x00000002 577#define HAL_BEACON_SWBA_EN 0x00000004 578} HAL_BEACON_TIMERS; 579 580/* 581 * Per-node statistics maintained by the driver for use in 582 * optimizing signal quality and other operational aspects. 583 */ 584typedef struct { 585 uint32_t ns_avgbrssi; /* average beacon rssi */ 586 uint32_t ns_avgrssi; /* average data rssi */ 587 uint32_t ns_avgtxrssi; /* average tx rssi */ 588} HAL_NODE_STATS; 589 590#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 591 592struct ath_desc; 593struct ath_tx_status; 594struct ath_rx_status; 595struct ieee80211_channel; 596 597/* 598 * Hardware Access Layer (HAL) API. 599 * 600 * Clients of the HAL call ath_hal_attach to obtain a reference to an 601 * ath_hal structure for use with the device. Hardware-related operations 602 * that follow must call back into the HAL through interface, supplying 603 * the reference as the first parameter. Note that before using the 604 * reference returned by ath_hal_attach the caller should verify the 605 * ABI version number. 606 */ 607struct ath_hal { 608 uint32_t ah_magic; /* consistency check magic number */ 609 uint16_t ah_devid; /* PCI device ID */ 610 uint16_t ah_subvendorid; /* PCI subvendor ID */ 611 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 612 HAL_BUS_TAG ah_st; /* params for register r+w */ 613 HAL_BUS_HANDLE ah_sh; 614 HAL_CTRY_CODE ah_countryCode; 615 616 uint32_t ah_macVersion; /* MAC version id */ 617 uint16_t ah_macRev; /* MAC revision */ 618 uint16_t ah_phyRev; /* PHY revision */ 619 /* NB: when only one radio is present the rev is in 5Ghz */ 620 uint16_t ah_analog5GhzRev;/* 5GHz radio revision */ 621 uint16_t ah_analog2GhzRev;/* 2GHz radio revision */ 622 623 uint16_t *ah_eepromdata; /* eeprom buffer, if needed */ 624 625 const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, 626 u_int mode); 627 void __ahdecl(*ah_detach)(struct ath_hal*); 628 629 /* Reset functions */ 630 HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, 631 struct ieee80211_channel *, 632 HAL_BOOL bChannelChange, HAL_STATUS *status); 633 HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); 634 HAL_BOOL __ahdecl(*ah_disable)(struct ath_hal *); 635 void __ahdecl(*ah_configPCIE)(struct ath_hal *, HAL_BOOL restore); 636 void __ahdecl(*ah_disablePCIE)(struct ath_hal *); 637 void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); 638 HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, 639 struct ieee80211_channel *, HAL_BOOL *); 640 HAL_BOOL __ahdecl(*ah_perCalibrationN)(struct ath_hal *, 641 struct ieee80211_channel *, u_int chainMask, 642 HAL_BOOL longCal, HAL_BOOL *isCalDone); 643 HAL_BOOL __ahdecl(*ah_resetCalValid)(struct ath_hal *, 644 const struct ieee80211_channel *); 645 HAL_BOOL __ahdecl(*ah_setTxPower)(struct ath_hal *, 646 const struct ieee80211_channel *, uint16_t *); 647 HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 648 HAL_BOOL __ahdecl(*ah_setBoardValues)(struct ath_hal *, 649 const struct ieee80211_channel *); 650 651 /* Transmit functions */ 652 HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, 653 HAL_BOOL incTrigLevel); 654 int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, 655 const HAL_TXQ_INFO *qInfo); 656 HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, 657 const HAL_TXQ_INFO *qInfo); 658 HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, 659 HAL_TXQ_INFO *qInfo); 660 HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); 661 HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); 662 uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); 663 HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, uint32_t txdp); 664 uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); 665 HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); 666 HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); 667 HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, 668 u_int pktLen, u_int hdrLen, 669 HAL_PKT_TYPE type, u_int txPower, 670 u_int txRate0, u_int txTries0, 671 u_int keyIx, u_int antMode, u_int flags, 672 u_int rtsctsRate, u_int rtsctsDuration, 673 u_int compicvLen, u_int compivLen, 674 u_int comp); 675 HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, 676 u_int txRate1, u_int txTries1, 677 u_int txRate2, u_int txTries2, 678 u_int txRate3, u_int txTries3); 679 HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, 680 u_int segLen, HAL_BOOL firstSeg, 681 HAL_BOOL lastSeg, const struct ath_desc *); 682 HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, 683 struct ath_desc *, struct ath_tx_status *); 684 void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 685 void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); 686 HAL_BOOL __ahdecl(*ah_getTxCompletionRates)(struct ath_hal *, 687 const struct ath_desc *ds, int *rates, int *tries); 688 689 /* Receive Functions */ 690 uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); 691 void __ahdecl(*ah_setRxDP)(struct ath_hal*, uint32_t rxdp); 692 void __ahdecl(*ah_enableReceive)(struct ath_hal*); 693 HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); 694 void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); 695 void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); 696 void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, 697 uint32_t filter0, uint32_t filter1); 698 HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, 699 uint32_t index); 700 HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, 701 uint32_t index); 702 uint32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); 703 void __ahdecl(*ah_setRxFilter)(struct ath_hal*, uint32_t); 704 HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, 705 uint32_t size, u_int flags); 706 HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, 707 struct ath_desc *, uint32_t phyAddr, 708 struct ath_desc *next, uint64_t tsf, 709 struct ath_rx_status *); 710 void __ahdecl(*ah_rxMonitor)(struct ath_hal *, 711 const HAL_NODE_STATS *, 712 const struct ieee80211_channel *); 713 void __ahdecl(*ah_aniPoll)(struct ath_hal *, 714 const struct ieee80211_channel *); 715 void __ahdecl(*ah_procMibEvent)(struct ath_hal *, 716 const HAL_NODE_STATS *); 717 718 /* Misc Functions */ 719 HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, 720 HAL_CAPABILITY_TYPE, uint32_t capability, 721 uint32_t *result); 722 HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, 723 HAL_CAPABILITY_TYPE, uint32_t capability, 724 uint32_t setting, HAL_STATUS *); 725 HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, 726 const void *args, uint32_t argsize, 727 void **result, uint32_t *resultsize); 728 void __ahdecl(*ah_getMacAddress)(struct ath_hal *, uint8_t *); 729 HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const uint8_t*); 730 void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 731 HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const uint8_t*); 732 HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, 733 uint16_t, HAL_STATUS *); 734 void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); 735 void __ahdecl(*ah_writeAssocid)(struct ath_hal*, 736 const uint8_t *bssid, uint16_t assocId); 737 HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, 738 uint32_t gpio, HAL_GPIO_MUX_TYPE); 739 HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, uint32_t gpio); 740 uint32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, uint32_t gpio); 741 HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, 742 uint32_t gpio, uint32_t val); 743 void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, uint32_t); 744 uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); 745 uint64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); 746 void __ahdecl(*ah_resetTsf)(struct ath_hal*); 747 HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); 748 void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, 749 HAL_MIB_STATS*); 750 HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); 751 u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); 752 void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); 753 HAL_ANT_SETTING __ahdecl(*ah_getAntennaSwitch)(struct ath_hal*); 754 HAL_BOOL __ahdecl(*ah_setAntennaSwitch)(struct ath_hal*, 755 HAL_ANT_SETTING); 756 HAL_BOOL __ahdecl(*ah_setSifsTime)(struct ath_hal*, u_int); 757 u_int __ahdecl(*ah_getSifsTime)(struct ath_hal*); 758 HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); 759 u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); 760 HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); 761 u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); 762 HAL_BOOL __ahdecl(*ah_setAckCTSRate)(struct ath_hal*, u_int); 763 u_int __ahdecl(*ah_getAckCTSRate)(struct ath_hal*); 764 HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); 765 u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); 766 HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, uint16_t, int); 767 void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, uint8_t, int); 768 769 /* Key Cache Functions */ 770 uint32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); 771 HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, uint16_t); 772 HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, 773 uint16_t); 774 HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, 775 uint16_t, const HAL_KEYVAL *, 776 const uint8_t *, int); 777 HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, 778 uint16_t, const uint8_t *); 779 780 /* Power Management Functions */ 781 HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, 782 HAL_POWER_MODE mode, int setChip); 783 HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); 784 int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, 785 const struct ieee80211_channel *); 786 787 /* Beacon Management Functions */ 788 void __ahdecl(*ah_setBeaconTimers)(struct ath_hal*, 789 const HAL_BEACON_TIMERS *); 790 /* NB: deprecated, use ah_setBeaconTimers instead */ 791 void __ahdecl(*ah_beaconInit)(struct ath_hal *, 792 uint32_t nexttbtt, uint32_t intval); 793 void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, 794 const HAL_BEACON_STATE *); 795 void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); 796 797 /* 802.11n Functions */ 798 HAL_BOOL __ahdecl(*ah_chainTxDesc)(struct ath_hal *, 799 struct ath_desc *, u_int, u_int, HAL_PKT_TYPE, 800 u_int, HAL_CIPHER, uint8_t, u_int, HAL_BOOL, 801 HAL_BOOL); 802 HAL_BOOL __ahdecl(*ah_setupFirstTxDesc)(struct ath_hal *, 803 struct ath_desc *, u_int, u_int, u_int, 804 u_int, u_int, u_int, u_int, u_int); 805 HAL_BOOL __ahdecl(*ah_setupLastTxDesc)(struct ath_hal *, 806 struct ath_desc *, const struct ath_desc *); 807 void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *, 808 struct ath_desc *, u_int, u_int, 809 HAL_11N_RATE_SERIES [], u_int, u_int); 810 void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *, 811 struct ath_desc *, u_int); 812 void __ahdecl(*ah_clr11nAggr)(struct ath_hal *, 813 struct ath_desc *); 814 void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *, 815 struct ath_desc *, u_int); 816 uint32_t __ahdecl(*ah_get11nExtBusy)(struct ath_hal *); 817 void __ahdecl(*ah_set11nMac2040)(struct ath_hal *, 818 HAL_HT_MACMODE); 819 HAL_HT_RXCLEAR __ahdecl(*ah_get11nRxClear)(struct ath_hal *ah); 820 void __ahdecl(*ah_set11nRxClear)(struct ath_hal *, 821 HAL_HT_RXCLEAR); 822 823 /* Interrupt functions */ 824 HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); 825 HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); 826 HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); 827 HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); 828}; 829 830/* 831 * Check the PCI vendor ID and device ID against Atheros' values 832 * and return a printable description for any Atheros hardware. 833 * AH_NULL is returned if the ID's do not describe Atheros hardware. 834 */ 835extern const char *__ahdecl ath_hal_probe(uint16_t vendorid, uint16_t devid); 836 837/* 838 * Attach the HAL for use with the specified device. The device is 839 * defined by the PCI device ID. The caller provides an opaque pointer 840 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 841 * HAL state block for later use. Hardware register accesses are done 842 * using the specified bus tag and handle. On successful return a 843 * reference to a state block is returned that must be supplied in all 844 * subsequent HAL calls. Storage associated with this reference is 845 * dynamically allocated and must be freed by calling the ah_detach 846 * method when the client is done. If the attach operation fails a 847 * null (AH_NULL) reference will be returned and a status code will 848 * be returned if the status parameter is non-zero. 849 */ 850extern struct ath_hal * __ahdecl ath_hal_attach(uint16_t devid, HAL_SOFTC, 851 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata, HAL_STATUS* status); 852 853extern const char *ath_hal_mac_name(struct ath_hal *); 854extern const char *ath_hal_rf_name(struct ath_hal *); 855 856/* 857 * Regulatory interfaces. Drivers should use ath_hal_init_channels to 858 * request a set of channels for a particular country code and/or 859 * regulatory domain. If CTRY_DEFAULT and SKU_NONE are specified then 860 * this list is constructed according to the contents of the EEPROM. 861 * ath_hal_getchannels acts similarly but does not alter the operating 862 * state; this can be used to collect information for a particular 863 * regulatory configuration. Finally ath_hal_set_channels installs a 864 * channel list constructed outside the driver. The HAL will adopt the 865 * channel list and setup internal state according to the specified 866 * regulatory configuration (e.g. conformance test limits). 867 * 868 * For all interfaces the channel list is returned in the supplied array. 869 * maxchans defines the maximum size of this array. nchans contains the 870 * actual number of channels returned. If a problem occurred then a 871 * status code != HAL_OK is returned. 872 */ 873struct ieee80211_channel; 874 875/* 876 * Return a list of channels according to the specified regulatory. 877 */ 878extern HAL_STATUS __ahdecl ath_hal_getchannels(struct ath_hal *, 879 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 880 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn, 881 HAL_BOOL enableExtendedChannels); 882 883/* 884 * Return a list of channels and install it as the current operating 885 * regulatory list. 886 */ 887extern HAL_STATUS __ahdecl ath_hal_init_channels(struct ath_hal *, 888 struct ieee80211_channel *chans, u_int maxchans, int *nchans, 889 u_int modeSelect, HAL_CTRY_CODE cc, HAL_REG_DOMAIN rd, 890 HAL_BOOL enableExtendedChannels); 891 892/* 893 * Install the list of channels as the current operating regulatory 894 * and setup related state according to the country code and sku. 895 */ 896extern HAL_STATUS __ahdecl ath_hal_set_channels(struct ath_hal *, 897 struct ieee80211_channel *chans, int nchans, 898 HAL_CTRY_CODE cc, HAL_REG_DOMAIN regDmn); 899 900/* 901 * Calibrate noise floor data following a channel scan or similar. 902 * This must be called prior retrieving noise floor data. 903 */ 904extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); 905 906/* 907 * Return bit mask of wireless modes supported by the hardware. 908 */ 909extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*); 910 911/* 912 * Calculate the packet TX time for a legacy or 11n frame 913 */ 914extern uint32_t __ahdecl ath_hal_pkt_txtime(struct ath_hal *ah, 915 const HAL_RATE_TABLE *rates, uint32_t frameLen, 916 uint16_t rateix, HAL_BOOL isht40, HAL_BOOL shortPreamble); 917 918/* 919 * Calculate the duration of an 11n frame. 920 */ 921extern uint32_t __ahdecl ath_computedur_ht(uint32_t frameLen, uint16_t rate, 922 int streams, HAL_BOOL isht40, HAL_BOOL isShortGI); 923 924/* 925 * Calculate the transmit duration of a legacy frame. 926 */ 927extern uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, 928 const HAL_RATE_TABLE *rates, uint32_t frameLen, 929 uint16_t rateix, HAL_BOOL shortPreamble); 930#endif /* _ATH_AH_H_ */ 931