1183724Ssos/*- 2230132Suqs * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3183724Ssos * All rights reserved. 4183724Ssos * 5183724Ssos * Redistribution and use in source and binary forms, with or without 6183724Ssos * modification, are permitted provided that the following conditions 7183724Ssos * are met: 8183724Ssos * 1. Redistributions of source code must retain the above copyright 9183724Ssos * notice, this list of conditions and the following disclaimer, 10183724Ssos * without modification, immediately at the beginning of the file. 11183724Ssos * 2. Redistributions in binary form must reproduce the above copyright 12183724Ssos * notice, this list of conditions and the following disclaimer in the 13183724Ssos * documentation and/or other materials provided with the distribution. 14183724Ssos * 15183724Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183724Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17183724Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18183724Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19183724Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20183724Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21183724Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22183724Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23183724Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24183724Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25183724Ssos */ 26183724Ssos 27183724Ssos#include <sys/cdefs.h> 28183724Ssos__FBSDID("$FreeBSD: releng/10.2/sys/dev/ata/chipsets/ata-ati.c 281140 2015-04-06 08:23:06Z mav $"); 29183724Ssos 30183724Ssos#include <sys/param.h> 31183724Ssos#include <sys/module.h> 32183724Ssos#include <sys/systm.h> 33183724Ssos#include <sys/kernel.h> 34183724Ssos#include <sys/ata.h> 35183724Ssos#include <sys/bus.h> 36183724Ssos#include <sys/endian.h> 37183724Ssos#include <sys/malloc.h> 38183724Ssos#include <sys/lock.h> 39183724Ssos#include <sys/mutex.h> 40183724Ssos#include <sys/sema.h> 41183724Ssos#include <sys/taskqueue.h> 42183724Ssos#include <vm/uma.h> 43183724Ssos#include <machine/stdarg.h> 44183724Ssos#include <machine/resource.h> 45183724Ssos#include <machine/bus.h> 46183724Ssos#include <sys/rman.h> 47183724Ssos#include <dev/pci/pcivar.h> 48183724Ssos#include <dev/pci/pcireg.h> 49183724Ssos#include <dev/ata/ata-all.h> 50183724Ssos#include <dev/ata/ata-pci.h> 51183724Ssos#include <ata_if.h> 52183724Ssos 53183724Ssos/* local prototypes */ 54183724Ssosstatic int ata_ati_chipinit(device_t dev); 55228200Smavstatic int ata_ati_dumb_ch_attach(device_t dev); 56201993Smavstatic int ata_ati_ixp700_ch_attach(device_t dev); 57200171Smavstatic int ata_ati_setmode(device_t dev, int target, int mode); 58183724Ssos 59183724Ssos/* misc defines */ 60233282Smarius#define SII_MEMIO 1 /* must match ata_siliconimage.c's definition */ 61233282Smarius#define SII_BUG 0x04 /* must match ata_siliconimage.c's definition */ 62233282Smarius 63233282Smarius#define ATI_SATA SII_MEMIO 64233282Smarius#define ATI_PATA 0x02 65183724Ssos#define ATI_AHCI 0x04 66183724Ssos 67228200Smavstatic int force_ahci = 1; 68228200SmavTUNABLE_INT("hw.ahci.force", &force_ahci); 69183724Ssos 70183724Ssos/* 71183724Ssos * ATI chipset support functions 72183724Ssos */ 73183724Ssosstatic int 74183724Ssosata_ati_probe(device_t dev) 75183724Ssos{ 76183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 77242625Sdim static const struct ata_chip_id ids[] = 78183724Ssos {{ ATA_ATI_IXP200, 0x00, ATI_PATA, 0, ATA_UDMA5, "IXP200" }, 79183724Ssos { ATA_ATI_IXP300, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP300" }, 80233282Smarius { ATA_ATI_IXP300_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP300" }, 81183724Ssos { ATA_ATI_IXP400, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP400" }, 82233282Smarius { ATA_ATI_IXP400_S1, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 83233282Smarius { ATA_ATI_IXP400_S2, 0x00, ATI_SATA, SII_BUG, ATA_SA150, "IXP400" }, 84183724Ssos { ATA_ATI_IXP600, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP600" }, 85183724Ssos { ATA_ATI_IXP600_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP600" }, 86191568Sjkim { ATA_ATI_IXP700, 0x00, ATI_PATA, 0, ATA_UDMA6, "IXP700/800" }, 87191568Sjkim { ATA_ATI_IXP700_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 88191568Sjkim { ATA_ATI_IXP700_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 89191568Sjkim { ATA_ATI_IXP700_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 90191568Sjkim { ATA_ATI_IXP700_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP700/800" }, 91191568Sjkim { ATA_ATI_IXP800_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 92191568Sjkim { ATA_ATI_IXP800_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "IXP800" }, 93244146Smav { ATA_AMD_HUDSON2, 0x00, ATI_PATA, 0, ATA_UDMA6, "Hudson-2" }, 94244146Smav { ATA_AMD_HUDSON2_S1, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 95244146Smav { ATA_AMD_HUDSON2_S2, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 96244146Smav { ATA_AMD_HUDSON2_S3, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 97244146Smav { ATA_AMD_HUDSON2_S4, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 98244146Smav { ATA_AMD_HUDSON2_S5, 0x00, ATI_AHCI, 0, ATA_SA300, "Hudson-2" }, 99183724Ssos { 0, 0, 0, 0, 0, 0}}; 100183724Ssos 101268250Smarius if (pci_get_vendor(dev) != ATA_AMD_ID && pci_get_vendor(dev) != ATA_ATI_ID) 102183724Ssos return ENXIO; 103183724Ssos 104183724Ssos if (!(ctlr->chip = ata_match_chip(dev, ids))) 105183724Ssos return ENXIO; 106183724Ssos 107183724Ssos ata_set_desc(dev); 108183724Ssos 109183724Ssos switch (ctlr->chip->cfg1) { 110183724Ssos case ATI_PATA: 111183724Ssos ctlr->chipinit = ata_ati_chipinit; 112183724Ssos break; 113183724Ssos case ATI_SATA: 114183724Ssos /* 115183724Ssos * the ATI SATA controller is actually a SiI 3112 controller 116183724Ssos */ 117183724Ssos ctlr->chipinit = ata_sii_chipinit; 118183724Ssos break; 119183724Ssos case ATI_AHCI: 120228200Smav if (force_ahci == 1 || pci_get_subclass(dev) != PCIS_STORAGE_IDE) 121228200Smav ctlr->chipinit = ata_ahci_chipinit; 122228200Smav else 123228200Smav ctlr->chipinit = ata_ati_chipinit; 124183724Ssos break; 125183724Ssos } 126281140Smav return (BUS_PROBE_LOW_PRIORITY); 127183724Ssos} 128183724Ssos 129183724Ssosstatic int 130183724Ssosata_ati_chipinit(device_t dev) 131183724Ssos{ 132183724Ssos struct ata_pci_controller *ctlr = device_get_softc(dev); 133197783Sjkim device_t smbdev; 134201993Smav uint8_t satacfg; 135183724Ssos 136183724Ssos if (ata_setup_interrupt(dev, ata_generic_intr)) 137183724Ssos return ENXIO; 138183724Ssos 139228200Smav if (ctlr->chip->cfg1 == ATI_AHCI) { 140228200Smav ctlr->ch_attach = ata_ati_dumb_ch_attach; 141228200Smav ctlr->setmode = ata_sata_setmode; 142228200Smav return (0); 143228200Smav } 144197783Sjkim switch (ctlr->chip->chipid) { 145197783Sjkim case ATA_ATI_IXP600: 146197783Sjkim /* IXP600 only has 1 PATA channel */ 147183724Ssos ctlr->channels = 1; 148197783Sjkim break; 149197783Sjkim case ATA_ATI_IXP700: 150197783Sjkim /* 151197783Sjkim * When "combined mode" is enabled, an additional PATA channel is 152197783Sjkim * emulated with two SATA ports and appears on this device. 153197783Sjkim * This mode can only be detected via SMB controller. 154197783Sjkim */ 155197783Sjkim smbdev = pci_find_device(ATA_ATI_ID, 0x4385); 156197783Sjkim if (smbdev != NULL) { 157197783Sjkim satacfg = pci_read_config(smbdev, 0xad, 1); 158197783Sjkim if (bootverbose) 159197783Sjkim device_printf(dev, "SATA controller %s (%s%s channel)\n", 160197783Sjkim (satacfg & 0x01) == 0 ? "disabled" : "enabled", 161197783Sjkim (satacfg & 0x08) == 0 ? "" : "combined mode, ", 162197783Sjkim (satacfg & 0x10) == 0 ? "primary" : "secondary"); 163201993Smav ctlr->chipset_data = (void *)(uintptr_t)satacfg; 164197783Sjkim /* 165197783Sjkim * If SATA controller is enabled but combined mode is disabled, 166197783Sjkim * we have only one PATA channel. Ignore a non-existent channel. 167197783Sjkim */ 168197783Sjkim if ((satacfg & 0x09) == 0x01) 169197783Sjkim ctlr->ichannels &= ~(1 << ((satacfg & 0x10) >> 4)); 170201993Smav else { 171201993Smav ctlr->ch_attach = ata_ati_ixp700_ch_attach; 172201993Smav } 173197783Sjkim } 174197783Sjkim break; 175197783Sjkim } 176197783Sjkim 177183724Ssos ctlr->setmode = ata_ati_setmode; 178183724Ssos return 0; 179183724Ssos} 180183724Ssos 181200171Smavstatic int 182228200Smavata_ati_dumb_ch_attach(device_t dev) 183228200Smav{ 184228200Smav struct ata_channel *ch = device_get_softc(dev); 185228200Smav 186228200Smav if (ata_pci_ch_attach(dev)) 187228200Smav return ENXIO; 188228200Smav ch->flags |= ATA_SATA; 189228200Smav return (0); 190228200Smav} 191228200Smav 192228200Smavstatic int 193201993Smavata_ati_ixp700_ch_attach(device_t dev) 194201993Smav{ 195201993Smav struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 196201993Smav struct ata_channel *ch = device_get_softc(dev); 197201993Smav uint8_t satacfg = (uint8_t)(uintptr_t)ctlr->chipset_data; 198201993Smav 199201993Smav /* Setup the usual register normal pci style. */ 200201993Smav if (ata_pci_ch_attach(dev)) 201201993Smav return ENXIO; 202201993Smav 203201993Smav /* One of channels is PATA, another is SATA. */ 204201993Smav if (ch->unit == ((satacfg & 0x10) >> 4)) 205201993Smav ch->flags |= ATA_SATA; 206201993Smav return (0); 207201993Smav} 208201993Smav 209201993Smavstatic int 210200171Smavata_ati_setmode(device_t dev, int target, int mode) 211183724Ssos{ 212200171Smav device_t parent = device_get_parent(dev); 213200171Smav struct ata_pci_controller *ctlr = device_get_softc(parent); 214200171Smav struct ata_channel *ch = device_get_softc(dev); 215200171Smav int devno = (ch->unit << 1) + target; 216200171Smav int offset = (devno ^ 0x01) << 3; 217200171Smav int piomode; 218233282Smarius static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 219233282Smarius static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 220183724Ssos 221200171Smav mode = min(mode, ctlr->chip->max_dma); 222183724Ssos if (mode >= ATA_UDMA0) { 223200171Smav /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 224200171Smav pci_write_config(parent, 0x56, 225200171Smav (pci_read_config(parent, 0x56, 2) & 226183724Ssos ~(0xf << (devno << 2))) | 227183724Ssos ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 228200171Smav pci_write_config(parent, 0x54, 229200171Smav pci_read_config(parent, 0x54, 1) | 230183724Ssos (0x01 << devno), 1); 231200171Smav pci_write_config(parent, 0x44, 232200171Smav (pci_read_config(parent, 0x44, 4) & 233183724Ssos ~(0xff << offset)) | 234183724Ssos (dmatimings[2] << offset), 4); 235200171Smav piomode = ATA_PIO4; 236200171Smav } else if (mode >= ATA_WDMA0) { 237200171Smav /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 238200171Smav pci_write_config(parent, 0x54, 239200171Smav pci_read_config(parent, 0x54, 1) & 240183724Ssos ~(0x01 << devno), 1); 241200171Smav pci_write_config(parent, 0x44, 242200171Smav (pci_read_config(parent, 0x44, 4) & 243183724Ssos ~(0xff << offset)) | 244183724Ssos (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 245200171Smav piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 246200171Smav (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 247200171Smav } else { 248200171Smav /* Disable UDMA, set requested PIO. */ 249200171Smav pci_write_config(parent, 0x54, 250200171Smav pci_read_config(parent, 0x54, 1) & 251200171Smav ~(0x01 << devno), 1); 252200171Smav piomode = mode; 253183724Ssos } 254200171Smav /* Set PIO mode and timings, calculated above. */ 255200171Smav pci_write_config(parent, 0x4a, 256200171Smav (pci_read_config(parent, 0x4a, 2) & 257183724Ssos ~(0xf << (devno << 2))) | 258200171Smav ((piomode - ATA_PIO0) << (devno<<2)),2); 259200171Smav pci_write_config(parent, 0x40, 260200171Smav (pci_read_config(parent, 0x40, 4) & 261183724Ssos ~(0xff << offset)) | 262200171Smav (piotimings[ata_mode2idx(piomode)] << offset), 4); 263200171Smav return (mode); 264183724Ssos} 265183724Ssos 266183724SsosATA_DECLARE_DRIVER(ata_ati); 267183724SsosMODULE_DEPEND(ata_ati, ata_ahci, 1, 1, 1); 268183724SsosMODULE_DEPEND(ata_ati, ata_sii, 1, 1, 1); 269