ata-ahci.c revision 193277
1/*- 2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-ahci.c 193277 2009-06-01 21:42:26Z mav $"); 29 30#include "opt_ata.h" 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/kernel.h> 35#include <sys/ata.h> 36#include <sys/bus.h> 37#include <sys/endian.h> 38#include <sys/malloc.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/sema.h> 42#include <sys/taskqueue.h> 43#include <vm/uma.h> 44#include <machine/stdarg.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/rman.h> 48#include <dev/pci/pcivar.h> 49#include <dev/pci/pcireg.h> 50#include <dev/ata/ata-all.h> 51#include <dev/ata/ata-pci.h> 52#include <ata_if.h> 53 54/* local prototypes */ 55static int ata_ahci_suspend(device_t dev); 56static int ata_ahci_status(device_t dev); 57static int ata_ahci_begin_transaction(struct ata_request *request); 58static int ata_ahci_end_transaction(struct ata_request *request); 59static int ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result); 60static int ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t result); 61static int ata_ahci_hardreset(device_t dev, int port, uint32_t *signature); 62static u_int32_t ata_ahci_softreset(device_t dev, int port); 63static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 64static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *equest); 65static void ata_ahci_dmainit(device_t dev); 66static void ata_ahci_start(device_t dev); 67static void ata_ahci_stop(device_t dev); 68static void ata_ahci_clo(device_t dev); 69static void ata_ahci_start_fr(device_t dev); 70static void ata_ahci_stop_fr(device_t dev); 71 72/* 73 * AHCI v1.x compliant SATA chipset support functions 74 */ 75static int 76ata_ahci_probe(device_t dev) 77{ 78 struct ata_pci_controller *ctlr = device_get_softc(dev); 79 char buffer[64]; 80 81 /* is this a possible AHCI candidate ? */ 82 if (pci_get_class(dev) != PCIC_STORAGE || 83 pci_get_subclass(dev) != PCIS_STORAGE_SATA) 84 return (ENXIO); 85 86 /* is this PCI device flagged as an AHCI compliant chip ? */ 87 if (pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0) 88 return (ENXIO); 89 90 if (bootverbose) 91 sprintf(buffer, "%s (ID=%08x) AHCI controller", 92 ata_pcivendor2str(dev), pci_get_devid(dev)); 93 else 94 sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev)); 95 device_set_desc_copy(dev, buffer); 96 ctlr->chipinit = ata_ahci_chipinit; 97 return (BUS_PROBE_GENERIC); 98} 99 100int 101ata_ahci_chipinit(device_t dev) 102{ 103 struct ata_pci_controller *ctlr = device_get_softc(dev); 104 int error, speed; 105 u_int32_t caps, version; 106 107 /* if we have a memory BAR(5) we are likely on an AHCI part */ 108 ctlr->r_type2 = SYS_RES_MEMORY; 109 ctlr->r_rid2 = PCIR_BAR(5); 110 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 111 &ctlr->r_rid2, RF_ACTIVE))) 112 return ENXIO; 113 114 /* setup interrupt delivery if not done allready by a vendor driver */ 115 if (!ctlr->r_irq) { 116 if (ata_setup_interrupt(dev, ata_generic_intr)) { 117 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 118 return ENXIO; 119 } 120 } 121 else 122 device_printf(dev, "AHCI called from vendor specific driver\n"); 123 124 /* reset controller */ 125 if ((error = ata_ahci_ctlr_reset(dev)) != 0) { 126 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2); 127 return (error); 128 }; 129 130 /* get the number of HW channels */ 131 ctlr->ichannels = ATA_INL(ctlr->r_res2, ATA_AHCI_PI); 132 ctlr->channels = 133 MAX(flsl(ctlr->ichannels), 134 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_NPMASK) + 1); 135 136 ctlr->reset = ata_ahci_reset; 137 ctlr->ch_attach = ata_ahci_ch_attach; 138 ctlr->ch_detach = ata_ahci_ch_detach; 139 ctlr->ch_suspend = ata_ahci_ch_suspend; 140 ctlr->ch_resume = ata_ahci_ch_resume; 141 ctlr->setmode = ata_sata_setmode; 142 ctlr->suspend = ata_ahci_suspend; 143 ctlr->resume = ata_ahci_ctlr_reset; 144 145 /* announce we support the HW */ 146 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS); 147 caps = ATA_INL(ctlr->r_res2, ATA_AHCI_CAP); 148 speed = (caps & ATA_AHCI_CAP_ISS) >> ATA_AHCI_CAP_ISS_SHIFT; 149 device_printf(dev, 150 "AHCI v%x.%02x controller with %d %sGbps ports, PM %s\n", 151 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 152 ((version >> 4) & 0xf0) + (version & 0x0f), 153 (caps & ATA_AHCI_CAP_NPMASK) + 1, 154 ((speed == 1) ? "1.5":((speed == 2) ? "3": 155 ((speed == 3) ? "6":"?"))), 156 (caps & ATA_AHCI_CAP_SPM) ? 157 "supported" : "not supported"); 158 if (bootverbose) { 159 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 160 (caps & ATA_AHCI_CAP_64BIT) ? " 64bit":"", 161 (caps & ATA_AHCI_CAP_SNCQ) ? " NCQ":"", 162 (caps & ATA_AHCI_CAP_SSNTF) ? " SNTF":"", 163 (caps & ATA_AHCI_CAP_SMPS) ? " MPS":"", 164 (caps & ATA_AHCI_CAP_SSS) ? " SS":"", 165 (caps & ATA_AHCI_CAP_SALP) ? " ALP":"", 166 (caps & ATA_AHCI_CAP_SAL) ? " AL":"", 167 (caps & ATA_AHCI_CAP_SCLO) ? " CLO":"", 168 ((speed == 1) ? "1.5":((speed == 2) ? "3": 169 ((speed == 3) ? "6":"?")))); 170 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 171 (caps & ATA_AHCI_CAP_SAM) ? " AM":"", 172 (caps & ATA_AHCI_CAP_SPM) ? " PM":"", 173 (caps & ATA_AHCI_CAP_FBSS) ? " FBS":"", 174 (caps & ATA_AHCI_CAP_PMD) ? " PMD":"", 175 (caps & ATA_AHCI_CAP_SSC) ? " SSC":"", 176 (caps & ATA_AHCI_CAP_PSC) ? " PSC":"", 177 ((caps & ATA_AHCI_CAP_NCS) >> ATA_AHCI_CAP_NCS_SHIFT) + 1, 178 (caps & ATA_AHCI_CAP_CCCS) ? " CCC":"", 179 (caps & ATA_AHCI_CAP_EMS) ? " EM":"", 180 (caps & ATA_AHCI_CAP_SXS) ? " eSATA":"", 181 (caps & ATA_AHCI_CAP_NPMASK) + 1); 182 } 183 return 0; 184} 185 186int 187ata_ahci_ctlr_reset(device_t dev) 188{ 189 struct ata_pci_controller *ctlr = device_get_softc(dev); 190 int timeout; 191 192 /* enable AHCI mode */ 193 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 194 195 /* reset AHCI controller */ 196 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE|ATA_AHCI_GHC_HR); 197 for (timeout = 1000; timeout > 0; timeout--) { 198 DELAY(1000); 199 if ((ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) == 0) 200 break; 201 } 202 if (timeout == 0) { 203 device_printf(dev, "AHCI controller reset failure\n"); 204 return ENXIO; 205 } 206 207 /* reenable AHCI mode */ 208 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE); 209 210 /* clear interrupts */ 211 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS)); 212 213 /* enable AHCI interrupts */ 214 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 215 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE); 216 217 return 0; 218} 219 220static int 221ata_ahci_suspend(device_t dev) 222{ 223 struct ata_pci_controller *ctlr = device_get_softc(dev); 224 225 /* disable interupts so the state change(s) doesn't trigger */ 226 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, 227 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & (~ATA_AHCI_GHC_IE)); 228 return 0; 229} 230 231int 232ata_ahci_ch_attach(device_t dev) 233{ 234 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 235 struct ata_channel *ch = device_get_softc(dev); 236 int offset = ch->unit << 7; 237 238 ata_ahci_dmainit(dev); 239 240 /* set the SATA resources */ 241 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 242 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset; 243 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 244 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset; 245 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 246 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset; 247 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2; 248 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset; 249 250 ch->hw.status = ata_ahci_status; 251 ch->hw.begin_transaction = ata_ahci_begin_transaction; 252 ch->hw.end_transaction = ata_ahci_end_transaction; 253 ch->hw.command = NULL; /* not used here */ 254 ch->hw.softreset = ata_ahci_softreset; 255 ch->hw.pm_read = ata_ahci_pm_read; 256 ch->hw.pm_write = ata_ahci_pm_write; 257 258 ata_ahci_ch_resume(dev); 259 return 0; 260} 261 262int 263ata_ahci_ch_detach(device_t dev) 264{ 265 266 ata_ahci_ch_suspend(dev); 267 ata_dmafini(dev); 268 return (0); 269} 270 271int 272ata_ahci_ch_suspend(device_t dev) 273{ 274 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 275 struct ata_channel *ch = device_get_softc(dev); 276 int offset = ch->unit << 7; 277 278 /* Disable port interrupts. */ 279 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 280 /* Reset command register. */ 281 ata_ahci_stop(dev); 282 ata_ahci_stop_fr(dev); 283 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 0); 284 285 /* Allow everything including partial and slumber modes. */ 286 ATA_IDX_OUTL(ch, ATA_SCONTROL, 0); 287 /* Request slumber mode transition and give some time to get there. */ 288 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SLUMBER); 289 DELAY(100); 290 /* Disable PHY. */ 291 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_DISABLE); 292 293 return (0); 294} 295 296int 297ata_ahci_ch_resume(device_t dev) 298{ 299 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 300 struct ata_channel *ch = device_get_softc(dev); 301 uint64_t work; 302 int offset = ch->unit << 7; 303 304 /* Disable port interrupts */ 305 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 306 307 /* setup work areas */ 308 work = ch->dma.work_bus + ATA_AHCI_CL_OFFSET; 309 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff); 310 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32); 311 312 work = ch->dma.work_bus + ATA_AHCI_FB_OFFSET; 313 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff); 314 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32); 315 316 /* activate the channel and power/spin up device */ 317 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 318 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD | 319 ((ch->pm_level > 1) ? ATA_AHCI_P_CMD_ALPE : 0) | 320 ((ch->pm_level > 2) ? ATA_AHCI_P_CMD_ASP : 0 ))); 321 ata_ahci_start_fr(dev); 322 ata_ahci_start(dev); 323 324 return (0); 325} 326 327static int 328ata_ahci_status(device_t dev) 329{ 330 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 331 struct ata_channel *ch = device_get_softc(dev); 332 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS); 333 int offset = ch->unit << 7; 334 335#define ATA_AHCI_STATBITS \ 336 (ATA_AHCI_P_IX_IF|ATA_AHCI_P_IX_HBD|ATA_AHCI_P_IX_HBF|ATA_AHCI_P_IX_TFE) 337 338 if (action & (1 << ch->unit)) { 339 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset); 340 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset); 341 342 /* clear interrupt(s) */ 343 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus); 344 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, 1 << ch->unit); 345 346 /* do we have any PHY events ? */ 347 if (istatus & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC)) 348 ata_sata_phy_check_events(dev); 349 350 /* do we have a potentially hanging engine to take care of? */ 351 /* XXX SOS what todo on NCQ */ 352 if ((istatus & ATA_AHCI_STATBITS) && (cstatus & 1)) { 353 354 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 355 int timeout = 0; 356 357 /* kill off all activity on this channel */ 358 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 359 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 360 361 /* XXX SOS this is not entirely wrong */ 362 do { 363 DELAY(1000); 364 if (timeout++ > 1000) { 365 device_printf(dev, "stopping AHCI engine failed\n"); 366 break; 367 } 368 } while (ATA_INL(ctlr->r_res2, 369 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 370 371 /* start operations on this channel */ 372 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 373 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST)); 374 375 return 1; 376 } 377 else 378 /* XXX SOS what todo on NCQ */ 379 return (!(cstatus & 1)); 380 } 381 return 0; 382} 383 384/* must be called with ATA channel locked and state_mtx held */ 385static int 386ata_ahci_begin_transaction(struct ata_request *request) 387{ 388 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 389 struct ata_channel *ch = device_get_softc(request->parent); 390 struct ata_device *atadev = device_get_softc(request->dev); 391 struct ata_ahci_cmd_tab *ctp; 392 struct ata_ahci_cmd_list *clp; 393 int offset = ch->unit << 7; 394 int port = atadev->unit & 0x0f; 395 int entries = 0; 396 int fis_size; 397 398 /* get a piece of the workspace for this request */ 399 ctp = (struct ata_ahci_cmd_tab *) 400 (ch->dma.work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE*request->tag)); 401 402 /* setup the FIS for this request */ 403 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) { 404 device_printf(request->dev, "setting up SATA FIS failed\n"); 405 request->result = EIO; 406 return ATA_OP_FINISHED; 407 } 408 409 /* if request moves data setup and load SG list */ 410 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) { 411 if (ch->dma.load(request, ctp->prd_tab, &entries)) { 412 device_printf(request->dev, "setting up DMA failed\n"); 413 request->result = EIO; 414 return ATA_OP_FINISHED; 415 } 416 } 417 418 /* setup the command list entry */ 419 clp = (struct ata_ahci_cmd_list *) 420 (ch->dma.work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE*request->tag)); 421 422 clp->prd_length = entries; 423 clp->cmd_flags = (request->flags & ATA_R_WRITE ? ATA_AHCI_CMD_WRITE : 0) | 424 (request->flags & ATA_R_ATAPI ? 425 (ATA_AHCI_CMD_ATAPI | ATA_AHCI_CMD_PREFETCH) : 0) | 426 (fis_size / sizeof(u_int32_t)) | 427 (port << 12); 428 clp->bytecount = 0; 429 clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET + 430 (ATA_AHCI_CT_SIZE * request->tag)); 431 432 /* clear eventual ACTIVE bit */ 433 ATA_IDX_OUTL(ch, ATA_SACTIVE, 434 ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << request->tag)); 435 436 /* set command type bit */ 437 if (request->flags & ATA_R_ATAPI) 438 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 439 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) | 440 ATA_AHCI_P_CMD_ATAPI); 441 else 442 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 443 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & 444 ~ATA_AHCI_P_CMD_ATAPI); 445 446 /* issue command to controller */ 447 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << request->tag)); 448 449 if (!(request->flags & ATA_R_ATAPI)) { 450 /* device reset doesn't interrupt */ 451 if (request->u.ata.command == ATA_DEVICE_RESET) { 452 u_int32_t tf_data; 453 int timeout = 1000000; 454 455 do { 456 DELAY(10); 457 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7)); 458 } while ((tf_data & ATA_S_BUSY) && timeout--); 459 if (bootverbose) 460 device_printf(ch->dev, "device_reset timeout=%dus\n", 461 (1000000-timeout)*10); 462 request->status = tf_data; 463 if (request->status & ATA_S_ERROR) 464 request->error = tf_data >> 8; 465 return ATA_OP_FINISHED; 466 } 467 } 468 469 /* start the timeout */ 470 callout_reset(&request->callout, request->timeout * hz, 471 (timeout_t*)ata_timeout, request); 472 return ATA_OP_CONTINUES; 473} 474 475/* must be called with ATA channel locked and state_mtx held */ 476static int 477ata_ahci_end_transaction(struct ata_request *request) 478{ 479 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev)); 480 struct ata_channel *ch = device_get_softc(request->parent); 481 struct ata_ahci_cmd_list *clp; 482 u_int32_t tf_data; 483 int offset = ch->unit << 7; 484 485 /* kill the timeout */ 486 callout_stop(&request->callout); 487 488 /* get status */ 489 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset); 490 request->status = tf_data; 491 492 /* if error status get details */ 493 if (request->status & ATA_S_ERROR) 494 request->error = tf_data >> 8; 495 496 /* on control commands read back registers to the request struct */ 497 if (request->flags & ATA_R_CONTROL) { 498 struct ata_device *atadev = device_get_softc(request->dev); 499 u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40; 500 501 request->u.ata.count = fis[12] | ((u_int16_t)fis[13] << 8); 502 request->u.ata.lba = fis[4] | ((u_int64_t)fis[5] << 8) | 503 ((u_int64_t)fis[6] << 16); 504 if (atadev->flags & ATA_D_48BIT_ACTIVE) 505 request->u.ata.lba |= ((u_int64_t)fis[8] << 24) | 506 ((u_int64_t)fis[9] << 32) | 507 ((u_int64_t)fis[10] << 40); 508 else 509 request->u.ata.lba |= ((u_int64_t)(fis[7] & 0x0f) << 24); 510 } 511 512 /* record how much data we actually moved */ 513 clp = (struct ata_ahci_cmd_list *) 514 (ch->dma.work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE*request->tag)); 515 request->donecount = clp->bytecount; 516 517 /* release SG list etc */ 518 ch->dma.unload(request); 519 520 return ATA_OP_FINISHED; 521} 522 523static int 524ata_ahci_issue_cmd(device_t dev, u_int16_t flags, int timeout) 525{ 526 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 527 struct ata_channel *ch = device_get_softc(dev); 528 struct ata_ahci_cmd_list *clp = 529 (struct ata_ahci_cmd_list *)(ch->dma.work + ATA_AHCI_CL_OFFSET); 530 struct ata_ahci_cmd_tab *ctp = 531 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET); 532 u_int32_t status = 0; 533 int offset = ch->unit << 7; 534 int port = (ctp->cfis[1] & 0x0f); 535 int count; 536 537 clp->prd_length = 0; 538 clp->cmd_flags = (20 / sizeof(u_int32_t)) | flags | (port << 12); 539 clp->bytecount = 0; 540 clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET); 541 542 /* issue command to controller */ 543 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, 1); 544 545 /* poll for command finished */ 546 for (count = 0; count < timeout; count++) { 547 DELAY(1000); 548 if (!((status = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset)) & 1)) 549 break; 550 } 551 552 /* clear interrupts */ 553 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 554 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 555 556 if (timeout && (count >= timeout)) { 557 if (bootverbose) { 558 device_printf(dev, "ahci_issue_cmd timeout: %d of %dms, status=%08x\n", 559 count, timeout, status); 560 } 561 return EIO; 562 } 563 564 return 0; 565} 566 567static int 568ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result) 569{ 570 struct ata_channel *ch = device_get_softc(dev); 571 struct ata_ahci_cmd_tab *ctp = 572 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET); 573 u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40; 574 575 bzero(ctp->cfis, 64); 576 ctp->cfis[0] = 0x27; /* host to device */ 577 ctp->cfis[1] = 0x8f; /* command FIS to PM port */ 578 ctp->cfis[2] = ATA_READ_PM; 579 ctp->cfis[3] = reg; 580 ctp->cfis[7] = port | ATA_D_LBA; 581 ctp->cfis[15] = ATA_A_4BIT; 582 583 if (ata_ahci_issue_cmd(dev, 0, 10)) { 584 device_printf(dev, "error reading PM port\n"); 585 return EIO; 586 } 587 588 *result = fis[12] | (fis[4] << 8) | (fis[5] << 16) | (fis[6] << 24); 589 return 0; 590} 591 592static int 593ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t value) 594{ 595 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 596 struct ata_channel *ch = device_get_softc(dev); 597 struct ata_ahci_cmd_tab *ctp = 598 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET); 599 int offset = ch->unit << 7; 600 601 bzero(ctp->cfis, 64); 602 ctp->cfis[0] = 0x27; /* host to device */ 603 ctp->cfis[1] = 0x8f; /* command FIS to PM port */ 604 ctp->cfis[2] = ATA_WRITE_PM; 605 ctp->cfis[3] = reg; 606 ctp->cfis[7] = port | ATA_D_LBA; 607 ctp->cfis[12] = value & 0xff; 608 ctp->cfis[4] = (value >> 8) & 0xff;; 609 ctp->cfis[5] = (value >> 16) & 0xff;; 610 ctp->cfis[6] = (value >> 24) & 0xff;; 611 ctp->cfis[15] = ATA_A_4BIT; 612 613 if (ata_ahci_issue_cmd(dev, 0, 100)) { 614 device_printf(dev, "error writing PM port\n"); 615 return ATA_E_ABORT; 616 } 617 618 return (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) >> 8) & 0xff; 619} 620 621static void 622ata_ahci_stop(device_t dev) 623{ 624 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 625 struct ata_channel *ch = device_get_softc(dev); 626 u_int32_t cmd; 627 int offset = ch->unit << 7; 628 int timeout; 629 630 /* kill off all activity on this channel */ 631 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 632 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 633 cmd & ~ATA_AHCI_P_CMD_ST); 634 635 /* XXX SOS this is not entirely wrong */ 636 timeout = 0; 637 do { 638 DELAY(1000); 639 if (timeout++ > 1000) { 640 device_printf(dev, "stopping AHCI engine failed\n"); 641 break; 642 } 643 } 644 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR); 645} 646 647static void 648ata_ahci_clo(device_t dev) 649{ 650 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 651 struct ata_channel *ch = device_get_softc(dev); 652 u_int32_t cmd; 653 int offset = ch->unit << 7; 654 int timeout; 655 656 /* issue Command List Override if supported */ 657 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SCLO) { 658 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 659 cmd |= ATA_AHCI_P_CMD_CLO; 660 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd); 661 timeout = 0; 662 do { 663 DELAY(1000); 664 if (timeout++ > 1000) { 665 device_printf(dev, "executing CLO failed\n"); 666 break; 667 } 668 } 669 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO); 670 } 671} 672 673static void 674ata_ahci_start(device_t dev) 675{ 676 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 677 struct ata_channel *ch = device_get_softc(dev); 678 u_int32_t cmd; 679 int offset = ch->unit << 7; 680 681 /* clear SATA error register */ 682 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR)); 683 684 /* clear any interrupts pending on this channel */ 685 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, 686 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset)); 687 688 /* start operations on this channel */ 689 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 690 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 691 cmd | ATA_AHCI_P_CMD_ST | 692 (ch->devices & ATA_PORTMULTIPLIER ? ATA_AHCI_P_CMD_PMA : 0)); 693} 694 695static void 696ata_ahci_stop_fr(device_t dev) 697{ 698 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 699 struct ata_channel *ch = device_get_softc(dev); 700 u_int32_t cmd; 701 int offset = ch->unit << 7; 702 int timeout; 703 704 /* kill off all activity on this channel */ 705 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 706 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd & ~ATA_AHCI_P_CMD_FRE); 707 708 timeout = 0; 709 do { 710 DELAY(1000); 711 if (timeout++ > 1000) { 712 device_printf(dev, "stopping AHCI FR engine failed\n"); 713 break; 714 } 715 } 716 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_FR); 717} 718 719static void 720ata_ahci_start_fr(device_t dev) 721{ 722 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 723 struct ata_channel *ch = device_get_softc(dev); 724 u_int32_t cmd; 725 int offset = ch->unit << 7; 726 727 /* start FIS reception on this channel */ 728 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset); 729 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd | ATA_AHCI_P_CMD_FRE); 730} 731 732static int 733ata_ahci_wait_ready(device_t dev, int t) 734{ 735 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 736 struct ata_channel *ch = device_get_softc(dev); 737 int offset = ch->unit << 7; 738 int timeout = 0; 739 uint32_t val; 740 741 while ((val = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset)) & 742 (ATA_S_BUSY | ATA_S_DRQ)) { 743 DELAY(1000); 744 if (timeout++ > t) { 745 device_printf(dev, "port is not ready (timeout %dms) tfd = %08x\n", t, val); 746 return (EBUSY); 747 } 748 } 749 if (bootverbose) 750 device_printf(dev, "ready wait time=%dms\n", timeout); 751 return (0); 752} 753 754static int 755ata_ahci_hardreset(device_t dev, int port, uint32_t *signature) 756{ 757 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 758 struct ata_channel *ch = device_get_softc(dev); 759 int offset = ch->unit << 7; 760 761 *signature = 0xffffffff; 762 ata_ahci_stop(dev); 763 /* Reset port */ 764 if (!ata_sata_phy_reset(dev, port, 0)) 765 return (ENOENT); 766 /* Wait for clearing busy status. */ 767 if (ata_ahci_wait_ready(dev, 10000)) { 768 device_printf(dev, "hardware reset timeout\n"); 769 return (EBUSY); 770 } 771 *signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 772 ata_ahci_start(dev); 773 return (0); 774} 775 776static u_int32_t 777ata_ahci_softreset(device_t dev, int port) 778{ 779 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 780 struct ata_channel *ch = device_get_softc(dev); 781 int offset = ch->unit << 7; 782 struct ata_ahci_cmd_tab *ctp = 783 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET); 784 785 if (bootverbose) 786 device_printf(dev, "software reset port %d...\n", port); 787 788 /* kick controller into sane state */ 789 ata_ahci_stop(dev); 790 ata_ahci_clo(dev); 791 ata_ahci_start(dev); 792 793 /* pull reset active */ 794 bzero(ctp->cfis, 64); 795 ctp->cfis[0] = 0x27; 796 ctp->cfis[1] = port & 0x0f; 797 //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM; 798 ctp->cfis[15] = (ATA_A_4BIT | ATA_A_RESET); 799 800 if (ata_ahci_issue_cmd(dev, ATA_AHCI_CMD_RESET | ATA_AHCI_CMD_CLR_BUSY,100)) { 801 device_printf(dev, "software reset set timeout\n"); 802 return (-1); 803 } 804 805 ata_udelay(50); 806 807 /* pull reset inactive -> device softreset */ 808 bzero(ctp->cfis, 64); 809 ctp->cfis[0] = 0x27; 810 ctp->cfis[1] = port & 0x0f; 811 //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM; 812 ctp->cfis[15] = ATA_A_4BIT; 813 ata_ahci_issue_cmd(dev, 0, 3000); 814 815 if (ata_ahci_wait_ready(dev, 0)) { 816 device_printf(dev, "software reset clear timeout\n"); 817 return (-1); 818 } 819 820 return ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset); 821} 822 823void 824ata_ahci_reset(device_t dev) 825{ 826 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 827 struct ata_channel *ch = device_get_softc(dev); 828 u_int32_t signature; 829 int offset = ch->unit << 7; 830 831 if (bootverbose) 832 device_printf(dev, "AHCI reset...\n"); 833 834 /* Disable port interrupts */ 835 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0); 836 837 if (ata_ahci_hardreset(dev, -1, &signature)) { 838 if (bootverbose) 839 device_printf(dev, "AHCI reset done: phy reset found no device\n"); 840 ch->devices = 0; 841 842 /* enable wanted port interrupts */ 843 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 844 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC)); 845 return; 846 } 847 848 /* enable wanted port interrupts */ 849 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 850 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF | 851 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF | 852 ((ch->pm_level == 0) ? ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC : 0) | 853 ATA_AHCI_P_IX_DP | ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | 854 ATA_AHCI_P_IX_DS | ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR)); 855 856 /* only probe for PortMultiplier if HW has support */ 857 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SPM) { 858 signature = ata_ahci_softreset(dev, ATA_PM); 859 /* Workaround for some ATI chips, failing to soft-reset 860 * when port multiplicator supported, but absent. 861 * XXX: We can also check PxIS.IPMS==1 here to be sure. */ 862 if (signature == 0xffffffff) 863 signature = ata_ahci_softreset(dev, 0); 864 } else { 865 signature = ata_ahci_softreset(dev, 0); 866 } 867 if (bootverbose) 868 device_printf(dev, "SIGNATURE: %08x\n", signature); 869 870 switch (signature >> 16) { 871 case 0x0000: 872 ch->devices = ATA_ATA_MASTER; 873 break; 874 case 0x9669: 875 ch->devices = ATA_PORTMULTIPLIER; 876 ata_pm_identify(dev); 877 break; 878 case 0xeb14: 879 ch->devices = ATA_ATAPI_MASTER; 880 break; 881 default: /* SOS XXX */ 882 if (bootverbose) 883 device_printf(dev, "Unknown signature, assuming disk device\n"); 884 ch->devices = ATA_ATA_MASTER; 885 } 886 if (bootverbose) 887 device_printf(dev, "AHCI reset done: devices=%08x\n", ch->devices); 888} 889 890static void 891ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 892{ 893 struct ata_dmasetprd_args *args = xsc; 894 struct ata_ahci_dma_prd *prd = args->dmatab; 895 int i; 896 897 if (!(args->error = error)) { 898 for (i = 0; i < nsegs; i++) { 899 prd[i].dba = htole64(segs[i].ds_addr); 900 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK); 901 } 902 } 903 904 KASSERT(nsegs <= ATA_AHCI_DMA_ENTRIES, ("too many DMA segment entries\n")); 905 args->nsegs = nsegs; 906} 907 908static void 909ata_ahci_dmainit(device_t dev) 910{ 911 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 912 struct ata_channel *ch = device_get_softc(dev); 913 914 ata_dmainit(dev); 915 /* note start and stop are not used here */ 916 ch->dma.setprd = ata_ahci_dmasetprd; 917 ch->dma.max_iosize = 8192 * DEV_BSIZE; 918 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT) 919 ch->dma.max_address = BUS_SPACE_MAXADDR; 920} 921 922static int 923ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request) 924{ 925 bzero(ctp->cfis, 64); 926 if (request->flags & ATA_R_ATAPI) { 927 bzero(ctp->acmd, 32); 928 bcopy(request->u.atapi.ccb, ctp->acmd, 16); 929 } 930 return ata_request2fis_h2d(request, &ctp->cfis[0]); 931} 932 933ATA_DECLARE_DRIVER(ata_ahci); 934