1/*-
2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer,
10 *    without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: releng/10.2/sys/dev/ata/ata-sata.c 249213 2013-04-06 19:12:49Z marius $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/kernel.h>
33#include <sys/ata.h>
34#include <sys/bus.h>
35#include <sys/endian.h>
36#include <sys/malloc.h>
37#include <sys/lock.h>
38#include <sys/mutex.h>
39#include <sys/sema.h>
40#include <sys/taskqueue.h>
41#include <vm/uma.h>
42#include <machine/stdarg.h>
43#include <machine/resource.h>
44#include <machine/bus.h>
45#include <sys/rman.h>
46#include <dev/ata/ata-all.h>
47#include <ata_if.h>
48
49void
50ata_sata_phy_check_events(device_t dev, int port)
51{
52    struct ata_channel *ch = device_get_softc(dev);
53    u_int32_t error, status;
54
55    if (ata_sata_scr_read(ch, port, ATA_SERROR, &error))
56	return;
57
58    /* Check that SError value is sane. */
59    if (error == 0xffffffff)
60	return;
61
62    /* Clear set error bits/interrupt. */
63    if (error)
64	ata_sata_scr_write(ch, port, ATA_SERROR, error);
65
66    /* if we have a connection event deal with it */
67    if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
68	if (bootverbose) {
69	    if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status)) {
70		    device_printf(dev, "PHYRDY change\n");
71	    } else if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
72		((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
73		((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) {
74		    device_printf(dev, "CONNECT requested\n");
75	    } else
76		    device_printf(dev, "DISCONNECT requested\n");
77	}
78	taskqueue_enqueue(taskqueue_thread, &ch->conntask);
79    }
80}
81
82int
83ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val)
84{
85
86    if (ch->hw.pm_read != NULL)
87	return (ch->hw.pm_read(ch->dev, port, reg, val));
88    if (ch->r_io[reg].res) {
89	*val = ATA_IDX_INL(ch, reg);
90	return (0);
91    }
92    return (-1);
93}
94
95int
96ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val)
97{
98
99    if (ch->hw.pm_write != NULL)
100	return (ch->hw.pm_write(ch->dev, port, reg, val));
101    if (ch->r_io[reg].res) {
102	ATA_IDX_OUTL(ch, reg, val);
103	return (0);
104    }
105    return (-1);
106}
107
108static int
109ata_sata_connect(struct ata_channel *ch, int port, int quick)
110{
111    u_int32_t status;
112    int timeout, t;
113
114    /* wait up to 1 second for "connect well" */
115    timeout = (quick == 2) ? 0 : 100;
116    t = 0;
117    while (1) {
118	if (ata_sata_scr_read(ch, port, ATA_SSTATUS, &status))
119	    return (0);
120	if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
121	    ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
122	    ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
123	    break;
124	if (++t > timeout)
125	    break;
126	ata_udelay(10000);
127    }
128    if (bootverbose) {
129	if (t > timeout) {
130	    if (port < 0) {
131		device_printf(ch->dev, "SATA connect timeout status=%08x\n",
132		    status);
133	    } else {
134		device_printf(ch->dev, "p%d: SATA connect timeout status=%08x\n",
135		    port, status);
136	    }
137	} else if (port < 0) {
138	    device_printf(ch->dev, "SATA connect time=%dms status=%08x\n",
139		t * 10, status);
140	} else {
141	    device_printf(ch->dev, "p%d: SATA connect time=%dms status=%08x\n",
142		port, t * 10, status);
143	}
144    }
145
146    /* clear SATA error register */
147    ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
148
149    return ((t > timeout) ? 0 : 1);
150}
151
152int
153ata_sata_phy_reset(device_t dev, int port, int quick)
154{
155    struct ata_channel *ch = device_get_softc(dev);
156    int loop, retry, sata_rev;
157    uint32_t val, val1;
158
159    sata_rev = ch->user[port < 0 ? 0 : port].revision;
160    if (sata_rev > 0)
161	quick = 0;
162
163    if (quick) {
164	if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
165	    return (0);
166	if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE) {
167	    ata_sata_scr_write(ch, port, ATA_SCONTROL,
168		ATA_SC_DET_IDLE | ((ch->pm_level > 0) ? 0 :
169		ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER));
170	    return ata_sata_connect(ch, port, quick);
171	}
172    }
173
174    if (bootverbose) {
175	if (port < 0) {
176	    device_printf(dev, "hard reset ...\n");
177	} else {
178	    device_printf(dev, "p%d: hard reset ...\n", port);
179	}
180    }
181    if (sata_rev == 1)
182	val1 = ATA_SC_SPD_SPEED_GEN1;
183    else if (sata_rev == 2)
184	val1 = ATA_SC_SPD_SPEED_GEN2;
185    else if (sata_rev == 3)
186	val1 = ATA_SC_SPD_SPEED_GEN3;
187    else
188	val1 = 0;
189    for (retry = 0; retry < 10; retry++) {
190	for (loop = 0; loop < 10; loop++) {
191	    if (ata_sata_scr_write(ch, port, ATA_SCONTROL, ATA_SC_DET_RESET |
192		    val1 | ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))
193		goto fail;
194	    ata_udelay(100);
195	    if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
196		goto fail;
197	    if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_RESET)
198		break;
199	}
200	ata_udelay(5000);
201	for (loop = 0; loop < 10; loop++) {
202	    if (ata_sata_scr_write(ch, port, ATA_SCONTROL,
203		    ATA_SC_DET_IDLE | val1 | ((ch->pm_level > 0) ? 0 :
204		    ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)))
205		goto fail;
206	    ata_udelay(100);
207	    if (ata_sata_scr_read(ch, port, ATA_SCONTROL, &val))
208		goto fail;
209	    if ((val & ATA_SC_DET_MASK) == 0)
210		return ata_sata_connect(ch, port, 0);
211	}
212    }
213fail:
214    /* Clear SATA error register. */
215    ata_sata_scr_write(ch, port, ATA_SERROR, 0xffffffff);
216
217    if (bootverbose) {
218	if (port < 0) {
219	    device_printf(dev, "hard reset failed\n");
220	} else {
221	    device_printf(dev, "p%d: hard reset failed\n", port);
222	}
223    }
224    return (0);
225}
226
227int
228ata_sata_setmode(device_t dev, int target, int mode)
229{
230
231	return (min(mode, ATA_UDMA5));
232}
233
234int
235ata_sata_getrev(device_t dev, int target)
236{
237	struct ata_channel *ch = device_get_softc(dev);
238
239	if (ch->r_io[ATA_SSTATUS].res)
240		return ((ATA_IDX_INL(ch, ATA_SSTATUS) & 0x0f0) >> 4);
241	return (0xff);
242}
243
244int
245ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
246{
247
248    if (request->flags & ATA_R_ATAPI) {
249	fis[0] = 0x27;  		/* host to device */
250	fis[1] = 0x80 | (request->unit & 0x0f);
251	fis[2] = ATA_PACKET_CMD;
252	if (request->flags & (ATA_R_READ | ATA_R_WRITE))
253	    fis[3] = ATA_F_DMA;
254	else {
255	    fis[5] = request->transfersize;
256	    fis[6] = request->transfersize >> 8;
257	}
258	fis[7] = ATA_D_LBA;
259	fis[15] = ATA_A_4BIT;
260	return 20;
261    }
262    else {
263	fis[0] = 0x27;			/* host to device */
264	fis[1] = 0x80 | (request->unit & 0x0f);
265	fis[2] = request->u.ata.command;
266	fis[3] = request->u.ata.feature;
267	fis[4] = request->u.ata.lba;
268	fis[5] = request->u.ata.lba >> 8;
269	fis[6] = request->u.ata.lba >> 16;
270	fis[7] = ATA_D_LBA;
271	if (!(request->flags & ATA_R_48BIT))
272	    fis[7] |= (ATA_D_IBM | (request->u.ata.lba >> 24 & 0x0f));
273	fis[8] = request->u.ata.lba >> 24;
274	fis[9] = request->u.ata.lba >> 32;
275	fis[10] = request->u.ata.lba >> 40;
276	fis[11] = request->u.ata.feature >> 8;
277	fis[12] = request->u.ata.count;
278	fis[13] = request->u.ata.count >> 8;
279	fis[15] = ATA_A_4BIT;
280	return 20;
281    }
282    return 0;
283}
284
285void
286ata_pm_identify(device_t dev)
287{
288    struct ata_channel *ch = device_get_softc(dev);
289    u_int32_t pm_chipid, pm_revision, pm_ports;
290    int port;
291
292    /* get PM vendor & product data */
293    if (ch->hw.pm_read(dev, ATA_PM, 0, &pm_chipid)) {
294	device_printf(dev, "error getting PM vendor data\n");
295	return;
296    }
297
298    /* get PM revision data */
299    if (ch->hw.pm_read(dev, ATA_PM, 1, &pm_revision)) {
300	device_printf(dev, "error getting PM revison data\n");
301	return;
302    }
303
304    /* get number of HW ports on the PM */
305    if (ch->hw.pm_read(dev, ATA_PM, 2, &pm_ports)) {
306	device_printf(dev, "error getting PM port info\n");
307	return;
308    }
309    pm_ports &= 0x0000000f;
310
311    /* chip specific quirks */
312    switch (pm_chipid) {
313    case 0x37261095:
314	/* This PM declares 6 ports, while only 5 of them are real.
315	 * Port 5 is enclosure management bridge port, which has implementation
316	 * problems, causing probe faults. Hide it for now. */
317	device_printf(dev, "SiI 3726 (rev=%x) Port Multiplier with %d (5) ports\n",
318		      pm_revision, pm_ports);
319	pm_ports = 5;
320	break;
321
322    case 0x47261095:
323	/* This PM declares 7 ports, while only 5 of them are real.
324	 * Port 5 is some fake "Config  Disk" with 640 sectors size,
325	 * port 6 is enclosure management bridge port.
326	 * Both fake ports has implementation problems, causing
327	 * probe faults. Hide them for now. */
328	device_printf(dev, "SiI 4726 (rev=%x) Port Multiplier with %d (5) ports\n",
329		      pm_revision, pm_ports);
330	pm_ports = 5;
331	break;
332
333    default:
334	device_printf(dev, "Port Multiplier (id=%08x rev=%x) with %d ports\n",
335		      pm_chipid, pm_revision, pm_ports);
336    }
337
338    /* reset all ports and register if anything connected */
339    for (port=0; port < pm_ports; port++) {
340	u_int32_t signature;
341
342	if (!ata_sata_phy_reset(dev, port, 1))
343	    continue;
344
345	/*
346	 * XXX: I have no idea how to properly wait for PMP port hardreset
347	 * completion. Without this delay soft reset does not completes
348	 * successfully.
349	 */
350	DELAY(1000000);
351
352	signature = ch->hw.softreset(dev, port);
353
354	if (bootverbose)
355	    device_printf(dev, "p%d: SIGNATURE=%08x\n", port, signature);
356
357	/* figure out whats there */
358	switch (signature >> 16) {
359	case 0x0000:
360	    ch->devices |= (ATA_ATA_MASTER << port);
361	    continue;
362	case 0xeb14:
363	    ch->devices |= (ATA_ATAPI_MASTER << port);
364	    continue;
365	}
366    }
367}
368