ata-dma.c revision 91672
1/*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 91672 2002-03-05 09:24:19Z sos $ 29 */ 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/ata.h> 34#include <sys/bio.h> 35#include <sys/malloc.h> 36#include <sys/bus.h> 37#include <sys/disk.h> 38#include <sys/devicestat.h> 39#include <vm/vm.h> 40#include <vm/pmap.h> 41#include <pci/pcivar.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/ata/ata-all.h> 45 46/* prototypes */ 47static void cyrix_timing(struct ata_channel *, int, int); 48static void promise_timing(struct ata_channel *, int, int); 49static void hpt_timing(struct ata_channel *, int, int); 50 51/* misc defines */ 52#ifdef __alpha__ 53#undef vtophys 54#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 55#endif 56#define ATAPI_DEVICE(ch, device) \ 57 ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || \ 58 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)) 59 60void * 61ata_dmaalloc(struct ata_channel *ch, int device) 62{ 63 void *dmatab; 64 65 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 66 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 67 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 68 ata_printf(ch, device, "dmatab crosses page boundary, no DMA\n"); 69 free(dmatab, M_DEVBUF); 70 dmatab = NULL; 71 } 72 } 73 return dmatab; 74} 75 76void 77ata_dmainit(struct ata_channel *ch, int device, 78 int apiomode, int wdmamode, int udmamode) 79{ 80 struct ata_device *atadev = &ch->device[ATA_DEV(device)]; 81 device_t parent = device_get_parent(ch->dev); 82 int devno = (ch->unit << 1) + ATA_DEV(device); 83 int error; 84 85 /* set our most pessimistic default mode */ 86 atadev->mode = ATA_PIO; 87 88 if (!ch->r_bmio) 89 return; 90 91 /* if simplex controller, only allow DMA on primary channel */ 92 if (ch->unit == 1) { 93 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 94 ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 95 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 96 if (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 97 ata_prtdev(atadev, "simplex device, DMA on primary only\n"); 98 return; 99 } 100 } 101 102 /* DMA engine address alignment is usually 1 word (2 bytes) */ 103 ch->alignment = 0x1; 104 105#if 1 106 if (udmamode > 2 && !ch->device[ATA_DEV(device)].param->hwres_cblid) { 107 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); 108 udmamode = 2; 109 } 110#endif 111 switch (ch->chiptype) { 112 113 case 0x248a8086: /* Intel ICH3 mobile */ 114 case 0x248b8086: /* Intel ICH3 */ 115 case 0x244a8086: /* Intel ICH2 mobile */ 116 case 0x244b8086: /* Intel ICH2 */ 117 if (udmamode >= 5) { 118 int32_t mask48, new48; 119 int16_t word54; 120 121 word54 = pci_read_config(parent, 0x54, 2); 122 if (word54 & (0x10 << devno)) { 123 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 124 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 125 if (bootverbose) 126 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n", 127 (error) ? "failed" : "success"); 128 if (!error) { 129 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 130 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 131 pci_write_config(parent, 0x48, 132 (pci_read_config(parent, 0x48, 4) & 133 ~mask48) | new48, 4); 134 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 135 atadev->mode = ATA_UDMA5; 136 return; 137 } 138 } 139 } 140 /* make sure eventual ATA100 mode from the BIOS is disabled */ 141 pci_write_config(parent, 0x54, 142 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 143 /* FALLTHROUGH */ 144 145 case 0x24118086: /* Intel ICH */ 146 case 0x76018086: /* Intel ICH */ 147 if (udmamode >= 4) { 148 int32_t mask48, new48; 149 int16_t word54; 150 151 word54 = pci_read_config(parent, 0x54, 2); 152 if (word54 & (0x10 << devno)) { 153 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 154 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 155 if (bootverbose) 156 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n", 157 (error) ? "failed" : "success"); 158 if (!error) { 159 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 160 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 161 pci_write_config(parent, 0x48, 162 (pci_read_config(parent, 0x48, 4) & 163 ~mask48) | new48, 4); 164 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 165 atadev->mode = ATA_UDMA4; 166 return; 167 } 168 } 169 } 170 /* make sure eventual ATA66 mode from the BIOS is disabled */ 171 pci_write_config(parent, 0x54, 172 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 173 /* FALLTHROUGH */ 174 175 case 0x71118086: /* Intel PIIX4 */ 176 case 0x84CA8086: /* Intel PIIX4 */ 177 case 0x71998086: /* Intel PIIX4e */ 178 case 0x24218086: /* Intel ICH0 */ 179 if (udmamode >= 2) { 180 int32_t mask48, new48; 181 182 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 183 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 184 if (bootverbose) 185 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n", 186 (error) ? "failed" : "success"); 187 if (!error) { 188 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 189 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 190 pci_write_config(parent, 0x48, 191 (pci_read_config(parent, 0x48, 4) & 192 ~mask48) | new48, 4); 193 atadev->mode = ATA_UDMA2; 194 return; 195 } 196 } 197 /* make sure eventual ATA33 mode from the BIOS is disabled */ 198 pci_write_config(parent, 0x48, 199 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 200 /* FALLTHROUGH */ 201 202 case 0x70108086: /* Intel PIIX3 */ 203 if (wdmamode >= 2 && apiomode >= 4) { 204 int32_t mask40, new40, mask44, new44; 205 206 /* if SITRE not set doit for both channels */ 207 if (!((pci_read_config(parent,0x40,4)>>(ch->unit<<8))&0x4000)) { 208 new40 = pci_read_config(parent, 0x40, 4); 209 new44 = pci_read_config(parent, 0x44, 4); 210 if (!(new40 & 0x00004000)) { 211 new44 &= ~0x0000000f; 212 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 213 } 214 if (!(new40 & 0x40000000)) { 215 new44 &= ~0x000000f0; 216 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 217 } 218 new40 |= 0x40004000; 219 pci_write_config(parent, 0x40, new40, 4); 220 pci_write_config(parent, 0x44, new44, 4); 221 } 222 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 223 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 224 if (bootverbose) 225 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 226 (error) ? "failed" : "success"); 227 if (!error) { 228 if (device == ATA_MASTER) { 229 mask40 = 0x0000330f; 230 new40 = 0x00002307; 231 mask44 = 0; 232 new44 = 0; 233 } 234 else { 235 mask40 = 0x000000f0; 236 new40 = 0x00000070; 237 mask44 = 0x0000000f; 238 new44 = 0x0000000b; 239 } 240 if (ch->unit) { 241 mask40 <<= 16; 242 new40 <<= 16; 243 mask44 <<= 4; 244 new44 <<= 4; 245 } 246 pci_write_config(parent, 0x40, 247 (pci_read_config(parent, 0x40, 4) & ~mask40)| 248 new40, 4); 249 pci_write_config(parent, 0x44, 250 (pci_read_config(parent, 0x44, 4) & ~mask44)| 251 new44, 4); 252 atadev->mode = ATA_WDMA2; 253 return; 254 } 255 } 256 /* we could set PIO mode timings, but we assume the BIOS did that */ 257 break; 258 259 case 0x12308086: /* Intel PIIX */ 260 if (wdmamode >= 2 && apiomode >= 4) { 261 int32_t word40; 262 263 word40 = pci_read_config(parent, 0x40, 4); 264 word40 >>= ch->unit * 16; 265 266 /* Check for timing config usable for DMA on controller */ 267 if (!((word40 & 0x3300) == 0x2300 && 268 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 269 break; 270 271 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 272 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 273 if (bootverbose) 274 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 275 (error) ? "failed" : "success"); 276 if (!error) { 277 atadev->mode = ATA_WDMA2; 278 return; 279 } 280 } 281 break; 282 283 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 284 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 285 if (pci_get_revid(parent) < 0xc2 && 286 ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 287 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n"); 288 break; 289 } 290 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) { 291 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 292 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 293 if (bootverbose) 294 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n", 295 (error) ? "failed" : "success"); 296 if (!error) { 297 int32_t word54 = pci_read_config(parent, 0x54, 4); 298 299 pci_write_config(parent, 0x4b, 300 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 301 word54 &= ~(0x000f000f << (devno << 2)); 302 word54 |= (0x000f0005 << (devno << 2)); 303 pci_write_config(parent, 0x54, word54, 4); 304 pci_write_config(parent, 0x53, 305 pci_read_config(parent, 0x53, 1) | 0x03, 1); 306 atadev->mode = ATA_UDMA5; 307 return; 308 } 309 } 310 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) { 311 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 312 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 313 if (bootverbose) 314 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n", 315 (error) ? "failed" : "success"); 316 if (!error) { 317 int32_t word54 = pci_read_config(parent, 0x54, 4); 318 319 pci_write_config(parent, 0x4b, 320 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 321 word54 &= ~(0x000f000f << (devno << 2)); 322 word54 |= (0x00080005 << (devno << 2)); 323 pci_write_config(parent, 0x54, word54, 4); 324 pci_write_config(parent, 0x53, 325 pci_read_config(parent, 0x53, 1) | 0x03, 1); 326 atadev->mode = ATA_UDMA4; 327 return; 328 } 329 } 330 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 331 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 332 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 333 if (bootverbose) 334 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n", 335 (error) ? "failed" : "success"); 336 if (!error) { 337 int32_t word54 = pci_read_config(parent, 0x54, 4); 338 339 word54 &= ~(0x000f000f << (devno << 2)); 340 word54 |= (0x000a0005 << (devno << 2)); 341 pci_write_config(parent, 0x54, word54, 4); 342 pci_write_config(parent, 0x53, 343 pci_read_config(parent, 0x53, 1) | 0x03, 1); 344 ch->flags |= ATA_ATAPI_DMA_RO; 345 atadev->mode = ATA_UDMA2; 346 return; 347 } 348 } 349 350 /* make sure eventual UDMA mode from the BIOS is disabled */ 351 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 352 ~(0x0008 << (devno << 2)), 2); 353 354 if (wdmamode >= 2 && apiomode >= 4) { 355 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 356 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 357 if (bootverbose) 358 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n", 359 (error) ? "failed" : "success"); 360 if (!error) { 361 pci_write_config(parent, 0x53, 362 pci_read_config(parent, 0x53, 1) | 0x03, 1); 363 ch->flags |= ATA_ATAPI_DMA_RO; 364 atadev->mode = ATA_WDMA2; 365 return; 366 } 367 } 368 pci_write_config(parent, 0x53, 369 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 370 /* we could set PIO mode timings, but we assume the BIOS did that */ 371 break; 372 373 case 0x74111022: /* AMD 766 */ 374 if (udmamode >= 5) { 375 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 376 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 377 if (bootverbose) 378 ata_prtdev(atadev, "%s setting UDMA5 on AMD chip\n", 379 (error) ? "failed" : "success"); 380 if (!error) { 381 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 382 atadev->mode = ATA_UDMA5; 383 return; 384 } 385 } 386 /* FALLTHROUGH */ 387 388 case 0x74091022: /* AMD 756 */ 389 if (udmamode >= 4) { 390 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 391 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 392 if (bootverbose) 393 ata_prtdev(atadev, "%s setting UDMA4 on AMD chip\n", 394 (error) ? "failed" : "success"); 395 if (!error) { 396 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 397 atadev->mode = ATA_UDMA4; 398 return; 399 } 400 } 401 goto via_82c586; 402 403 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */ 404 { 405 int via_modes[4][7] = { 406 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 */ 407 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* ATA66 */ 408 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* ATA100 */ 409 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }}; /* ATA133 */ 410 int *reg_val = NULL; 411 412 if (ata_find_dev(parent, 0x31471106, 0x40)) { /* 8233a */ 413 udmamode = imin(udmamode, 6); 414 reg_val = via_modes[3]; 415 } 416 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */ 417 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */ 418 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */ 419 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */ 420 udmamode = imin(udmamode, 5); 421 reg_val = via_modes[2]; 422 } 423 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */ 424 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 425 udmamode = imin(udmamode, 4); 426 reg_val = via_modes[1]; 427 } 428 else if (ata_find_dev(parent, 0x06861106, 0x0)) { /* 82C686 */ 429 udmamode = imin(udmamode, 2); 430 reg_val = via_modes[1]; 431 } 432 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 433 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 434via_82c586: 435 udmamode = imin(udmamode, 2); 436 reg_val = via_modes[0]; 437 } 438 else 439 udmamode = 0; 440 441 if (udmamode >= 6) { 442 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 443 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 444 if (bootverbose) 445 ata_prtdev(atadev, "%s setting UDMA6 on VIA chip\n", 446 (error) ? "failed" : "success"); 447 if (!error) { 448 pci_write_config(parent, 0x53 - devno, reg_val[6], 1); 449 atadev->mode = ATA_UDMA6; 450 return; 451 } 452 } 453 if (udmamode >= 5) { 454 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 455 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 456 if (bootverbose) 457 ata_prtdev(atadev, "%s setting UDMA5 on VIA chip\n", 458 (error) ? "failed" : "success"); 459 if (!error) { 460 pci_write_config(parent, 0x53 - devno, reg_val[5], 1); 461 atadev->mode = ATA_UDMA5; 462 return; 463 } 464 } 465 if (udmamode >= 4) { 466 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 467 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 468 if (bootverbose) 469 ata_prtdev(atadev, "%s setting UDMA4 on VIA chip\n", 470 (error) ? "failed" : "success"); 471 if (!error) { 472 pci_write_config(parent, 0x53 - devno, reg_val[4], 1); 473 atadev->mode = ATA_UDMA4; 474 return; 475 } 476 } 477 if (udmamode >= 2) { 478 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 479 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 480 if (bootverbose) 481 ata_prtdev(atadev, "%s setting UDMA2 on VIA chip\n", 482 (error) ? "failed" : "success"); 483 if (!error) { 484 pci_write_config(parent, 0x53 - devno, reg_val[2], 1); 485 atadev->mode = ATA_UDMA2; 486 return; 487 } 488 } 489 490 } 491 if (wdmamode >= 2 && apiomode >= 4) { 492 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 493 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 494 if (bootverbose) 495 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n", 496 (error) ? "failed" : "success", 497 (ch->chiptype == 0x74091022) ? "AMD" : "VIA"); 498 if (!error) { 499 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 500 pci_write_config(parent, 0x4b - devno, 0x31, 1); 501 atadev->mode = ATA_WDMA2; 502 return; 503 } 504 } 505 /* we could set PIO mode timings, but we assume the BIOS did that */ 506 break; 507 508 case 0x55131039: /* SiS 5591 */ 509 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 510 ata_find_dev(parent, 0x06331039, 0x00) || /* SiS 633 */ 511 ata_find_dev(parent, 0x06351039, 0x00) || /* SiS 635 */ 512 ata_find_dev(parent, 0x06401039, 0x00) || /* SiS 640 */ 513 ata_find_dev(parent, 0x06451039, 0x00) || /* SiS 645 */ 514 ata_find_dev(parent, 0x06501039, 0x00) || /* SiS 650 */ 515 ata_find_dev(parent, 0x07301039, 0x00) || /* SiS 730 */ 516 ata_find_dev(parent, 0x07331039, 0x00) || /* SiS 733 */ 517 ata_find_dev(parent, 0x07351039, 0x00) || /* SiS 735 */ 518 ata_find_dev(parent, 0x07401039, 0x00) || /* SiS 740 */ 519 ata_find_dev(parent, 0x07451039, 0x00) || /* SiS 745 */ 520 ata_find_dev(parent, 0x07501039, 0x00)) { /* SiS 750 */ 521 int8_t reg = 0x40 + (devno << 1); 522 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 523 524 if (udmamode >= 5) { 525 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 526 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 527 if (bootverbose) 528 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n", 529 (error) ? "failed" : "success"); 530 if (!error) { 531 pci_write_config(parent, reg, val | 0x8000, 2); 532 atadev->mode = ATA_UDMA5; 533 return; 534 } 535 } 536 if (udmamode >= 4) { 537 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 538 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 539 if (bootverbose) 540 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 541 (error) ? "failed" : "success"); 542 if (!error) { 543 pci_write_config(parent, reg, val | 0x9000, 2); 544 atadev->mode = ATA_UDMA4; 545 return; 546 } 547 } 548 if (udmamode >= 2) { 549 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 550 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 551 if (bootverbose) 552 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 553 (error) ? "failed" : "success"); 554 if (!error) { 555 pci_write_config(parent, reg, val | 0xb000, 2); 556 atadev->mode = ATA_UDMA2; 557 return; 558 } 559 } 560 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 561 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 562 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 563 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 564 int8_t reg = 0x40 + (devno << 1); 565 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 566 567 if (udmamode >= 4) { 568 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 569 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 570 if (bootverbose) 571 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 572 (error) ? "failed" : "success"); 573 if (!error) { 574 pci_write_config(parent, reg, val | 0x9000, 2); 575 atadev->mode = ATA_UDMA4; 576 return; 577 } 578 } 579 if (udmamode >= 2) { 580 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 581 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 582 if (bootverbose) 583 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 584 (error) ? "failed" : "success"); 585 if (!error) { 586 pci_write_config(parent, reg, val | 0xa000, 2); 587 atadev->mode = ATA_UDMA2; 588 return; 589 } 590 } 591 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 592 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 593 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 594 if (bootverbose) 595 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 596 (error) ? "failed" : "success"); 597 if (!error) { 598 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 599 atadev->mode = ATA_UDMA2; 600 return; 601 } 602 } 603 if (wdmamode >=2 && apiomode >= 4) { 604 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 605 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 606 if (bootverbose) 607 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n", 608 (error) ? "failed" : "success"); 609 if (!error) { 610 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 611 atadev->mode = ATA_WDMA2; 612 return; 613 } 614 } 615 /* we could set PIO mode timings, but we assume the BIOS did that */ 616 break; 617 618 case 0x06491095: /* CMD 649 ATA100 controller */ 619 if (udmamode >= 5) { 620 u_int8_t umode; 621 622 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 623 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 624 if (bootverbose) 625 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n", 626 (error) ? "failed" : "success"); 627 if (!error) { 628 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1); 629 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 630 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 631 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1); 632 atadev->mode = ATA_UDMA5; 633 return; 634 } 635 } 636 /* FALLTHROUGH */ 637 638 case 0x06481095: /* CMD 648 ATA66 controller */ 639 if (udmamode >= 4) { 640 u_int8_t umode; 641 642 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 643 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 644 if (bootverbose) 645 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n", 646 (error) ? "failed" : "success"); 647 if (!error) { 648 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1); 649 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 650 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 651 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1); 652 atadev->mode = ATA_UDMA4; 653 return; 654 } 655 } 656 if (udmamode >= 2) { 657 u_int8_t umode; 658 659 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 660 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 661 if (bootverbose) 662 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n", 663 (error) ? "failed" : "success"); 664 if (!error) { 665 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1); 666 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 667 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 668 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1); 669 atadev->mode = ATA_UDMA2; 670 return; 671 } 672 } 673 /* make sure eventual UDMA mode from the BIOS is disabled */ 674 pci_write_config(parent, ch->unit ? 0x7b : 0x73, 675 pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1)& 676 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 677 /* FALLTHROUGH */ 678 679 case 0x06461095: /* CMD 646 ATA controller */ 680 if (wdmamode >= 2 && apiomode >= 4) { 681 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 682 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 683 if (bootverbose) 684 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n", 685 error ? "failed" : "success"); 686 if (!error) { 687 int32_t offset = (devno < 3) ? (devno << 1) : 7; 688 689 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 690 atadev->mode = ATA_WDMA2; 691 return; 692 } 693 } 694 /* we could set PIO mode timings, but we assume the BIOS did that */ 695 break; 696 697 case 0xc6931080: /* Cypress 82c693 ATA controller */ 698 if (wdmamode >= 2 && apiomode >= 4) { 699 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 700 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 701 if (bootverbose) 702 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n", 703 error ? "failed" : "success"); 704 if (!error) { 705 pci_write_config(ch->dev, ch->unit ? 0x4e:0x4c, 0x2020, 2); 706 atadev->mode = ATA_WDMA2; 707 return; 708 } 709 } 710 /* we could set PIO mode timings, but we assume the BIOS did that */ 711 break; 712 713 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 714 ch->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 715 if (udmamode >= 2) { 716 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 717 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 718 if (bootverbose) 719 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n", 720 (error) ? "failed" : "success"); 721 if (!error) { 722 cyrix_timing(ch, devno, ATA_UDMA2); 723 atadev->mode = ATA_UDMA2; 724 return; 725 } 726 } 727 if (wdmamode >= 2 && apiomode >= 4) { 728 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 729 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 730 if (bootverbose) 731 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n", 732 (error) ? "failed" : "success"); 733 if (!error) { 734 cyrix_timing(ch, devno, ATA_WDMA2); 735 atadev->mode = ATA_WDMA2; 736 return; 737 } 738 } 739 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 740 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 741 ATA_WAIT_READY); 742 if (bootverbose) 743 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n", 744 (error) ? "failed" : "success", 745 ata_mode2str(ATA_PIO0 + apiomode)); 746 cyrix_timing(ch, devno, ATA_PIO0 + apiomode); 747 atadev->mode = ATA_PIO0 + apiomode; 748 return; 749 750 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 751 if (udmamode >= 2) { 752 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 753 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 754 if (bootverbose) 755 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n", 756 (error) ? "failed" : "success"); 757 if (!error) { 758 u_int16_t reg56; 759 760 pci_write_config(parent, 0x54, 761 pci_read_config(parent, 0x54, 1) | 762 (0x01 << devno), 1); 763 reg56 = pci_read_config(parent, 0x56, 2); 764 reg56 &= ~(0xf << (devno * 4)); 765 reg56 |= (0x2 << (devno * 4)); 766 pci_write_config(parent, 0x56, reg56, 2); 767 atadev->mode = ATA_UDMA2; 768 return; 769 } 770 } 771 if (wdmamode >= 2 && apiomode >= 4) { 772 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 773 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 774 if (bootverbose) 775 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n", 776 (error) ? "failed" : "success"); 777 if (!error) { 778 int offset = (ch->unit * 2) + (device == ATA_MASTER); 779 int word44 = pci_read_config(parent, 0x44, 4); 780 781 pci_write_config(parent, 0x54, 782 pci_read_config(parent, 0x54, 1) & 783 ~(0x01 << devno), 1); 784 word44 &= ~(0xff << (offset << 8)); 785 word44 |= (0x20 << (offset << 8)); 786 pci_write_config(parent, 0x44, 0x20, 4); 787 atadev->mode = ATA_WDMA2; 788 return; 789 } 790 } 791 /* we could set PIO mode timings, but we assume the BIOS did that */ 792 break; 793 794 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 795 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 796 if (udmamode >= 6 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 797 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 798 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 799 if (bootverbose) 800 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n", 801 (error) ? "failed" : "success"); 802 if (!error) { 803 atadev->mode = ATA_UDMA6; 804 return; 805 } 806 } 807 /* FALLTHROUGH */ 808 809 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 810 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 811 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 812 if (udmamode >= 5 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 813 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 814 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 815 if (bootverbose) 816 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 817 (error) ? "failed" : "success"); 818 if (!error) { 819 atadev->mode = ATA_UDMA5; 820 return; 821 } 822 } 823 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 824 if (udmamode >= 4 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 825 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 826 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 827 if (bootverbose) 828 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 829 (error) ? "failed" : "success"); 830 if (!error) { 831 atadev->mode = ATA_UDMA4; 832 return; 833 } 834 } 835 if (udmamode >= 2) { 836 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 837 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 838 if (bootverbose) 839 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n", 840 (error) ? "failed" : "success"); 841 if (!error) { 842 atadev->mode = ATA_UDMA2; 843 return; 844 } 845 } 846 if (wdmamode >= 2 && apiomode >= 4) { 847 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 848 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 849 if (bootverbose) 850 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 851 (error) ? "failed" : "success"); 852 if (!error) { 853 atadev->mode = ATA_WDMA2; 854 return; 855 } 856 } 857 break; 858 859 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 860 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 861 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && 862 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){ 863 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 864 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 865 if (bootverbose) 866 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 867 (error) ? "failed" : "success"); 868 if (!error) { 869 promise_timing(ch, devno, ATA_UDMA5); 870 atadev->mode = ATA_UDMA5; 871 return; 872 } 873 } 874 /* FALLTHROUGH */ 875 876 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 877 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && 878 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){ 879 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 880 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 881 if (bootverbose) 882 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 883 (error) ? "failed" : "success"); 884 if (!error) { 885 promise_timing(ch, devno, ATA_UDMA4); 886 atadev->mode = ATA_UDMA4; 887 return; 888 } 889 } 890 /* FALLTHROUGH */ 891 892 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 893 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) { 894 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 895 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 896 if (bootverbose) 897 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n", 898 (error) ? "failed" : "success"); 899 if (!error) { 900 promise_timing(ch, devno, ATA_UDMA2); 901 atadev->mode = ATA_UDMA2; 902 return; 903 } 904 } 905 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) { 906 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 907 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 908 if (bootverbose) 909 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 910 (error) ? "failed" : "success"); 911 if (!error) { 912 promise_timing(ch, devno, ATA_WDMA2); 913 atadev->mode = ATA_WDMA2; 914 return; 915 } 916 } 917 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 918 ATA_PIO0 + apiomode, 919 ATA_C_F_SETXFER, ATA_WAIT_READY); 920 if (bootverbose) 921 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n", 922 (error) ? "failed" : "success", 923 (apiomode >= 0) ? apiomode : 0); 924 promise_timing(ch, devno, ATA_PIO0 + apiomode); 925 atadev->mode = ATA_PIO0 + apiomode; 926 return; 927 928 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 929 case 0x00051103: /* HighPoint HPT372 controllers */ 930 case 0x00081103: /* HighPoint HPT374 controllers */ 931 if (!ATAPI_DEVICE(ch, device) && udmamode >= 6 && 932 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) || 933 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) || 934 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07)) && 935 !(pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01:0x02))) { 936 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 937 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 938 if (bootverbose) 939 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n", 940 (error) ? "failed" : "success"); 941 if (!error) { 942 hpt_timing(ch, devno, ATA_UDMA6); 943 atadev->mode = ATA_UDMA6; 944 return; 945 } 946 } 947 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && 948 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) || 949 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) || 950 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07)) && 951 !(pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01:0x02))) { 952 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 953 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 954 if (bootverbose) 955 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n", 956 (error) ? "failed" : "success"); 957 if (!error) { 958 hpt_timing(ch, devno, ATA_UDMA5); 959 atadev->mode = ATA_UDMA5; 960 return; 961 } 962 } 963 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && 964 !(pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01:0x02))) { 965 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 966 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 967 if (bootverbose) 968 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n", 969 (error) ? "failed" : "success"); 970 if (!error) { 971 hpt_timing(ch, devno, ATA_UDMA4); 972 atadev->mode = ATA_UDMA4; 973 return; 974 } 975 } 976 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) { 977 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 978 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 979 if (bootverbose) 980 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n", 981 (error) ? "failed" : "success"); 982 if (!error) { 983 hpt_timing(ch, devno, ATA_UDMA2); 984 atadev->mode = ATA_UDMA2; 985 return; 986 } 987 } 988 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) { 989 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 990 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 991 if (bootverbose) 992 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n", 993 (error) ? "failed" : "success"); 994 if (!error) { 995 hpt_timing(ch, devno, ATA_WDMA2); 996 atadev->mode = ATA_WDMA2; 997 return; 998 } 999 } 1000 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1001 ATA_PIO0 + apiomode, 1002 ATA_C_F_SETXFER, ATA_WAIT_READY); 1003 if (bootverbose) 1004 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n", 1005 (error) ? "failed" : "success", 1006 (apiomode >= 0) ? apiomode : 0); 1007 hpt_timing(ch, devno, ATA_PIO0 + apiomode); 1008 atadev->mode = ATA_PIO0 + apiomode; 1009 return; 1010 1011 case 0x000116ca: /* Cenatek Rocket Drive controller */ 1012 if (wdmamode >= 0 && 1013 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 1014 ((device==ATA_MASTER)?ATA_BMSTAT_DMA_MASTER:ATA_BMSTAT_DMA_SLAVE))) 1015 atadev->mode = ATA_DMA; 1016 else 1017 atadev->mode = ATA_PIO; 1018 return; 1019 1020 default: /* unknown controller chip */ 1021 /* better not try generic DMA on ATAPI devices it almost never works */ 1022 if ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 1023 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)) 1024 break; 1025 1026 /* if controller says its setup for DMA take the easy way out */ 1027 /* the downside is we dont know what DMA mode we are in */ 1028 if ((udmamode >= 0 || wdmamode >= 2) && 1029 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 1030 ((device==ATA_MASTER) ? 1031 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 1032 atadev->mode = ATA_DMA; 1033 return; 1034 } 1035 1036 /* well, we have no support for this, but try anyways */ 1037 if ((wdmamode >= 2 && apiomode >= 4) && ch->r_bmio) { 1038 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1039 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1040 if (bootverbose) 1041 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n", 1042 (error) ? "failed" : "success"); 1043 if (!error) { 1044 atadev->mode = ATA_WDMA2; 1045 return; 1046 } 1047 } 1048 } 1049 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1050 ATA_C_F_SETXFER, ATA_WAIT_READY); 1051 if (bootverbose) 1052 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n", 1053 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1054 if (!error) 1055 atadev->mode = ATA_PIO0 + apiomode; 1056 else { 1057 if (bootverbose) 1058 ata_prtdev(atadev, "using PIO mode set by BIOS\n"); 1059 atadev->mode = ATA_PIO; 1060 } 1061} 1062 1063int 1064ata_dmasetup(struct ata_channel *ch, int device, struct ata_dmaentry *dmatab, 1065 caddr_t data, int32_t count) 1066{ 1067 u_int32_t dma_count, dma_base; 1068 int i = 0; 1069 1070 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) { 1071 ata_printf(ch, device, "non aligned DMA transfer attempted\n"); 1072 return -1; 1073 } 1074 1075 if (!count) { 1076 ata_printf(ch, device, "zero length DMA transfer attempted\n"); 1077 return -1; 1078 } 1079 1080 dma_base = vtophys(data); 1081 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 1082 data += dma_count; 1083 count -= dma_count; 1084 1085 while (count) { 1086 dmatab[i].base = dma_base; 1087 dmatab[i].count = (dma_count & 0xffff); 1088 i++; 1089 if (i >= ATA_DMA_ENTRIES) { 1090 ata_printf(ch, device, "too many segments in DMA table\n"); 1091 return -1; 1092 } 1093 dma_base = vtophys(data); 1094 dma_count = imin(count, PAGE_SIZE); 1095 data += imin(count, PAGE_SIZE); 1096 count -= imin(count, PAGE_SIZE); 1097 } 1098 dmatab[i].base = dma_base; 1099 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 1100 return 0; 1101} 1102 1103void 1104ata_dmastart(struct ata_channel *ch, int device, 1105 struct ata_dmaentry *dmatab, int dir) 1106{ 1107 ch->flags |= ATA_DMA_ACTIVE; 1108 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 1109 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1110 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1111 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 1112 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1113 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1114 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1115} 1116 1117int 1118ata_dmadone(struct ata_channel *ch) 1119{ 1120 int error; 1121 1122 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1123 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1124 ch->flags &= ~ATA_DMA_ACTIVE; 1125 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT); 1126 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1127 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1128 return error & ATA_BMSTAT_MASK; 1129} 1130 1131int 1132ata_dmastatus(struct ata_channel *ch) 1133{ 1134 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1135} 1136 1137static void 1138cyrix_timing(struct ata_channel *ch, int devno, int mode) 1139{ 1140 u_int32_t reg20 = 0x0000e132; 1141 u_int32_t reg24 = 0x00017771; 1142 1143 switch (mode) { 1144 case ATA_PIO0: reg20 = 0x0000e132; break; 1145 case ATA_PIO1: reg20 = 0x00018121; break; 1146 case ATA_PIO2: reg20 = 0x00024020; break; 1147 case ATA_PIO3: reg20 = 0x00032010; break; 1148 case ATA_PIO4: reg20 = 0x00040010; break; 1149 case ATA_WDMA2: reg24 = 0x00002020; break; 1150 case ATA_UDMA2: reg24 = 0x00911030; break; 1151 } 1152 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x20, reg20); 1153 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x24, reg24); 1154} 1155 1156static void 1157promise_timing(struct ata_channel *ch, int devno, int mode) 1158{ 1159 u_int32_t timing = 0; 1160 struct promise_timing { 1161 u_int8_t pa:4; 1162 u_int8_t prefetch:1; 1163 u_int8_t iordy:1; 1164 u_int8_t errdy:1; 1165 u_int8_t syncin:1; 1166 u_int8_t pb:5; 1167 u_int8_t mb:3; 1168 u_int8_t mc:4; 1169 u_int8_t dmaw:1; 1170 u_int8_t dmar:1; 1171 u_int8_t iordyp:1; 1172 u_int8_t dmarqp:1; 1173 u_int8_t reserved:8; 1174 } *t = (struct promise_timing*)&timing; 1175 1176 t->iordy = 1; t->iordyp = 1; 1177 if (mode >= ATA_DMA) { 1178 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1179 } 1180 1181 switch (ch->chiptype) { 1182 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1183 switch (mode) { 1184 default: 1185 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1186 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1187 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1188 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1189 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1190 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1191 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1192 } 1193 break; 1194 1195 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1196 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1197 case 0x0d30105a: /* Promise OEM ATA 100 */ 1198 switch (mode) { 1199 default: 1200 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1201 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1202 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1203 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1204 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1205 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1206 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1207 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1208 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1209 } 1210 break; 1211 } 1212 pci_write_config(device_get_parent(ch->dev), 0x60 + (devno<<2), timing, 4); 1213} 1214 1215static void 1216hpt_timing(struct ata_channel *ch, int devno, int mode) 1217{ 1218 device_t parent = device_get_parent(ch->dev); 1219 u_int32_t timing; 1220 if (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07) { 1221 switch (mode) { /* HPT374 */ 1222 case ATA_PIO0: timing = 0x0ac1f48a; break; 1223 case ATA_PIO1: timing = 0x0ac1f465; break; 1224 case ATA_PIO2: timing = 0x0a81f454; break; 1225 case ATA_PIO3: timing = 0x0a81f443; break; 1226 case ATA_PIO4: timing = 0x0a81f442; break; 1227 case ATA_WDMA2: timing = 0x22808242; break; 1228 case ATA_UDMA2: timing = 0x120c8242; break; 1229 case ATA_UDMA4: timing = 0x12ac8242; break; 1230 case ATA_UDMA5: timing = 0x12848242; break; 1231 case ATA_UDMA6: timing = 0x12808242; break; 1232 default: timing = 0x0d029d5e; 1233 } 1234 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1235 pci_write_config(parent, 0x5b, 1236 (pci_read_config(parent, 0x5b, 1) & 0x01) | 0x20, 1); 1237 } 1238 else if ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) || 1239 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01)) { 1240 switch (mode) { /* HPT372 */ 1241 case ATA_PIO0: timing = 0x0d029d5e; break; 1242 case ATA_PIO1: timing = 0x0d029d26; break; 1243 case ATA_PIO2: timing = 0x0c829ca6; break; 1244 case ATA_PIO3: timing = 0x0c829c84; break; 1245 case ATA_PIO4: timing = 0x0c829c62; break; 1246 case ATA_WDMA2: timing = 0x2c829262; break; 1247 case ATA_UDMA2: timing = 0x1c91dc62; break; 1248 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1249 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1250 case ATA_UDMA6: timing = 0x1c81dc62; break; 1251 default: timing = 0x0d029d5e; 1252 } 1253 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1254 pci_write_config(parent, 0x5b, 1255 (pci_read_config(parent, 0x5b, 1) & 0x01) | 0x20, 1); 1256 } 1257 else if (ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) { 1258 switch (mode) { /* HPT370 */ 1259 case ATA_PIO0: timing = 0x06914e57; break; 1260 case ATA_PIO1: timing = 0x06914e43; break; 1261 case ATA_PIO2: timing = 0x06514e33; break; 1262 case ATA_PIO3: timing = 0x06514e22; break; 1263 case ATA_PIO4: timing = 0x06514e21; break; 1264 case ATA_WDMA2: timing = 0x26514e21; break; 1265 case ATA_UDMA2: timing = 0x16494e31; break; 1266 case ATA_UDMA4: timing = 0x16454e31; break; 1267 case ATA_UDMA5: timing = 0x16454e31; break; 1268 default: timing = 0x06514e57; 1269 } 1270 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1271 pci_write_config(parent, 0x5b, 0x22, 1); 1272 } 1273 else { /* HPT36[68] */ 1274 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1275 case 0x85: /* 25Mhz */ 1276 switch (mode) { 1277 case ATA_PIO0: timing = 0xc0d08585; break; 1278 case ATA_PIO1: timing = 0xc0d08572; break; 1279 case ATA_PIO2: timing = 0xc0ca8542; break; 1280 case ATA_PIO3: timing = 0xc0ca8532; break; 1281 case ATA_PIO4: timing = 0xc0ca8521; break; 1282 case ATA_WDMA2: timing = 0xa0ca8521; break; 1283 case ATA_UDMA2: timing = 0x90cf8521; break; 1284 case ATA_UDMA4: timing = 0x90c98521; break; 1285 default: timing = 0x01208585; 1286 } 1287 break; 1288 default: 1289 case 0xa7: /* 33MHz */ 1290 switch (mode) { 1291 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1292 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1293 case ATA_PIO2: timing = 0xc0d0a753; break; 1294 case ATA_PIO3: timing = 0xc0c8a742; break; 1295 case ATA_PIO4: timing = 0xc0c8a731; break; 1296 case ATA_WDMA2: timing = 0xa0c8a731; break; 1297 case ATA_UDMA2: timing = 0x90caa731; break; 1298 case ATA_UDMA4: timing = 0x90c9a731; break; 1299 default: timing = 0x0120a7a7; 1300 } 1301 break; 1302 case 0xd9: /* 40Mhz */ 1303 switch (mode) { 1304 case ATA_PIO0: timing = 0xc018d9d9; break; 1305 case ATA_PIO1: timing = 0xc010d9c7; break; 1306 case ATA_PIO2: timing = 0xc010d997; break; 1307 case ATA_PIO3: timing = 0xc010d974; break; 1308 case ATA_PIO4: timing = 0xc008d963; break; 1309 case ATA_WDMA2: timing = 0xa008d943; break; 1310 case ATA_UDMA2: timing = 0x900bd943; break; 1311 case ATA_UDMA4: timing = 0x900fd943; break; 1312 default: timing = 0x0120d9d9; 1313 } 1314 } 1315 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1316 } 1317} 1318