ata-dma.c revision 67435
1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 67435 2000-10-22 12:17:38Z sos $ 29 */ 30 31#include "pci.h" 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bio.h> 35#include <sys/malloc.h> 36#include <sys/bus.h> 37#include <sys/disk.h> 38#include <sys/devicestat.h> 39#include <vm/vm.h> 40#include <vm/pmap.h> 41#if NPCI > 0 42#include <pci/pcivar.h> 43#endif 44#include <machine/bus.h> 45#include <dev/ata/ata-all.h> 46 47#if NPCI > 0 48 49/* prototypes */ 50static void cyrix_timing(struct ata_softc *, int, int); 51static void promise_timing(struct ata_softc *, int, int); 52static void hpt_timing(struct ata_softc *, int, int); 53 54/* misc defines */ 55#ifdef __alpha__ 56#undef vtophys 57#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 58#endif 59 60void * 61ata_dmaalloc(struct ata_softc *scp, int device) 62{ 63 void *dmatab; 64 65 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 66 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 67 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 68 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 69 free(dmatab, M_DEVBUF); 70 dmatab = NULL; 71 } 72 } 73 return dmatab; 74} 75 76void 77ata_dmainit(struct ata_softc *scp, int device, 78 int apiomode, int wdmamode, int udmamode) 79{ 80 device_t parent = device_get_parent(scp->dev); 81 int devno = (scp->channel << 1) + ATA_DEV(device); 82 int error; 83 84 /* set our most pessimistic default mode */ 85 scp->mode[ATA_DEV(device)] = ATA_PIO; 86 87 if (!scp->bmaddr) 88 return; 89 90 /* if simplex controller, only allow DMA on primary channel */ 91 if (scp->channel == 1) { 92 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 93 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 94 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 95 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 96 return; 97 } 98 } 99 100 /* DMA engine address alignment is usually 1 word (2 bytes) */ 101 scp->alignment = 0x1; 102 103 if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 104 ata_printf(scp, device, 105 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 106 udmamode = 2; 107 } 108 109 switch (scp->chiptype) { 110 111 case 0x244b8086: /* Intel ICH2 */ 112 if (udmamode >= 5) { 113 int32_t mask48, new48; 114 int16_t word54; 115 116 word54 = pci_read_config(parent, 0x54, 2); 117 if (word54 & (0x10 << devno)) { 118 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 119 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 120 if (bootverbose) 121 ata_printf(scp, device, 122 "%s setting UDMA5 on ICH2 chip\n", 123 (error) ? "failed" : "success"); 124 if (!error) { 125 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 126 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 127 pci_write_config(parent, 0x48, 128 (pci_read_config(parent, 0x48, 4) & 129 ~mask48) | new48, 4); 130 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 131 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 132 return; 133 } 134 } 135 } 136 /* make sure eventual ATA100 mode from the BIOS is disabled */ 137 pci_write_config(parent, 0x54, 138 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 139 /* FALLTHROUGH */ 140 141 case 0x24118086: /* Intel ICH */ 142 if (udmamode >= 4) { 143 int32_t mask48, new48; 144 int16_t word54; 145 146 word54 = pci_read_config(parent, 0x54, 2); 147 if (word54 & (0x10 << devno)) { 148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 149 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 150 if (bootverbose) 151 ata_printf(scp, device, 152 "%s setting UDMA4 on ICH%s chip\n", 153 (error) ? "failed" : "success", 154 (scp->chiptype == 0x244b8086) ? "2" : ""); 155 if (!error) { 156 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 157 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 158 pci_write_config(parent, 0x48, 159 (pci_read_config(parent, 0x48, 4) & 160 ~mask48) | new48, 4); 161 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 162 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 163 return; 164 } 165 } 166 } 167 /* make sure eventual ATA66 mode from the BIOS is disabled */ 168 pci_write_config(parent, 0x54, 169 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 170 /* FALLTHROUGH */ 171 172 case 0x71118086: /* Intel PIIX4 */ 173 case 0x71998086: /* Intel PIIX4e */ 174 case 0x24218086: /* Intel ICH0 */ 175 if (udmamode >= 2) { 176 int32_t mask48, new48; 177 178 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 179 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 180 if (bootverbose) 181 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 182 (error) ? "failed" : "success", 183 (scp->chiptype == 0x244b8086) ? "ICH2" : 184 (scp->chiptype == 0x24118086) ? "ICH" : 185 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 186 if (!error) { 187 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 188 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 189 pci_write_config(parent, 0x48, 190 (pci_read_config(parent, 0x48, 4) & 191 ~mask48) | new48, 4); 192 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 193 return; 194 } 195 } 196 /* make sure eventual ATA33 mode from the BIOS is disabled */ 197 pci_write_config(parent, 0x48, 198 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 199 /* FALLTHROUGH */ 200 201 case 0x70108086: /* Intel PIIX3 */ 202 if (wdmamode >= 2 && apiomode >= 4) { 203 int32_t mask40, new40, mask44, new44; 204 205 /* if SITRE not set doit for both channels */ 206 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 207 new40 = pci_read_config(parent, 0x40, 4); 208 new44 = pci_read_config(parent, 0x44, 4); 209 if (!(new40 & 0x00004000)) { 210 new44 &= ~0x0000000f; 211 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 212 } 213 if (!(new40 & 0x40000000)) { 214 new44 &= ~0x000000f0; 215 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 216 } 217 new40 |= 0x40004000; 218 pci_write_config(parent, 0x40, new40, 4); 219 pci_write_config(parent, 0x44, new44, 4); 220 } 221 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 222 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 223 if (bootverbose) 224 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 225 (error) ? "failed" : "success", 226 (scp->chiptype == 0x244b8086) ? "ICH2" : 227 (scp->chiptype == 0x24118086) ? "ICH" : 228 (scp->chiptype == 0x24218086) ? "ICH0" : 229 (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 230 if (!error) { 231 if (device == ATA_MASTER) { 232 mask40 = 0x0000330f; 233 new40 = 0x00002307; 234 mask44 = 0; 235 new44 = 0; 236 } 237 else { 238 mask40 = 0x000000f0; 239 new40 = 0x00000070; 240 mask44 = 0x0000000f; 241 new44 = 0x0000000b; 242 } 243 if (scp->channel) { 244 mask40 <<= 16; 245 new40 <<= 16; 246 mask44 <<= 4; 247 new44 <<= 4; 248 } 249 pci_write_config(parent, 0x40, 250 (pci_read_config(parent, 0x40, 4) & ~mask40)| 251 new40, 4); 252 pci_write_config(parent, 0x44, 253 (pci_read_config(parent, 0x44, 4) & ~mask44)| 254 new44, 4); 255 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 256 return; 257 } 258 } 259 /* we could set PIO mode timings, but we assume the BIOS did that */ 260 break; 261 262 case 0x12308086: /* Intel PIIX */ 263 if (wdmamode >= 2 && apiomode >= 4) { 264 int32_t word40; 265 266 word40 = pci_read_config(parent, 0x40, 4); 267 word40 >>= scp->channel * 16; 268 269 /* Check for timing config usable for DMA on controller */ 270 if (!((word40 & 0x3300) == 0x2300 && 271 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 272 break; 273 274 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 275 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 276 if (bootverbose) 277 ata_printf(scp, device, 278 "%s setting WDMA2 on PIIX chip\n", 279 (error) ? "failed" : "success"); 280 if (!error) { 281 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 282 return; 283 } 284 } 285 break; 286 287 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 288 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 289 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 290 ata_printf(scp, device, 291 "Aladdin: two atapi devices on this channel, no DMA\n"); 292 break; 293 } 294 if (udmamode >= 2 && pci_get_revid(parent) > 0x20) { 295 int32_t word54 = pci_read_config(parent, 0x54, 4); 296 297 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 298 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 299 if (bootverbose) 300 ata_printf(scp, device, 301 "%s setting UDMA2 on Aladdin chip\n", 302 (error) ? "failed" : "success"); 303 if (!error) { 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (0x000a0005 << (devno << 2)); 306 pci_write_config(parent, 0x54, word54, 4); 307 pci_write_config(parent, 0x53, 308 pci_read_config(parent, 0x53, 1) | 0x03, 1); 309 scp->flags |= ATA_ATAPI_DMA_RO; 310 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 311 return; 312 } 313 } 314 if (wdmamode >= 2 && apiomode >= 4) { 315 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 316 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 317 if (bootverbose) 318 ata_printf(scp, device, 319 "%s setting WDMA2 on Aladdin chip\n", 320 (error) ? "failed" : "success"); 321 if (!error) { 322 pci_write_config(parent, 0x53, 323 pci_read_config(parent, 0x53, 1) | 0x03, 1); 324 scp->flags |= ATA_ATAPI_DMA_RO; 325 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 326 return; 327 } 328 } 329 pci_write_config(parent, 0x53, 330 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 331 /* we could set PIO mode timings, but we assume the BIOS did that */ 332 break; 333 334 case 0x74091022: /* AMD 756 */ 335 if (udmamode >= 4) { 336 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 337 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 338 if (bootverbose) 339 ata_printf(scp, device, 340 "%s setting UDMA4 on AMD chip\n", 341 (error) ? "failed" : "success"); 342 if (!error) { 343 pci_write_config(parent, 0x53 - devno, 0xc3, 1); 344 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 345 return; 346 } 347 } 348 goto via_82c586; 349 350 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 351 if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 352 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 353 354 if (udmamode >= 4) { 355 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 356 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 357 if (bootverbose) 358 ata_printf(scp, device, 359 "%s setting UDMA4 on VIA chip\n", 360 (error) ? "failed" : "success"); 361 if (!error) { 362 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 363 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 364 return; 365 } 366 } 367 if (udmamode >= 2) { 368 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 369 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 370 if (bootverbose) 371 ata_printf(scp, device, 372 "%s setting UDMA2 on VIA chip\n", 373 (error) ? "failed" : "success"); 374 if (!error) { 375 pci_write_config(parent, 0x53 - devno, 0xea, 1); 376 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 377 return; 378 } 379 } 380 } 381 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 382 ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */ 383via_82c586: 384 if (udmamode >= 2) { 385 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 386 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 387 if (bootverbose) 388 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 389 (error) ? "failed" : "success", 390 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 391 if (!error) { 392 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 393 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 394 return; 395 } 396 } 397 } 398 if (wdmamode >= 2 && apiomode >= 4) { 399 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 400 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 401 if (bootverbose) 402 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 403 (error) ? "failed" : "success", 404 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 405 if (!error) { 406 pci_write_config(parent, 0x53 - devno, 0x82, 1); 407 pci_write_config(parent, 0x4b - devno, 0x31, 1); 408 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 409 return; 410 } 411 } 412 /* we could set PIO mode timings, but we assume the BIOS did that */ 413 break; 414 415 case 0x55131039: /* SiS 5591 */ 416 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 417 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 418 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 419 if (bootverbose) 420 ata_printf(scp, device, 421 "%s setting UDMA2 on SiS chip\n", 422 (error) ? "failed" : "success"); 423 if (!error) { 424 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 425 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 426 return; 427 } 428 } 429 if (wdmamode >=2 && apiomode >= 4) { 430 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 431 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 432 if (bootverbose) 433 ata_printf(scp, device, 434 "%s setting WDMA2 on SiS chip\n", 435 (error) ? "failed" : "success"); 436 if (!error) { 437 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 438 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 439 return; 440 } 441 } 442 /* we could set PIO mode timings, but we assume the BIOS did that */ 443 break; 444 445 case 0x06491095: /* CMD 649 ATA100 controller */ 446 if (udmamode >= 5) { 447 u_int8_t umode; 448 449 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 450 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 451 if (bootverbose) 452 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 453 (error) ? "failed" : "success"); 454 if (!error) { 455 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 456 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 457 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 458 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 459 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 460 return; 461 } 462 } 463 /* FALLTHROUGH */ 464 465 case 0x06481095: /* CMD 648 ATA66 controller */ 466 if (udmamode >= 4) { 467 u_int8_t umode; 468 469 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 470 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 471 if (bootverbose) 472 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 473 (error) ? "failed" : "success"); 474 if (!error) { 475 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 476 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 477 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 478 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 479 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 480 return; 481 } 482 } 483 if (udmamode >= 2) { 484 u_int8_t umode; 485 486 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 487 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 488 if (bootverbose) 489 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 490 (error) ? "failed" : "success"); 491 if (!error) { 492 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 493 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 494 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 495 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 496 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 497 return; 498 } 499 } 500 /* make sure eventual UDMA mode from the BIOS is disabled */ 501 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 502 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 503 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 504 /* FALLTHROUGH */ 505 506 case 0x06461095: /* CMD 646 ATA controller */ 507 if (wdmamode >= 2 && apiomode >= 4) { 508 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 509 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 510 if (bootverbose) 511 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 512 error ? "failed" : "success"); 513 if (!error) { 514 int32_t offset = (devno < 3) ? (devno << 1) : 7; 515 516 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 517 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 518 return; 519 } 520 } 521 /* we could set PIO mode timings, but we assume the BIOS did that */ 522 break; 523 524 case 0xc6931080: /* Cypress 82c693 ATA controller */ 525 if (wdmamode >= 2 && apiomode >= 4) { 526 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 527 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 528 if (bootverbose) 529 ata_printf(scp, device, 530 "%s setting WDMA2 on Cypress chip\n", 531 error ? "failed" : "success"); 532 if (!error) { 533 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 534 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 535 return; 536 } 537 } 538 /* we could set PIO mode timings, but we assume the BIOS did that */ 539 break; 540 541 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 542 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 543 if (udmamode >= 2) { 544 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 545 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 546 if (bootverbose) 547 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 548 (error) ? "failed" : "success"); 549 if (!error) { 550 cyrix_timing(scp, devno, ATA_UDMA2); 551 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 552 return; 553 } 554 } 555 if (wdmamode >= 2 && apiomode >= 4) { 556 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 557 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 558 if (bootverbose) 559 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 560 (error) ? "failed" : "success"); 561 if (!error) { 562 cyrix_timing(scp, devno, ATA_WDMA2); 563 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 564 return; 565 } 566 } 567 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 568 ata_pio2mode(apiomode), ATA_C_F_SETXFER, 569 ATA_WAIT_READY); 570 if (bootverbose) 571 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 572 (error) ? "failed" : "success", 573 ata_mode2str(ata_pio2mode(apiomode))); 574 cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 575 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 576 return; 577 578 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 579 if (udmamode >= 2) { 580 u_int16_t reg56; 581 582 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 583 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 584 if (bootverbose) 585 ata_printf(scp, device, 586 "%s setting UDMA2 on ServerWorks chip\n", 587 (error) ? "failed" : "success"); 588 if (!error) { 589 pci_write_config(parent, 0x54, 590 pci_read_config(parent, 0x54, 1) | 591 (0x01 << devno), 1); 592 reg56 = pci_read_config(parent, 0x56, 2); 593 reg56 &= ~(0xf << (devno * 4)); 594 reg56 |= (0x2 << (devno * 4)); 595 pci_write_config(parent, 0x56, reg56, 2); 596 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 597 return; 598 } 599 } 600 if (wdmamode >= 2 && apiomode >= 4) { 601 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 602 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 603 if (bootverbose) 604 ata_printf(scp, device, 605 "%s setting WDMA2 on ServerWorks chip\n", 606 (error) ? "failed" : "success"); 607 if (!error) { 608 int offset = (scp->channel * 2) + (device == ATA_MASTER); 609 int word44 = pci_read_config(parent, 0x44, 4); 610 611 pci_write_config(parent, 0x54, 612 pci_read_config(parent, 0x54, 1) & 613 ~(0x01 << devno), 1); 614 word44 &= ~(0xff << (offset << 8)); 615 word44 |= (0x20 << (offset << 8)); 616 pci_write_config(parent, 0x44, 0x20, 4); 617 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 618 return; 619 } 620 } 621 /* we could set PIO mode timings, but we assume the BIOS did that */ 622 break; 623 624 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 625 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 626 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 627 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 628 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 629 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 630 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 631 break; 632 633 if (udmamode >= 5 && 634 (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 635 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 636 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 637 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 638 if (bootverbose) 639 ata_printf(scp, device, 640 "%s setting UDMA5 on Promise chip\n", 641 (error) ? "failed" : "success"); 642 if (!error) { 643 promise_timing(scp, devno, ATA_UDMA5); 644 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 645 return; 646 } 647 } 648 if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 649 scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 650 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 651 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 652 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 653 if (bootverbose) 654 ata_printf(scp, device, 655 "%s setting UDMA4 on Promise chip\n", 656 (error) ? "failed" : "success"); 657 if (!error) { 658 promise_timing(scp, devno, ATA_UDMA4); 659 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 660 return; 661 } 662 } 663 if (udmamode >= 2) { 664 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 665 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 666 if (bootverbose) 667 ata_printf(scp, device, 668 "%s setting UDMA2 on Promise chip\n", 669 (error) ? "failed" : "success"); 670 if (!error) { 671 promise_timing(scp, devno, ATA_UDMA2); 672 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 673 return; 674 } 675 } 676 if (wdmamode >= 2 && apiomode >= 4) { 677 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 678 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 679 if (bootverbose) 680 ata_printf(scp, device, 681 "%s setting WDMA2 on Promise chip\n", 682 (error) ? "failed" : "success"); 683 if (!error) { 684 promise_timing(scp, devno, ATA_WDMA2); 685 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 686 return; 687 } 688 } 689 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 690 ata_pio2mode(apiomode), 691 ATA_C_F_SETXFER, ATA_WAIT_READY); 692 if (bootverbose) 693 ata_printf(scp, device, 694 "%s setting PIO%d on Promise chip\n", 695 (error) ? "failed" : "success", 696 (apiomode >= 0) ? apiomode : 0); 697 promise_timing(scp, devno, ata_pio2mode(apiomode)); 698 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 699 return; 700 701 case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 702 /* no ATAPI devices for now */ 703 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 704 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 705 break; 706 707 if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 708 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 709 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 710 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 711 if (bootverbose) 712 ata_printf(scp, device, 713 "%s setting UDMA5 on HighPoint chip\n", 714 (error) ? "failed" : "success"); 715 if (!error) { 716 hpt_timing(scp, devno, ATA_UDMA5); 717 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 718 return; 719 } 720 } 721 if (udmamode >=4 && 722 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 723 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 724 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 725 if (bootverbose) 726 ata_printf(scp, device, 727 "%s setting UDMA4 on HighPoint chip\n", 728 (error) ? "failed" : "success"); 729 if (!error) { 730 hpt_timing(scp, devno, ATA_UDMA4); 731 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 732 return; 733 } 734 } 735 if (udmamode >= 2) { 736 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 737 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 738 if (bootverbose) 739 ata_printf(scp, device, 740 "%s setting UDMA2 on HighPoint chip\n", 741 (error) ? "failed" : "success"); 742 if (!error) { 743 hpt_timing(scp, devno, ATA_UDMA2); 744 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 745 return; 746 } 747 } 748 if (wdmamode >= 2 && apiomode >= 4) { 749 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 750 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 751 if (bootverbose) 752 ata_printf(scp, device, 753 "%s setting WDMA2 on HighPoint chip\n", 754 (error) ? "failed" : "success"); 755 if (!error) { 756 hpt_timing(scp, devno, ATA_WDMA2); 757 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 758 return; 759 } 760 } 761 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 762 ata_pio2mode(apiomode), 763 ATA_C_F_SETXFER, ATA_WAIT_READY); 764 if (bootverbose) 765 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 766 (error) ? "failed" : "success", 767 (apiomode >= 0) ? apiomode : 0); 768 hpt_timing(scp, devno, ata_pio2mode(apiomode)); 769 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 770 return; 771 772 default: /* unknown controller chip */ 773 /* better not try generic DMA on ATAPI devices it almost never works */ 774 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 775 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 776 break; 777 778 /* if controller says its setup for DMA take the easy way out */ 779 /* the downside is we dont know what DMA mode we are in */ 780 if ((udmamode >= 0 || wdmamode > 1) && 781 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 782 ((device==ATA_MASTER) ? 783 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 784 scp->mode[ATA_DEV(device)] = ATA_DMA; 785 return; 786 } 787 788 /* well, we have no support for this, but try anyways */ 789 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 790 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 791 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 792 if (bootverbose) 793 ata_printf(scp, device, 794 "%s setting WDMA2 on generic chip\n", 795 (error) ? "failed" : "success"); 796 if (!error) { 797 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 798 return; 799 } 800 } 801 } 802 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 803 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 804 if (bootverbose) 805 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 806 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 807 if (!error) 808 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 809 else { 810 if (bootverbose) 811 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 812 scp->mode[ATA_DEV(device)] = ATA_PIO; 813 } 814} 815 816int 817ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 818 caddr_t data, int32_t count) 819{ 820 u_int32_t dma_count, dma_base; 821 int i = 0; 822 823 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 824 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 825 return -1; 826 } 827 828 if (!count) { 829 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 830 return -1; 831 } 832 833 dma_base = vtophys(data); 834 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 835 data += dma_count; 836 count -= dma_count; 837 838 while (count) { 839 dmatab[i].base = dma_base; 840 dmatab[i].count = (dma_count & 0xffff); 841 i++; 842 if (i >= ATA_DMA_ENTRIES) { 843 ata_printf(scp, device, "too many segments in DMA table\n"); 844 return -1; 845 } 846 dma_base = vtophys(data); 847 dma_count = min(count, PAGE_SIZE); 848 data += min(count, PAGE_SIZE); 849 count -= min(count, PAGE_SIZE); 850 } 851 dmatab[i].base = dma_base; 852 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 853 return 0; 854} 855 856void 857ata_dmastart(struct ata_softc *scp, int device, 858 struct ata_dmaentry *dmatab, int dir) 859{ 860 scp->flags |= ATA_DMA_ACTIVE; 861 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 862 outb(scp->bmaddr + ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 863 outb(scp->bmaddr + ATA_BMSTAT_PORT, 864 (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 865 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 866 outb(scp->bmaddr + ATA_BMCMD_PORT, 867 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 868} 869 870int 871ata_dmadone(struct ata_softc *scp) 872{ 873 outb(scp->bmaddr + ATA_BMCMD_PORT, 874 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 875 scp->flags &= ~ATA_DMA_ACTIVE; 876 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 877} 878 879int 880ata_dmastatus(struct ata_softc *scp) 881{ 882 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 883} 884 885static void 886cyrix_timing(struct ata_softc *scp, int devno, int mode) 887{ 888 u_int32_t reg20 = 0x0000e132; 889 u_int32_t reg24 = 0x00017771; 890 891 switch (mode) { 892 case ATA_PIO0: reg20 = 0x0000e132; break; 893 case ATA_PIO1: reg20 = 0x00018121; break; 894 case ATA_PIO2: reg20 = 0x00024020; break; 895 case ATA_PIO3: reg20 = 0x00032010; break; 896 case ATA_PIO4: reg20 = 0x00040010; break; 897 case ATA_WDMA2: reg24 = 0x00002020; break; 898 case ATA_UDMA2: reg24 = 0x00911030; break; 899 } 900 outl(scp->bmaddr + (devno * 8) + 0x20, reg20); 901 outl(scp->bmaddr + (devno * 8) + 0x24, reg24); 902} 903 904static void 905promise_timing(struct ata_softc *scp, int devno, int mode) 906{ 907 u_int32_t timing = 0; 908 struct promise_timing { 909 u_int8_t pa:4; 910 u_int8_t prefetch:1; 911 u_int8_t iordy:1; 912 u_int8_t errdy:1; 913 u_int8_t syncin:1; 914 u_int8_t pb:5; 915 u_int8_t mb:3; 916 u_int8_t mc:4; 917 u_int8_t dmaw:1; 918 u_int8_t dmar:1; 919 u_int8_t iordyp:1; 920 u_int8_t dmarqp:1; 921 u_int8_t reserved:8; 922 } *t = (struct promise_timing*)&timing; 923 924 t->iordy = 1; t->iordyp = 1; 925 if (mode >= ATA_DMA) { 926 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 927 } 928 929 switch (scp->chiptype) { 930 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 931 switch (mode) { 932 default: 933 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 934 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 935 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 936 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 937 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 938 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 939 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 940 } 941 break; 942 943 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 944 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 945 case 0x0d30105a: /* Promise OEM ATA 100 */ 946 switch (mode) { 947 default: 948 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 949 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 950 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 951 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 952 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 953 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 954 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 955 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 956 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 957 } 958 break; 959 } 960 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 961} 962 963static void 964hpt_timing(struct ata_softc *scp, int devno, int mode) 965{ 966 device_t parent = device_get_parent(scp->dev); 967 u_int32_t timing; 968 969 if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 970 switch (mode) { 971 case ATA_PIO0: timing = 0x06914e57; break; 972 case ATA_PIO1: timing = 0x06914e43; break; 973 case ATA_PIO2: timing = 0x06514e33; break; 974 case ATA_PIO3: timing = 0x06514e22; break; 975 case ATA_PIO4: timing = 0x06514e21; break; 976 case ATA_WDMA2: timing = 0x26514e21; break; 977 case ATA_UDMA2: timing = 0x16494e31; break; 978 case ATA_UDMA4: timing = 0x16454e31; break; 979 case ATA_UDMA5: timing = 0x16454e31; break; 980 default: timing = 0x06514e57; 981 } 982 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 983 pci_write_config(parent, 0x5b, 0x22, 1); 984 } 985 else { /* HPT36[68] */ 986 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 987 case 0x85: /* 25Mhz */ 988 switch (mode) { 989 case ATA_PIO0: timing = 0xc0d08585; break; 990 case ATA_PIO1: timing = 0xc0d08572; break; 991 case ATA_PIO2: timing = 0xc0ca8542; break; 992 case ATA_PIO3: timing = 0xc0ca8532; break; 993 case ATA_PIO4: timing = 0xc0ca8521; break; 994 case ATA_WDMA2: timing = 0xa0ca8521; break; 995 case ATA_UDMA2: timing = 0x90cf8521; break; 996 case ATA_UDMA4: timing = 0x90c98521; break; 997 default: timing = 0x01208585; 998 } 999 break; 1000 default: 1001 case 0xa7: /* 33MHz */ 1002 switch (mode) { 1003 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1004 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1005 case ATA_PIO2: timing = 0xc0d0a753; break; 1006 case ATA_PIO3: timing = 0xc0c8a742; break; 1007 case ATA_PIO4: timing = 0xc0c8a731; break; 1008 case ATA_WDMA2: timing = 0xa0c8a731; break; 1009 case ATA_UDMA2: timing = 0x90caa731; break; 1010 case ATA_UDMA4: timing = 0x90c9a731; break; 1011 default: timing = 0x0120a7a7; 1012 } 1013 break; 1014 case 0xd9: /* 40Mhz */ 1015 switch (mode) { 1016 case ATA_PIO0: timing = 0xc018d9d9; break; 1017 case ATA_PIO1: timing = 0xc010d9c7; break; 1018 case ATA_PIO2: timing = 0xc010d997; break; 1019 case ATA_PIO3: timing = 0xc010d974; break; 1020 case ATA_PIO4: timing = 0xc008d963; break; 1021 case ATA_WDMA2: timing = 0xa008d943; break; 1022 case ATA_UDMA2: timing = 0x900bd943; break; 1023 case ATA_UDMA4: timing = 0x900fd943; break; 1024 default: timing = 0x0120d9d9; 1025 } 1026 } 1027 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1028 } 1029} 1030 1031#else /* NPCI > 0 */ 1032 1033void * 1034ata_dmaalloc(struct ata_softc *scp, int device) 1035{ 1036 return 0; 1037} 1038 1039void 1040ata_dmainit(struct ata_softc *scp, int device, 1041 int piomode, int wdmamode, int udmamode) 1042{ 1043} 1044 1045int 1046ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 1047 caddr_t data, int32_t count) 1048{ 1049 return -1; 1050} 1051 1052void 1053ata_dmastart(struct ata_softc *scp, int device, 1054 struct ata_dmaentry *dmatab, int dir) 1055{ 1056} 1057 1058int 1059ata_dmadone(struct ata_softc *scp) 1060{ 1061 return -1; 1062} 1063 1064int 1065ata_dmastatus(struct ata_softc *scp) 1066{ 1067 return -1; 1068} 1069 1070#endif /* NPCI > 0 */ 1071